intel/skylake/cnl-sst-dsp.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Cannonlake SST DSP Support
0004  *
0005  * Copyright (C) 2016-17, Intel Corporation.
0006  */
0007
0008 #ifndef __CNL_SST_DSP_H__
0009 #define __CNL_SST_DSP_H__
0010
0011 struct sst_dsp;
0012 struct sst_dsp_device;
0013 struct sst_generic_ipc;
0014
0015 /* Intel HD Audio General DSP Registers */
0016 #define CNL_ADSP_GEN_BASE       0x0
0017 #define CNL_ADSP_REG_ADSPCS     (CNL_ADSP_GEN_BASE + 0x04)
0018 #define CNL_ADSP_REG_ADSPIC     (CNL_ADSP_GEN_BASE + 0x08)
0019 #define CNL_ADSP_REG_ADSPIS     (CNL_ADSP_GEN_BASE + 0x0c)
0020
0021 /* Intel HD Audio Inter-Processor Communication Registers */
0022 #define CNL_ADSP_IPC_BASE               0xc0
0023 #define CNL_ADSP_REG_HIPCTDR            (CNL_ADSP_IPC_BASE + 0x00)
0024 #define CNL_ADSP_REG_HIPCTDA            (CNL_ADSP_IPC_BASE + 0x04)
0025 #define CNL_ADSP_REG_HIPCTDD            (CNL_ADSP_IPC_BASE + 0x08)
0026 #define CNL_ADSP_REG_HIPCIDR            (CNL_ADSP_IPC_BASE + 0x10)
0027 #define CNL_ADSP_REG_HIPCIDA            (CNL_ADSP_IPC_BASE + 0x14)
0028 #define CNL_ADSP_REG_HIPCIDD            (CNL_ADSP_IPC_BASE + 0x18)
0029 #define CNL_ADSP_REG_HIPCCTL            (CNL_ADSP_IPC_BASE + 0x28)
0030
0031 /* HIPCTDR */
0032 #define CNL_ADSP_REG_HIPCTDR_BUSY   BIT(31)
0033
0034 /* HIPCTDA */
0035 #define CNL_ADSP_REG_HIPCTDA_DONE   BIT(31)
0036
0037 /* HIPCIDR */
0038 #define CNL_ADSP_REG_HIPCIDR_BUSY   BIT(31)
0039
0040 /* HIPCIDA */
0041 #define CNL_ADSP_REG_HIPCIDA_DONE   BIT(31)
0042
0043 /* CNL HIPCCTL */
0044 #define CNL_ADSP_REG_HIPCCTL_DONE   BIT(1)
0045 #define CNL_ADSP_REG_HIPCCTL_BUSY   BIT(0)
0046
0047 /* CNL HIPCT */
0048 #define CNL_ADSP_REG_HIPCT_BUSY     BIT(31)
0049
0050 /* Intel HD Audio SRAM Window 1 */
0051 #define CNL_ADSP_SRAM1_BASE     0xa0000
0052
0053 #define CNL_ADSP_MMIO_LEN       0x10000
0054
0055 #define CNL_ADSP_W0_STAT_SZ     0x1000
0056
0057 #define CNL_ADSP_W0_UP_SZ       0x1000
0058
0059 #define CNL_ADSP_W1_SZ          0x1000
0060
0061 #define CNL_FW_STS_MASK         0xf
0062
0063 #define CNL_ADSPIC_IPC          0x1
0064 #define CNL_ADSPIS_IPC          0x1
0065
0066 #define CNL_DSP_CORES       4
0067 #define CNL_DSP_CORES_MASK  ((1 << CNL_DSP_CORES) - 1)
0068
0069 /* core reset - asserted high */
0070 #define CNL_ADSPCS_CRST_SHIFT   0
0071 #define CNL_ADSPCS_CRST(x)  (x << CNL_ADSPCS_CRST_SHIFT)
0072
0073 /* core run/stall - when set to 1 core is stalled */
0074 #define CNL_ADSPCS_CSTALL_SHIFT 8
0075 #define CNL_ADSPCS_CSTALL(x)    (x << CNL_ADSPCS_CSTALL_SHIFT)
0076
0077 /* set power active - when set to 1 turn core on */
0078 #define CNL_ADSPCS_SPA_SHIFT    16
0079 #define CNL_ADSPCS_SPA(x)   (x << CNL_ADSPCS_SPA_SHIFT)
0080
0081 /* current power active - power status of cores, set by hardware */
0082 #define CNL_ADSPCS_CPA_SHIFT    24
0083 #define CNL_ADSPCS_CPA(x)   (x << CNL_ADSPCS_CPA_SHIFT)
0084
0085 int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
0086 int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
0087 irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id);
0088 void cnl_dsp_free(struct sst_dsp *dsp);
0089
0090 void cnl_ipc_int_enable(struct sst_dsp *ctx);
0091 void cnl_ipc_int_disable(struct sst_dsp *ctx);
0092 void cnl_ipc_op_int_enable(struct sst_dsp *ctx);
0093 void cnl_ipc_op_int_disable(struct sst_dsp *ctx);
0094 bool cnl_ipc_int_status(struct sst_dsp *ctx);
0095 void cnl_ipc_free(struct sst_generic_ipc *ipc);
0096
0097 int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
0098              const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
0099              struct skl_dev **dsp);
0100 int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl);
0101 void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl);
0102
0103 #endif /*__CNL_SST_DSP_H__*/