intel/common/sst-dsp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel Smart Sound Technology (SST) DSP Core Driver
0004  *
0005  * Copyright (C) 2013, Intel Corporation. All rights reserved.
0006  */
0007
0008 #include <linux/slab.h>
0009 #include <linux/export.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/io-64-nonatomic-lo-hi.h>
0014 #include <linux/delay.h>
0015
0016 #include "sst-dsp.h"
0017 #include "sst-dsp-priv.h"
0018
0019 #define CREATE_TRACE_POINTS
0020 #include <trace/events/intel-sst.h>
0021
0022 /* Internal generic low-level SST IO functions - can be overidden */
0023 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
0024 {
0025     writel(value, addr + offset);
0026 }
0027 EXPORT_SYMBOL_GPL(sst_shim32_write);
0028
0029 u32 sst_shim32_read(void __iomem *addr, u32 offset)
0030 {
0031     return readl(addr + offset);
0032 }
0033 EXPORT_SYMBOL_GPL(sst_shim32_read);
0034
0035 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
0036 {
0037     writeq(value, addr + offset);
0038 }
0039 EXPORT_SYMBOL_GPL(sst_shim32_write64);
0040
0041 u64 sst_shim32_read64(void __iomem *addr, u32 offset)
0042 {
0043     return readq(addr + offset);
0044 }
0045 EXPORT_SYMBOL_GPL(sst_shim32_read64);
0046
0047 /* Public API */
0048 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
0049 {
0050     unsigned long flags;
0051
0052     spin_lock_irqsave(&sst->spinlock, flags);
0053     sst->ops->write(sst->addr.shim, offset, value);
0054     spin_unlock_irqrestore(&sst->spinlock, flags);
0055 }
0056 EXPORT_SYMBOL_GPL(sst_dsp_shim_write);
0057
0058 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
0059 {
0060     unsigned long flags;
0061     u32 val;
0062
0063     spin_lock_irqsave(&sst->spinlock, flags);
0064     val = sst->ops->read(sst->addr.shim, offset);
0065     spin_unlock_irqrestore(&sst->spinlock, flags);
0066
0067     return val;
0068 }
0069 EXPORT_SYMBOL_GPL(sst_dsp_shim_read);
0070
0071 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
0072 {
0073     sst->ops->write(sst->addr.shim, offset, value);
0074 }
0075 EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);
0076
0077 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
0078 {
0079     return sst->ops->read(sst->addr.shim, offset);
0080 }
0081 EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);
0082
0083 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
0084                 u32 mask, u32 value)
0085 {
0086     bool change;
0087     unsigned int old, new;
0088     u32 ret;
0089
0090     ret = sst_dsp_shim_read_unlocked(sst, offset);
0091
0092     old = ret;
0093     new = (old & (~mask)) | (value & mask);
0094
0095     change = (old != new);
0096     if (change)
0097         sst_dsp_shim_write_unlocked(sst, offset, new);
0098
0099     return change;
0100 }
0101 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);
0102
0103 /* This is for registers bits with attribute RWC */
0104 void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
0105                 u32 mask, u32 value)
0106 {
0107     unsigned int old, new;
0108     u32 ret;
0109
0110     ret = sst_dsp_shim_read_unlocked(sst, offset);
0111
0112     old = ret;
0113     new = (old & (~mask)) | (value & mask);
0114
0115     sst_dsp_shim_write_unlocked(sst, offset, new);
0116 }
0117 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);
0118
0119 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
0120                 u32 mask, u32 value)
0121 {
0122     unsigned long flags;
0123     bool change;
0124
0125     spin_lock_irqsave(&sst->spinlock, flags);
0126     change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
0127     spin_unlock_irqrestore(&sst->spinlock, flags);
0128     return change;
0129 }
0130 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);
0131
0132 /* This is for registers bits with attribute RWC */
0133 void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
0134                 u32 mask, u32 value)
0135 {
0136     unsigned long flags;
0137
0138     spin_lock_irqsave(&sst->spinlock, flags);
0139     sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
0140     spin_unlock_irqrestore(&sst->spinlock, flags);
0141 }
0142 EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
0143
0144 int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
0145              u32 target, u32 time, char *operation)
0146 {
0147     u32 reg;
0148     unsigned long timeout;
0149     int k = 0, s = 500;
0150
0151     /*
0152      * split the loop into sleeps of varying resolution. more accurately,
0153      * the range of wakeups are:
0154      * Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
0155      * Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
0156      * (usleep_range (500, 1000) and usleep_range(5000, 10000) are
0157      * both possible in this phase depending on whether k > 10 or not).
0158      * Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
0159      */
0160
0161     timeout = jiffies + msecs_to_jiffies(time);
0162     while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
0163         && time_before(jiffies, timeout)) {
0164         k++;
0165         if (k > 10)
0166             s = 5000;
0167
0168         usleep_range(s, 2*s);
0169     }
0170
0171     if ((reg & mask) == target) {
0172         dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
0173                     reg, operation);
0174
0175         return 0;
0176     }
0177
0178     dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
0179                     reg, operation);
0180     return -ETIME;
0181 }
0182 EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
0183
0184 int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
0185     u32 outbox_offset, size_t outbox_size)
0186 {
0187     sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
0188     sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
0189     sst->mailbox.in_size = inbox_size;
0190     sst->mailbox.out_size = outbox_size;
0191     return 0;
0192 }
0193 EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);
0194
0195 void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes)
0196 {
0197     u32 i;
0198
0199     trace_sst_ipc_outbox_write(bytes);
0200
0201     memcpy_toio(sst->mailbox.out_base, message, bytes);
0202
0203     for (i = 0; i < bytes; i += 4)
0204         trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i));
0205 }
0206 EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);
0207
0208 void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes)
0209 {
0210     u32 i;
0211
0212     trace_sst_ipc_outbox_read(bytes);
0213
0214     memcpy_fromio(message, sst->mailbox.out_base, bytes);
0215
0216     for (i = 0; i < bytes; i += 4)
0217         trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i));
0218 }
0219 EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);
0220
0221 void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes)
0222 {
0223     u32 i;
0224
0225     trace_sst_ipc_inbox_write(bytes);
0226
0227     memcpy_toio(sst->mailbox.in_base, message, bytes);
0228
0229     for (i = 0; i < bytes; i += 4)
0230         trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i));
0231 }
0232 EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);
0233
0234 void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes)
0235 {
0236     u32 i;
0237
0238     trace_sst_ipc_inbox_read(bytes);
0239
0240     memcpy_fromio(message, sst->mailbox.in_base, bytes);
0241
0242     for (i = 0; i < bytes; i += 4)
0243         trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i));
0244 }
0245 EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);
0246
0247 /* Module information */
0248 MODULE_AUTHOR("Liam Girdwood");
0249 MODULE_DESCRIPTION("Intel SST Core");
0250 MODULE_LICENSE("GPL v2");