intel/catpt/registers.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright(c) 2020 Intel Corporation. All rights reserved.
0004  *
0005  * Author: Cezary Rojewski <cezary.rojewski@intel.com>
0006  */
0007
0008 #ifndef __SND_SOC_INTEL_CATPT_REGS_H
0009 #define __SND_SOC_INTEL_CATPT_REGS_H
0010
0011 #include <linux/bitops.h>
0012 #include <linux/iopoll.h>
0013 #include <uapi/linux/pci_regs.h>
0014
0015 #define CATPT_SHIM_REGS_SIZE    4096
0016 #define CATPT_DMA_REGS_SIZE 1024
0017 #define CATPT_DMA_COUNT     2
0018 #define CATPT_SSP_REGS_SIZE 512
0019
0020 /* DSP Shim registers */
0021
0022 #define CATPT_SHIM_CS1      0x00
0023 #define CATPT_SHIM_ISC      0x18
0024 #define CATPT_SHIM_ISD      0x20
0025 #define CATPT_SHIM_IMC      0x28
0026 #define CATPT_SHIM_IMD      0x30
0027 #define CATPT_SHIM_IPCC     0x38
0028 #define CATPT_SHIM_IPCD     0x40
0029 #define CATPT_SHIM_CLKCTL   0x78
0030 #define CATPT_SHIM_CS2      0x80
0031 #define CATPT_SHIM_LTRC     0xE0
0032 #define CATPT_SHIM_HMDC     0xE8
0033
0034 #define CATPT_CS_LPCS       BIT(31)
0035 #define CATPT_CS_SFCR(ssp)  BIT(27 + (ssp))
0036 #define CATPT_CS_S1IOCS     BIT(23)
0037 #define CATPT_CS_S0IOCS     BIT(21)
0038 #define CATPT_CS_PCE        BIT(15)
0039 #define CATPT_CS_SDPM(ssp)  BIT(11 + (ssp))
0040 #define CATPT_CS_STALL      BIT(10)
0041 #define CATPT_CS_DCS        GENMASK(6, 4)
0042 /* b100 DSP core & audio fabric high clock */
0043 #define CATPT_CS_DCS_HIGH   (0x4 << 4)
0044 #define CATPT_CS_SBCS(ssp)  BIT(2 + (ssp))
0045 #define CATPT_CS_RST        BIT(1)
0046
0047 #define CATPT_ISC_IPCDB     BIT(1)
0048 #define CATPT_ISC_IPCCD     BIT(0)
0049 #define CATPT_ISD_DCPWM     BIT(31)
0050 #define CATPT_ISD_IPCCB     BIT(1)
0051 #define CATPT_ISD_IPCDD     BIT(0)
0052
0053 #define CATPT_IMC_IPCDB     BIT(1)
0054 #define CATPT_IMC_IPCCD     BIT(0)
0055 #define CATPT_IMD_IPCCB     BIT(1)
0056 #define CATPT_IMD_IPCDD     BIT(0)
0057
0058 #define CATPT_IPCC_BUSY     BIT(31)
0059 #define CATPT_IPCC_DONE     BIT(30)
0060 #define CATPT_IPCD_BUSY     BIT(31)
0061 #define CATPT_IPCD_DONE     BIT(30)
0062
0063 #define CATPT_CLKCTL_CFCIP  BIT(31)
0064 #define CATPT_CLKCTL_SMOS   GENMASK(25, 24)
0065
0066 #define CATPT_HMDC_HDDA(e, ch)  BIT(8 * (e) + (ch))
0067
0068 /* defaults to reset SHIM registers to after each power cycle */
0069 #define CATPT_CS_DEFAULT    0x8480040E
0070 #define CATPT_ISC_DEFAULT   0x0
0071 #define CATPT_ISD_DEFAULT   0x0
0072 #define CATPT_IMC_DEFAULT   0x7FFF0003
0073 #define CATPT_IMD_DEFAULT   0x7FFF0003
0074 #define CATPT_IPCC_DEFAULT  0x0
0075 #define CATPT_IPCD_DEFAULT  0x0
0076 #define CATPT_CLKCTL_DEFAULT    0x7FF
0077 #define CATPT_CS2_DEFAULT   0x0
0078 #define CATPT_LTRC_DEFAULT  0x0
0079 #define CATPT_HMDC_DEFAULT  0x0
0080
0081 /* PCI Configuration registers */
0082
0083 #define CATPT_PCI_PMCAPID   0x80
0084 #define CATPT_PCI_PMCS      (CATPT_PCI_PMCAPID + PCI_PM_CTRL)
0085 #define CATPT_PCI_VDRTCTL0  0xA0
0086 #define CATPT_PCI_VDRTCTL2  0xA8
0087
0088 #define CATPT_VDRTCTL2_DTCGE    BIT(10)
0089 #define CATPT_VDRTCTL2_DCLCGE   BIT(1)
0090 #define CATPT_VDRTCTL2_CGEALL   0xF7F
0091
0092 /* LPT PCI Configuration bits */
0093
0094 #define LPT_VDRTCTL0_DSRAMPGE(b)    BIT(16 + (b))
0095 #define LPT_VDRTCTL0_DSRAMPGE_MASK  GENMASK(31, 16)
0096 #define LPT_VDRTCTL0_ISRAMPGE(b)    BIT(6 + (b))
0097 #define LPT_VDRTCTL0_ISRAMPGE_MASK  GENMASK(15, 6)
0098 #define LPT_VDRTCTL0_D3SRAMPGD      BIT(2)
0099 #define LPT_VDRTCTL0_D3PGD      BIT(1)
0100 #define LPT_VDRTCTL0_APLLSE     BIT(0)
0101
0102 /* WPT PCI Configuration bits */
0103
0104 #define WPT_VDRTCTL0_DSRAMPGE(b)    BIT(12 + (b))
0105 #define WPT_VDRTCTL0_DSRAMPGE_MASK  GENMASK(31, 12)
0106 #define WPT_VDRTCTL0_ISRAMPGE(b)    BIT(2 + (b))
0107 #define WPT_VDRTCTL0_ISRAMPGE_MASK  GENMASK(11, 2)
0108 #define WPT_VDRTCTL0_D3SRAMPGD      BIT(1)
0109 #define WPT_VDRTCTL0_D3PGD      BIT(0)
0110
0111 #define WPT_VDRTCTL2_APLLSE     BIT(31)
0112
0113 /* defaults to reset SSP registers to after each power cycle */
0114 #define CATPT_SSC0_DEFAULT      0x0
0115 #define CATPT_SSC1_DEFAULT      0x0
0116 #define CATPT_SSS_DEFAULT       0xF004
0117 #define CATPT_SSIT_DEFAULT      0x0
0118 #define CATPT_SSD_DEFAULT       0xC43893A3
0119 #define CATPT_SSTO_DEFAULT      0x0
0120 #define CATPT_SSPSP_DEFAULT     0x0
0121 #define CATPT_SSTSA_DEFAULT     0x0
0122 #define CATPT_SSRSA_DEFAULT     0x0
0123 #define CATPT_SSTSS_DEFAULT     0x0
0124 #define CATPT_SSCR2_DEFAULT     0x0
0125 #define CATPT_SSPSP2_DEFAULT        0x0
0126
0127 /* Physically the same block, access address differs between host and dsp */
0128 #define CATPT_DSP_DRAM_OFFSET       0x400000
0129 #define catpt_to_host_offset(offset)    ((offset) & ~(CATPT_DSP_DRAM_OFFSET))
0130 #define catpt_to_dsp_offset(offset) ((offset) | CATPT_DSP_DRAM_OFFSET)
0131
0132 #define CATPT_MEMBLOCK_SIZE 0x8000
0133 #define catpt_num_dram(cdev)    (hweight_long((cdev)->spec->dram_mask))
0134 #define catpt_num_iram(cdev)    (hweight_long((cdev)->spec->iram_mask))
0135 #define catpt_dram_size(cdev)   (catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE)
0136 #define catpt_iram_size(cdev)   (catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE)
0137
0138 /* registry I/O helpers */
0139
0140 #define catpt_shim_addr(cdev) \
0141     ((cdev)->lpe_ba + (cdev)->spec->host_shim_offset)
0142 #define catpt_dma_addr(cdev, dma) \
0143     ((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma])
0144 #define catpt_ssp_addr(cdev, ssp) \
0145     ((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp])
0146 #define catpt_inbox_addr(cdev) \
0147     ((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset)
0148 #define catpt_outbox_addr(cdev) \
0149     ((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset)
0150
0151 #define catpt_writel_ssp(cdev, ssp, reg, val) \
0152     writel(val, catpt_ssp_addr(cdev, ssp) + (reg))
0153
0154 #define catpt_readl_shim(cdev, reg) \
0155     readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
0156 #define catpt_writel_shim(cdev, reg, val) \
0157     writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg)
0158 #define catpt_updatel_shim(cdev, reg, mask, val) \
0159     catpt_writel_shim(cdev, reg, \
0160               (catpt_readl_shim(cdev, reg) & ~(mask)) | (val))
0161
0162 #define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \
0163     readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_##reg, \
0164                val, cond, delay_us, timeout_us)
0165
0166 #define catpt_readl_pci(cdev, reg) \
0167     readl(cdev->pci_ba + CATPT_PCI_##reg)
0168 #define catpt_writel_pci(cdev, reg, val) \
0169     writel(val, cdev->pci_ba + CATPT_PCI_##reg)
0170 #define catpt_updatel_pci(cdev, reg, mask, val) \
0171     catpt_writel_pci(cdev, reg, \
0172              (catpt_readl_pci(cdev, reg) & ~(mask)) | (val))
0173
0174 #define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \
0175     readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_##reg, \
0176                val, cond, delay_us, timeout_us)
0177
0178 #endif