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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
0004  *                     Cherrytrail and Braswell, with RT5645 codec.
0005  *
0006  *  Copyright (C) 2015 Intel Corp
0007  *  Author: Fang, Yang A <yang.a.fang@intel.com>
0008  *          N,Harshapriya <harshapriya.n@intel.com>
0009  *  This file is modified from cht_bsw_rt5672.c
0010  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0011  *
0012  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/acpi.h>
0018 #include <linux/clk.h>
0019 #include <linux/dmi.h>
0020 #include <linux/slab.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/jack.h>
0025 #include <sound/soc-acpi.h>
0026 #include "../../codecs/rt5645.h"
0027 #include "../atom/sst-atom-controls.h"
0028 #include "../common/soc-intel-quirks.h"
0029 
0030 #define CHT_PLAT_CLK_3_HZ   19200000
0031 #define CHT_CODEC_DAI1  "rt5645-aif1"
0032 #define CHT_CODEC_DAI2  "rt5645-aif2"
0033 
0034 struct cht_acpi_card {
0035     char *codec_id;
0036     int codec_type;
0037     struct snd_soc_card *soc_card;
0038 };
0039 
0040 struct cht_mc_private {
0041     struct snd_soc_jack jack;
0042     struct cht_acpi_card *acpi_card;
0043     char codec_name[SND_ACPI_I2C_ID_LEN];
0044     struct clk *mclk;
0045 };
0046 
0047 #define CHT_RT5645_MAP(quirk)   ((quirk) & GENMASK(7, 0))
0048 #define CHT_RT5645_SSP2_AIF2     BIT(16) /* default is using AIF1  */
0049 #define CHT_RT5645_SSP0_AIF1     BIT(17)
0050 #define CHT_RT5645_SSP0_AIF2     BIT(18)
0051 #define CHT_RT5645_PMC_PLT_CLK_0 BIT(19)
0052 
0053 static unsigned long cht_rt5645_quirk = 0;
0054 
0055 static void log_quirks(struct device *dev)
0056 {
0057     if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2)
0058         dev_info(dev, "quirk SSP2_AIF2 enabled");
0059     if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1)
0060         dev_info(dev, "quirk SSP0_AIF1 enabled");
0061     if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)
0062         dev_info(dev, "quirk SSP0_AIF2 enabled");
0063     if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0)
0064         dev_info(dev, "quirk PMC_PLT_CLK_0 enabled");
0065 }
0066 
0067 static int platform_clock_control(struct snd_soc_dapm_widget *w,
0068         struct snd_kcontrol *k, int  event)
0069 {
0070     struct snd_soc_dapm_context *dapm = w->dapm;
0071     struct snd_soc_card *card = dapm->card;
0072     struct snd_soc_dai *codec_dai;
0073     struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
0074     int ret;
0075 
0076     codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI1);
0077     if (!codec_dai)
0078         codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI2);
0079 
0080     if (!codec_dai) {
0081         dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
0082         return -EIO;
0083     }
0084 
0085     if (SND_SOC_DAPM_EVENT_ON(event)) {
0086         ret = clk_prepare_enable(ctx->mclk);
0087         if (ret < 0) {
0088             dev_err(card->dev,
0089                 "could not configure MCLK state");
0090             return ret;
0091         }
0092     } else {
0093         /* Set codec sysclk source to its internal clock because codec PLL will
0094          * be off when idle and MCLK will also be off when codec is
0095          * runtime suspended. Codec needs clock for jack detection and button
0096          * press. MCLK is turned off with clock framework or ACPI.
0097          */
0098         ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK,
0099                     48000 * 512, SND_SOC_CLOCK_IN);
0100         if (ret < 0) {
0101             dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
0102             return ret;
0103         }
0104 
0105         clk_disable_unprepare(ctx->mclk);
0106     }
0107 
0108     return 0;
0109 }
0110 
0111 static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
0112     SND_SOC_DAPM_HP("Headphone", NULL),
0113     SND_SOC_DAPM_MIC("Headset Mic", NULL),
0114     SND_SOC_DAPM_MIC("Int Mic", NULL),
0115     SND_SOC_DAPM_MIC("Int Analog Mic", NULL),
0116     SND_SOC_DAPM_SPK("Ext Spk", NULL),
0117     SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
0118             platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0119 };
0120 
0121 static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
0122     {"IN1P", NULL, "Headset Mic"},
0123     {"IN1N", NULL, "Headset Mic"},
0124     {"DMIC L1", NULL, "Int Mic"},
0125     {"DMIC R1", NULL, "Int Mic"},
0126     {"IN2P", NULL, "Int Analog Mic"},
0127     {"IN2N", NULL, "Int Analog Mic"},
0128     {"Headphone", NULL, "HPOL"},
0129     {"Headphone", NULL, "HPOR"},
0130     {"Ext Spk", NULL, "SPOL"},
0131     {"Ext Spk", NULL, "SPOR"},
0132     {"Headphone", NULL, "Platform Clock"},
0133     {"Headset Mic", NULL, "Platform Clock"},
0134     {"Int Mic", NULL, "Platform Clock"},
0135     {"Int Analog Mic", NULL, "Platform Clock"},
0136     {"Int Analog Mic", NULL, "micbias1"},
0137     {"Int Analog Mic", NULL, "micbias2"},
0138     {"Ext Spk", NULL, "Platform Clock"},
0139 };
0140 
0141 static const struct snd_soc_dapm_route cht_rt5650_audio_map[] = {
0142     {"IN1P", NULL, "Headset Mic"},
0143     {"IN1N", NULL, "Headset Mic"},
0144     {"DMIC L2", NULL, "Int Mic"},
0145     {"DMIC R2", NULL, "Int Mic"},
0146     {"Headphone", NULL, "HPOL"},
0147     {"Headphone", NULL, "HPOR"},
0148     {"Ext Spk", NULL, "SPOL"},
0149     {"Ext Spk", NULL, "SPOR"},
0150     {"Headphone", NULL, "Platform Clock"},
0151     {"Headset Mic", NULL, "Platform Clock"},
0152     {"Int Mic", NULL, "Platform Clock"},
0153     {"Ext Spk", NULL, "Platform Clock"},
0154 };
0155 
0156 static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif1_map[] = {
0157     {"AIF1 Playback", NULL, "ssp2 Tx"},
0158     {"ssp2 Tx", NULL, "codec_out0"},
0159     {"ssp2 Tx", NULL, "codec_out1"},
0160     {"codec_in0", NULL, "ssp2 Rx" },
0161     {"codec_in1", NULL, "ssp2 Rx" },
0162     {"ssp2 Rx", NULL, "AIF1 Capture"},
0163 };
0164 
0165 static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif2_map[] = {
0166     {"AIF2 Playback", NULL, "ssp2 Tx"},
0167     {"ssp2 Tx", NULL, "codec_out0"},
0168     {"ssp2 Tx", NULL, "codec_out1"},
0169     {"codec_in0", NULL, "ssp2 Rx" },
0170     {"codec_in1", NULL, "ssp2 Rx" },
0171     {"ssp2 Rx", NULL, "AIF2 Capture"},
0172 };
0173 
0174 static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif1_map[] = {
0175     {"AIF1 Playback", NULL, "ssp0 Tx"},
0176     {"ssp0 Tx", NULL, "modem_out"},
0177     {"modem_in", NULL, "ssp0 Rx" },
0178     {"ssp0 Rx", NULL, "AIF1 Capture"},
0179 };
0180 
0181 static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif2_map[] = {
0182     {"AIF2 Playback", NULL, "ssp0 Tx"},
0183     {"ssp0 Tx", NULL, "modem_out"},
0184     {"modem_in", NULL, "ssp0 Rx" },
0185     {"ssp0 Rx", NULL, "AIF2 Capture"},
0186 };
0187 
0188 static const struct snd_kcontrol_new cht_mc_controls[] = {
0189     SOC_DAPM_PIN_SWITCH("Headphone"),
0190     SOC_DAPM_PIN_SWITCH("Headset Mic"),
0191     SOC_DAPM_PIN_SWITCH("Int Mic"),
0192     SOC_DAPM_PIN_SWITCH("Int Analog Mic"),
0193     SOC_DAPM_PIN_SWITCH("Ext Spk"),
0194 };
0195 
0196 static struct snd_soc_jack_pin cht_bsw_jack_pins[] = {
0197     {
0198         .pin    = "Headphone",
0199         .mask   = SND_JACK_HEADPHONE,
0200     },
0201     {
0202         .pin    = "Headset Mic",
0203         .mask   = SND_JACK_MICROPHONE,
0204     },
0205 };
0206 
0207 static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
0208                  struct snd_pcm_hw_params *params)
0209 {
0210     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0211     struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
0212     int ret;
0213 
0214     /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
0215     ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
0216                   CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);
0217     if (ret < 0) {
0218         dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
0219         return ret;
0220     }
0221 
0222     ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
0223                 params_rate(params) * 512, SND_SOC_CLOCK_IN);
0224     if (ret < 0) {
0225         dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
0226         return ret;
0227     }
0228 
0229     return 0;
0230 }
0231 
0232 static int cht_rt5645_quirk_cb(const struct dmi_system_id *id)
0233 {
0234     cht_rt5645_quirk = (unsigned long)id->driver_data;
0235     return 1;
0236 }
0237 
0238 static const struct dmi_system_id cht_rt5645_quirk_table[] = {
0239     {
0240         /* Strago family Chromebooks */
0241         .callback = cht_rt5645_quirk_cb,
0242         .matches = {
0243             DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
0244         },
0245         .driver_data = (void *)CHT_RT5645_PMC_PLT_CLK_0,
0246     },
0247     {
0248     },
0249 };
0250 
0251 static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
0252 {
0253     struct snd_soc_card *card = runtime->card;
0254     struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);
0255     struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
0256     int jack_type;
0257     int ret;
0258 
0259     if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
0260         (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
0261         /* Select clk_i2s2_asrc as ASRC clock source */
0262         rt5645_sel_asrc_clk_src(component,
0263                     RT5645_DA_STEREO_FILTER |
0264                     RT5645_DA_MONO_L_FILTER |
0265                     RT5645_DA_MONO_R_FILTER |
0266                     RT5645_AD_STEREO_FILTER,
0267                     RT5645_CLK_SEL_I2S2_ASRC);
0268     } else {
0269         /* Select clk_i2s1_asrc as ASRC clock source */
0270         rt5645_sel_asrc_clk_src(component,
0271                     RT5645_DA_STEREO_FILTER |
0272                     RT5645_DA_MONO_L_FILTER |
0273                     RT5645_DA_MONO_R_FILTER |
0274                     RT5645_AD_STEREO_FILTER,
0275                     RT5645_CLK_SEL_I2S1_ASRC);
0276     }
0277 
0278     if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) {
0279         ret = snd_soc_dapm_add_routes(&card->dapm,
0280                     cht_rt5645_ssp2_aif2_map,
0281                     ARRAY_SIZE(cht_rt5645_ssp2_aif2_map));
0282     } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) {
0283         ret = snd_soc_dapm_add_routes(&card->dapm,
0284                     cht_rt5645_ssp0_aif1_map,
0285                     ARRAY_SIZE(cht_rt5645_ssp0_aif1_map));
0286     } else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2) {
0287         ret = snd_soc_dapm_add_routes(&card->dapm,
0288                     cht_rt5645_ssp0_aif2_map,
0289                     ARRAY_SIZE(cht_rt5645_ssp0_aif2_map));
0290     } else {
0291         ret = snd_soc_dapm_add_routes(&card->dapm,
0292                     cht_rt5645_ssp2_aif1_map,
0293                     ARRAY_SIZE(cht_rt5645_ssp2_aif1_map));
0294     }
0295     if (ret)
0296         return ret;
0297 
0298     if (ctx->acpi_card->codec_type == CODEC_TYPE_RT5650)
0299         jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
0300                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
0301                     SND_JACK_BTN_2 | SND_JACK_BTN_3;
0302     else
0303         jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE;
0304 
0305     ret = snd_soc_card_jack_new_pins(runtime->card, "Headset", jack_type,
0306                      &ctx->jack, cht_bsw_jack_pins,
0307                      ARRAY_SIZE(cht_bsw_jack_pins));
0308     if (ret) {
0309         dev_err(runtime->dev, "Headset jack creation failed %d\n", ret);
0310         return ret;
0311     }
0312 
0313     rt5645_set_jack_detect(component, &ctx->jack, &ctx->jack, &ctx->jack);
0314 
0315 
0316     /*
0317      * The firmware might enable the clock at
0318      * boot (this information may or may not
0319      * be reflected in the enable clock register).
0320      * To change the rate we must disable the clock
0321      * first to cover these cases. Due to common
0322      * clock framework restrictions that do not allow
0323      * to disable a clock that has not been enabled,
0324      * we need to enable the clock first.
0325      */
0326     ret = clk_prepare_enable(ctx->mclk);
0327     if (!ret)
0328         clk_disable_unprepare(ctx->mclk);
0329 
0330     ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
0331 
0332     if (ret)
0333         dev_err(runtime->dev, "unable to set MCLK rate\n");
0334 
0335     return ret;
0336 }
0337 
0338 static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
0339                 struct snd_pcm_hw_params *params)
0340 {
0341     int ret;
0342     struct snd_interval *rate = hw_param_interval(params,
0343             SNDRV_PCM_HW_PARAM_RATE);
0344     struct snd_interval *channels = hw_param_interval(params,
0345                         SNDRV_PCM_HW_PARAM_CHANNELS);
0346 
0347     /* The DSP will covert the FE rate to 48k, stereo, 24bits */
0348     rate->min = rate->max = 48000;
0349     channels->min = channels->max = 2;
0350 
0351     if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
0352         (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
0353 
0354         /* set SSP0 to 16-bit */
0355         params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
0356 
0357         /*
0358          * Default mode for SSP configuration is TDM 4 slot, override config
0359          * with explicit setting to I2S 2ch 16-bit. The word length is set with
0360          * dai_set_tdm_slot() since there is no other API exposed
0361          */
0362         ret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0),
0363                     SND_SOC_DAIFMT_I2S     |
0364                     SND_SOC_DAIFMT_NB_NF   |
0365                     SND_SOC_DAIFMT_BP_FP
0366             );
0367         if (ret < 0) {
0368             dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
0369             return ret;
0370         }
0371 
0372         ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0),
0373                     SND_SOC_DAIFMT_I2S     |
0374                     SND_SOC_DAIFMT_NB_NF   |
0375                     SND_SOC_DAIFMT_BC_FC
0376             );
0377         if (ret < 0) {
0378             dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
0379             return ret;
0380         }
0381 
0382         ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_cpu(rtd, 0), 0x3, 0x3, 2, 16);
0383         if (ret < 0) {
0384             dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
0385             return ret;
0386         }
0387 
0388     } else {
0389 
0390         /* set SSP2 to 24-bit */
0391         params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
0392 
0393         /*
0394          * Default mode for SSP configuration is TDM 4 slot
0395          */
0396         ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0),
0397                     SND_SOC_DAIFMT_DSP_B |
0398                     SND_SOC_DAIFMT_IB_NF |
0399                     SND_SOC_DAIFMT_BC_FC);
0400         if (ret < 0) {
0401             dev_err(rtd->dev, "can't set format to TDM %d\n", ret);
0402             return ret;
0403         }
0404 
0405         /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */
0406         ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_codec(rtd, 0), 0xF, 0xF, 4, 24);
0407         if (ret < 0) {
0408             dev_err(rtd->dev, "can't set codec TDM slot %d\n", ret);
0409             return ret;
0410         }
0411     }
0412     return 0;
0413 }
0414 
0415 static int cht_aif1_startup(struct snd_pcm_substream *substream)
0416 {
0417     return snd_pcm_hw_constraint_single(substream->runtime,
0418             SNDRV_PCM_HW_PARAM_RATE, 48000);
0419 }
0420 
0421 static const struct snd_soc_ops cht_aif1_ops = {
0422     .startup = cht_aif1_startup,
0423 };
0424 
0425 static const struct snd_soc_ops cht_be_ssp2_ops = {
0426     .hw_params = cht_aif1_hw_params,
0427 };
0428 
0429 SND_SOC_DAILINK_DEF(dummy,
0430     DAILINK_COMP_ARRAY(COMP_DUMMY()));
0431 
0432 SND_SOC_DAILINK_DEF(media,
0433     DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
0434 
0435 SND_SOC_DAILINK_DEF(deepbuffer,
0436     DAILINK_COMP_ARRAY(COMP_CPU("deepbuffer-cpu-dai")));
0437 
0438 SND_SOC_DAILINK_DEF(ssp2_port,
0439     DAILINK_COMP_ARRAY(COMP_CPU("ssp2-port")));
0440 SND_SOC_DAILINK_DEF(ssp2_codec,
0441     DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5645:00", "rt5645-aif1")));
0442 
0443 SND_SOC_DAILINK_DEF(platform,
0444     DAILINK_COMP_ARRAY(COMP_PLATFORM("sst-mfld-platform")));
0445 
0446 static struct snd_soc_dai_link cht_dailink[] = {
0447     [MERR_DPCM_AUDIO] = {
0448         .name = "Audio Port",
0449         .stream_name = "Audio",
0450         .nonatomic = true,
0451         .dynamic = 1,
0452         .dpcm_playback = 1,
0453         .dpcm_capture = 1,
0454         .ops = &cht_aif1_ops,
0455         SND_SOC_DAILINK_REG(media, dummy, platform),
0456     },
0457     [MERR_DPCM_DEEP_BUFFER] = {
0458         .name = "Deep-Buffer Audio Port",
0459         .stream_name = "Deep-Buffer Audio",
0460         .nonatomic = true,
0461         .dynamic = 1,
0462         .dpcm_playback = 1,
0463         .ops = &cht_aif1_ops,
0464         SND_SOC_DAILINK_REG(deepbuffer, dummy, platform),
0465     },
0466     /* CODEC<->CODEC link */
0467     /* back ends */
0468     {
0469         .name = "SSP2-Codec",
0470         .id = 0,
0471         .no_pcm = 1,
0472         .init = cht_codec_init,
0473         .be_hw_params_fixup = cht_codec_fixup,
0474         .dpcm_playback = 1,
0475         .dpcm_capture = 1,
0476         .ops = &cht_be_ssp2_ops,
0477         SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform),
0478     },
0479 };
0480 
0481 /* use space before codec name to simplify card ID, and simplify driver name */
0482 #define SOF_CARD_RT5645_NAME "bytcht rt5645" /* card name 'sof-bytcht rt5645' */
0483 #define SOF_CARD_RT5650_NAME "bytcht rt5650" /* card name 'sof-bytcht rt5650' */
0484 #define SOF_DRIVER_NAME "SOF"
0485 
0486 #define CARD_RT5645_NAME "chtrt5645"
0487 #define CARD_RT5650_NAME "chtrt5650"
0488 #define DRIVER_NAME NULL /* card name will be used for driver name */
0489 
0490 /* SoC card */
0491 static struct snd_soc_card snd_soc_card_chtrt5645 = {
0492     .owner = THIS_MODULE,
0493     .dai_link = cht_dailink,
0494     .num_links = ARRAY_SIZE(cht_dailink),
0495     .dapm_widgets = cht_dapm_widgets,
0496     .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
0497     .dapm_routes = cht_rt5645_audio_map,
0498     .num_dapm_routes = ARRAY_SIZE(cht_rt5645_audio_map),
0499     .controls = cht_mc_controls,
0500     .num_controls = ARRAY_SIZE(cht_mc_controls),
0501 };
0502 
0503 static struct snd_soc_card snd_soc_card_chtrt5650 = {
0504     .owner = THIS_MODULE,
0505     .dai_link = cht_dailink,
0506     .num_links = ARRAY_SIZE(cht_dailink),
0507     .dapm_widgets = cht_dapm_widgets,
0508     .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
0509     .dapm_routes = cht_rt5650_audio_map,
0510     .num_dapm_routes = ARRAY_SIZE(cht_rt5650_audio_map),
0511     .controls = cht_mc_controls,
0512     .num_controls = ARRAY_SIZE(cht_mc_controls),
0513 };
0514 
0515 static struct cht_acpi_card snd_soc_cards[] = {
0516     {"10EC5640", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
0517     {"10EC5645", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
0518     {"10EC5648", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
0519     {"10EC3270", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
0520     {"10EC5650", CODEC_TYPE_RT5650, &snd_soc_card_chtrt5650},
0521 };
0522 
0523 static char cht_rt5645_codec_name[SND_ACPI_I2C_ID_LEN];
0524 
0525 struct acpi_chan_package {   /* ACPICA seems to require 64 bit integers */
0526     u64 aif_value;       /* 1: AIF1, 2: AIF2 */
0527     u64 mclock_value;    /* usually 25MHz (0x17d7940), ignored */
0528 };
0529 
0530 static int snd_cht_mc_probe(struct platform_device *pdev)
0531 {
0532     struct snd_soc_card *card = snd_soc_cards[0].soc_card;
0533     struct snd_soc_acpi_mach *mach;
0534     const char *platform_name;
0535     struct cht_mc_private *drv;
0536     struct acpi_device *adev;
0537     bool sof_parent;
0538     bool found = false;
0539     bool is_bytcr = false;
0540     int dai_index = 0;
0541     int ret_val = 0;
0542     int i;
0543     const char *mclk_name;
0544 
0545     drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
0546     if (!drv)
0547         return -ENOMEM;
0548 
0549     mach = pdev->dev.platform_data;
0550 
0551     for (i = 0; i < ARRAY_SIZE(snd_soc_cards); i++) {
0552         if (acpi_dev_found(snd_soc_cards[i].codec_id) &&
0553             (!strncmp(snd_soc_cards[i].codec_id, mach->id, 8))) {
0554             dev_dbg(&pdev->dev,
0555                 "found codec %s\n", snd_soc_cards[i].codec_id);
0556             card = snd_soc_cards[i].soc_card;
0557             drv->acpi_card = &snd_soc_cards[i];
0558             found = true;
0559             break;
0560         }
0561     }
0562 
0563     if (!found) {
0564         dev_err(&pdev->dev, "No matching HID found in supported list\n");
0565         return -ENODEV;
0566     }
0567 
0568     card->dev = &pdev->dev;
0569     sprintf(drv->codec_name, "i2c-%s:00", drv->acpi_card->codec_id);
0570 
0571     /* set correct codec name */
0572     for (i = 0; i < ARRAY_SIZE(cht_dailink); i++)
0573         if (!strcmp(card->dai_link[i].codecs->name,
0574                 "i2c-10EC5645:00")) {
0575             card->dai_link[i].codecs->name = drv->codec_name;
0576             dai_index = i;
0577         }
0578 
0579     /* fixup codec name based on HID */
0580     adev = acpi_dev_get_first_match_dev(mach->id, NULL, -1);
0581     if (adev) {
0582         snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name),
0583              "i2c-%s", acpi_dev_name(adev));
0584         put_device(&adev->dev);
0585         cht_dailink[dai_index].codecs->name = cht_rt5645_codec_name;
0586     }
0587 
0588     /*
0589      * swap SSP0 if bytcr is detected
0590      * (will be overridden if DMI quirk is detected)
0591      */
0592     if (soc_intel_is_byt()) {
0593         if (mach->mach_params.acpi_ipc_irq_index == 0)
0594             is_bytcr = true;
0595     }
0596 
0597     if (is_bytcr) {
0598         /*
0599          * Baytrail CR platforms may have CHAN package in BIOS, try
0600          * to find relevant routing quirk based as done on Windows
0601          * platforms. We have to read the information directly from the
0602          * BIOS, at this stage the card is not created and the links
0603          * with the codec driver/pdata are non-existent
0604          */
0605 
0606         struct acpi_chan_package chan_package = { 0 };
0607 
0608         /* format specified: 2 64-bit integers */
0609         struct acpi_buffer format = {sizeof("NN"), "NN"};
0610         struct acpi_buffer state = {0, NULL};
0611         struct snd_soc_acpi_package_context pkg_ctx;
0612         bool pkg_found = false;
0613 
0614         state.length = sizeof(chan_package);
0615         state.pointer = &chan_package;
0616 
0617         pkg_ctx.name = "CHAN";
0618         pkg_ctx.length = 2;
0619         pkg_ctx.format = &format;
0620         pkg_ctx.state = &state;
0621         pkg_ctx.data_valid = false;
0622 
0623         pkg_found = snd_soc_acpi_find_package_from_hid(mach->id,
0624                                    &pkg_ctx);
0625         if (pkg_found) {
0626             if (chan_package.aif_value == 1) {
0627                 dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
0628                 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF1;
0629             } else  if (chan_package.aif_value == 2) {
0630                 dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
0631                 cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
0632             } else {
0633                 dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
0634                 pkg_found = false;
0635             }
0636         }
0637 
0638         if (!pkg_found) {
0639             /* no BIOS indications, assume SSP0-AIF2 connection */
0640             cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
0641         }
0642     }
0643 
0644     /* check quirks before creating card */
0645     dmi_check_system(cht_rt5645_quirk_table);
0646     log_quirks(&pdev->dev);
0647 
0648     if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
0649         (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2))
0650         cht_dailink[dai_index].codecs->dai_name = "rt5645-aif2";
0651 
0652     if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
0653         (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2))
0654         cht_dailink[dai_index].cpus->dai_name = "ssp0-port";
0655 
0656     /* override platform name, if required */
0657     platform_name = mach->mach_params.platform;
0658 
0659     ret_val = snd_soc_fixup_dai_links_platform_name(card,
0660                             platform_name);
0661     if (ret_val)
0662         return ret_val;
0663 
0664     if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0)
0665         mclk_name = "pmc_plt_clk_0";
0666     else
0667         mclk_name = "pmc_plt_clk_3";
0668 
0669     drv->mclk = devm_clk_get(&pdev->dev, mclk_name);
0670     if (IS_ERR(drv->mclk)) {
0671         dev_err(&pdev->dev, "Failed to get MCLK from %s: %ld\n",
0672             mclk_name, PTR_ERR(drv->mclk));
0673         return PTR_ERR(drv->mclk);
0674     }
0675 
0676     snd_soc_card_set_drvdata(card, drv);
0677 
0678     sof_parent = snd_soc_acpi_sof_parent(&pdev->dev);
0679 
0680     /* set card and driver name */
0681     if (sof_parent) {
0682         snd_soc_card_chtrt5645.name = SOF_CARD_RT5645_NAME;
0683         snd_soc_card_chtrt5645.driver_name = SOF_DRIVER_NAME;
0684         snd_soc_card_chtrt5650.name = SOF_CARD_RT5650_NAME;
0685         snd_soc_card_chtrt5650.driver_name = SOF_DRIVER_NAME;
0686     } else {
0687         snd_soc_card_chtrt5645.name = CARD_RT5645_NAME;
0688         snd_soc_card_chtrt5645.driver_name = DRIVER_NAME;
0689         snd_soc_card_chtrt5650.name = CARD_RT5650_NAME;
0690         snd_soc_card_chtrt5650.driver_name = DRIVER_NAME;
0691     }
0692 
0693     /* set pm ops */
0694     if (sof_parent)
0695         pdev->dev.driver->pm = &snd_soc_pm_ops;
0696 
0697     ret_val = devm_snd_soc_register_card(&pdev->dev, card);
0698     if (ret_val) {
0699         dev_err(&pdev->dev,
0700             "snd_soc_register_card failed %d\n", ret_val);
0701         return ret_val;
0702     }
0703     platform_set_drvdata(pdev, card);
0704     return ret_val;
0705 }
0706 
0707 static struct platform_driver snd_cht_mc_driver = {
0708     .driver = {
0709         .name = "cht-bsw-rt5645",
0710     },
0711     .probe = snd_cht_mc_probe,
0712 };
0713 
0714 module_platform_driver(snd_cht_mc_driver)
0715 
0716 MODULE_DESCRIPTION("ASoC Intel(R) Braswell Machine driver");
0717 MODULE_AUTHOR("Fang, Yang A,N,Harshapriya");
0718 MODULE_LICENSE("GPL v2");
0719 MODULE_ALIAS("platform:cht-bsw-rt5645");
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