intel/avs/registers.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
0004  *
0005  * Authors: Cezary Rojewski <cezary.rojewski@intel.com>
0006  *          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
0007  */
0008
0009 #ifndef __SOUND_SOC_INTEL_AVS_REGS_H
0010 #define __SOUND_SOC_INTEL_AVS_REGS_H
0011
0012 #define AZX_PCIREG_PGCTL        0x44
0013 #define AZX_PCIREG_CGCTL        0x48
0014 #define AZX_PGCTL_LSRMD_MASK        BIT(4)
0015 #define AZX_CGCTL_MISCBDCGE_MASK    BIT(6)
0016 #define AZX_VS_EM2_L1SEN        BIT(13)
0017 #define AZX_VS_EM2_DUM          BIT(23)
0018
0019 /* Intel HD Audio General DSP Registers */
0020 #define AVS_ADSP_GEN_BASE       0x0
0021 #define AVS_ADSP_REG_ADSPCS     (AVS_ADSP_GEN_BASE + 0x04)
0022 #define AVS_ADSP_REG_ADSPIC     (AVS_ADSP_GEN_BASE + 0x08)
0023 #define AVS_ADSP_REG_ADSPIS     (AVS_ADSP_GEN_BASE + 0x0C)
0024
0025 #define AVS_ADSP_ADSPIC_IPC     BIT(0)
0026 #define AVS_ADSP_ADSPIC_CLDMA       BIT(1)
0027 #define AVS_ADSP_ADSPIS_IPC     BIT(0)
0028 #define AVS_ADSP_ADSPIS_CLDMA       BIT(1)
0029
0030 #define AVS_ADSPCS_CRST_MASK(cm)    (cm)
0031 #define AVS_ADSPCS_CSTALL_MASK(cm)  ((cm) << 8)
0032 #define AVS_ADSPCS_SPA_MASK(cm)     ((cm) << 16)
0033 #define AVS_ADSPCS_CPA_MASK(cm)     ((cm) << 24)
0034 #define AVS_MAIN_CORE_MASK      BIT(0)
0035
0036 #define AVS_ADSP_HIPCCTL_BUSY       BIT(0)
0037 #define AVS_ADSP_HIPCCTL_DONE       BIT(1)
0038
0039 /* SKL Intel HD Audio Inter-Processor Communication Registers */
0040 #define SKL_ADSP_IPC_BASE       0x40
0041 #define SKL_ADSP_REG_HIPCT      (SKL_ADSP_IPC_BASE + 0x00)
0042 #define SKL_ADSP_REG_HIPCTE     (SKL_ADSP_IPC_BASE + 0x04)
0043 #define SKL_ADSP_REG_HIPCI      (SKL_ADSP_IPC_BASE + 0x08)
0044 #define SKL_ADSP_REG_HIPCIE     (SKL_ADSP_IPC_BASE + 0x0C)
0045 #define SKL_ADSP_REG_HIPCCTL        (SKL_ADSP_IPC_BASE + 0x10)
0046
0047 #define SKL_ADSP_HIPCI_BUSY     BIT(31)
0048 #define SKL_ADSP_HIPCIE_DONE        BIT(30)
0049 #define SKL_ADSP_HIPCT_BUSY     BIT(31)
0050
0051 /* Intel HD Audio SRAM windows base addresses */
0052 #define SKL_ADSP_SRAM_BASE_OFFSET   0x8000
0053 #define SKL_ADSP_SRAM_WINDOW_SIZE   0x2000
0054 #define APL_ADSP_SRAM_BASE_OFFSET   0x80000
0055 #define APL_ADSP_SRAM_WINDOW_SIZE   0x20000
0056
0057 /* Constants used when accessing SRAM, space shared with firmware */
0058 #define AVS_FW_REG_BASE(adev)       ((adev)->spec->sram_base_offset)
0059 #define AVS_FW_REG_STATUS(adev)     (AVS_FW_REG_BASE(adev) + 0x0)
0060 #define AVS_FW_REG_ERROR_CODE(adev) (AVS_FW_REG_BASE(adev) + 0x4)
0061
0062 #define AVS_FW_REGS_SIZE        PAGE_SIZE
0063 #define AVS_FW_REGS_WINDOW      0
0064 /* DSP -> HOST communication window */
0065 #define AVS_UPLINK_WINDOW       AVS_FW_REGS_WINDOW
0066 /* HOST -> DSP communication window */
0067 #define AVS_DOWNLINK_WINDOW     1
0068 #define AVS_DEBUG_WINDOW        2
0069
0070 /* registry I/O helpers */
0071 #define avs_sram_offset(adev, window_idx) \
0072     ((adev)->spec->sram_base_offset + \
0073      (adev)->spec->sram_window_size * (window_idx))
0074
0075 #define avs_sram_addr(adev, window_idx) \
0076     ((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
0077
0078 #define avs_uplink_addr(adev) \
0079     (avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE)
0080 #define avs_downlink_addr(adev) \
0081     avs_sram_addr(adev, AVS_DOWNLINK_WINDOW)
0082
0083 #endif /* __SOUND_SOC_INTEL_AVS_REGS_H */