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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
0004 //
0005 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
0006 //          Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
0007 //
0008 // Special thanks to:
0009 //    Krzysztof Hejmowski <krzysztof.hejmowski@intel.com>
0010 //    Michal Sienkiewicz <michal.sienkiewicz@intel.com>
0011 //    Filip Proborszcz
0012 //
0013 // for sharing Intel AudioDSP expertise and helping shape the very
0014 // foundation of this driver
0015 //
0016 
0017 #include <linux/module.h>
0018 #include <linux/pci.h>
0019 #include <sound/hda_codec.h>
0020 #include <sound/hda_i915.h>
0021 #include <sound/hda_register.h>
0022 #include <sound/hdaudio.h>
0023 #include <sound/hdaudio_ext.h>
0024 #include <sound/intel-dsp-config.h>
0025 #include <sound/intel-nhlt.h>
0026 #include "../../codecs/hda.h"
0027 #include "avs.h"
0028 #include "cldma.h"
0029 
0030 static void
0031 avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
0032 {
0033     struct pci_dev *pci = to_pci_dev(bus->dev);
0034     u32 data;
0035 
0036     pci_read_config_dword(pci, reg, &data);
0037     data &= ~mask;
0038     data |= (value & mask);
0039     pci_write_config_dword(pci, reg, data);
0040 }
0041 
0042 void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
0043 {
0044     u32 value;
0045 
0046     value = enable ? 0 : AZX_PGCTL_LSRMD_MASK;
0047     avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL,
0048                     AZX_PGCTL_LSRMD_MASK, value);
0049 }
0050 
0051 static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
0052 {
0053     u32 value;
0054 
0055     value = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
0056     avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, value);
0057 }
0058 
0059 void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
0060 {
0061     avs_hdac_clock_gating_enable(&adev->base.core, enable);
0062 }
0063 
0064 void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
0065 {
0066     u32 value;
0067 
0068     value = enable ? AZX_VS_EM2_L1SEN : 0;
0069     snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value);
0070 }
0071 
0072 static int avs_hdac_bus_init_streams(struct hdac_bus *bus)
0073 {
0074     unsigned int cp_streams, pb_streams;
0075     unsigned int gcap;
0076 
0077     gcap = snd_hdac_chip_readw(bus, GCAP);
0078     cp_streams = (gcap >> 8) & 0x0F;
0079     pb_streams = (gcap >> 12) & 0x0F;
0080     bus->num_streams = cp_streams + pb_streams;
0081 
0082     snd_hdac_ext_stream_init_all(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
0083     snd_hdac_ext_stream_init_all(bus, cp_streams, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
0084 
0085     return snd_hdac_bus_alloc_stream_pages(bus);
0086 }
0087 
0088 static bool avs_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
0089 {
0090     struct hdac_ext_link *hlink;
0091     bool ret;
0092 
0093     avs_hdac_clock_gating_enable(bus, false);
0094     ret = snd_hdac_bus_init_chip(bus, full_reset);
0095 
0096     /* Reset stream-to-link mapping */
0097     list_for_each_entry(hlink, &bus->hlink_list, list)
0098         writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
0099 
0100     avs_hdac_clock_gating_enable(bus, true);
0101 
0102     /* Set DUM bit to address incorrect position reporting for capture
0103      * streams. In order to do so, CTRL needs to be out of reset state
0104      */
0105     snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
0106 
0107     return ret;
0108 }
0109 
0110 static int probe_codec(struct hdac_bus *bus, int addr)
0111 {
0112     struct hda_codec *codec;
0113     unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
0114                (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
0115     unsigned int res = -1;
0116     int ret;
0117 
0118     mutex_lock(&bus->cmd_mutex);
0119     snd_hdac_bus_send_cmd(bus, cmd);
0120     snd_hdac_bus_get_response(bus, addr, &res);
0121     mutex_unlock(&bus->cmd_mutex);
0122     if (res == -1)
0123         return -EIO;
0124 
0125     dev_dbg(bus->dev, "codec #%d probed OK: 0x%x\n", addr, res);
0126 
0127     codec = snd_hda_codec_device_init(to_hda_bus(bus), addr, "hdaudioB%dD%d", bus->idx, addr);
0128     if (IS_ERR(codec)) {
0129         dev_err(bus->dev, "init codec failed: %ld\n", PTR_ERR(codec));
0130         return PTR_ERR(codec);
0131     }
0132     /*
0133      * Allow avs_core suspend by forcing suspended state on all
0134      * of its codec child devices. Component interested in
0135      * dealing with hda codecs directly takes pm responsibilities
0136      */
0137     pm_runtime_set_suspended(hda_codec_dev(codec));
0138 
0139     /* configure effectively creates new ASoC component */
0140     ret = snd_hda_codec_configure(codec);
0141     if (ret < 0) {
0142         dev_err(bus->dev, "failed to config codec %d\n", ret);
0143         return ret;
0144     }
0145 
0146     return 0;
0147 }
0148 
0149 static void avs_hdac_bus_probe_codecs(struct hdac_bus *bus)
0150 {
0151     int c;
0152 
0153     /* First try to probe all given codec slots */
0154     for (c = 0; c < HDA_MAX_CODECS; c++) {
0155         if (!(bus->codec_mask & BIT(c)))
0156             continue;
0157 
0158         if (!probe_codec(bus, c))
0159             /* success, continue probing */
0160             continue;
0161 
0162         /*
0163          * Some BIOSen give you wrong codec addresses
0164          * that don't exist
0165          */
0166         dev_warn(bus->dev, "Codec #%d probe error; disabling it...\n", c);
0167         bus->codec_mask &= ~BIT(c);
0168         /*
0169          * More badly, accessing to a non-existing
0170          * codec often screws up the controller bus,
0171          * and disturbs the further communications.
0172          * Thus if an error occurs during probing,
0173          * better to reset the controller bus to get
0174          * back to the sanity state.
0175          */
0176         snd_hdac_bus_stop_chip(bus);
0177         avs_hdac_bus_init_chip(bus, true);
0178     }
0179 }
0180 
0181 static void avs_hda_probe_work(struct work_struct *work)
0182 {
0183     struct avs_dev *adev = container_of(work, struct avs_dev, probe_work);
0184     struct hdac_bus *bus = &adev->base.core;
0185     struct hdac_ext_link *hlink;
0186     int ret;
0187 
0188     pm_runtime_set_active(bus->dev); /* clear runtime_error flag */
0189 
0190     ret = snd_hdac_i915_init(bus);
0191     if (ret < 0)
0192         dev_info(bus->dev, "i915 init unsuccessful: %d\n", ret);
0193 
0194     snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
0195     avs_hdac_bus_init_chip(bus, true);
0196     avs_hdac_bus_probe_codecs(bus);
0197     snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
0198 
0199     /* with all codecs probed, links can be powered down */
0200     list_for_each_entry(hlink, &bus->hlink_list, list)
0201         snd_hdac_ext_bus_link_put(bus, hlink);
0202 
0203     snd_hdac_ext_bus_ppcap_enable(bus, true);
0204     snd_hdac_ext_bus_ppcap_int_enable(bus, true);
0205 
0206     ret = avs_dsp_first_boot_firmware(adev);
0207     if (ret < 0)
0208         return;
0209 
0210     adev->nhlt = intel_nhlt_init(adev->dev);
0211     if (!adev->nhlt)
0212         dev_info(bus->dev, "platform has no NHLT\n");
0213 
0214     avs_register_all_boards(adev);
0215 
0216     /* configure PM */
0217     pm_runtime_set_autosuspend_delay(bus->dev, 2000);
0218     pm_runtime_use_autosuspend(bus->dev);
0219     pm_runtime_mark_last_busy(bus->dev);
0220     pm_runtime_put_autosuspend(bus->dev);
0221     pm_runtime_allow(bus->dev);
0222 }
0223 
0224 static void hdac_stream_update_pos(struct hdac_stream *stream, u64 buffer_size)
0225 {
0226     u64 prev_pos, pos, num_bytes;
0227 
0228     div64_u64_rem(stream->curr_pos, buffer_size, &prev_pos);
0229     pos = snd_hdac_stream_get_pos_posbuf(stream);
0230 
0231     if (pos < prev_pos)
0232         num_bytes = (buffer_size - prev_pos) +  pos;
0233     else
0234         num_bytes = pos - prev_pos;
0235 
0236     stream->curr_pos += num_bytes;
0237 }
0238 
0239 /* called from IRQ */
0240 static void hdac_update_stream(struct hdac_bus *bus, struct hdac_stream *stream)
0241 {
0242     if (stream->substream) {
0243         snd_pcm_period_elapsed(stream->substream);
0244     } else if (stream->cstream) {
0245         u64 buffer_size = stream->cstream->runtime->buffer_size;
0246 
0247         hdac_stream_update_pos(stream, buffer_size);
0248         snd_compr_fragment_elapsed(stream->cstream);
0249     }
0250 }
0251 
0252 static irqreturn_t hdac_bus_irq_handler(int irq, void *context)
0253 {
0254     struct hdac_bus *bus = context;
0255     u32 mask, int_enable;
0256     u32 status;
0257     int ret = IRQ_NONE;
0258 
0259     if (!pm_runtime_active(bus->dev))
0260         return ret;
0261 
0262     spin_lock(&bus->reg_lock);
0263 
0264     status = snd_hdac_chip_readl(bus, INTSTS);
0265     if (status == 0 || status == UINT_MAX) {
0266         spin_unlock(&bus->reg_lock);
0267         return ret;
0268     }
0269 
0270     /* clear rirb int */
0271     status = snd_hdac_chip_readb(bus, RIRBSTS);
0272     if (status & RIRB_INT_MASK) {
0273         if (status & RIRB_INT_RESPONSE)
0274             snd_hdac_bus_update_rirb(bus);
0275         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
0276     }
0277 
0278     mask = (0x1 << bus->num_streams) - 1;
0279 
0280     status = snd_hdac_chip_readl(bus, INTSTS);
0281     status &= mask;
0282     if (status) {
0283         /* Disable stream interrupts; Re-enable in bottom half */
0284         int_enable = snd_hdac_chip_readl(bus, INTCTL);
0285         snd_hdac_chip_writel(bus, INTCTL, (int_enable & (~mask)));
0286         ret = IRQ_WAKE_THREAD;
0287     } else {
0288         ret = IRQ_HANDLED;
0289     }
0290 
0291     spin_unlock(&bus->reg_lock);
0292     return ret;
0293 }
0294 
0295 static irqreturn_t hdac_bus_irq_thread(int irq, void *context)
0296 {
0297     struct hdac_bus *bus = context;
0298     u32 status;
0299     u32 int_enable;
0300     u32 mask;
0301     unsigned long flags;
0302 
0303     status = snd_hdac_chip_readl(bus, INTSTS);
0304 
0305     snd_hdac_bus_handle_stream_irq(bus, status, hdac_update_stream);
0306 
0307     /* Re-enable stream interrupts */
0308     mask = (0x1 << bus->num_streams) - 1;
0309     spin_lock_irqsave(&bus->reg_lock, flags);
0310     int_enable = snd_hdac_chip_readl(bus, INTCTL);
0311     snd_hdac_chip_writel(bus, INTCTL, (int_enable | mask));
0312     spin_unlock_irqrestore(&bus->reg_lock, flags);
0313 
0314     return IRQ_HANDLED;
0315 }
0316 
0317 static int avs_hdac_acquire_irq(struct avs_dev *adev)
0318 {
0319     struct hdac_bus *bus = &adev->base.core;
0320     struct pci_dev *pci = to_pci_dev(bus->dev);
0321     int ret;
0322 
0323     /* request one and check that we only got one interrupt */
0324     ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI | PCI_IRQ_LEGACY);
0325     if (ret != 1) {
0326         dev_err(adev->dev, "Failed to allocate IRQ vector: %d\n", ret);
0327         return ret;
0328     }
0329 
0330     ret = pci_request_irq(pci, 0, hdac_bus_irq_handler, hdac_bus_irq_thread, bus,
0331                   KBUILD_MODNAME);
0332     if (ret < 0) {
0333         dev_err(adev->dev, "Failed to request stream IRQ handler: %d\n", ret);
0334         goto free_vector;
0335     }
0336 
0337     ret = pci_request_irq(pci, 0, avs_dsp_irq_handler, avs_dsp_irq_thread, adev,
0338                   KBUILD_MODNAME);
0339     if (ret < 0) {
0340         dev_err(adev->dev, "Failed to request IPC IRQ handler: %d\n", ret);
0341         goto free_stream_irq;
0342     }
0343 
0344     return 0;
0345 
0346 free_stream_irq:
0347     pci_free_irq(pci, 0, bus);
0348 free_vector:
0349     pci_free_irq_vectors(pci);
0350     return ret;
0351 }
0352 
0353 static int avs_bus_init(struct avs_dev *adev, struct pci_dev *pci, const struct pci_device_id *id)
0354 {
0355     struct hda_bus *bus = &adev->base;
0356     struct avs_ipc *ipc;
0357     struct device *dev = &pci->dev;
0358     int ret;
0359 
0360     ret = snd_hdac_ext_bus_init(&bus->core, dev, NULL, &soc_hda_ext_bus_ops);
0361     if (ret < 0)
0362         return ret;
0363 
0364     bus->core.use_posbuf = 1;
0365     bus->core.bdl_pos_adj = 0;
0366     bus->core.sync_write = 1;
0367     bus->pci = pci;
0368     bus->mixer_assigned = -1;
0369     mutex_init(&bus->prepare_mutex);
0370 
0371     ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL);
0372     if (!ipc)
0373         return -ENOMEM;
0374     ret = avs_ipc_init(ipc, dev);
0375     if (ret < 0)
0376         return ret;
0377 
0378     adev->dev = dev;
0379     adev->spec = (const struct avs_spec *)id->driver_data;
0380     adev->ipc = ipc;
0381     adev->hw_cfg.dsp_cores = hweight_long(AVS_MAIN_CORE_MASK);
0382     INIT_WORK(&adev->probe_work, avs_hda_probe_work);
0383     INIT_LIST_HEAD(&adev->comp_list);
0384     INIT_LIST_HEAD(&adev->path_list);
0385     INIT_LIST_HEAD(&adev->fw_list);
0386     init_completion(&adev->fw_ready);
0387     spin_lock_init(&adev->path_list_lock);
0388     mutex_init(&adev->modres_mutex);
0389     mutex_init(&adev->comp_list_mutex);
0390     mutex_init(&adev->path_mutex);
0391 
0392     return 0;
0393 }
0394 
0395 static int avs_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
0396 {
0397     struct hdac_bus *bus;
0398     struct avs_dev *adev;
0399     struct device *dev = &pci->dev;
0400     int ret;
0401 
0402     ret = snd_intel_dsp_driver_probe(pci);
0403     if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_AVS)
0404         return -ENODEV;
0405 
0406     ret = pcim_enable_device(pci);
0407     if (ret < 0)
0408         return ret;
0409 
0410     adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
0411     if (!adev)
0412         return -ENOMEM;
0413     ret = avs_bus_init(adev, pci, id);
0414     if (ret < 0) {
0415         dev_err(dev, "failed to init avs bus: %d\n", ret);
0416         return ret;
0417     }
0418 
0419     ret = pci_request_regions(pci, "AVS HDAudio");
0420     if (ret < 0)
0421         return ret;
0422 
0423     bus = &adev->base.core;
0424     bus->addr = pci_resource_start(pci, 0);
0425     bus->remap_addr = pci_ioremap_bar(pci, 0);
0426     if (!bus->remap_addr) {
0427         dev_err(bus->dev, "ioremap error\n");
0428         ret = -ENXIO;
0429         goto err_remap_bar0;
0430     }
0431 
0432     adev->dsp_ba = pci_ioremap_bar(pci, 4);
0433     if (!adev->dsp_ba) {
0434         dev_err(bus->dev, "ioremap error\n");
0435         ret = -ENXIO;
0436         goto err_remap_bar4;
0437     }
0438 
0439     snd_hdac_bus_parse_capabilities(bus);
0440     if (bus->mlcap)
0441         snd_hdac_ext_bus_get_ml_capabilities(bus);
0442 
0443     if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))
0444         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0445     dma_set_max_seg_size(dev, UINT_MAX);
0446 
0447     ret = avs_hdac_bus_init_streams(bus);
0448     if (ret < 0) {
0449         dev_err(dev, "failed to init streams: %d\n", ret);
0450         goto err_init_streams;
0451     }
0452 
0453     ret = avs_hdac_acquire_irq(adev);
0454     if (ret < 0) {
0455         dev_err(bus->dev, "failed to acquire irq: %d\n", ret);
0456         goto err_acquire_irq;
0457     }
0458 
0459     pci_set_master(pci);
0460     pci_set_drvdata(pci, bus);
0461     device_disable_async_suspend(dev);
0462 
0463     schedule_work(&adev->probe_work);
0464 
0465     return 0;
0466 
0467 err_acquire_irq:
0468     snd_hdac_bus_free_stream_pages(bus);
0469     snd_hdac_stream_free_all(bus);
0470 err_init_streams:
0471     iounmap(adev->dsp_ba);
0472 err_remap_bar4:
0473     iounmap(bus->remap_addr);
0474 err_remap_bar0:
0475     pci_release_regions(pci);
0476     return ret;
0477 }
0478 
0479 static void avs_pci_remove(struct pci_dev *pci)
0480 {
0481     struct hdac_device *hdev, *save;
0482     struct hdac_bus *bus = pci_get_drvdata(pci);
0483     struct avs_dev *adev = hdac_to_avs(bus);
0484 
0485     cancel_work_sync(&adev->probe_work);
0486     avs_ipc_block(adev->ipc);
0487 
0488     avs_unregister_all_boards(adev);
0489 
0490     if (adev->nhlt)
0491         intel_nhlt_free(adev->nhlt);
0492 
0493     if (avs_platattr_test(adev, CLDMA))
0494         hda_cldma_free(&code_loader);
0495 
0496     snd_hdac_stop_streams_and_chip(bus);
0497     avs_dsp_op(adev, int_control, false);
0498     snd_hdac_ext_bus_ppcap_int_enable(bus, false);
0499 
0500     /* it is safe to remove all codecs from the system now */
0501     list_for_each_entry_safe(hdev, save, &bus->codec_list, list)
0502         snd_hda_codec_unregister(hdac_to_hda_codec(hdev));
0503 
0504     snd_hdac_bus_free_stream_pages(bus);
0505     snd_hdac_stream_free_all(bus);
0506     /* reverse ml_capabilities */
0507     snd_hdac_link_free_all(bus);
0508     snd_hdac_ext_bus_exit(bus);
0509 
0510     avs_dsp_core_disable(adev, GENMASK(adev->hw_cfg.dsp_cores - 1, 0));
0511     snd_hdac_ext_bus_ppcap_enable(bus, false);
0512 
0513     /* snd_hdac_stop_streams_and_chip does that already? */
0514     snd_hdac_bus_stop_chip(bus);
0515     snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
0516     if (bus->audio_component)
0517         snd_hdac_i915_exit(bus);
0518 
0519     avs_module_info_free(adev);
0520     pci_free_irq(pci, 0, adev);
0521     pci_free_irq(pci, 0, bus);
0522     pci_free_irq_vectors(pci);
0523     iounmap(bus->remap_addr);
0524     iounmap(adev->dsp_ba);
0525     pci_release_regions(pci);
0526 
0527     /* Firmware is not needed anymore */
0528     avs_release_firmwares(adev);
0529 
0530     /* pm_runtime_forbid() can rpm_resume() which we do not want */
0531     pm_runtime_disable(&pci->dev);
0532     pm_runtime_forbid(&pci->dev);
0533     pm_runtime_enable(&pci->dev);
0534     pm_runtime_get_noresume(&pci->dev);
0535 }
0536 
0537 static int __maybe_unused avs_suspend_common(struct avs_dev *adev)
0538 {
0539     struct hdac_bus *bus = &adev->base.core;
0540     int ret;
0541 
0542     flush_work(&adev->probe_work);
0543 
0544     snd_hdac_ext_bus_link_power_down_all(bus);
0545 
0546     ret = avs_ipc_set_dx(adev, AVS_MAIN_CORE_MASK, false);
0547     /*
0548      * pm_runtime is blocked on DSP failure but system-wide suspend is not.
0549      * Do not block entire system from suspending if that's the case.
0550      */
0551     if (ret && ret != -EPERM) {
0552         dev_err(adev->dev, "set dx failed: %d\n", ret);
0553         return AVS_IPC_RET(ret);
0554     }
0555 
0556     avs_ipc_block(adev->ipc);
0557     avs_dsp_op(adev, int_control, false);
0558     snd_hdac_ext_bus_ppcap_int_enable(bus, false);
0559 
0560     ret = avs_dsp_core_disable(adev, AVS_MAIN_CORE_MASK);
0561     if (ret < 0) {
0562         dev_err(adev->dev, "core_mask %ld disable failed: %d\n", AVS_MAIN_CORE_MASK, ret);
0563         return ret;
0564     }
0565 
0566     snd_hdac_ext_bus_ppcap_enable(bus, false);
0567     /* disable LP SRAM retention */
0568     avs_hda_power_gating_enable(adev, false);
0569     snd_hdac_bus_stop_chip(bus);
0570     /* disable CG when putting controller to reset */
0571     avs_hdac_clock_gating_enable(bus, false);
0572     snd_hdac_bus_enter_link_reset(bus);
0573     avs_hdac_clock_gating_enable(bus, true);
0574 
0575     snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
0576 
0577     return 0;
0578 }
0579 
0580 static int __maybe_unused avs_resume_common(struct avs_dev *adev, bool purge)
0581 {
0582     struct hdac_bus *bus = &adev->base.core;
0583     struct hdac_ext_link *hlink;
0584     int ret;
0585 
0586     snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
0587     avs_hdac_bus_init_chip(bus, true);
0588 
0589     snd_hdac_ext_bus_ppcap_enable(bus, true);
0590     snd_hdac_ext_bus_ppcap_int_enable(bus, true);
0591 
0592     ret = avs_dsp_boot_firmware(adev, purge);
0593     if (ret < 0) {
0594         dev_err(adev->dev, "firmware boot failed: %d\n", ret);
0595         return ret;
0596     }
0597 
0598     /* turn off the links that were off before suspend */
0599     list_for_each_entry(hlink, &bus->hlink_list, list) {
0600         if (!hlink->ref_count)
0601             snd_hdac_ext_bus_link_power_down(hlink);
0602     }
0603 
0604     /* check dma status and clean up CORB/RIRB buffers */
0605     if (!bus->cmd_dma_state)
0606         snd_hdac_bus_stop_cmd_io(bus);
0607 
0608     return 0;
0609 }
0610 
0611 static int __maybe_unused avs_suspend(struct device *dev)
0612 {
0613     return avs_suspend_common(to_avs_dev(dev));
0614 }
0615 
0616 static int __maybe_unused avs_resume(struct device *dev)
0617 {
0618     return avs_resume_common(to_avs_dev(dev), true);
0619 }
0620 
0621 static int __maybe_unused avs_runtime_suspend(struct device *dev)
0622 {
0623     return avs_suspend_common(to_avs_dev(dev));
0624 }
0625 
0626 static int __maybe_unused avs_runtime_resume(struct device *dev)
0627 {
0628     return avs_resume_common(to_avs_dev(dev), true);
0629 }
0630 
0631 static const struct dev_pm_ops avs_dev_pm = {
0632     SET_SYSTEM_SLEEP_PM_OPS(avs_suspend, avs_resume)
0633     SET_RUNTIME_PM_OPS(avs_runtime_suspend, avs_runtime_resume, NULL)
0634 };
0635 
0636 static const struct avs_spec skl_desc = {
0637     .name = "skl",
0638     .min_fw_version = {
0639         .major = 9,
0640         .minor = 21,
0641         .hotfix = 0,
0642         .build = 4732,
0643     },
0644     .dsp_ops = &skl_dsp_ops,
0645     .core_init_mask = 1,
0646     .attributes = AVS_PLATATTR_CLDMA,
0647     .sram_base_offset = SKL_ADSP_SRAM_BASE_OFFSET,
0648     .sram_window_size = SKL_ADSP_SRAM_WINDOW_SIZE,
0649     .rom_status = SKL_ADSP_SRAM_BASE_OFFSET,
0650 };
0651 
0652 static const struct avs_spec apl_desc = {
0653     .name = "apl",
0654     .min_fw_version = {
0655         .major = 9,
0656         .minor = 22,
0657         .hotfix = 1,
0658         .build = 4323,
0659     },
0660     .dsp_ops = &apl_dsp_ops,
0661     .core_init_mask = 3,
0662     .attributes = AVS_PLATATTR_IMR,
0663     .sram_base_offset = APL_ADSP_SRAM_BASE_OFFSET,
0664     .sram_window_size = APL_ADSP_SRAM_WINDOW_SIZE,
0665     .rom_status = APL_ADSP_SRAM_BASE_OFFSET,
0666 };
0667 
0668 static const struct pci_device_id avs_ids[] = {
0669     { PCI_VDEVICE(INTEL, 0x9d70), (unsigned long)&skl_desc }, /* SKL */
0670     { PCI_VDEVICE(INTEL, 0x9d71), (unsigned long)&skl_desc }, /* KBL */
0671     { PCI_VDEVICE(INTEL, 0x5a98), (unsigned long)&apl_desc }, /* APL */
0672     { PCI_VDEVICE(INTEL, 0x3198), (unsigned long)&apl_desc }, /* GML */
0673     { 0 }
0674 };
0675 MODULE_DEVICE_TABLE(pci, avs_ids);
0676 
0677 static struct pci_driver avs_pci_driver = {
0678     .name = KBUILD_MODNAME,
0679     .id_table = avs_ids,
0680     .probe = avs_pci_probe,
0681     .remove = avs_pci_remove,
0682     .driver = {
0683         .pm = &avs_dev_pm,
0684     },
0685 };
0686 module_pci_driver(avs_pci_driver);
0687 
0688 MODULE_AUTHOR("Cezary Rojewski <cezary.rojewski@intel.com>");
0689 MODULE_AUTHOR("Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>");
0690 MODULE_DESCRIPTION("Intel cAVS sound driver");
0691 MODULE_LICENSE("GPL");
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