soc/img/img-parallel-out.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * IMG parallel output controller driver
0004  *
0005  * Copyright (C) 2015 Imagination Technologies Ltd.
0006  *
0007  * Author: Damien Horsley <Damien.Horsley@imgtec.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/reset.h>
0018
0019 #include <sound/core.h>
0020 #include <sound/dmaengine_pcm.h>
0021 #include <sound/initval.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025
0026 #define IMG_PRL_OUT_TX_FIFO     0
0027
0028 #define IMG_PRL_OUT_CTL         0x4
0029 #define IMG_PRL_OUT_CTL_CH_MASK     BIT(4)
0030 #define IMG_PRL_OUT_CTL_PACKH_MASK  BIT(3)
0031 #define IMG_PRL_OUT_CTL_EDGE_MASK   BIT(2)
0032 #define IMG_PRL_OUT_CTL_ME_MASK     BIT(1)
0033 #define IMG_PRL_OUT_CTL_SRST_MASK   BIT(0)
0034
0035 struct img_prl_out {
0036     void __iomem *base;
0037     struct clk *clk_sys;
0038     struct clk *clk_ref;
0039     struct snd_dmaengine_dai_dma_data dma_data;
0040     struct device *dev;
0041     struct reset_control *rst;
0042 };
0043
0044 static int img_prl_out_suspend(struct device *dev)
0045 {
0046     struct img_prl_out *prl = dev_get_drvdata(dev);
0047
0048     clk_disable_unprepare(prl->clk_ref);
0049
0050     return 0;
0051 }
0052
0053 static int img_prl_out_resume(struct device *dev)
0054 {
0055     struct img_prl_out *prl = dev_get_drvdata(dev);
0056     int ret;
0057
0058     ret = clk_prepare_enable(prl->clk_ref);
0059     if (ret) {
0060         dev_err(dev, "clk_enable failed: %d\n", ret);
0061         return ret;
0062     }
0063
0064     return 0;
0065 }
0066
0067 static inline void img_prl_out_writel(struct img_prl_out *prl,
0068                 u32 val, u32 reg)
0069 {
0070     writel(val, prl->base + reg);
0071 }
0072
0073 static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg)
0074 {
0075     return readl(prl->base + reg);
0076 }
0077
0078 static void img_prl_out_reset(struct img_prl_out *prl)
0079 {
0080     u32 ctl;
0081
0082     ctl = img_prl_out_readl(prl, IMG_PRL_OUT_CTL) &
0083             ~IMG_PRL_OUT_CTL_ME_MASK;
0084
0085     reset_control_assert(prl->rst);
0086     reset_control_deassert(prl->rst);
0087
0088     img_prl_out_writel(prl, ctl, IMG_PRL_OUT_CTL);
0089 }
0090
0091 static int img_prl_out_trigger(struct snd_pcm_substream *substream, int cmd,
0092             struct snd_soc_dai *dai)
0093 {
0094     struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
0095     u32 reg;
0096
0097     switch (cmd) {
0098     case SNDRV_PCM_TRIGGER_START:
0099     case SNDRV_PCM_TRIGGER_RESUME:
0100     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0101         reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
0102         reg |= IMG_PRL_OUT_CTL_ME_MASK;
0103         img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
0104         break;
0105     case SNDRV_PCM_TRIGGER_STOP:
0106     case SNDRV_PCM_TRIGGER_SUSPEND:
0107     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0108         img_prl_out_reset(prl);
0109         break;
0110     default:
0111         return -EINVAL;
0112     }
0113
0114     return 0;
0115 }
0116
0117 static int img_prl_out_hw_params(struct snd_pcm_substream *substream,
0118     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0119 {
0120     struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
0121     unsigned int rate, channels;
0122     u32 reg, control_set = 0;
0123
0124     rate = params_rate(params);
0125     channels = params_channels(params);
0126
0127     switch (params_format(params)) {
0128     case SNDRV_PCM_FORMAT_S32_LE:
0129         control_set |= IMG_PRL_OUT_CTL_PACKH_MASK;
0130         break;
0131     case SNDRV_PCM_FORMAT_S24_LE:
0132         break;
0133     default:
0134         return -EINVAL;
0135     }
0136
0137     if (channels != 2)
0138         return -EINVAL;
0139
0140     clk_set_rate(prl->clk_ref, rate * 256);
0141
0142     reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
0143     reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set;
0144     img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
0145
0146     return 0;
0147 }
0148
0149 static int img_prl_out_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0150 {
0151     struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
0152     u32 reg, control_set = 0;
0153     int ret;
0154
0155     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0156     case SND_SOC_DAIFMT_NB_NF:
0157         break;
0158     case SND_SOC_DAIFMT_NB_IF:
0159         control_set |= IMG_PRL_OUT_CTL_EDGE_MASK;
0160         break;
0161     default:
0162         return -EINVAL;
0163     }
0164
0165     ret = pm_runtime_resume_and_get(prl->dev);
0166     if (ret < 0)
0167         return ret;
0168
0169     reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL);
0170     reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set;
0171     img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL);
0172     pm_runtime_put(prl->dev);
0173
0174     return 0;
0175 }
0176
0177 static const struct snd_soc_dai_ops img_prl_out_dai_ops = {
0178     .trigger = img_prl_out_trigger,
0179     .hw_params = img_prl_out_hw_params,
0180     .set_fmt = img_prl_out_set_fmt
0181 };
0182
0183 static int img_prl_out_dai_probe(struct snd_soc_dai *dai)
0184 {
0185     struct img_prl_out *prl = snd_soc_dai_get_drvdata(dai);
0186
0187     snd_soc_dai_init_dma_data(dai, &prl->dma_data, NULL);
0188
0189     return 0;
0190 }
0191
0192 static struct snd_soc_dai_driver img_prl_out_dai = {
0193     .probe = img_prl_out_dai_probe,
0194     .playback = {
0195         .channels_min = 2,
0196         .channels_max = 2,
0197         .rates = SNDRV_PCM_RATE_8000_192000,
0198         .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S24_LE
0199     },
0200     .ops = &img_prl_out_dai_ops
0201 };
0202
0203 static const struct snd_soc_component_driver img_prl_out_component = {
0204     .name = "img-prl-out",
0205     .legacy_dai_naming = 1,
0206 };
0207
0208 static int img_prl_out_probe(struct platform_device *pdev)
0209 {
0210     struct img_prl_out *prl;
0211     struct resource *res;
0212     void __iomem *base;
0213     int ret;
0214     struct device *dev = &pdev->dev;
0215
0216     prl = devm_kzalloc(&pdev->dev, sizeof(*prl), GFP_KERNEL);
0217     if (!prl)
0218         return -ENOMEM;
0219
0220     platform_set_drvdata(pdev, prl);
0221
0222     prl->dev = &pdev->dev;
0223
0224     base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0225     if (IS_ERR(base))
0226         return PTR_ERR(base);
0227
0228     prl->base = base;
0229
0230     prl->rst = devm_reset_control_get_exclusive(&pdev->dev, "rst");
0231     if (IS_ERR(prl->rst))
0232         return dev_err_probe(&pdev->dev, PTR_ERR(prl->rst),
0233                      "No top level reset found\n");
0234
0235     prl->clk_sys = devm_clk_get(&pdev->dev, "sys");
0236     if (IS_ERR(prl->clk_sys))
0237         return dev_err_probe(dev, PTR_ERR(prl->clk_sys),
0238                      "Failed to acquire clock 'sys'\n");
0239
0240     prl->clk_ref = devm_clk_get(&pdev->dev, "ref");
0241     if (IS_ERR(prl->clk_ref))
0242         return dev_err_probe(dev, PTR_ERR(prl->clk_ref),
0243                      "Failed to acquire clock 'ref'\n");
0244
0245     ret = clk_prepare_enable(prl->clk_sys);
0246     if (ret)
0247         return ret;
0248
0249     img_prl_out_writel(prl, IMG_PRL_OUT_CTL_EDGE_MASK, IMG_PRL_OUT_CTL);
0250     img_prl_out_reset(prl);
0251
0252     pm_runtime_enable(&pdev->dev);
0253     if (!pm_runtime_enabled(&pdev->dev)) {
0254         ret = img_prl_out_resume(&pdev->dev);
0255         if (ret)
0256             goto err_pm_disable;
0257     }
0258
0259     prl->dma_data.addr = res->start + IMG_PRL_OUT_TX_FIFO;
0260     prl->dma_data.addr_width = 4;
0261     prl->dma_data.maxburst = 4;
0262
0263     ret = devm_snd_soc_register_component(&pdev->dev,
0264             &img_prl_out_component,
0265             &img_prl_out_dai, 1);
0266     if (ret)
0267         goto err_suspend;
0268
0269     ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
0270     if (ret)
0271         goto err_suspend;
0272
0273     return 0;
0274
0275 err_suspend:
0276     if (!pm_runtime_status_suspended(&pdev->dev))
0277         img_prl_out_suspend(&pdev->dev);
0278 err_pm_disable:
0279     pm_runtime_disable(&pdev->dev);
0280     clk_disable_unprepare(prl->clk_sys);
0281
0282     return ret;
0283 }
0284
0285 static int img_prl_out_dev_remove(struct platform_device *pdev)
0286 {
0287     struct img_prl_out *prl = platform_get_drvdata(pdev);
0288
0289     pm_runtime_disable(&pdev->dev);
0290     if (!pm_runtime_status_suspended(&pdev->dev))
0291         img_prl_out_suspend(&pdev->dev);
0292
0293     clk_disable_unprepare(prl->clk_sys);
0294
0295     return 0;
0296 }
0297
0298 static const struct of_device_id img_prl_out_of_match[] = {
0299     { .compatible = "img,parallel-out" },
0300     {}
0301 };
0302 MODULE_DEVICE_TABLE(of, img_prl_out_of_match);
0303
0304 static const struct dev_pm_ops img_prl_out_pm_ops = {
0305     SET_RUNTIME_PM_OPS(img_prl_out_suspend,
0306                img_prl_out_resume, NULL)
0307 };
0308
0309 static struct platform_driver img_prl_out_driver = {
0310     .driver = {
0311         .name = "img-parallel-out",
0312         .of_match_table = img_prl_out_of_match,
0313         .pm = &img_prl_out_pm_ops
0314     },
0315     .probe = img_prl_out_probe,
0316     .remove = img_prl_out_dev_remove
0317 };
0318 module_platform_driver(img_prl_out_driver);
0319
0320 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
0321 MODULE_DESCRIPTION("IMG Parallel Output Driver");
0322 MODULE_LICENSE("GPL v2");