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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * IMG I2S input controller driver
0004  *
0005  * Copyright (C) 2015 Imagination Technologies Ltd.
0006  *
0007  * Author: Damien Horsley <Damien.Horsley@imgtec.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/reset.h>
0018 
0019 #include <sound/core.h>
0020 #include <sound/dmaengine_pcm.h>
0021 #include <sound/initval.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 
0026 #define IMG_I2S_IN_RX_FIFO          0x0
0027 
0028 #define IMG_I2S_IN_CTL              0x4
0029 #define IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK     0xfffffffc
0030 #define IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT      2
0031 #define IMG_I2S_IN_CTL_16PACK_MASK      BIT(1)
0032 #define IMG_I2S_IN_CTL_ME_MASK          BIT(0)
0033 
0034 #define IMG_I2S_IN_CH_CTL           0x4
0035 #define IMG_I2S_IN_CH_CTL_CCDEL_MASK        0x38000
0036 #define IMG_I2S_IN_CH_CTL_CCDEL_SHIFT       15
0037 #define IMG_I2S_IN_CH_CTL_FEN_MASK      BIT(14)
0038 #define IMG_I2S_IN_CH_CTL_FMODE_MASK        BIT(13)
0039 #define IMG_I2S_IN_CH_CTL_16PACK_MASK       BIT(12)
0040 #define IMG_I2S_IN_CH_CTL_JUST_MASK     BIT(10)
0041 #define IMG_I2S_IN_CH_CTL_PACKH_MASK        BIT(9)
0042 #define IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK    BIT(8)
0043 #define IMG_I2S_IN_CH_CTL_BLKP_MASK     BIT(7)
0044 #define IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK   BIT(6)
0045 #define IMG_I2S_IN_CH_CTL_LRD_MASK      BIT(3)
0046 #define IMG_I2S_IN_CH_CTL_FW_MASK       BIT(2)
0047 #define IMG_I2S_IN_CH_CTL_SW_MASK       BIT(1)
0048 #define IMG_I2S_IN_CH_CTL_ME_MASK       BIT(0)
0049 
0050 #define IMG_I2S_IN_CH_STRIDE            0x20
0051 
0052 struct img_i2s_in {
0053     void __iomem *base;
0054     struct clk *clk_sys;
0055     struct snd_dmaengine_dai_dma_data dma_data;
0056     struct device *dev;
0057     unsigned int max_i2s_chan;
0058     void __iomem *channel_base;
0059     unsigned int active_channels;
0060     struct snd_soc_dai_driver dai_driver;
0061     u32 suspend_ctl;
0062     u32 *suspend_ch_ctl;
0063 };
0064 
0065 static int img_i2s_in_runtime_suspend(struct device *dev)
0066 {
0067     struct img_i2s_in *i2s = dev_get_drvdata(dev);
0068 
0069     clk_disable_unprepare(i2s->clk_sys);
0070 
0071     return 0;
0072 }
0073 
0074 static int img_i2s_in_runtime_resume(struct device *dev)
0075 {
0076     struct img_i2s_in *i2s = dev_get_drvdata(dev);
0077     int ret;
0078 
0079     ret = clk_prepare_enable(i2s->clk_sys);
0080     if (ret) {
0081         dev_err(dev, "Unable to enable sys clock\n");
0082         return ret;
0083     }
0084 
0085     return 0;
0086 }
0087 
0088 static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg)
0089 {
0090     writel(val, i2s->base + reg);
0091 }
0092 
0093 static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg)
0094 {
0095     return readl(i2s->base + reg);
0096 }
0097 
0098 static inline void img_i2s_in_ch_writel(struct img_i2s_in *i2s, u32 chan,
0099                     u32 val, u32 reg)
0100 {
0101     writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
0102 }
0103 
0104 static inline u32 img_i2s_in_ch_readl(struct img_i2s_in *i2s, u32 chan,
0105                     u32 reg)
0106 {
0107     return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg);
0108 }
0109 
0110 static inline void img_i2s_in_ch_disable(struct img_i2s_in *i2s, u32 chan)
0111 {
0112     u32 reg;
0113 
0114     reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
0115     reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK;
0116     img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
0117 }
0118 
0119 static inline void img_i2s_in_ch_enable(struct img_i2s_in *i2s, u32 chan)
0120 {
0121     u32 reg;
0122 
0123     reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL);
0124     reg |= IMG_I2S_IN_CH_CTL_ME_MASK;
0125     img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL);
0126 }
0127 
0128 static inline void img_i2s_in_disable(struct img_i2s_in *i2s)
0129 {
0130     u32 reg;
0131 
0132     reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
0133     reg &= ~IMG_I2S_IN_CTL_ME_MASK;
0134     img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
0135 }
0136 
0137 static inline void img_i2s_in_enable(struct img_i2s_in *i2s)
0138 {
0139     u32 reg;
0140 
0141     reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
0142     reg |= IMG_I2S_IN_CTL_ME_MASK;
0143     img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
0144 }
0145 
0146 static inline void img_i2s_in_flush(struct img_i2s_in *i2s)
0147 {
0148     int i;
0149     u32 reg;
0150 
0151     for (i = 0; i < i2s->active_channels; i++) {
0152         reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
0153         reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
0154         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0155         reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK;
0156         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0157     }
0158 }
0159 
0160 static int img_i2s_in_trigger(struct snd_pcm_substream *substream, int cmd,
0161     struct snd_soc_dai *dai)
0162 {
0163     struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
0164 
0165     switch (cmd) {
0166     case SNDRV_PCM_TRIGGER_START:
0167     case SNDRV_PCM_TRIGGER_RESUME:
0168     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0169         img_i2s_in_enable(i2s);
0170         break;
0171 
0172     case SNDRV_PCM_TRIGGER_STOP:
0173     case SNDRV_PCM_TRIGGER_SUSPEND:
0174     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0175         img_i2s_in_disable(i2s);
0176         break;
0177     default:
0178         return -EINVAL;
0179     }
0180 
0181     return 0;
0182 }
0183 
0184 static int img_i2s_in_check_rate(struct img_i2s_in *i2s,
0185         unsigned int sample_rate, unsigned int frame_size,
0186         unsigned int *bclk_filter_enable,
0187         unsigned int *bclk_filter_value)
0188 {
0189     unsigned int bclk_freq, cur_freq;
0190 
0191     bclk_freq = sample_rate * frame_size;
0192 
0193     cur_freq = clk_get_rate(i2s->clk_sys);
0194 
0195     if (cur_freq >= bclk_freq * 8) {
0196         *bclk_filter_enable = 1;
0197         *bclk_filter_value = 0;
0198     } else if (cur_freq >= bclk_freq * 7) {
0199         *bclk_filter_enable = 1;
0200         *bclk_filter_value = 1;
0201     } else if (cur_freq >= bclk_freq * 6) {
0202         *bclk_filter_enable = 0;
0203         *bclk_filter_value = 0;
0204     } else {
0205         dev_err(i2s->dev,
0206             "Sys clock rate %u insufficient for sample rate %u\n",
0207             cur_freq, sample_rate);
0208         return -EINVAL;
0209     }
0210 
0211     return 0;
0212 }
0213 
0214 static int img_i2s_in_hw_params(struct snd_pcm_substream *substream,
0215     struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0216 {
0217     struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
0218     unsigned int rate, channels, i2s_channels, frame_size;
0219     unsigned int bclk_filter_enable, bclk_filter_value;
0220     int i, ret = 0;
0221     u32 reg, control_mask, chan_control_mask;
0222     u32 control_set = 0, chan_control_set = 0;
0223     snd_pcm_format_t format;
0224 
0225     rate = params_rate(params);
0226     format = params_format(params);
0227     channels = params_channels(params);
0228     i2s_channels = channels / 2;
0229 
0230     switch (format) {
0231     case SNDRV_PCM_FORMAT_S32_LE:
0232         frame_size = 64;
0233         chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
0234         chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
0235         chan_control_set |= IMG_I2S_IN_CH_CTL_PACKH_MASK;
0236         break;
0237     case SNDRV_PCM_FORMAT_S24_LE:
0238         frame_size = 64;
0239         chan_control_set |= IMG_I2S_IN_CH_CTL_SW_MASK;
0240         chan_control_set |= IMG_I2S_IN_CH_CTL_FW_MASK;
0241         break;
0242     case SNDRV_PCM_FORMAT_S16_LE:
0243         frame_size = 32;
0244         control_set |= IMG_I2S_IN_CTL_16PACK_MASK;
0245         chan_control_set |= IMG_I2S_IN_CH_CTL_16PACK_MASK;
0246         break;
0247     default:
0248         return -EINVAL;
0249     }
0250 
0251     if ((channels < 2) ||
0252         (channels > (i2s->max_i2s_chan * 2)) ||
0253         (channels % 2))
0254         return -EINVAL;
0255 
0256     control_set |= ((i2s_channels - 1) << IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT);
0257 
0258     ret = img_i2s_in_check_rate(i2s, rate, frame_size,
0259             &bclk_filter_enable, &bclk_filter_value);
0260     if (ret < 0)
0261         return ret;
0262 
0263     if (bclk_filter_enable)
0264         chan_control_set |= IMG_I2S_IN_CH_CTL_FEN_MASK;
0265 
0266     if (bclk_filter_value)
0267         chan_control_set |= IMG_I2S_IN_CH_CTL_FMODE_MASK;
0268 
0269     control_mask = IMG_I2S_IN_CTL_16PACK_MASK |
0270                IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK;
0271 
0272     chan_control_mask = IMG_I2S_IN_CH_CTL_16PACK_MASK |
0273                 IMG_I2S_IN_CH_CTL_FEN_MASK |
0274                 IMG_I2S_IN_CH_CTL_FMODE_MASK |
0275                 IMG_I2S_IN_CH_CTL_SW_MASK |
0276                 IMG_I2S_IN_CH_CTL_FW_MASK |
0277                 IMG_I2S_IN_CH_CTL_PACKH_MASK;
0278 
0279     reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
0280     reg = (reg & ~control_mask) | control_set;
0281     img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL);
0282 
0283     for (i = 0; i < i2s->active_channels; i++)
0284         img_i2s_in_ch_disable(i2s, i);
0285 
0286     for (i = 0; i < i2s->max_i2s_chan; i++) {
0287         reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
0288         reg = (reg & ~chan_control_mask) | chan_control_set;
0289         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0290     }
0291 
0292     i2s->active_channels = i2s_channels;
0293 
0294     img_i2s_in_flush(i2s);
0295 
0296     for (i = 0; i < i2s->active_channels; i++)
0297         img_i2s_in_ch_enable(i2s, i);
0298 
0299     return 0;
0300 }
0301 
0302 static int img_i2s_in_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0303 {
0304     struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
0305     int i, ret;
0306     u32 chan_control_mask, lrd_set = 0, blkp_set = 0, chan_control_set = 0;
0307     u32 reg;
0308 
0309     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0310     case SND_SOC_DAIFMT_NB_NF:
0311         lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
0312         break;
0313     case SND_SOC_DAIFMT_NB_IF:
0314         break;
0315     case SND_SOC_DAIFMT_IB_NF:
0316         lrd_set |= IMG_I2S_IN_CH_CTL_LRD_MASK;
0317         blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
0318         break;
0319     case SND_SOC_DAIFMT_IB_IF:
0320         blkp_set |= IMG_I2S_IN_CH_CTL_BLKP_MASK;
0321         break;
0322     default:
0323         return -EINVAL;
0324     }
0325 
0326     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0327     case SND_SOC_DAIFMT_I2S:
0328         chan_control_set |= IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
0329         break;
0330     case SND_SOC_DAIFMT_LEFT_J:
0331         break;
0332     default:
0333         return -EINVAL;
0334     }
0335 
0336     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0337     case SND_SOC_DAIFMT_BC_FC:
0338         break;
0339     default:
0340         return -EINVAL;
0341     }
0342 
0343     chan_control_mask = IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK;
0344 
0345     ret = pm_runtime_resume_and_get(i2s->dev);
0346     if (ret < 0)
0347         return ret;
0348 
0349     for (i = 0; i < i2s->active_channels; i++)
0350         img_i2s_in_ch_disable(i2s, i);
0351 
0352     /*
0353      * BLKP and LRD must be set during separate register writes
0354      */
0355     for (i = 0; i < i2s->max_i2s_chan; i++) {
0356         reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
0357         reg = (reg & ~chan_control_mask) | chan_control_set;
0358         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0359         reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set;
0360         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0361         reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set;
0362         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0363     }
0364 
0365     for (i = 0; i < i2s->active_channels; i++)
0366         img_i2s_in_ch_enable(i2s, i);
0367 
0368     pm_runtime_put(i2s->dev);
0369 
0370     return 0;
0371 }
0372 
0373 static const struct snd_soc_dai_ops img_i2s_in_dai_ops = {
0374     .trigger = img_i2s_in_trigger,
0375     .hw_params = img_i2s_in_hw_params,
0376     .set_fmt = img_i2s_in_set_fmt
0377 };
0378 
0379 static int img_i2s_in_dai_probe(struct snd_soc_dai *dai)
0380 {
0381     struct img_i2s_in *i2s = snd_soc_dai_get_drvdata(dai);
0382 
0383     snd_soc_dai_init_dma_data(dai, NULL, &i2s->dma_data);
0384 
0385     return 0;
0386 }
0387 
0388 static const struct snd_soc_component_driver img_i2s_in_component = {
0389     .name = "img-i2s-in",
0390     .legacy_dai_naming = 1,
0391 };
0392 
0393 static int img_i2s_in_dma_prepare_slave_config(struct snd_pcm_substream *st,
0394     struct snd_pcm_hw_params *params, struct dma_slave_config *sc)
0395 {
0396     unsigned int i2s_channels = params_channels(params) / 2;
0397     struct snd_soc_pcm_runtime *rtd = st->private_data;
0398     struct snd_dmaengine_dai_dma_data *dma_data;
0399     int ret;
0400 
0401     dma_data = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), st);
0402 
0403     ret = snd_hwparams_to_dma_slave_config(st, params, sc);
0404     if (ret)
0405         return ret;
0406 
0407     sc->src_addr = dma_data->addr;
0408     sc->src_addr_width = dma_data->addr_width;
0409     sc->src_maxburst = 4 * i2s_channels;
0410 
0411     return 0;
0412 }
0413 
0414 static const struct snd_dmaengine_pcm_config img_i2s_in_dma_config = {
0415     .prepare_slave_config = img_i2s_in_dma_prepare_slave_config
0416 };
0417 
0418 static int img_i2s_in_probe(struct platform_device *pdev)
0419 {
0420     struct img_i2s_in *i2s;
0421     struct resource *res;
0422     void __iomem *base;
0423     int ret, i;
0424     struct reset_control *rst;
0425     unsigned int max_i2s_chan_pow_2;
0426     struct device *dev = &pdev->dev;
0427 
0428     i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
0429     if (!i2s)
0430         return -ENOMEM;
0431 
0432     platform_set_drvdata(pdev, i2s);
0433 
0434     i2s->dev = dev;
0435 
0436     base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0437     if (IS_ERR(base))
0438         return PTR_ERR(base);
0439 
0440     i2s->base = base;
0441 
0442     if (of_property_read_u32(pdev->dev.of_node, "img,i2s-channels",
0443             &i2s->max_i2s_chan)) {
0444         dev_err(dev, "No img,i2s-channels property\n");
0445         return -EINVAL;
0446     }
0447 
0448     max_i2s_chan_pow_2 = 1 << get_count_order(i2s->max_i2s_chan);
0449 
0450     i2s->channel_base = base + (max_i2s_chan_pow_2 * 0x20);
0451 
0452     i2s->clk_sys = devm_clk_get(dev, "sys");
0453     if (IS_ERR(i2s->clk_sys))
0454         return dev_err_probe(dev, PTR_ERR(i2s->clk_sys),
0455                      "Failed to acquire clock 'sys'\n");
0456 
0457     pm_runtime_enable(&pdev->dev);
0458     if (!pm_runtime_enabled(&pdev->dev)) {
0459         ret = img_i2s_in_runtime_resume(&pdev->dev);
0460         if (ret)
0461             goto err_pm_disable;
0462     }
0463     ret = pm_runtime_resume_and_get(&pdev->dev);
0464     if (ret < 0)
0465         goto err_suspend;
0466 
0467     i2s->active_channels = 1;
0468     i2s->dma_data.addr = res->start + IMG_I2S_IN_RX_FIFO;
0469     i2s->dma_data.addr_width = 4;
0470 
0471     i2s->dai_driver.probe = img_i2s_in_dai_probe;
0472     i2s->dai_driver.capture.channels_min = 2;
0473     i2s->dai_driver.capture.channels_max = i2s->max_i2s_chan * 2;
0474     i2s->dai_driver.capture.rates = SNDRV_PCM_RATE_8000_192000;
0475     i2s->dai_driver.capture.formats = SNDRV_PCM_FMTBIT_S32_LE |
0476         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE;
0477     i2s->dai_driver.ops = &img_i2s_in_dai_ops;
0478 
0479     rst = devm_reset_control_get_exclusive(dev, "rst");
0480     if (IS_ERR(rst)) {
0481         if (PTR_ERR(rst) == -EPROBE_DEFER) {
0482             ret = -EPROBE_DEFER;
0483             pm_runtime_put(&pdev->dev);
0484             goto err_suspend;
0485         }
0486 
0487         dev_dbg(dev, "No top level reset found\n");
0488 
0489         img_i2s_in_disable(i2s);
0490 
0491         for (i = 0; i < i2s->max_i2s_chan; i++)
0492             img_i2s_in_ch_disable(i2s, i);
0493     } else {
0494         reset_control_assert(rst);
0495         reset_control_deassert(rst);
0496     }
0497 
0498     img_i2s_in_writel(i2s, 0, IMG_I2S_IN_CTL);
0499 
0500     for (i = 0; i < i2s->max_i2s_chan; i++)
0501         img_i2s_in_ch_writel(i2s, i,
0502             (4 << IMG_I2S_IN_CH_CTL_CCDEL_SHIFT) |
0503             IMG_I2S_IN_CH_CTL_JUST_MASK |
0504             IMG_I2S_IN_CH_CTL_FW_MASK, IMG_I2S_IN_CH_CTL);
0505 
0506     pm_runtime_put(&pdev->dev);
0507 
0508     i2s->suspend_ch_ctl = devm_kcalloc(dev,
0509         i2s->max_i2s_chan, sizeof(*i2s->suspend_ch_ctl), GFP_KERNEL);
0510     if (!i2s->suspend_ch_ctl) {
0511         ret = -ENOMEM;
0512         goto err_suspend;
0513     }
0514 
0515     ret = devm_snd_soc_register_component(dev, &img_i2s_in_component,
0516                         &i2s->dai_driver, 1);
0517     if (ret)
0518         goto err_suspend;
0519 
0520     ret = devm_snd_dmaengine_pcm_register(dev, &img_i2s_in_dma_config, 0);
0521     if (ret)
0522         goto err_suspend;
0523 
0524     return 0;
0525 
0526 err_suspend:
0527     if (!pm_runtime_enabled(&pdev->dev))
0528         img_i2s_in_runtime_suspend(&pdev->dev);
0529 err_pm_disable:
0530     pm_runtime_disable(&pdev->dev);
0531 
0532     return ret;
0533 }
0534 
0535 static int img_i2s_in_dev_remove(struct platform_device *pdev)
0536 {
0537     pm_runtime_disable(&pdev->dev);
0538     if (!pm_runtime_status_suspended(&pdev->dev))
0539         img_i2s_in_runtime_suspend(&pdev->dev);
0540 
0541     return 0;
0542 }
0543 
0544 #ifdef CONFIG_PM_SLEEP
0545 static int img_i2s_in_suspend(struct device *dev)
0546 {
0547     struct img_i2s_in *i2s = dev_get_drvdata(dev);
0548     int i, ret;
0549     u32 reg;
0550 
0551     if (pm_runtime_status_suspended(dev)) {
0552         ret = img_i2s_in_runtime_resume(dev);
0553         if (ret)
0554             return ret;
0555     }
0556 
0557     for (i = 0; i < i2s->max_i2s_chan; i++) {
0558         reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL);
0559         i2s->suspend_ch_ctl[i] = reg;
0560     }
0561 
0562     i2s->suspend_ctl = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL);
0563 
0564     img_i2s_in_runtime_suspend(dev);
0565 
0566     return 0;
0567 }
0568 
0569 static int img_i2s_in_resume(struct device *dev)
0570 {
0571     struct img_i2s_in *i2s = dev_get_drvdata(dev);
0572     int i, ret;
0573     u32 reg;
0574 
0575     ret = img_i2s_in_runtime_resume(dev);
0576     if (ret)
0577         return ret;
0578 
0579     for (i = 0; i < i2s->max_i2s_chan; i++) {
0580         reg = i2s->suspend_ch_ctl[i];
0581         img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL);
0582     }
0583 
0584     img_i2s_in_writel(i2s, i2s->suspend_ctl, IMG_I2S_IN_CTL);
0585 
0586     if (pm_runtime_status_suspended(dev))
0587         img_i2s_in_runtime_suspend(dev);
0588 
0589     return 0;
0590 }
0591 #endif
0592 
0593 static const struct of_device_id img_i2s_in_of_match[] = {
0594     { .compatible = "img,i2s-in" },
0595     {}
0596 };
0597 MODULE_DEVICE_TABLE(of, img_i2s_in_of_match);
0598 
0599 static const struct dev_pm_ops img_i2s_in_pm_ops = {
0600     SET_RUNTIME_PM_OPS(img_i2s_in_runtime_suspend,
0601                img_i2s_in_runtime_resume, NULL)
0602     SET_SYSTEM_SLEEP_PM_OPS(img_i2s_in_suspend, img_i2s_in_resume)
0603 };
0604 
0605 static struct platform_driver img_i2s_in_driver = {
0606     .driver = {
0607         .name = "img-i2s-in",
0608         .of_match_table = img_i2s_in_of_match,
0609         .pm = &img_i2s_in_pm_ops
0610     },
0611     .probe = img_i2s_in_probe,
0612     .remove = img_i2s_in_dev_remove
0613 };
0614 module_platform_driver(img_i2s_in_driver);
0615 
0616 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
0617 MODULE_DESCRIPTION("IMG I2S Input Driver");
0618 MODULE_LICENSE("GPL v2");
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