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0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright 2019 NXP
0003 
0004 #include <linux/bitrev.h>
0005 #include <linux/clk.h>
0006 #include <linux/firmware.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/module.h>
0009 #include <linux/of_platform.h>
0010 #include <linux/pm_runtime.h>
0011 #include <linux/regmap.h>
0012 #include <linux/reset.h>
0013 #include <sound/dmaengine_pcm.h>
0014 #include <sound/pcm_iec958.h>
0015 #include <sound/pcm_params.h>
0016 
0017 #include "fsl_xcvr.h"
0018 #include "imx-pcm.h"
0019 
0020 #define FSL_XCVR_CAPDS_SIZE 256
0021 
0022 struct fsl_xcvr_soc_data {
0023     const char *fw_name;
0024 };
0025 
0026 struct fsl_xcvr {
0027     const struct fsl_xcvr_soc_data *soc_data;
0028     struct platform_device *pdev;
0029     struct regmap *regmap;
0030     struct clk *ipg_clk;
0031     struct clk *pll_ipg_clk;
0032     struct clk *phy_clk;
0033     struct clk *spba_clk;
0034     struct reset_control *reset;
0035     u8 streams;
0036     u32 mode;
0037     u32 arc_mode;
0038     void __iomem *ram_addr;
0039     struct snd_dmaengine_dai_dma_data dma_prms_rx;
0040     struct snd_dmaengine_dai_dma_data dma_prms_tx;
0041     struct snd_aes_iec958 rx_iec958;
0042     struct snd_aes_iec958 tx_iec958;
0043     u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
0044 };
0045 
0046 static const struct fsl_xcvr_pll_conf {
0047     u8 mfi;   /* min=0x18, max=0x38 */
0048     u32 mfn;  /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
0049     u32 mfd;  /* unsigned int */
0050     u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
0051 } fsl_xcvr_pll_cfg[] = {
0052     { .mfi = 54, .mfn = 1,  .mfd = 6,   .fout = 1300000000, }, /* 1.3 GHz */
0053     { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, },  /* 8000 Hz */
0054     { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, },  /* 11025 Hz */
0055     { .mfi = 29, .mfn = 1,  .mfd = 6,   .fout = 700000000, },  /* 700 MHz */
0056 };
0057 
0058 /*
0059  * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
0060  * stream. Todo: to check how this case can be considered below
0061  */
0062 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
0063 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = {
0064     .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
0065     .list = fsl_xcvr_earc_channels,
0066 };
0067 
0068 static const u32 fsl_xcvr_earc_rates[] = {
0069     32000, 44100, 48000, 64000, 88200, 96000,
0070     128000, 176400, 192000, 256000, 352800, 384000,
0071     512000, 705600, 768000, 1024000, 1411200, 1536000,
0072 };
0073 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
0074     .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
0075     .list = fsl_xcvr_earc_rates,
0076 };
0077 
0078 static const u32 fsl_xcvr_spdif_channels[] = { 2, };
0079 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = {
0080     .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
0081     .list = fsl_xcvr_spdif_channels,
0082 };
0083 
0084 static const u32 fsl_xcvr_spdif_rates[] = {
0085     32000, 44100, 48000, 88200, 96000, 176400, 192000,
0086 };
0087 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
0088     .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
0089     .list = fsl_xcvr_spdif_rates,
0090 };
0091 
0092 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol,
0093                  struct snd_ctl_elem_value *ucontrol)
0094 {
0095     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0096     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0097     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0098     unsigned int *item = ucontrol->value.enumerated.item;
0099 
0100     xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]);
0101 
0102     return 0;
0103 }
0104 
0105 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol,
0106                  struct snd_ctl_elem_value *ucontrol)
0107 {
0108     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0109     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0110 
0111     ucontrol->value.enumerated.item[0] = xcvr->arc_mode;
0112 
0113     return 0;
0114 }
0115 
0116 static const u32 fsl_xcvr_phy_arc_cfg[] = {
0117     FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
0118 };
0119 
0120 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", };
0121 static const struct soc_enum fsl_xcvr_arc_mode_enum =
0122     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode);
0123 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl =
0124     SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum,
0125              fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put);
0126 
0127 /* Capabilities data structure, bytes */
0128 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol,
0129                       struct snd_ctl_elem_info *uinfo)
0130 {
0131     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0132     uinfo->count = FSL_XCVR_CAPDS_SIZE;
0133 
0134     return 0;
0135 }
0136 
0137 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol,
0138                   struct snd_ctl_elem_value *ucontrol)
0139 {
0140     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0141     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0142 
0143     memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE);
0144 
0145     return 0;
0146 }
0147 
0148 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol,
0149                   struct snd_ctl_elem_value *ucontrol)
0150 {
0151     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0152     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0153 
0154     memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE);
0155 
0156     return 0;
0157 }
0158 
0159 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = {
0160     .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0161     .name = "Capabilities Data Structure",
0162     .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0163     .info = fsl_xcvr_type_capds_bytes_info,
0164     .get = fsl_xcvr_capds_get,
0165     .put = fsl_xcvr_capds_put,
0166 };
0167 
0168 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name,
0169                  bool active)
0170 {
0171     struct snd_soc_card *card = dai->component->card;
0172     struct snd_kcontrol *kctl;
0173     bool enabled;
0174 
0175     kctl = snd_soc_card_get_kcontrol(card, name);
0176     if (kctl == NULL)
0177         return -ENOENT;
0178 
0179     enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0);
0180     if (active == enabled)
0181         return 0; /* nothing to do */
0182 
0183     if (active)
0184         kctl->vd[0].access |=  SNDRV_CTL_ELEM_ACCESS_WRITE;
0185     else
0186         kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE;
0187 
0188     snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
0189 
0190     return 1;
0191 }
0192 
0193 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol,
0194                  struct snd_ctl_elem_value *ucontrol)
0195 {
0196     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0197     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0198     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0199     unsigned int *item = ucontrol->value.enumerated.item;
0200     struct snd_soc_card *card = dai->component->card;
0201     struct snd_soc_pcm_runtime *rtd;
0202 
0203     xcvr->mode = snd_soc_enum_item_to_val(e, item[0]);
0204 
0205     fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
0206                   (xcvr->mode == FSL_XCVR_MODE_ARC));
0207     fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
0208                   (xcvr->mode == FSL_XCVR_MODE_EARC));
0209     /* Allow playback for SPDIF only */
0210     rtd = snd_soc_get_pcm_runtime(card, card->dai_link);
0211     rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count =
0212         (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0);
0213     return 0;
0214 }
0215 
0216 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol,
0217                  struct snd_ctl_elem_value *ucontrol)
0218 {
0219     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0220     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0221 
0222     ucontrol->value.enumerated.item[0] = xcvr->mode;
0223 
0224     return 0;
0225 }
0226 
0227 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", };
0228 static const struct soc_enum fsl_xcvr_mode_enum =
0229     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode);
0230 static struct snd_kcontrol_new fsl_xcvr_mode_kctl =
0231     SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
0232              fsl_xcvr_mode_get, fsl_xcvr_mode_put);
0233 
0234 /** phy: true => phy, false => pll */
0235 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
0236 {
0237     struct device *dev = &xcvr->pdev->dev;
0238     u32 val, idx, tidx;
0239     int ret;
0240 
0241     idx  = BIT(phy ? 26 : 24);
0242     tidx = BIT(phy ? 27 : 25);
0243 
0244     regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
0245     regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
0246     regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
0247     regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
0248 
0249     ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val,
0250                        (val & idx) == ((val & tidx) >> 1),
0251                        10, 10000);
0252     if (ret)
0253         dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n",
0254             phy ? "PHY" : "PLL", reg, data);
0255     return ret;
0256 }
0257 
0258 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
0259 {
0260     struct device *dev = &xcvr->pdev->dev;
0261     u32 i, div = 0, log2;
0262     int ret;
0263 
0264     for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
0265         if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
0266             div = fsl_xcvr_pll_cfg[i].fout / freq;
0267             break;
0268         }
0269     }
0270 
0271     if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg))
0272         return -EINVAL;
0273 
0274     log2 = ilog2(div);
0275 
0276     /* Release AI interface from reset */
0277     ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
0278                FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
0279     if (ret < 0) {
0280         dev_err(dev, "Error while setting IER0: %d\n", ret);
0281         return ret;
0282     }
0283 
0284     /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */
0285     fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET,
0286               FSL_XCVR_PLL_BANDGAP_EN_VBG, 0);
0287 
0288     /* PLL: CTRL0: DIV_INTEGER */
0289     fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0);
0290     /* PLL: NUMERATOR: MFN */
0291     fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0);
0292     /* PLL: DENOMINATOR: MFD */
0293     fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0);
0294     /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */
0295     fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
0296               FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0);
0297     udelay(25);
0298     /* PLL: CTRL0: Clear Hold Ring Off */
0299     fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR,
0300               FSL_XCVR_PLL_CTRL0_HROFF, 0);
0301     udelay(100);
0302     if (tx) { /* TX is enabled for SPDIF only */
0303         /* PLL: POSTDIV: PDIV0 */
0304         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
0305                   FSL_XCVR_PLL_PDIVx(log2, 0), 0);
0306         /* PLL: CTRL_SET: CLKMUX0_EN */
0307         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
0308                   FSL_XCVR_PLL_CTRL0_CM0_EN, 0);
0309     } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */
0310         /* PLL: POSTDIV: PDIV1 */
0311         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
0312                   FSL_XCVR_PLL_PDIVx(log2, 1), 0);
0313         /* PLL: CTRL_SET: CLKMUX1_EN */
0314         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
0315                   FSL_XCVR_PLL_CTRL0_CM1_EN, 0);
0316     } else { /* SPDIF / ARC RX */
0317         /* PLL: POSTDIV: PDIV2 */
0318         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV,
0319                   FSL_XCVR_PLL_PDIVx(log2, 2), 0);
0320         /* PLL: CTRL_SET: CLKMUX2_EN */
0321         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET,
0322                   FSL_XCVR_PLL_CTRL0_CM2_EN, 0);
0323     }
0324 
0325     if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
0326         /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
0327         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
0328                   FSL_XCVR_PHY_CTRL_TSDIFF_OE |
0329                   FSL_XCVR_PHY_CTRL_PHY_EN, 1);
0330         /* PHY: CTRL2_SET: EARC_TX_MODE */
0331         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
0332                   FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
0333     } else if (!tx) { /* SPDIF / ARC RX mode */
0334         if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
0335             /* PHY: CTRL_SET: SPDIF_EN */
0336             fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
0337                       FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
0338         else    /* PHY: CTRL_SET: ARC RX setup */
0339             fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
0340                       FSL_XCVR_PHY_CTRL_PHY_EN |
0341                       FSL_XCVR_PHY_CTRL_RX_CM_EN |
0342                       fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1);
0343     }
0344 
0345     dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n",
0346         freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi,
0347         fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2);
0348     return 0;
0349 }
0350 
0351 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
0352 {
0353     struct device *dev = &xcvr->pdev->dev;
0354     int ret;
0355 
0356     clk_disable_unprepare(xcvr->phy_clk);
0357     ret = clk_set_rate(xcvr->phy_clk, freq);
0358     if (ret < 0) {
0359         dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
0360         return ret;
0361     }
0362     ret = clk_prepare_enable(xcvr->phy_clk);
0363     if (ret) {
0364         dev_err(dev, "failed to start PHY clock: %d\n", ret);
0365         return ret;
0366     }
0367 
0368     /* Release AI interface from reset */
0369     ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
0370                FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
0371     if (ret < 0) {
0372         dev_err(dev, "Error while setting IER0: %d\n", ret);
0373         return ret;
0374     }
0375 
0376     if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
0377         /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
0378         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
0379                   FSL_XCVR_PHY_CTRL_TSDIFF_OE |
0380                   FSL_XCVR_PHY_CTRL_PHY_EN, 1);
0381         /* PHY: CTRL2_SET: EARC_TX_MODE */
0382         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET,
0383                   FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1);
0384     } else { /* SPDIF mode */
0385         /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
0386         fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET,
0387                   FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
0388                   FSL_XCVR_PHY_CTRL_SPDIF_EN, 1);
0389     }
0390 
0391     dev_dbg(dev, "PLL Fexp: %u\n", freq);
0392 
0393     return 0;
0394 }
0395 
0396 #define FSL_XCVR_SPDIF_RX_FREQ  175000000
0397 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
0398                 struct snd_soc_dai *dai)
0399 {
0400     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0401     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0402     u32 m_ctl = 0, v_ctl = 0;
0403     u32 r = substream->runtime->rate, ch = substream->runtime->channels;
0404     u32 fout = 32 * r * ch * 10 * 2;
0405     int ret = 0;
0406 
0407     switch (xcvr->mode) {
0408     case FSL_XCVR_MODE_SPDIF:
0409     case FSL_XCVR_MODE_ARC:
0410         if (tx) {
0411             ret = fsl_xcvr_en_aud_pll(xcvr, fout);
0412             if (ret < 0) {
0413                 dev_err(dai->dev, "Failed to set TX freq %u: %d\n",
0414                     fout, ret);
0415                 return ret;
0416             }
0417 
0418             ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
0419                        FSL_XCVR_TX_DPTH_CTRL_FRM_FMT);
0420             if (ret < 0) {
0421                 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret);
0422                 return ret;
0423             }
0424 
0425             /**
0426              * set SPDIF MODE - this flag is used to gate
0427              * SPDIF output, useless for SPDIF RX
0428              */
0429             m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
0430             v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
0431         } else {
0432             /**
0433              * Clear RX FIFO, flip RX FIFO bits,
0434              * disable eARC related HW mode detects
0435              */
0436             ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
0437                        FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
0438                        FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO |
0439                        FSL_XCVR_RX_DPTH_CTRL_COMP |
0440                        FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
0441             if (ret < 0) {
0442                 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
0443                 return ret;
0444             }
0445 
0446             ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx);
0447             if (ret < 0) {
0448                 dev_err(dai->dev, "Failed to set RX freq %u: %d\n",
0449                     FSL_XCVR_SPDIF_RX_FREQ, ret);
0450                 return ret;
0451             }
0452         }
0453         break;
0454     case FSL_XCVR_MODE_EARC:
0455         if (!tx) {
0456             /** Clear RX FIFO, flip RX FIFO bits */
0457             ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET,
0458                        FSL_XCVR_RX_DPTH_CTRL_STORE_FMT |
0459                        FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO);
0460             if (ret < 0) {
0461                 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret);
0462                 return ret;
0463             }
0464 
0465             /** Enable eARC related HW mode detects */
0466             ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR,
0467                        FSL_XCVR_RX_DPTH_CTRL_COMP |
0468                        FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL);
0469             if (ret < 0) {
0470                 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret);
0471                 return ret;
0472             }
0473         }
0474 
0475         /* clear CMDC RESET */
0476         m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
0477         /* set TX_RX_MODE */
0478         m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE;
0479         v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0);
0480         break;
0481     }
0482 
0483     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
0484                  FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL);
0485     if (ret < 0) {
0486         dev_err(dai->dev, "Error while setting IER0: %d\n", ret);
0487         return ret;
0488     }
0489 
0490     /* set DPATH RESET */
0491     m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
0492     v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx);
0493     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl);
0494     if (ret < 0) {
0495         dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret);
0496         return ret;
0497     }
0498 
0499     return 0;
0500 }
0501 
0502 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream,
0503                const struct snd_pcm_hw_constraint_list *channels,
0504                const struct snd_pcm_hw_constraint_list *rates)
0505 {
0506     struct snd_pcm_runtime *rt = substream->runtime;
0507     int ret;
0508 
0509     ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
0510                      channels);
0511     if (ret < 0)
0512         return ret;
0513 
0514     ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE,
0515                      rates);
0516     if (ret < 0)
0517         return ret;
0518 
0519     return 0;
0520 }
0521 
0522 static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
0523                 struct snd_soc_dai *dai)
0524 {
0525     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0526     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0527     int ret = 0;
0528 
0529     if (xcvr->streams & BIT(substream->stream)) {
0530         dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R");
0531         return -EBUSY;
0532     }
0533 
0534     switch (xcvr->mode) {
0535     case FSL_XCVR_MODE_SPDIF:
0536     case FSL_XCVR_MODE_ARC:
0537         ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr,
0538                       &fsl_xcvr_spdif_rates_constr);
0539         break;
0540     case FSL_XCVR_MODE_EARC:
0541         ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr,
0542                       &fsl_xcvr_earc_rates_constr);
0543         break;
0544     }
0545     if (ret < 0)
0546         return ret;
0547 
0548     xcvr->streams |= BIT(substream->stream);
0549 
0550     /* Disable XCVR controls if there is stream started */
0551     fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
0552     fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
0553     fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
0554 
0555     return 0;
0556 }
0557 
0558 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
0559                   struct snd_soc_dai *dai)
0560 {
0561     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0562     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0563     u32 mask = 0, val = 0;
0564     int ret;
0565 
0566     xcvr->streams &= ~BIT(substream->stream);
0567 
0568     /* Enable XCVR controls if there is no stream started */
0569     if (!xcvr->streams) {
0570         fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
0571         fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
0572                       (xcvr->mode == FSL_XCVR_MODE_ARC));
0573         fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
0574                       (xcvr->mode == FSL_XCVR_MODE_EARC));
0575 
0576         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
0577                      FSL_XCVR_IRQ_EARC_ALL, 0);
0578         if (ret < 0) {
0579             dev_err(dai->dev, "Failed to set IER0: %d\n", ret);
0580             return;
0581         }
0582 
0583         /* clear SPDIF MODE */
0584         if (xcvr->mode == FSL_XCVR_MODE_SPDIF)
0585             mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE;
0586     }
0587 
0588     if (xcvr->mode == FSL_XCVR_MODE_EARC) {
0589         /* set CMDC RESET */
0590         mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
0591         val  |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx);
0592     }
0593 
0594     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
0595     if (ret < 0) {
0596         dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret);
0597         return;
0598     }
0599 }
0600 
0601 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
0602                 struct snd_soc_dai *dai)
0603 {
0604     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0605     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0606     int ret;
0607 
0608     switch (cmd) {
0609     case SNDRV_PCM_TRIGGER_START:
0610     case SNDRV_PCM_TRIGGER_RESUME:
0611     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0612         if (tx) {
0613             switch (xcvr->mode) {
0614             case FSL_XCVR_MODE_EARC:
0615                 /* set isr_cmdc_tx_en, w1c */
0616                 ret = regmap_write(xcvr->regmap,
0617                            FSL_XCVR_ISR_SET,
0618                            FSL_XCVR_ISR_CMDC_TX_EN);
0619                 if (ret < 0) {
0620                     dev_err(dai->dev, "err updating isr %d\n", ret);
0621                     return ret;
0622                 }
0623                 fallthrough;
0624             case FSL_XCVR_MODE_SPDIF:
0625                 ret = regmap_write(xcvr->regmap,
0626                      FSL_XCVR_TX_DPTH_CTRL_SET,
0627                      FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
0628                 if (ret < 0) {
0629                     dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret);
0630                     return ret;
0631                 }
0632                 break;
0633             }
0634         }
0635 
0636         /* enable DMA RD/WR */
0637         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
0638                      FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0);
0639         if (ret < 0) {
0640             dev_err(dai->dev, "Failed to enable DMA: %d\n", ret);
0641             return ret;
0642         }
0643 
0644         /* clear DPATH RESET */
0645         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
0646                      FSL_XCVR_EXT_CTRL_DPTH_RESET(tx),
0647                      0);
0648         if (ret < 0) {
0649             dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret);
0650             return ret;
0651         }
0652 
0653         break;
0654     case SNDRV_PCM_TRIGGER_STOP:
0655     case SNDRV_PCM_TRIGGER_SUSPEND:
0656     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0657         /* disable DMA RD/WR */
0658         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
0659                      FSL_XCVR_EXT_CTRL_DMA_DIS(tx),
0660                      FSL_XCVR_EXT_CTRL_DMA_DIS(tx));
0661         if (ret < 0) {
0662             dev_err(dai->dev, "Failed to disable DMA: %d\n", ret);
0663             return ret;
0664         }
0665 
0666         if (tx) {
0667             switch (xcvr->mode) {
0668             case FSL_XCVR_MODE_SPDIF:
0669                 ret = regmap_write(xcvr->regmap,
0670                      FSL_XCVR_TX_DPTH_CTRL_CLR,
0671                      FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX);
0672                 if (ret < 0) {
0673                     dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
0674                     return ret;
0675                 }
0676                 fallthrough;
0677             case FSL_XCVR_MODE_EARC:
0678                 /* clear ISR_CMDC_TX_EN, W1C */
0679                 ret = regmap_write(xcvr->regmap,
0680                            FSL_XCVR_ISR_CLR,
0681                            FSL_XCVR_ISR_CMDC_TX_EN);
0682                 if (ret < 0) {
0683                     dev_err(dai->dev,
0684                         "Err updating ISR %d\n", ret);
0685                     return ret;
0686                 }
0687                 break;
0688             }
0689         }
0690         break;
0691     default:
0692         return -EINVAL;
0693     }
0694 
0695     return 0;
0696 }
0697 
0698 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr)
0699 {
0700     struct device *dev = &xcvr->pdev->dev;
0701     const struct firmware *fw;
0702     int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET;
0703     u32 mask, val;
0704 
0705     ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev);
0706     if (ret) {
0707         dev_err(dev, "failed to request firmware.\n");
0708         return ret;
0709     }
0710 
0711     rem = fw->size;
0712 
0713     /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */
0714     if (rem > 16384) {
0715         dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem);
0716         release_firmware(fw);
0717         return -ENOMEM;
0718     }
0719 
0720     for (page = 0; page < 10; page++) {
0721         ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
0722                      FSL_XCVR_EXT_CTRL_PAGE_MASK,
0723                      FSL_XCVR_EXT_CTRL_PAGE(page));
0724         if (ret < 0) {
0725             dev_err(dev, "FW: failed to set page %d, err=%d\n",
0726                 page, ret);
0727             goto err_firmware;
0728         }
0729 
0730         off = page * size;
0731         out = min(rem, size);
0732         /* IPG clock is assumed to be running, otherwise it will hang */
0733         if (out > 0) {
0734             /* write firmware into code memory */
0735             memcpy_toio(xcvr->ram_addr, fw->data + off, out);
0736             rem -= out;
0737             if (rem == 0) {
0738                 /* last part of firmware written */
0739                 /* clean remaining part of code memory page */
0740                 memset_io(xcvr->ram_addr + out, 0, size - out);
0741             }
0742         } else {
0743             /* clean current page, including data memory */
0744             memset_io(xcvr->ram_addr, 0, size);
0745         }
0746     }
0747 
0748 err_firmware:
0749     release_firmware(fw);
0750     if (ret < 0)
0751         return ret;
0752 
0753     /* configure watermarks */
0754     mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK;
0755     val  = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX);
0756     val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX);
0757     /* disable DMA RD/WR */
0758     mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
0759     val  |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS;
0760     /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
0761     mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK;
0762     val  |= FSL_XCVR_EXT_CTRL_PAGE(8);
0763 
0764     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val);
0765     if (ret < 0) {
0766         dev_err(dev, "Failed to set watermarks: %d\n", ret);
0767         return ret;
0768     }
0769 
0770     /* Store Capabilities Data Structure into Data RAM */
0771     memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds,
0772             FSL_XCVR_CAPDS_SIZE);
0773     return 0;
0774 }
0775 
0776 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol,
0777                      struct snd_ctl_elem_info *uinfo)
0778 {
0779     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
0780     uinfo->count = 1;
0781 
0782     return 0;
0783 }
0784 
0785 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol,
0786                        struct snd_ctl_elem_info *uinfo)
0787 {
0788     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0789     uinfo->count = sizeof_field(struct snd_aes_iec958, status);
0790 
0791     return 0;
0792 }
0793 
0794 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol,
0795                   struct snd_ctl_elem_value *ucontrol)
0796 {
0797     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0798     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0799 
0800     memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24);
0801 
0802     return 0;
0803 }
0804 
0805 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol,
0806                   struct snd_ctl_elem_value *ucontrol)
0807 {
0808     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0809     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0810 
0811     memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24);
0812 
0813     return 0;
0814 }
0815 
0816 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol,
0817                   struct snd_ctl_elem_value *ucontrol)
0818 {
0819     struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
0820     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0821 
0822     memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24);
0823 
0824     return 0;
0825 }
0826 
0827 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = {
0828     /* Channel status controller */
0829     {
0830         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0831         .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
0832         .access = SNDRV_CTL_ELEM_ACCESS_READ,
0833         .info = fsl_xcvr_type_iec958_info,
0834         .get = fsl_xcvr_rx_cs_get,
0835     },
0836     /* Capture channel status, bytes */
0837     {
0838         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0839         .name = "Capture Channel Status",
0840         .access = SNDRV_CTL_ELEM_ACCESS_READ,
0841         .info = fsl_xcvr_type_iec958_bytes_info,
0842         .get = fsl_xcvr_rx_cs_get,
0843     },
0844 };
0845 
0846 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = {
0847     /* Channel status controller */
0848     {
0849         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0850         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
0851         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0852         .info = fsl_xcvr_type_iec958_info,
0853         .get = fsl_xcvr_tx_cs_get,
0854         .put = fsl_xcvr_tx_cs_put,
0855     },
0856     /* Playback channel status, bytes */
0857     {
0858         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
0859         .name = "Playback Channel Status",
0860         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
0861         .info = fsl_xcvr_type_iec958_bytes_info,
0862         .get = fsl_xcvr_tx_cs_get,
0863         .put = fsl_xcvr_tx_cs_put,
0864     },
0865 };
0866 
0867 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = {
0868     .prepare = fsl_xcvr_prepare,
0869     .startup = fsl_xcvr_startup,
0870     .shutdown = fsl_xcvr_shutdown,
0871     .trigger = fsl_xcvr_trigger,
0872 };
0873 
0874 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
0875 {
0876     struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai);
0877 
0878     snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
0879 
0880     snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
0881     snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
0882     snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
0883     snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
0884                  ARRAY_SIZE(fsl_xcvr_tx_ctls));
0885     snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
0886                  ARRAY_SIZE(fsl_xcvr_rx_ctls));
0887     return 0;
0888 }
0889 
0890 static struct snd_soc_dai_driver fsl_xcvr_dai = {
0891     .probe  = fsl_xcvr_dai_probe,
0892     .ops = &fsl_xcvr_dai_ops,
0893     .playback = {
0894         .stream_name = "CPU-Playback",
0895         .channels_min = 1,
0896         .channels_max = 32,
0897         .rate_min = 32000,
0898         .rate_max = 1536000,
0899         .rates = SNDRV_PCM_RATE_KNOT,
0900         .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
0901     },
0902     .capture = {
0903         .stream_name = "CPU-Capture",
0904         .channels_min = 1,
0905         .channels_max = 32,
0906         .rate_min = 32000,
0907         .rate_max = 1536000,
0908         .rates = SNDRV_PCM_RATE_KNOT,
0909         .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
0910     },
0911 };
0912 
0913 static const struct snd_soc_component_driver fsl_xcvr_comp = {
0914     .name           = "fsl-xcvr-dai",
0915     .legacy_dai_naming  = 1,
0916 };
0917 
0918 static const struct reg_default fsl_xcvr_reg_defaults[] = {
0919     { FSL_XCVR_VERSION, 0x00000000 },
0920     { FSL_XCVR_EXT_CTRL,    0xF8204040 },
0921     { FSL_XCVR_EXT_STATUS,  0x00000000 },
0922     { FSL_XCVR_EXT_IER0,    0x00000000 },
0923     { FSL_XCVR_EXT_IER1,    0x00000000 },
0924     { FSL_XCVR_EXT_ISR, 0x00000000 },
0925     { FSL_XCVR_EXT_ISR_SET, 0x00000000 },
0926     { FSL_XCVR_EXT_ISR_CLR, 0x00000000 },
0927     { FSL_XCVR_EXT_ISR_TOG, 0x00000000 },
0928     { FSL_XCVR_IER,     0x00000000 },
0929     { FSL_XCVR_ISR,     0x00000000 },
0930     { FSL_XCVR_ISR_SET, 0x00000000 },
0931     { FSL_XCVR_ISR_CLR, 0x00000000 },
0932     { FSL_XCVR_ISR_TOG, 0x00000000 },
0933     { FSL_XCVR_RX_DPTH_CTRL,    0x00002C89 },
0934     { FSL_XCVR_RX_DPTH_CTRL_SET,    0x00002C89 },
0935     { FSL_XCVR_RX_DPTH_CTRL_CLR,    0x00002C89 },
0936     { FSL_XCVR_RX_DPTH_CTRL_TOG,    0x00002C89 },
0937     { FSL_XCVR_TX_DPTH_CTRL,    0x00000000 },
0938     { FSL_XCVR_TX_DPTH_CTRL_SET,    0x00000000 },
0939     { FSL_XCVR_TX_DPTH_CTRL_CLR,    0x00000000 },
0940     { FSL_XCVR_TX_DPTH_CTRL_TOG,    0x00000000 },
0941     { FSL_XCVR_TX_CS_DATA_0,    0x00000000 },
0942     { FSL_XCVR_TX_CS_DATA_1,    0x00000000 },
0943     { FSL_XCVR_TX_CS_DATA_2,    0x00000000 },
0944     { FSL_XCVR_TX_CS_DATA_3,    0x00000000 },
0945     { FSL_XCVR_TX_CS_DATA_4,    0x00000000 },
0946     { FSL_XCVR_TX_CS_DATA_5,    0x00000000 },
0947     { FSL_XCVR_DEBUG_REG_0,     0x00000000 },
0948     { FSL_XCVR_DEBUG_REG_1,     0x00000000 },
0949 };
0950 
0951 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
0952 {
0953     switch (reg) {
0954     case FSL_XCVR_VERSION:
0955     case FSL_XCVR_EXT_CTRL:
0956     case FSL_XCVR_EXT_STATUS:
0957     case FSL_XCVR_EXT_IER0:
0958     case FSL_XCVR_EXT_IER1:
0959     case FSL_XCVR_EXT_ISR:
0960     case FSL_XCVR_EXT_ISR_SET:
0961     case FSL_XCVR_EXT_ISR_CLR:
0962     case FSL_XCVR_EXT_ISR_TOG:
0963     case FSL_XCVR_IER:
0964     case FSL_XCVR_ISR:
0965     case FSL_XCVR_ISR_SET:
0966     case FSL_XCVR_ISR_CLR:
0967     case FSL_XCVR_ISR_TOG:
0968     case FSL_XCVR_PHY_AI_CTRL:
0969     case FSL_XCVR_PHY_AI_CTRL_SET:
0970     case FSL_XCVR_PHY_AI_CTRL_CLR:
0971     case FSL_XCVR_PHY_AI_CTRL_TOG:
0972     case FSL_XCVR_PHY_AI_RDATA:
0973     case FSL_XCVR_CLK_CTRL:
0974     case FSL_XCVR_RX_DPTH_CTRL:
0975     case FSL_XCVR_RX_DPTH_CTRL_SET:
0976     case FSL_XCVR_RX_DPTH_CTRL_CLR:
0977     case FSL_XCVR_RX_DPTH_CTRL_TOG:
0978     case FSL_XCVR_TX_DPTH_CTRL:
0979     case FSL_XCVR_TX_DPTH_CTRL_SET:
0980     case FSL_XCVR_TX_DPTH_CTRL_CLR:
0981     case FSL_XCVR_TX_DPTH_CTRL_TOG:
0982     case FSL_XCVR_TX_CS_DATA_0:
0983     case FSL_XCVR_TX_CS_DATA_1:
0984     case FSL_XCVR_TX_CS_DATA_2:
0985     case FSL_XCVR_TX_CS_DATA_3:
0986     case FSL_XCVR_TX_CS_DATA_4:
0987     case FSL_XCVR_TX_CS_DATA_5:
0988     case FSL_XCVR_DEBUG_REG_0:
0989     case FSL_XCVR_DEBUG_REG_1:
0990         return true;
0991     default:
0992         return false;
0993     }
0994 }
0995 
0996 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
0997 {
0998     switch (reg) {
0999     case FSL_XCVR_EXT_CTRL:
1000     case FSL_XCVR_EXT_IER0:
1001     case FSL_XCVR_EXT_IER1:
1002     case FSL_XCVR_EXT_ISR:
1003     case FSL_XCVR_EXT_ISR_SET:
1004     case FSL_XCVR_EXT_ISR_CLR:
1005     case FSL_XCVR_EXT_ISR_TOG:
1006     case FSL_XCVR_IER:
1007     case FSL_XCVR_ISR_SET:
1008     case FSL_XCVR_ISR_CLR:
1009     case FSL_XCVR_ISR_TOG:
1010     case FSL_XCVR_PHY_AI_CTRL:
1011     case FSL_XCVR_PHY_AI_CTRL_SET:
1012     case FSL_XCVR_PHY_AI_CTRL_CLR:
1013     case FSL_XCVR_PHY_AI_CTRL_TOG:
1014     case FSL_XCVR_PHY_AI_WDATA:
1015     case FSL_XCVR_CLK_CTRL:
1016     case FSL_XCVR_RX_DPTH_CTRL:
1017     case FSL_XCVR_RX_DPTH_CTRL_SET:
1018     case FSL_XCVR_RX_DPTH_CTRL_CLR:
1019     case FSL_XCVR_RX_DPTH_CTRL_TOG:
1020     case FSL_XCVR_TX_DPTH_CTRL_SET:
1021     case FSL_XCVR_TX_DPTH_CTRL_CLR:
1022     case FSL_XCVR_TX_DPTH_CTRL_TOG:
1023     case FSL_XCVR_TX_CS_DATA_0:
1024     case FSL_XCVR_TX_CS_DATA_1:
1025     case FSL_XCVR_TX_CS_DATA_2:
1026     case FSL_XCVR_TX_CS_DATA_3:
1027     case FSL_XCVR_TX_CS_DATA_4:
1028     case FSL_XCVR_TX_CS_DATA_5:
1029         return true;
1030     default:
1031         return false;
1032     }
1033 }
1034 
1035 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1036 {
1037     return fsl_xcvr_readable_reg(dev, reg);
1038 }
1039 
1040 static const struct regmap_config fsl_xcvr_regmap_cfg = {
1041     .reg_bits = 32,
1042     .reg_stride = 4,
1043     .val_bits = 32,
1044     .max_register = FSL_XCVR_MAX_REG,
1045     .reg_defaults = fsl_xcvr_reg_defaults,
1046     .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults),
1047     .readable_reg = fsl_xcvr_readable_reg,
1048     .volatile_reg = fsl_xcvr_volatile_reg,
1049     .writeable_reg = fsl_xcvr_writeable_reg,
1050     .cache_type = REGCACHE_FLAT,
1051 };
1052 
1053 static irqreturn_t irq0_isr(int irq, void *devid)
1054 {
1055     struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid;
1056     struct device *dev = &xcvr->pdev->dev;
1057     struct regmap *regmap = xcvr->regmap;
1058     void __iomem *reg_ctrl, *reg_buff;
1059     u32 isr, isr_clr = 0, val, i;
1060 
1061     regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr);
1062 
1063     if (isr & FSL_XCVR_IRQ_NEW_CS) {
1064         dev_dbg(dev, "Received new CS block\n");
1065         isr_clr |= FSL_XCVR_IRQ_NEW_CS;
1066         /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
1067         regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1068                    FSL_XCVR_EXT_CTRL_PAGE_MASK,
1069                    FSL_XCVR_EXT_CTRL_PAGE(8));
1070 
1071         /* Find updated CS buffer */
1072         reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
1073         reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
1074         memcpy_fromio(&val, reg_ctrl, sizeof(val));
1075         if (!val) {
1076             reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
1077             reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
1078             memcpy_fromio(&val, reg_ctrl, sizeof(val));
1079         }
1080 
1081         if (val) {
1082             /* copy CS buffer */
1083             memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
1084                       sizeof(xcvr->rx_iec958.status));
1085             for (i = 0; i < 6; i++) {
1086                 val = *(u32 *)(xcvr->rx_iec958.status + i*4);
1087                 *(u32 *)(xcvr->rx_iec958.status + i*4) =
1088                     bitrev32(val);
1089             }
1090             /* clear CS control register */
1091             memset_io(reg_ctrl, 0, sizeof(val));
1092         }
1093     }
1094     if (isr & FSL_XCVR_IRQ_NEW_UD) {
1095         dev_dbg(dev, "Received new UD block\n");
1096         isr_clr |= FSL_XCVR_IRQ_NEW_UD;
1097     }
1098     if (isr & FSL_XCVR_IRQ_MUTE) {
1099         dev_dbg(dev, "HW mute bit detected\n");
1100         isr_clr |= FSL_XCVR_IRQ_MUTE;
1101     }
1102     if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) {
1103         dev_dbg(dev, "RX/TX FIFO full/empty\n");
1104         isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR;
1105     }
1106     if (isr & FSL_XCVR_IRQ_ARC_MODE) {
1107         dev_dbg(dev, "CMDC SM falls out of eARC mode\n");
1108         isr_clr |= FSL_XCVR_IRQ_ARC_MODE;
1109     }
1110     if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) {
1111         dev_dbg(dev, "DMA read request\n");
1112         isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ;
1113     }
1114     if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) {
1115         dev_dbg(dev, "DMA write request\n");
1116         isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ;
1117     }
1118 
1119     if (isr_clr) {
1120         regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr);
1121         return IRQ_HANDLED;
1122     }
1123 
1124     return IRQ_NONE;
1125 }
1126 
1127 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
1128     .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1129 };
1130 
1131 static const struct of_device_id fsl_xcvr_dt_ids[] = {
1132     { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1133     { /* sentinel */ }
1134 };
1135 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
1136 
1137 static int fsl_xcvr_probe(struct platform_device *pdev)
1138 {
1139     struct device *dev = &pdev->dev;
1140     struct fsl_xcvr *xcvr;
1141     struct resource *rx_res, *tx_res;
1142     void __iomem *regs;
1143     int ret, irq;
1144 
1145     xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL);
1146     if (!xcvr)
1147         return -ENOMEM;
1148 
1149     xcvr->pdev = pdev;
1150     xcvr->soc_data = of_device_get_match_data(&pdev->dev);
1151 
1152     xcvr->ipg_clk = devm_clk_get(dev, "ipg");
1153     if (IS_ERR(xcvr->ipg_clk)) {
1154         dev_err(dev, "failed to get ipg clock\n");
1155         return PTR_ERR(xcvr->ipg_clk);
1156     }
1157 
1158     xcvr->phy_clk = devm_clk_get(dev, "phy");
1159     if (IS_ERR(xcvr->phy_clk)) {
1160         dev_err(dev, "failed to get phy clock\n");
1161         return PTR_ERR(xcvr->phy_clk);
1162     }
1163 
1164     xcvr->spba_clk = devm_clk_get(dev, "spba");
1165     if (IS_ERR(xcvr->spba_clk)) {
1166         dev_err(dev, "failed to get spba clock\n");
1167         return PTR_ERR(xcvr->spba_clk);
1168     }
1169 
1170     xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg");
1171     if (IS_ERR(xcvr->pll_ipg_clk)) {
1172         dev_err(dev, "failed to get pll_ipg clock\n");
1173         return PTR_ERR(xcvr->pll_ipg_clk);
1174     }
1175 
1176     xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram");
1177     if (IS_ERR(xcvr->ram_addr))
1178         return PTR_ERR(xcvr->ram_addr);
1179 
1180     regs = devm_platform_ioremap_resource_byname(pdev, "regs");
1181     if (IS_ERR(regs))
1182         return PTR_ERR(regs);
1183 
1184     xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs,
1185                          &fsl_xcvr_regmap_cfg);
1186     if (IS_ERR(xcvr->regmap)) {
1187         dev_err(dev, "failed to init XCVR regmap: %ld\n",
1188             PTR_ERR(xcvr->regmap));
1189         return PTR_ERR(xcvr->regmap);
1190     }
1191 
1192     xcvr->reset = devm_reset_control_get_exclusive(dev, NULL);
1193     if (IS_ERR(xcvr->reset)) {
1194         dev_err(dev, "failed to get XCVR reset control\n");
1195         return PTR_ERR(xcvr->reset);
1196     }
1197 
1198     /* get IRQs */
1199     irq = platform_get_irq(pdev, 0);
1200     if (irq < 0)
1201         return irq;
1202 
1203     ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr);
1204     if (ret) {
1205         dev_err(dev, "failed to claim IRQ0: %i\n", ret);
1206         return ret;
1207     }
1208 
1209     rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
1210     tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
1211     if (!rx_res || !tx_res) {
1212         dev_err(dev, "could not find rxfifo or txfifo resource\n");
1213         return -EINVAL;
1214     }
1215     xcvr->dma_prms_rx.chan_name = "rx";
1216     xcvr->dma_prms_tx.chan_name = "tx";
1217     xcvr->dma_prms_rx.addr = rx_res->start;
1218     xcvr->dma_prms_tx.addr = tx_res->start;
1219     xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX;
1220     xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX;
1221 
1222     platform_set_drvdata(pdev, xcvr);
1223     pm_runtime_enable(dev);
1224     regcache_cache_only(xcvr->regmap, true);
1225 
1226     /*
1227      * Register platform component before registering cpu dai for there
1228      * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1229      */
1230     ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
1231     if (ret) {
1232         pm_runtime_disable(dev);
1233         dev_err(dev, "failed to pcm register\n");
1234         return ret;
1235     }
1236 
1237     ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp,
1238                           &fsl_xcvr_dai, 1);
1239     if (ret) {
1240         pm_runtime_disable(dev);
1241         dev_err(dev, "failed to register component %s\n",
1242             fsl_xcvr_comp.name);
1243     }
1244 
1245     return ret;
1246 }
1247 
1248 static int fsl_xcvr_remove(struct platform_device *pdev)
1249 {
1250     pm_runtime_disable(&pdev->dev);
1251     return 0;
1252 }
1253 
1254 static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
1255 {
1256     struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1257     int ret;
1258 
1259     /*
1260      * Clear interrupts, when streams starts or resumes after
1261      * suspend, interrupts are enabled in prepare(), so no need
1262      * to enable interrupts in resume().
1263      */
1264     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
1265                  FSL_XCVR_IRQ_EARC_ALL, 0);
1266     if (ret < 0)
1267         dev_err(dev, "Failed to clear IER0: %d\n", ret);
1268 
1269     /* Assert M0+ reset */
1270     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1271                  FSL_XCVR_EXT_CTRL_CORE_RESET,
1272                  FSL_XCVR_EXT_CTRL_CORE_RESET);
1273     if (ret < 0)
1274         dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
1275 
1276     regcache_cache_only(xcvr->regmap, true);
1277 
1278     clk_disable_unprepare(xcvr->spba_clk);
1279     clk_disable_unprepare(xcvr->phy_clk);
1280     clk_disable_unprepare(xcvr->pll_ipg_clk);
1281     clk_disable_unprepare(xcvr->ipg_clk);
1282 
1283     return 0;
1284 }
1285 
1286 static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
1287 {
1288     struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
1289     int ret;
1290 
1291     ret = reset_control_assert(xcvr->reset);
1292     if (ret < 0) {
1293         dev_err(dev, "Failed to assert M0+ reset: %d\n", ret);
1294         return ret;
1295     }
1296 
1297     ret = clk_prepare_enable(xcvr->ipg_clk);
1298     if (ret) {
1299         dev_err(dev, "failed to start IPG clock.\n");
1300         return ret;
1301     }
1302 
1303     ret = clk_prepare_enable(xcvr->pll_ipg_clk);
1304     if (ret) {
1305         dev_err(dev, "failed to start PLL IPG clock.\n");
1306         goto stop_ipg_clk;
1307     }
1308 
1309     ret = clk_prepare_enable(xcvr->phy_clk);
1310     if (ret) {
1311         dev_err(dev, "failed to start PHY clock: %d\n", ret);
1312         goto stop_pll_ipg_clk;
1313     }
1314 
1315     ret = clk_prepare_enable(xcvr->spba_clk);
1316     if (ret) {
1317         dev_err(dev, "failed to start SPBA clock.\n");
1318         goto stop_phy_clk;
1319     }
1320 
1321     regcache_cache_only(xcvr->regmap, false);
1322     regcache_mark_dirty(xcvr->regmap);
1323     ret = regcache_sync(xcvr->regmap);
1324 
1325     if (ret) {
1326         dev_err(dev, "failed to sync regcache.\n");
1327         goto stop_spba_clk;
1328     }
1329 
1330     ret = reset_control_deassert(xcvr->reset);
1331     if (ret) {
1332         dev_err(dev, "failed to deassert M0+ reset.\n");
1333         goto stop_spba_clk;
1334     }
1335 
1336     ret = fsl_xcvr_load_firmware(xcvr);
1337     if (ret) {
1338         dev_err(dev, "failed to load firmware.\n");
1339         goto stop_spba_clk;
1340     }
1341 
1342     /* Release M0+ reset */
1343     ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
1344                  FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
1345     if (ret < 0) {
1346         dev_err(dev, "M0+ core release failed: %d\n", ret);
1347         goto stop_spba_clk;
1348     }
1349 
1350     /* Let M0+ core complete firmware initialization */
1351     msleep(50);
1352 
1353     return 0;
1354 
1355 stop_spba_clk:
1356     clk_disable_unprepare(xcvr->spba_clk);
1357 stop_phy_clk:
1358     clk_disable_unprepare(xcvr->phy_clk);
1359 stop_pll_ipg_clk:
1360     clk_disable_unprepare(xcvr->pll_ipg_clk);
1361 stop_ipg_clk:
1362     clk_disable_unprepare(xcvr->ipg_clk);
1363 
1364     return ret;
1365 }
1366 
1367 static const struct dev_pm_ops fsl_xcvr_pm_ops = {
1368     SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend,
1369                fsl_xcvr_runtime_resume,
1370                NULL)
1371     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1372                 pm_runtime_force_resume)
1373 };
1374 
1375 static struct platform_driver fsl_xcvr_driver = {
1376     .probe = fsl_xcvr_probe,
1377     .driver = {
1378         .name = "fsl,imx8mp-audio-xcvr",
1379         .pm = &fsl_xcvr_pm_ops,
1380         .of_match_table = fsl_xcvr_dt_ids,
1381     },
1382     .remove = fsl_xcvr_remove,
1383 };
1384 module_platform_driver(fsl_xcvr_driver);
1385 
1386 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
1387 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");
1388 MODULE_LICENSE("GPL v2");
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