soc/fsl/fsl_utils.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Freescale ALSA SoC Machine driver utility
0004 //
0005 // Author: Timur Tabi <timur@freescale.com>
0006 //
0007 // Copyright 2010 Freescale Semiconductor, Inc.
0008
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <sound/soc.h>
0014
0015 #include "fsl_utils.h"
0016
0017 /**
0018  * fsl_asoc_get_dma_channel - determine the dma channel for a SSI node
0019  *
0020  * @ssi_np: pointer to the SSI device tree node
0021  * @name: name of the phandle pointing to the dma channel
0022  * @dai: ASoC DAI link pointer to be filled with platform_name
0023  * @dma_channel_id: dma channel id to be returned
0024  * @dma_id: dma id to be returned
0025  *
0026  * This function determines the dma and channel id for given SSI node.  It
0027  * also discovers the platform_name for the ASoC DAI link.
0028  */
0029 int fsl_asoc_get_dma_channel(struct device_node *ssi_np,
0030                  const char *name,
0031                  struct snd_soc_dai_link *dai,
0032                  unsigned int *dma_channel_id,
0033                  unsigned int *dma_id)
0034 {
0035     struct resource res;
0036     struct device_node *dma_channel_np, *dma_np;
0037     const __be32 *iprop;
0038     int ret;
0039
0040     dma_channel_np = of_parse_phandle(ssi_np, name, 0);
0041     if (!dma_channel_np)
0042         return -EINVAL;
0043
0044     if (!of_device_is_compatible(dma_channel_np, "fsl,ssi-dma-channel")) {
0045         of_node_put(dma_channel_np);
0046         return -EINVAL;
0047     }
0048
0049     /* Determine the dev_name for the device_node.  This code mimics the
0050      * behavior of of_device_make_bus_id(). We need this because ASoC uses
0051      * the dev_name() of the device to match the platform (DMA) device with
0052      * the CPU (SSI) device.  It's all ugly and hackish, but it works (for
0053      * now).
0054      *
0055      * dai->platform name should already point to an allocated buffer.
0056      */
0057     ret = of_address_to_resource(dma_channel_np, 0, &res);
0058     if (ret) {
0059         of_node_put(dma_channel_np);
0060         return ret;
0061     }
0062     snprintf((char *)dai->platforms->name, DAI_NAME_SIZE, "%llx.%pOFn",
0063          (unsigned long long) res.start, dma_channel_np);
0064
0065     iprop = of_get_property(dma_channel_np, "cell-index", NULL);
0066     if (!iprop) {
0067         of_node_put(dma_channel_np);
0068         return -EINVAL;
0069     }
0070     *dma_channel_id = be32_to_cpup(iprop);
0071
0072     dma_np = of_get_parent(dma_channel_np);
0073     iprop = of_get_property(dma_np, "cell-index", NULL);
0074     if (!iprop) {
0075         of_node_put(dma_np);
0076         of_node_put(dma_channel_np);
0077         return -EINVAL;
0078     }
0079     *dma_id = be32_to_cpup(iprop);
0080
0081     of_node_put(dma_np);
0082     of_node_put(dma_channel_np);
0083
0084     return 0;
0085 }
0086 EXPORT_SYMBOL(fsl_asoc_get_dma_channel);
0087
0088 /**
0089  * fsl_asoc_get_pll_clocks - get two PLL clock source
0090  *
0091  * @dev: device pointer
0092  * @pll8k_clk: PLL clock pointer for 8kHz
0093  * @pll11k_clk: PLL clock pointer for 11kHz
0094  *
0095  * This function get two PLL clock source
0096  */
0097 void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
0098                  struct clk **pll11k_clk)
0099 {
0100     *pll8k_clk = devm_clk_get(dev, "pll8k");
0101     if (IS_ERR(*pll8k_clk))
0102         *pll8k_clk = NULL;
0103
0104     *pll11k_clk = devm_clk_get(dev, "pll11k");
0105     if (IS_ERR(*pll11k_clk))
0106         *pll11k_clk = NULL;
0107 }
0108 EXPORT_SYMBOL(fsl_asoc_get_pll_clocks);
0109
0110 /**
0111  * fsl_asoc_reparent_pll_clocks - set clock parent if necessary
0112  *
0113  * @dev: device pointer
0114  * @clk: root clock pointer
0115  * @pll8k_clk: PLL clock pointer for 8kHz
0116  * @pll11k_clk: PLL clock pointer for 11kHz
0117  * @ratio: target requency for root clock
0118  *
0119  * This function set root clock parent according to the target ratio
0120  */
0121 void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
0122                   struct clk *pll8k_clk,
0123                   struct clk *pll11k_clk, u64 ratio)
0124 {
0125     struct clk *p, *pll = NULL, *npll = NULL;
0126     bool reparent = false;
0127     int ret = 0;
0128
0129     if (!clk || !pll8k_clk || !pll11k_clk)
0130         return;
0131
0132     p = clk;
0133     while (p && pll8k_clk && pll11k_clk) {
0134         struct clk *pp = clk_get_parent(p);
0135
0136         if (clk_is_match(pp, pll8k_clk) ||
0137             clk_is_match(pp, pll11k_clk)) {
0138             pll = pp;
0139             break;
0140         }
0141         p = pp;
0142     }
0143
0144     npll = (do_div(ratio, 8000) ? pll11k_clk : pll8k_clk);
0145     reparent = (pll && !clk_is_match(pll, npll));
0146
0147     if (reparent) {
0148         ret = clk_set_parent(p, npll);
0149         if (ret < 0)
0150             dev_warn(dev, "failed to set parent:%d\n", ret);
0151     }
0152 }
0153 EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks);
0154
0155 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
0156 MODULE_DESCRIPTION("Freescale ASoC utility code");
0157 MODULE_LICENSE("GPL v2");