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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
0004 //
0005 // Author: Timur Tabi <timur@freescale.com>
0006 //
0007 // Copyright 2007-2010 Freescale Semiconductor, Inc.
0008 //
0009 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
0010 //
0011 // The i.MX SSI core has some nasty limitations in AC97 mode. While most
0012 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
0013 // one FIFO which combines all valid receive slots. We cannot even select
0014 // which slots we want to receive. The WM9712 with which this driver
0015 // was developed with always sends GPIO status data in slot 12 which
0016 // we receive in our (PCM-) data stream. The only chance we have is to
0017 // manually skip this data in the FIQ handler. With sampling rates different
0018 // from 48000Hz not every frame has valid receive data, so the ratio
0019 // between pcm data and GPIO status data changes. Our FIQ handler is not
0020 // able to handle this, hence this driver only works with 48000Hz sampling
0021 // rate.
0022 // Reading and writing AC97 registers is another challenge. The core
0023 // provides us status bits when the read register is updated with *another*
0024 // value. When we read the same register two times (and the register still
0025 // contains the same value) these status bits are not set. We work
0026 // around this by not polling these bits but only wait a fixed delay.
0027 
0028 #include <linux/init.h>
0029 #include <linux/io.h>
0030 #include <linux/module.h>
0031 #include <linux/interrupt.h>
0032 #include <linux/clk.h>
0033 #include <linux/ctype.h>
0034 #include <linux/device.h>
0035 #include <linux/delay.h>
0036 #include <linux/mutex.h>
0037 #include <linux/slab.h>
0038 #include <linux/spinlock.h>
0039 #include <linux/of.h>
0040 #include <linux/of_address.h>
0041 #include <linux/of_irq.h>
0042 #include <linux/of_platform.h>
0043 #include <linux/dma/imx-dma.h>
0044 
0045 #include <sound/core.h>
0046 #include <sound/pcm.h>
0047 #include <sound/pcm_params.h>
0048 #include <sound/initval.h>
0049 #include <sound/soc.h>
0050 #include <sound/dmaengine_pcm.h>
0051 
0052 #include "fsl_ssi.h"
0053 #include "imx-pcm.h"
0054 
0055 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
0056 #define RX 0
0057 #define TX 1
0058 
0059 /**
0060  * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
0061  *
0062  * The SSI has a limitation in that the samples must be in the same byte
0063  * order as the host CPU.  This is because when multiple bytes are written
0064  * to the STX register, the bytes and bits must be written in the same
0065  * order.  The STX is a shift register, so all the bits need to be aligned
0066  * (bit-endianness must match byte-endianness).  Processors typically write
0067  * the bits within a byte in the same order that the bytes of a word are
0068  * written in.  So if the host CPU is big-endian, then only big-endian
0069  * samples will be written to STX properly.
0070  */
0071 #ifdef __BIG_ENDIAN
0072 #define FSLSSI_I2S_FORMATS \
0073     (SNDRV_PCM_FMTBIT_S8 | \
0074      SNDRV_PCM_FMTBIT_S16_BE | \
0075      SNDRV_PCM_FMTBIT_S18_3BE | \
0076      SNDRV_PCM_FMTBIT_S20_3BE | \
0077      SNDRV_PCM_FMTBIT_S24_3BE | \
0078      SNDRV_PCM_FMTBIT_S24_BE)
0079 #else
0080 #define FSLSSI_I2S_FORMATS \
0081     (SNDRV_PCM_FMTBIT_S8 | \
0082      SNDRV_PCM_FMTBIT_S16_LE | \
0083      SNDRV_PCM_FMTBIT_S18_3LE | \
0084      SNDRV_PCM_FMTBIT_S20_3LE | \
0085      SNDRV_PCM_FMTBIT_S24_3LE | \
0086      SNDRV_PCM_FMTBIT_S24_LE)
0087 #endif
0088 
0089 /*
0090  * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1:
0091  *  - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
0092  *  - Also have NB_NF to mark these two clocks will not be inverted
0093  */
0094 #define FSLSSI_AC97_DAIFMT \
0095     (SND_SOC_DAIFMT_AC97 | \
0096      SND_SOC_DAIFMT_BC_FP | \
0097      SND_SOC_DAIFMT_NB_NF)
0098 
0099 #define FSLSSI_SIER_DBG_RX_FLAGS \
0100     (SSI_SIER_RFF0_EN | \
0101      SSI_SIER_RLS_EN | \
0102      SSI_SIER_RFS_EN | \
0103      SSI_SIER_ROE0_EN | \
0104      SSI_SIER_RFRC_EN)
0105 #define FSLSSI_SIER_DBG_TX_FLAGS \
0106     (SSI_SIER_TFE0_EN | \
0107      SSI_SIER_TLS_EN | \
0108      SSI_SIER_TFS_EN | \
0109      SSI_SIER_TUE0_EN | \
0110      SSI_SIER_TFRC_EN)
0111 
0112 enum fsl_ssi_type {
0113     FSL_SSI_MCP8610,
0114     FSL_SSI_MX21,
0115     FSL_SSI_MX35,
0116     FSL_SSI_MX51,
0117 };
0118 
0119 struct fsl_ssi_regvals {
0120     u32 sier;
0121     u32 srcr;
0122     u32 stcr;
0123     u32 scr;
0124 };
0125 
0126 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
0127 {
0128     switch (reg) {
0129     case REG_SSI_SACCEN:
0130     case REG_SSI_SACCDIS:
0131         return false;
0132     default:
0133         return true;
0134     }
0135 }
0136 
0137 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
0138 {
0139     switch (reg) {
0140     case REG_SSI_STX0:
0141     case REG_SSI_STX1:
0142     case REG_SSI_SRX0:
0143     case REG_SSI_SRX1:
0144     case REG_SSI_SISR:
0145     case REG_SSI_SFCSR:
0146     case REG_SSI_SACNT:
0147     case REG_SSI_SACADD:
0148     case REG_SSI_SACDAT:
0149     case REG_SSI_SATAG:
0150     case REG_SSI_SACCST:
0151     case REG_SSI_SOR:
0152         return true;
0153     default:
0154         return false;
0155     }
0156 }
0157 
0158 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
0159 {
0160     switch (reg) {
0161     case REG_SSI_SRX0:
0162     case REG_SSI_SRX1:
0163     case REG_SSI_SISR:
0164     case REG_SSI_SACADD:
0165     case REG_SSI_SACDAT:
0166     case REG_SSI_SATAG:
0167         return true;
0168     default:
0169         return false;
0170     }
0171 }
0172 
0173 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
0174 {
0175     switch (reg) {
0176     case REG_SSI_SRX0:
0177     case REG_SSI_SRX1:
0178     case REG_SSI_SACCST:
0179         return false;
0180     default:
0181         return true;
0182     }
0183 }
0184 
0185 static const struct regmap_config fsl_ssi_regconfig = {
0186     .max_register = REG_SSI_SACCDIS,
0187     .reg_bits = 32,
0188     .val_bits = 32,
0189     .reg_stride = 4,
0190     .val_format_endian = REGMAP_ENDIAN_NATIVE,
0191     .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
0192     .readable_reg = fsl_ssi_readable_reg,
0193     .volatile_reg = fsl_ssi_volatile_reg,
0194     .precious_reg = fsl_ssi_precious_reg,
0195     .writeable_reg = fsl_ssi_writeable_reg,
0196     .cache_type = REGCACHE_FLAT,
0197 };
0198 
0199 struct fsl_ssi_soc_data {
0200     bool imx;
0201     bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
0202     bool offline_config;
0203     u32 sisr_write_mask;
0204 };
0205 
0206 /**
0207  * struct fsl_ssi - per-SSI private data
0208  * @regs: Pointer to the regmap registers
0209  * @irq: IRQ of this SSI
0210  * @cpu_dai_drv: CPU DAI driver for this device
0211  * @dai_fmt: DAI configuration this device is currently used with
0212  * @streams: Mask of current active streams: BIT(TX) and BIT(RX)
0213  * @i2s_net: I2S and Network mode configurations of SCR register
0214  *           (this is the initial settings based on the DAI format)
0215  * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK
0216  * @use_dma: DMA is used or FIQ with stream filter
0217  * @use_dual_fifo: DMA with support for dual FIFO mode
0218  * @use_dyna_fifo: DMA with support for multi FIFO script
0219  * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree
0220  * @fifo_depth: Depth of the SSI FIFOs
0221  * @slot_width: Width of each DAI slot
0222  * @slots: Number of slots
0223  * @regvals: Specific RX/TX register settings
0224  * @clk: Clock source to access register
0225  * @baudclk: Clock source to generate bit and frame-sync clocks
0226  * @baudclk_streams: Active streams that are using baudclk
0227  * @regcache_sfcsr: Cache sfcsr register value during suspend and resume
0228  * @regcache_sacnt: Cache sacnt register value during suspend and resume
0229  * @dma_params_tx: DMA transmit parameters
0230  * @dma_params_rx: DMA receive parameters
0231  * @ssi_phys: physical address of the SSI registers
0232  * @fiq_params: FIQ stream filtering parameters
0233  * @card_pdev: Platform_device pointer to register a sound card for PowerPC or
0234  *             to register a CODEC platform device for AC97
0235  * @card_name: Platform_device name to register a sound card for PowerPC or
0236  *             to register a CODEC platform device for AC97
0237  * @card_idx: The index of SSI to register a sound card for PowerPC or
0238  *            to register a CODEC platform device for AC97
0239  * @dbg_stats: Debugging statistics
0240  * @soc: SoC specific data
0241  * @dev: Pointer to &pdev->dev
0242  * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are
0243  *                  @fifo_watermark or fewer words in TX fifo or
0244  *                  @fifo_watermark or more empty words in RX fifo.
0245  * @dma_maxburst: Max number of words to transfer in one go. So far,
0246  *                this is always the same as fifo_watermark.
0247  * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations
0248  * @audio_config: configure for dma multi fifo script
0249  */
0250 struct fsl_ssi {
0251     struct regmap *regs;
0252     int irq;
0253     struct snd_soc_dai_driver cpu_dai_drv;
0254 
0255     unsigned int dai_fmt;
0256     u8 streams;
0257     u8 i2s_net;
0258     bool synchronous;
0259     bool use_dma;
0260     bool use_dual_fifo;
0261     bool use_dyna_fifo;
0262     bool has_ipg_clk_name;
0263     unsigned int fifo_depth;
0264     unsigned int slot_width;
0265     unsigned int slots;
0266     struct fsl_ssi_regvals regvals[2];
0267 
0268     struct clk *clk;
0269     struct clk *baudclk;
0270     unsigned int baudclk_streams;
0271 
0272     u32 regcache_sfcsr;
0273     u32 regcache_sacnt;
0274 
0275     struct snd_dmaengine_dai_dma_data dma_params_tx;
0276     struct snd_dmaengine_dai_dma_data dma_params_rx;
0277     dma_addr_t ssi_phys;
0278 
0279     struct imx_pcm_fiq_params fiq_params;
0280 
0281     struct platform_device *card_pdev;
0282     char card_name[32];
0283     u32 card_idx;
0284 
0285     struct fsl_ssi_dbg dbg_stats;
0286 
0287     const struct fsl_ssi_soc_data *soc;
0288     struct device *dev;
0289 
0290     u32 fifo_watermark;
0291     u32 dma_maxburst;
0292 
0293     struct mutex ac97_reg_lock;
0294     struct sdma_peripheral_config audio_config[2];
0295 };
0296 
0297 /*
0298  * SoC specific data
0299  *
0300  * Notes:
0301  * 1) SSI in earlier SoCS has critical bits in control registers that
0302  *    cannot be changed after SSI starts running -- a software reset
0303  *    (set SSIEN to 0) is required to change their values. So adding
0304  *    an offline_config flag for these SoCs.
0305  * 2) SDMA is available since imx35. However, imx35 does not support
0306  *    DMA bits changing when SSI is running, so set offline_config.
0307  * 3) imx51 and later versions support register configurations when
0308  *    SSI is running (SSIEN); For these versions, DMA needs to be
0309  *    configured before SSI sends DMA request to avoid an undefined
0310  *    DMA request on the SDMA side.
0311  */
0312 
0313 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
0314     .imx = false,
0315     .offline_config = true,
0316     .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
0317                SSI_SISR_ROE0 | SSI_SISR_ROE1 |
0318                SSI_SISR_TUE0 | SSI_SISR_TUE1,
0319 };
0320 
0321 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
0322     .imx = true,
0323     .imx21regs = true,
0324     .offline_config = true,
0325     .sisr_write_mask = 0,
0326 };
0327 
0328 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
0329     .imx = true,
0330     .offline_config = true,
0331     .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
0332                SSI_SISR_ROE0 | SSI_SISR_ROE1 |
0333                SSI_SISR_TUE0 | SSI_SISR_TUE1,
0334 };
0335 
0336 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
0337     .imx = true,
0338     .offline_config = false,
0339     .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
0340                SSI_SISR_TUE0 | SSI_SISR_TUE1,
0341 };
0342 
0343 static const struct of_device_id fsl_ssi_ids[] = {
0344     { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
0345     { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
0346     { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
0347     { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
0348     {}
0349 };
0350 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
0351 
0352 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi)
0353 {
0354     return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
0355         SND_SOC_DAIFMT_AC97;
0356 }
0357 
0358 static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi)
0359 {
0360     return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
0361         SND_SOC_DAIFMT_BP_FP;
0362 }
0363 
0364 static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi)
0365 {
0366     return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
0367         SND_SOC_DAIFMT_BC_FP;
0368 }
0369 
0370 /**
0371  * fsl_ssi_isr - Interrupt handler to gather states
0372  * @irq: irq number
0373  * @dev_id: context
0374  */
0375 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
0376 {
0377     struct fsl_ssi *ssi = dev_id;
0378     struct regmap *regs = ssi->regs;
0379     u32 sisr, sisr2;
0380 
0381     regmap_read(regs, REG_SSI_SISR, &sisr);
0382 
0383     sisr2 = sisr & ssi->soc->sisr_write_mask;
0384     /* Clear the bits that we set */
0385     if (sisr2)
0386         regmap_write(regs, REG_SSI_SISR, sisr2);
0387 
0388     fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
0389 
0390     return IRQ_HANDLED;
0391 }
0392 
0393 /**
0394  * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with
0395  * cached values in regvals
0396  * @ssi: SSI context
0397  * @tx: direction
0398  *
0399  * Notes:
0400  * 1) For offline_config SoCs, enable all necessary bits of both streams
0401  *    when 1st stream starts, even if the opposite stream will not start
0402  * 2) It also clears FIFO before setting regvals; SOR is safe to set online
0403  */
0404 static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx)
0405 {
0406     struct fsl_ssi_regvals *vals = ssi->regvals;
0407     int dir = tx ? TX : RX;
0408     u32 sier, srcr, stcr;
0409 
0410     /* Clear dirty data in the FIFO; It also prevents channel slipping */
0411     regmap_update_bits(ssi->regs, REG_SSI_SOR,
0412                SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
0413 
0414     /*
0415      * On offline_config SoCs, SxCR and SIER are already configured when
0416      * the previous stream started. So skip all SxCR and SIER settings
0417      * to prevent online reconfigurations, then jump to set SCR directly
0418      */
0419     if (ssi->soc->offline_config && ssi->streams)
0420         goto enable_scr;
0421 
0422     if (ssi->soc->offline_config) {
0423         /*
0424          * Online reconfiguration not supported, so enable all bits for
0425          * both streams at once to avoid necessity of reconfigurations
0426          */
0427         srcr = vals[RX].srcr | vals[TX].srcr;
0428         stcr = vals[RX].stcr | vals[TX].stcr;
0429         sier = vals[RX].sier | vals[TX].sier;
0430     } else {
0431         /* Otherwise, only set bits for the current stream */
0432         srcr = vals[dir].srcr;
0433         stcr = vals[dir].stcr;
0434         sier = vals[dir].sier;
0435     }
0436 
0437     /* Configure SRCR, STCR and SIER at once */
0438     regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr);
0439     regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr);
0440     regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier);
0441 
0442 enable_scr:
0443     /*
0444      * Start DMA before setting TE to avoid FIFO underrun
0445      * which may cause a channel slip or a channel swap
0446      *
0447      * TODO: FIQ cases might also need this upon testing
0448      */
0449     if (ssi->use_dma && tx) {
0450         int try = 100;
0451         u32 sfcsr;
0452 
0453         /* Enable SSI first to send TX DMA request */
0454         regmap_update_bits(ssi->regs, REG_SSI_SCR,
0455                    SSI_SCR_SSIEN, SSI_SCR_SSIEN);
0456 
0457         /* Busy wait until TX FIFO not empty -- DMA working */
0458         do {
0459             regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr);
0460             if (SSI_SFCSR_TFCNT0(sfcsr))
0461                 break;
0462         } while (--try);
0463 
0464         /* FIFO still empty -- something might be wrong */
0465         if (!SSI_SFCSR_TFCNT0(sfcsr))
0466             dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n");
0467     }
0468     /* Enable all remaining bits in SCR */
0469     regmap_update_bits(ssi->regs, REG_SSI_SCR,
0470                vals[dir].scr, vals[dir].scr);
0471 
0472     /* Log the enabled stream to the mask */
0473     ssi->streams |= BIT(dir);
0474 }
0475 
0476 /*
0477  * Exclude bits that are used by the opposite stream
0478  *
0479  * When both streams are active, disabling some bits for the current stream
0480  * might break the other stream if these bits are used by it.
0481  *
0482  * @vals : regvals of the current stream
0483  * @avals: regvals of the opposite stream
0484  * @aactive: active state of the opposite stream
0485  *
0486  *  1) XOR vals and avals to get the differences if the other stream is active;
0487  *     Otherwise, return current vals if the other stream is not active
0488  *  2) AND the result of 1) with the current vals
0489  */
0490 #define _ssi_xor_shared_bits(vals, avals, aactive) \
0491     ((vals) ^ ((avals) * (aactive)))
0492 
0493 #define ssi_excl_shared_bits(vals, avals, aactive) \
0494     ((vals) & _ssi_xor_shared_bits(vals, avals, aactive))
0495 
0496 /**
0497  * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers
0498  * with cached values in regvals
0499  * @ssi: SSI context
0500  * @tx: direction
0501  *
0502  * Notes:
0503  * 1) For offline_config SoCs, to avoid online reconfigurations, disable all
0504  *    bits of both streams at once when the last stream is abort to end
0505  * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online
0506  */
0507 static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx)
0508 {
0509     struct fsl_ssi_regvals *vals, *avals;
0510     u32 sier, srcr, stcr, scr;
0511     int adir = tx ? RX : TX;
0512     int dir = tx ? TX : RX;
0513     bool aactive;
0514 
0515     /* Check if the opposite stream is active */
0516     aactive = ssi->streams & BIT(adir);
0517 
0518     vals = &ssi->regvals[dir];
0519 
0520     /* Get regvals of the opposite stream to keep opposite stream safe */
0521     avals = &ssi->regvals[adir];
0522 
0523     /*
0524      * To keep the other stream safe, exclude shared bits between
0525      * both streams, and get safe bits to disable current stream
0526      */
0527     scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive);
0528 
0529     /* Disable safe bits of SCR register for the current stream */
0530     regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0);
0531 
0532     /* Log the disabled stream to the mask */
0533     ssi->streams &= ~BIT(dir);
0534 
0535     /*
0536      * On offline_config SoCs, if the other stream is active, skip
0537      * SxCR and SIER settings to prevent online reconfigurations
0538      */
0539     if (ssi->soc->offline_config && aactive)
0540         goto fifo_clear;
0541 
0542     if (ssi->soc->offline_config) {
0543         /* Now there is only current stream active, disable all bits */
0544         srcr = vals->srcr | avals->srcr;
0545         stcr = vals->stcr | avals->stcr;
0546         sier = vals->sier | avals->sier;
0547     } else {
0548         /*
0549          * To keep the other stream safe, exclude shared bits between
0550          * both streams, and get safe bits to disable current stream
0551          */
0552         sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive);
0553         srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive);
0554         stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive);
0555     }
0556 
0557     /* Clear configurations of SRCR, STCR and SIER at once */
0558     regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0);
0559     regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0);
0560     regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0);
0561 
0562 fifo_clear:
0563     /* Clear remaining data in the FIFO */
0564     regmap_update_bits(ssi->regs, REG_SSI_SOR,
0565                SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
0566 }
0567 
0568 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
0569 {
0570     struct regmap *regs = ssi->regs;
0571 
0572     /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
0573     if (!ssi->soc->imx21regs) {
0574         /* Disable all channel slots */
0575         regmap_write(regs, REG_SSI_SACCDIS, 0xff);
0576         /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
0577         regmap_write(regs, REG_SSI_SACCEN, 0x300);
0578     }
0579 }
0580 
0581 /**
0582  * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and
0583  * SCR to later set them safely
0584  * @ssi: SSI context
0585  */
0586 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi)
0587 {
0588     struct fsl_ssi_regvals *vals = ssi->regvals;
0589 
0590     vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS;
0591     vals[RX].srcr = SSI_SRCR_RFEN0;
0592     vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE;
0593     vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS;
0594     vals[TX].stcr = SSI_STCR_TFEN0;
0595     vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE;
0596 
0597     /* AC97 has already enabled SSIEN, RE and TE, so ignore them */
0598     if (fsl_ssi_is_ac97(ssi))
0599         vals[RX].scr = vals[TX].scr = 0;
0600 
0601     if (ssi->use_dual_fifo) {
0602         vals[RX].srcr |= SSI_SRCR_RFEN1;
0603         vals[TX].stcr |= SSI_STCR_TFEN1;
0604     }
0605 
0606     if (ssi->use_dma) {
0607         vals[RX].sier |= SSI_SIER_RDMAE;
0608         vals[TX].sier |= SSI_SIER_TDMAE;
0609     } else {
0610         vals[RX].sier |= SSI_SIER_RIE;
0611         vals[TX].sier |= SSI_SIER_TIE;
0612     }
0613 }
0614 
0615 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
0616 {
0617     struct regmap *regs = ssi->regs;
0618 
0619     /* Setup the clock control register */
0620     regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
0621     regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
0622 
0623     /* Enable AC97 mode and startup the SSI */
0624     regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV);
0625 
0626     /* AC97 has to communicate with codec before starting a stream */
0627     regmap_update_bits(regs, REG_SSI_SCR,
0628                SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
0629                SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
0630 
0631     regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
0632 }
0633 
0634 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
0635                struct snd_soc_dai *dai)
0636 {
0637     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0638     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
0639     int ret;
0640 
0641     ret = clk_prepare_enable(ssi->clk);
0642     if (ret)
0643         return ret;
0644 
0645     /*
0646      * When using dual fifo mode, it is safer to ensure an even period
0647      * size. If appearing to an odd number while DMA always starts its
0648      * task from fifo0, fifo1 would be neglected at the end of each
0649      * period. But SSI would still access fifo1 with an invalid data.
0650      */
0651     if (ssi->use_dual_fifo || ssi->use_dyna_fifo)
0652         snd_pcm_hw_constraint_step(substream->runtime, 0,
0653                        SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
0654 
0655     return 0;
0656 }
0657 
0658 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
0659                  struct snd_soc_dai *dai)
0660 {
0661     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0662     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
0663 
0664     clk_disable_unprepare(ssi->clk);
0665 }
0666 
0667 /**
0668  * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock
0669  * @substream: ASoC substream
0670  * @dai: pointer to DAI
0671  * @hw_params: pointers to hw_params
0672  *
0673  * Notes: This function can be only called when using SSI as DAI master
0674  *
0675  * Quick instruction for parameters:
0676  * freq: Output BCLK frequency = samplerate * slots * slot_width
0677  *       (In 2-channel I2S Master mode, slot_width is fixed 32)
0678  */
0679 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
0680                 struct snd_soc_dai *dai,
0681                 struct snd_pcm_hw_params *hw_params)
0682 {
0683     bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0684     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
0685     struct regmap *regs = ssi->regs;
0686     u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
0687     unsigned long clkrate, baudrate, tmprate;
0688     unsigned int channels = params_channels(hw_params);
0689     unsigned int slot_width = params_width(hw_params);
0690     unsigned int slots = 2;
0691     u64 sub, savesub = 100000;
0692     unsigned int freq;
0693     bool baudclk_is_used;
0694     int ret;
0695 
0696     /* Override slots and slot_width if being specifically set... */
0697     if (ssi->slots)
0698         slots = ssi->slots;
0699     if (ssi->slot_width)
0700         slot_width = ssi->slot_width;
0701 
0702     /* ...but force 32 bits for stereo audio using I2S Master Mode */
0703     if (channels == 2 &&
0704         (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER)
0705         slot_width = 32;
0706 
0707     /* Generate bit clock based on the slot number and slot width */
0708     freq = slots * slot_width * params_rate(hw_params);
0709 
0710     /* Don't apply it to any non-baudclk circumstance */
0711     if (IS_ERR(ssi->baudclk))
0712         return -EINVAL;
0713 
0714     /*
0715      * Hardware limitation: The bclk rate must be
0716      * never greater than 1/5 IPG clock rate
0717      */
0718     if (freq * 5 > clk_get_rate(ssi->clk)) {
0719         dev_err(dai->dev, "bitclk > ipgclk / 5\n");
0720         return -EINVAL;
0721     }
0722 
0723     baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream));
0724 
0725     /* It should be already enough to divide clock by setting pm alone */
0726     psr = 0;
0727     div2 = 0;
0728 
0729     factor = (div2 + 1) * (7 * psr + 1) * 2;
0730 
0731     for (i = 0; i < 255; i++) {
0732         tmprate = freq * factor * (i + 1);
0733 
0734         if (baudclk_is_used)
0735             clkrate = clk_get_rate(ssi->baudclk);
0736         else
0737             clkrate = clk_round_rate(ssi->baudclk, tmprate);
0738 
0739         clkrate /= factor;
0740         afreq = clkrate / (i + 1);
0741 
0742         if (freq == afreq)
0743             sub = 0;
0744         else if (freq / afreq == 1)
0745             sub = freq - afreq;
0746         else if (afreq / freq == 1)
0747             sub = afreq - freq;
0748         else
0749             continue;
0750 
0751         /* Calculate the fraction */
0752         sub *= 100000;
0753         do_div(sub, freq);
0754 
0755         if (sub < savesub && !(i == 0)) {
0756             baudrate = tmprate;
0757             savesub = sub;
0758             pm = i;
0759         }
0760 
0761         /* We are lucky */
0762         if (savesub == 0)
0763             break;
0764     }
0765 
0766     /* No proper pm found if it is still remaining the initial value */
0767     if (pm == 999) {
0768         dev_err(dai->dev, "failed to handle the required sysclk\n");
0769         return -EINVAL;
0770     }
0771 
0772     stccr = SSI_SxCCR_PM(pm + 1);
0773     mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR;
0774 
0775     /* STCCR is used for RX in synchronous mode */
0776     tx2 = tx || ssi->synchronous;
0777     regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr);
0778 
0779     if (!baudclk_is_used) {
0780         ret = clk_set_rate(ssi->baudclk, baudrate);
0781         if (ret) {
0782             dev_err(dai->dev, "failed to set baudclk rate\n");
0783             return -EINVAL;
0784         }
0785     }
0786 
0787     return 0;
0788 }
0789 
0790 /**
0791  * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters
0792  * @substream: ASoC substream
0793  * @hw_params: pointers to hw_params
0794  * @dai: pointer to DAI
0795  *
0796  * Notes:
0797  * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily
0798  *    disabled on offline_config SoCs. Even for online configurable SoCs
0799  *    running in synchronous mode (both TX and RX use STCCR), it is not
0800  *    safe to re-configure them when both two streams start running.
0801  * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the
0802  *    fsl_ssi_set_bclk() if SSI is the DAI clock master.
0803  */
0804 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
0805                  struct snd_pcm_hw_params *hw_params,
0806                  struct snd_soc_dai *dai)
0807 {
0808     bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
0809     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
0810     struct fsl_ssi_regvals *vals = ssi->regvals;
0811     struct regmap *regs = ssi->regs;
0812     unsigned int channels = params_channels(hw_params);
0813     unsigned int sample_size = params_width(hw_params);
0814     u32 wl = SSI_SxCCR_WL(sample_size);
0815     int ret;
0816 
0817     if (fsl_ssi_is_i2s_clock_provider(ssi)) {
0818         ret = fsl_ssi_set_bclk(substream, dai, hw_params);
0819         if (ret)
0820             return ret;
0821 
0822         /* Do not enable the clock if it is already enabled */
0823         if (!(ssi->baudclk_streams & BIT(substream->stream))) {
0824             ret = clk_prepare_enable(ssi->baudclk);
0825             if (ret)
0826                 return ret;
0827 
0828             ssi->baudclk_streams |= BIT(substream->stream);
0829         }
0830     }
0831 
0832     /*
0833      * SSI is properly configured if it is enabled and running in
0834      * the synchronous mode; Note that AC97 mode is an exception
0835      * that should set separate configurations for STCCR and SRCCR
0836      * despite running in the synchronous mode.
0837      */
0838     if (ssi->streams && ssi->synchronous)
0839         return 0;
0840 
0841     if (!fsl_ssi_is_ac97(ssi)) {
0842         /*
0843          * Keep the ssi->i2s_net intact while having a local variable
0844          * to override settings for special use cases. Otherwise, the
0845          * ssi->i2s_net will lose the settings for regular use cases.
0846          */
0847         u8 i2s_net = ssi->i2s_net;
0848 
0849         /* Normal + Network mode to send 16-bit data in 32-bit frames */
0850         if (fsl_ssi_is_i2s_bc_fp(ssi) && sample_size == 16)
0851             i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET;
0852 
0853         /* Use Normal mode to send mono data at 1st slot of 2 slots */
0854         if (channels == 1)
0855             i2s_net = SSI_SCR_I2S_MODE_NORMAL;
0856 
0857         regmap_update_bits(regs, REG_SSI_SCR,
0858                    SSI_SCR_I2S_NET_MASK, i2s_net);
0859     }
0860 
0861     /* In synchronous mode, the SSI uses STCCR for capture */
0862     tx2 = tx || ssi->synchronous;
0863     regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
0864 
0865     if (ssi->use_dyna_fifo) {
0866         if (channels == 1) {
0867             ssi->audio_config[0].n_fifos_dst = 1;
0868             ssi->audio_config[1].n_fifos_src = 1;
0869             vals[RX].srcr &= ~SSI_SRCR_RFEN1;
0870             vals[TX].stcr &= ~SSI_STCR_TFEN1;
0871             vals[RX].scr  &= ~SSI_SCR_TCH_EN;
0872             vals[TX].scr  &= ~SSI_SCR_TCH_EN;
0873         } else {
0874             ssi->audio_config[0].n_fifos_dst = 2;
0875             ssi->audio_config[1].n_fifos_src = 2;
0876             vals[RX].srcr |= SSI_SRCR_RFEN1;
0877             vals[TX].stcr |= SSI_STCR_TFEN1;
0878             vals[RX].scr  |= SSI_SCR_TCH_EN;
0879             vals[TX].scr  |= SSI_SCR_TCH_EN;
0880         }
0881         ssi->dma_params_tx.peripheral_config = &ssi->audio_config[0];
0882         ssi->dma_params_tx.peripheral_size = sizeof(ssi->audio_config[0]);
0883         ssi->dma_params_rx.peripheral_config = &ssi->audio_config[1];
0884         ssi->dma_params_rx.peripheral_size = sizeof(ssi->audio_config[1]);
0885     }
0886 
0887     return 0;
0888 }
0889 
0890 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
0891                struct snd_soc_dai *dai)
0892 {
0893     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0894     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
0895 
0896     if (fsl_ssi_is_i2s_clock_provider(ssi) &&
0897         ssi->baudclk_streams & BIT(substream->stream)) {
0898         clk_disable_unprepare(ssi->baudclk);
0899         ssi->baudclk_streams &= ~BIT(substream->stream);
0900     }
0901 
0902     return 0;
0903 }
0904 
0905 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt)
0906 {
0907     u32 strcr = 0, scr = 0, stcr, srcr, mask;
0908     unsigned int slots;
0909 
0910     ssi->dai_fmt = fmt;
0911 
0912     /* Synchronize frame sync clock for TE to avoid data slipping */
0913     scr |= SSI_SCR_SYNC_TX_FS;
0914 
0915     /* Set to default shifting settings: LSB_ALIGNED */
0916     strcr |= SSI_STCR_TXBIT0;
0917 
0918     /* Use Network mode as default */
0919     ssi->i2s_net = SSI_SCR_NET;
0920     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0921     case SND_SOC_DAIFMT_I2S:
0922         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0923         case SND_SOC_DAIFMT_BP_FP:
0924             if (IS_ERR(ssi->baudclk)) {
0925                 dev_err(ssi->dev,
0926                     "missing baudclk for master mode\n");
0927                 return -EINVAL;
0928             }
0929             fallthrough;
0930         case SND_SOC_DAIFMT_BC_FP:
0931             ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER;
0932             break;
0933         case SND_SOC_DAIFMT_BC_FC:
0934             ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE;
0935             break;
0936         default:
0937             return -EINVAL;
0938         }
0939 
0940         slots = ssi->slots ? : 2;
0941         regmap_update_bits(ssi->regs, REG_SSI_STCCR,
0942                    SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
0943         regmap_update_bits(ssi->regs, REG_SSI_SRCCR,
0944                    SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
0945 
0946         /* Data on rising edge of bclk, frame low, 1clk before data */
0947         strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS;
0948         break;
0949     case SND_SOC_DAIFMT_LEFT_J:
0950         /* Data on rising edge of bclk, frame high */
0951         strcr |= SSI_STCR_TSCKP;
0952         break;
0953     case SND_SOC_DAIFMT_DSP_A:
0954         /* Data on rising edge of bclk, frame high, 1clk before data */
0955         strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS;
0956         break;
0957     case SND_SOC_DAIFMT_DSP_B:
0958         /* Data on rising edge of bclk, frame high */
0959         strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP;
0960         break;
0961     case SND_SOC_DAIFMT_AC97:
0962         /* Data on falling edge of bclk, frame high, 1clk before data */
0963         strcr |= SSI_STCR_TEFS;
0964         break;
0965     default:
0966         return -EINVAL;
0967     }
0968 
0969     scr |= ssi->i2s_net;
0970 
0971     /* DAI clock inversion */
0972     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0973     case SND_SOC_DAIFMT_NB_NF:
0974         /* Nothing to do for both normal cases */
0975         break;
0976     case SND_SOC_DAIFMT_IB_NF:
0977         /* Invert bit clock */
0978         strcr ^= SSI_STCR_TSCKP;
0979         break;
0980     case SND_SOC_DAIFMT_NB_IF:
0981         /* Invert frame clock */
0982         strcr ^= SSI_STCR_TFSI;
0983         break;
0984     case SND_SOC_DAIFMT_IB_IF:
0985         /* Invert both clocks */
0986         strcr ^= SSI_STCR_TSCKP;
0987         strcr ^= SSI_STCR_TFSI;
0988         break;
0989     default:
0990         return -EINVAL;
0991     }
0992 
0993     /* DAI clock provider masks */
0994     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0995     case SND_SOC_DAIFMT_BP_FP:
0996         /* Output bit and frame sync clocks */
0997         strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
0998         scr |= SSI_SCR_SYS_CLK_EN;
0999         break;
1000     case SND_SOC_DAIFMT_BC_FC:
1001         /* Input bit or frame sync clocks */
1002         break;
1003     case SND_SOC_DAIFMT_BC_FP:
1004         /* Input bit clock but output frame sync clock */
1005         strcr |= SSI_STCR_TFDIR;
1006         break;
1007     default:
1008         return -EINVAL;
1009     }
1010 
1011     stcr = strcr;
1012     srcr = strcr;
1013 
1014     /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
1015     if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) {
1016         srcr &= ~SSI_SRCR_RXDIR;
1017         scr |= SSI_SCR_SYN;
1018     }
1019 
1020     mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP |
1021            SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
1022 
1023     regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr);
1024     regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr);
1025 
1026     mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK |
1027            SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN;
1028     regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr);
1029 
1030     return 0;
1031 }
1032 
1033 /**
1034  * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format
1035  * @dai: pointer to DAI
1036  * @fmt: format mask
1037  */
1038 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1039 {
1040     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1041 
1042     /* AC97 configured DAIFMT earlier in the probe() */
1043     if (fsl_ssi_is_ac97(ssi))
1044         return 0;
1045 
1046     return _fsl_ssi_set_dai_fmt(ssi, fmt);
1047 }
1048 
1049 /**
1050  * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width
1051  * @dai: pointer to DAI
1052  * @tx_mask: mask for TX
1053  * @rx_mask: mask for RX
1054  * @slots: number of slots
1055  * @slot_width: number of bits per slot
1056  */
1057 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
1058                     u32 rx_mask, int slots, int slot_width)
1059 {
1060     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1061     struct regmap *regs = ssi->regs;
1062     u32 val;
1063 
1064     /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */
1065     if (slot_width & 1 || slot_width < 8 || slot_width > 24) {
1066         dev_err(dai->dev, "invalid slot width: %d\n", slot_width);
1067         return -EINVAL;
1068     }
1069 
1070     /* The slot number should be >= 2 if using Network mode or I2S mode */
1071     if (ssi->i2s_net && slots < 2) {
1072         dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n");
1073         return -EINVAL;
1074     }
1075 
1076     regmap_update_bits(regs, REG_SSI_STCCR,
1077                SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1078     regmap_update_bits(regs, REG_SSI_SRCCR,
1079                SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots));
1080 
1081     /* Save the SCR register value */
1082     regmap_read(regs, REG_SSI_SCR, &val);
1083     /* Temporarily enable SSI to allow SxMSKs to be configurable */
1084     regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN);
1085 
1086     regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
1087     regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
1088 
1089     /* Restore the value of SSIEN bit */
1090     regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
1091 
1092     ssi->slot_width = slot_width;
1093     ssi->slots = slots;
1094 
1095     return 0;
1096 }
1097 
1098 /**
1099  * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction.
1100  * @substream: ASoC substream
1101  * @cmd: trigger command
1102  * @dai: pointer to DAI
1103  *
1104  * The DMA channel is in external master start and pause mode, which
1105  * means the SSI completely controls the flow of data.
1106  */
1107 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1108                struct snd_soc_dai *dai)
1109 {
1110     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1111     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
1112     bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
1113 
1114     switch (cmd) {
1115     case SNDRV_PCM_TRIGGER_START:
1116     case SNDRV_PCM_TRIGGER_RESUME:
1117     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1118         /*
1119          * SACCST might be modified via AC Link by a CODEC if it sends
1120          * extra bits in their SLOTREQ requests, which'll accidentally
1121          * send valid data to slots other than normal playback slots.
1122          *
1123          * To be safe, configure SACCST right before TX starts.
1124          */
1125         if (tx && fsl_ssi_is_ac97(ssi))
1126             fsl_ssi_tx_ac97_saccst_setup(ssi);
1127         fsl_ssi_config_enable(ssi, tx);
1128         break;
1129 
1130     case SNDRV_PCM_TRIGGER_STOP:
1131     case SNDRV_PCM_TRIGGER_SUSPEND:
1132     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1133         fsl_ssi_config_disable(ssi, tx);
1134         break;
1135 
1136     default:
1137         return -EINVAL;
1138     }
1139 
1140     return 0;
1141 }
1142 
1143 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1144 {
1145     struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai);
1146 
1147     if (ssi->soc->imx && ssi->use_dma)
1148         snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx,
1149                       &ssi->dma_params_rx);
1150 
1151     return 0;
1152 }
1153 
1154 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1155     .startup = fsl_ssi_startup,
1156     .shutdown = fsl_ssi_shutdown,
1157     .hw_params = fsl_ssi_hw_params,
1158     .hw_free = fsl_ssi_hw_free,
1159     .set_fmt = fsl_ssi_set_dai_fmt,
1160     .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1161     .trigger = fsl_ssi_trigger,
1162 };
1163 
1164 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1165     .probe = fsl_ssi_dai_probe,
1166     .playback = {
1167         .stream_name = "CPU-Playback",
1168         .channels_min = 1,
1169         .channels_max = 32,
1170         .rates = SNDRV_PCM_RATE_CONTINUOUS,
1171         .formats = FSLSSI_I2S_FORMATS,
1172     },
1173     .capture = {
1174         .stream_name = "CPU-Capture",
1175         .channels_min = 1,
1176         .channels_max = 32,
1177         .rates = SNDRV_PCM_RATE_CONTINUOUS,
1178         .formats = FSLSSI_I2S_FORMATS,
1179     },
1180     .ops = &fsl_ssi_dai_ops,
1181 };
1182 
1183 static const struct snd_soc_component_driver fsl_ssi_component = {
1184     .name = "fsl-ssi",
1185     .legacy_dai_naming = 1,
1186 };
1187 
1188 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1189     .symmetric_channels = 1,
1190     .probe = fsl_ssi_dai_probe,
1191     .playback = {
1192         .stream_name = "AC97 Playback",
1193         .channels_min = 2,
1194         .channels_max = 2,
1195         .rates = SNDRV_PCM_RATE_8000_48000,
1196         .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20,
1197     },
1198     .capture = {
1199         .stream_name = "AC97 Capture",
1200         .channels_min = 2,
1201         .channels_max = 2,
1202         .rates = SNDRV_PCM_RATE_48000,
1203         /* 16-bit capture is broken (errata ERR003778) */
1204         .formats = SNDRV_PCM_FMTBIT_S20,
1205     },
1206     .ops = &fsl_ssi_dai_ops,
1207 };
1208 
1209 static struct fsl_ssi *fsl_ac97_data;
1210 
1211 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1212                    unsigned short val)
1213 {
1214     struct regmap *regs = fsl_ac97_data->regs;
1215     unsigned int lreg;
1216     unsigned int lval;
1217     int ret;
1218 
1219     if (reg > 0x7f)
1220         return;
1221 
1222     mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1223 
1224     ret = clk_prepare_enable(fsl_ac97_data->clk);
1225     if (ret) {
1226         pr_err("ac97 write clk_prepare_enable failed: %d\n",
1227             ret);
1228         goto ret_unlock;
1229     }
1230 
1231     lreg = reg <<  12;
1232     regmap_write(regs, REG_SSI_SACADD, lreg);
1233 
1234     lval = val << 4;
1235     regmap_write(regs, REG_SSI_SACDAT, lval);
1236 
1237     regmap_update_bits(regs, REG_SSI_SACNT,
1238                SSI_SACNT_RDWR_MASK, SSI_SACNT_WR);
1239     udelay(100);
1240 
1241     clk_disable_unprepare(fsl_ac97_data->clk);
1242 
1243 ret_unlock:
1244     mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1245 }
1246 
1247 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1248                     unsigned short reg)
1249 {
1250     struct regmap *regs = fsl_ac97_data->regs;
1251     unsigned short val = 0;
1252     u32 reg_val;
1253     unsigned int lreg;
1254     int ret;
1255 
1256     mutex_lock(&fsl_ac97_data->ac97_reg_lock);
1257 
1258     ret = clk_prepare_enable(fsl_ac97_data->clk);
1259     if (ret) {
1260         pr_err("ac97 read clk_prepare_enable failed: %d\n", ret);
1261         goto ret_unlock;
1262     }
1263 
1264     lreg = (reg & 0x7f) <<  12;
1265     regmap_write(regs, REG_SSI_SACADD, lreg);
1266     regmap_update_bits(regs, REG_SSI_SACNT,
1267                SSI_SACNT_RDWR_MASK, SSI_SACNT_RD);
1268 
1269     udelay(100);
1270 
1271     regmap_read(regs, REG_SSI_SACDAT, &reg_val);
1272     val = (reg_val >> 4) & 0xffff;
1273 
1274     clk_disable_unprepare(fsl_ac97_data->clk);
1275 
1276 ret_unlock:
1277     mutex_unlock(&fsl_ac97_data->ac97_reg_lock);
1278     return val;
1279 }
1280 
1281 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1282     .read = fsl_ssi_ac97_read,
1283     .write = fsl_ssi_ac97_write,
1284 };
1285 
1286 /**
1287  * fsl_ssi_hw_init - Initialize SSI registers
1288  * @ssi: SSI context
1289  */
1290 static int fsl_ssi_hw_init(struct fsl_ssi *ssi)
1291 {
1292     u32 wm = ssi->fifo_watermark;
1293 
1294     /* Initialize regvals */
1295     fsl_ssi_setup_regvals(ssi);
1296 
1297     /* Set watermarks */
1298     regmap_write(ssi->regs, REG_SSI_SFCSR,
1299              SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
1300              SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
1301 
1302     /* Enable Dual FIFO mode */
1303     if (ssi->use_dual_fifo)
1304         regmap_update_bits(ssi->regs, REG_SSI_SCR,
1305                    SSI_SCR_TCH_EN, SSI_SCR_TCH_EN);
1306 
1307     /* AC97 should start earlier to communicate with CODECs */
1308     if (fsl_ssi_is_ac97(ssi)) {
1309         _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt);
1310         fsl_ssi_setup_ac97(ssi);
1311     }
1312 
1313     return 0;
1314 }
1315 
1316 /**
1317  * fsl_ssi_hw_clean - Clear SSI registers
1318  * @ssi: SSI context
1319  */
1320 static void fsl_ssi_hw_clean(struct fsl_ssi *ssi)
1321 {
1322     /* Disable registers for AC97 */
1323     if (fsl_ssi_is_ac97(ssi)) {
1324         /* Disable TE and RE bits first */
1325         regmap_update_bits(ssi->regs, REG_SSI_SCR,
1326                    SSI_SCR_TE | SSI_SCR_RE, 0);
1327         /* Disable AC97 mode */
1328         regmap_write(ssi->regs, REG_SSI_SACNT, 0);
1329         /* Unset WAIT bits */
1330         regmap_write(ssi->regs, REG_SSI_SOR, 0);
1331         /* Disable SSI -- software reset */
1332         regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0);
1333     }
1334 }
1335 
1336 /*
1337  * Make every character in a string lower-case
1338  */
1339 static void make_lowercase(char *s)
1340 {
1341     if (!s)
1342         return;
1343     for (; *s; s++)
1344         *s = tolower(*s);
1345 }
1346 
1347 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1348                  struct fsl_ssi *ssi, void __iomem *iomem)
1349 {
1350     struct device *dev = &pdev->dev;
1351     int ret;
1352 
1353     /* Backward compatible for a DT without ipg clock name assigned */
1354     if (ssi->has_ipg_clk_name)
1355         ssi->clk = devm_clk_get(dev, "ipg");
1356     else
1357         ssi->clk = devm_clk_get(dev, NULL);
1358     if (IS_ERR(ssi->clk)) {
1359         ret = PTR_ERR(ssi->clk);
1360         dev_err(dev, "failed to get clock: %d\n", ret);
1361         return ret;
1362     }
1363 
1364     /* Enable the clock since regmap will not handle it in this case */
1365     if (!ssi->has_ipg_clk_name) {
1366         ret = clk_prepare_enable(ssi->clk);
1367         if (ret) {
1368             dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
1369             return ret;
1370         }
1371     }
1372 
1373     /* Do not error out for consumer cases that live without a baud clock */
1374     ssi->baudclk = devm_clk_get(dev, "baud");
1375     if (IS_ERR(ssi->baudclk))
1376         dev_dbg(dev, "failed to get baud clock: %ld\n",
1377              PTR_ERR(ssi->baudclk));
1378 
1379     ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1380     ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1381     ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1382     ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1383 
1384     /* Use even numbers to avoid channel swap due to SDMA script design */
1385     if (ssi->use_dual_fifo || ssi->use_dyna_fifo) {
1386         ssi->dma_params_tx.maxburst &= ~0x1;
1387         ssi->dma_params_rx.maxburst &= ~0x1;
1388     }
1389 
1390     if (!ssi->use_dma) {
1391         /*
1392          * Some boards use an incompatible codec. Use imx-fiq-pcm-audio
1393          * to get it working, as DMA is not possible in this situation.
1394          */
1395         ssi->fiq_params.irq = ssi->irq;
1396         ssi->fiq_params.base = iomem;
1397         ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
1398         ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
1399 
1400         ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
1401         if (ret)
1402             goto error_pcm;
1403     } else {
1404         ret = imx_pcm_dma_init(pdev);
1405         if (ret)
1406             goto error_pcm;
1407     }
1408 
1409     return 0;
1410 
1411 error_pcm:
1412     if (!ssi->has_ipg_clk_name)
1413         clk_disable_unprepare(ssi->clk);
1414 
1415     return ret;
1416 }
1417 
1418 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi)
1419 {
1420     if (!ssi->use_dma)
1421         imx_pcm_fiq_exit(pdev);
1422     if (!ssi->has_ipg_clk_name)
1423         clk_disable_unprepare(ssi->clk);
1424 }
1425 
1426 static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi)
1427 {
1428     struct device *dev = ssi->dev;
1429     struct device_node *np = dev->of_node;
1430     const char *p, *sprop;
1431     const __be32 *iprop;
1432     u32 dmas[4];
1433     int ret;
1434 
1435     ret = of_property_match_string(np, "clock-names", "ipg");
1436     /* Get error code if not found */
1437     ssi->has_ipg_clk_name = ret >= 0;
1438 
1439     /* Check if being used in AC97 mode */
1440     sprop = of_get_property(np, "fsl,mode", NULL);
1441     if (sprop && !strcmp(sprop, "ac97-slave")) {
1442         ssi->dai_fmt = FSLSSI_AC97_DAIFMT;
1443 
1444         ret = of_property_read_u32(np, "cell-index", &ssi->card_idx);
1445         if (ret) {
1446             dev_err(dev, "failed to get SSI index property\n");
1447             return -EINVAL;
1448         }
1449         strcpy(ssi->card_name, "ac97-codec");
1450     } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1451         /*
1452          * In synchronous mode, STCK and STFS ports are used by RX
1453          * as well. So the software should limit the sample rates,
1454          * sample bits and channels to be symmetric.
1455          *
1456          * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs
1457          * in the SSI synchronous mode however it does not have to
1458          * limit symmetric sample rates and sample bits.
1459          */
1460         ssi->synchronous = true;
1461     }
1462 
1463     /* Select DMA or FIQ */
1464     ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter");
1465 
1466     /* Fetch FIFO depth; Set to 8 for older DT without this property */
1467     iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1468     if (iprop)
1469         ssi->fifo_depth = be32_to_cpup(iprop);
1470     else
1471         ssi->fifo_depth = 8;
1472 
1473     /* Use dual FIFO mode depending on the support from SDMA script */
1474     ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1475     if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL)
1476         ssi->use_dual_fifo = true;
1477 
1478     if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI)
1479         ssi->use_dyna_fifo = true;
1480     /*
1481      * Backward compatible for older bindings by manually triggering the
1482      * machine driver's probe(). Use /compatible property, including the
1483      * address of CPU DAI driver structure, as the name of machine driver
1484      *
1485      * If card_name is set by AC97 earlier, bypass here since it uses a
1486      * different name to register the device.
1487      */
1488     if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) {
1489         struct device_node *root = of_find_node_by_path("/");
1490 
1491         sprop = of_get_property(root, "compatible", NULL);
1492         of_node_put(root);
1493         /* Strip "fsl," in the compatible name if applicable */
1494         p = strrchr(sprop, ',');
1495         if (p)
1496             sprop = p + 1;
1497         snprintf(ssi->card_name, sizeof(ssi->card_name),
1498              "snd-soc-%s", sprop);
1499         make_lowercase(ssi->card_name);
1500         ssi->card_idx = 0;
1501     }
1502 
1503     return 0;
1504 }
1505 
1506 static int fsl_ssi_probe(struct platform_device *pdev)
1507 {
1508     struct regmap_config regconfig = fsl_ssi_regconfig;
1509     struct device *dev = &pdev->dev;
1510     struct fsl_ssi *ssi;
1511     struct resource *res;
1512     void __iomem *iomem;
1513     int ret = 0;
1514 
1515     ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1516     if (!ssi)
1517         return -ENOMEM;
1518 
1519     ssi->dev = dev;
1520     ssi->soc = of_device_get_match_data(&pdev->dev);
1521 
1522     /* Probe from DT */
1523     ret = fsl_ssi_probe_from_dt(ssi);
1524     if (ret)
1525         return ret;
1526 
1527     if (fsl_ssi_is_ac97(ssi)) {
1528         memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai,
1529                sizeof(fsl_ssi_ac97_dai));
1530         fsl_ac97_data = ssi;
1531     } else {
1532         memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template,
1533                sizeof(fsl_ssi_dai_template));
1534     }
1535     ssi->cpu_dai_drv.name = dev_name(dev);
1536 
1537     iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1538     if (IS_ERR(iomem))
1539         return PTR_ERR(iomem);
1540     ssi->ssi_phys = res->start;
1541 
1542     if (ssi->soc->imx21regs) {
1543         /* No SACC{ST,EN,DIS} regs in imx21-class SSI */
1544         regconfig.max_register = REG_SSI_SRMSK;
1545         regconfig.num_reg_defaults_raw =
1546             REG_SSI_SRMSK / sizeof(uint32_t) + 1;
1547     }
1548 
1549     if (ssi->has_ipg_clk_name)
1550         ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem,
1551                               &regconfig);
1552     else
1553         ssi->regs = devm_regmap_init_mmio(dev, iomem, &regconfig);
1554     if (IS_ERR(ssi->regs)) {
1555         dev_err(dev, "failed to init register map\n");
1556         return PTR_ERR(ssi->regs);
1557     }
1558 
1559     ssi->irq = platform_get_irq(pdev, 0);
1560     if (ssi->irq < 0)
1561         return ssi->irq;
1562 
1563     /* Set software limitations for synchronous mode except AC97 */
1564     if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) {
1565         ssi->cpu_dai_drv.symmetric_rate = 1;
1566         ssi->cpu_dai_drv.symmetric_channels = 1;
1567         ssi->cpu_dai_drv.symmetric_sample_bits = 1;
1568     }
1569 
1570     /*
1571      * Configure TX and RX DMA watermarks -- when to send a DMA request
1572      *
1573      * Values should be tested to avoid FIFO under/over run. Set maxburst
1574      * to fifo_watermark to maxiumize DMA transaction to reduce overhead.
1575      */
1576     switch (ssi->fifo_depth) {
1577     case 15:
1578         /*
1579          * Set to 8 as a balanced configuration -- When TX FIFO has 8
1580          * empty slots, send a DMA request to fill these 8 slots. The
1581          * remaining 7 slots should be able to allow DMA to finish the
1582          * transaction before TX FIFO underruns; Same applies to RX.
1583          *
1584          * Tested with cases running at 48kHz @ 16 bits x 16 channels
1585          */
1586         ssi->fifo_watermark = 8;
1587         ssi->dma_maxburst = 8;
1588         break;
1589     case 8:
1590     default:
1591         /* Safely use old watermark configurations for older chips */
1592         ssi->fifo_watermark = ssi->fifo_depth - 2;
1593         ssi->dma_maxburst = ssi->fifo_depth - 2;
1594         break;
1595     }
1596 
1597     dev_set_drvdata(dev, ssi);
1598 
1599     if (ssi->soc->imx) {
1600         ret = fsl_ssi_imx_probe(pdev, ssi, iomem);
1601         if (ret)
1602             return ret;
1603     }
1604 
1605     if (fsl_ssi_is_ac97(ssi)) {
1606         mutex_init(&ssi->ac97_reg_lock);
1607         ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1608         if (ret) {
1609             dev_err(dev, "failed to set AC'97 ops\n");
1610             goto error_ac97_ops;
1611         }
1612     }
1613 
1614     ret = devm_snd_soc_register_component(dev, &fsl_ssi_component,
1615                           &ssi->cpu_dai_drv, 1);
1616     if (ret) {
1617         dev_err(dev, "failed to register DAI: %d\n", ret);
1618         goto error_asoc_register;
1619     }
1620 
1621     if (ssi->use_dma) {
1622         ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0,
1623                        dev_name(dev), ssi);
1624         if (ret < 0) {
1625             dev_err(dev, "failed to claim irq %u\n", ssi->irq);
1626             goto error_asoc_register;
1627         }
1628     }
1629 
1630     fsl_ssi_debugfs_create(&ssi->dbg_stats, dev);
1631 
1632     /* Initially configures SSI registers */
1633     fsl_ssi_hw_init(ssi);
1634 
1635     /* Register a platform device for older bindings or AC97 */
1636     if (ssi->card_name[0]) {
1637         struct device *parent = dev;
1638         /*
1639          * Do not set SSI dev as the parent of AC97 CODEC device since
1640          * it does not have a DT node. Otherwise ASoC core will assume
1641          * CODEC has the same DT node as the SSI, so it may bypass the
1642          * dai_probe() of SSI and then cause NULL DMA data pointers.
1643          */
1644         if (fsl_ssi_is_ac97(ssi))
1645             parent = NULL;
1646 
1647         ssi->card_pdev = platform_device_register_data(parent,
1648                 ssi->card_name, ssi->card_idx, NULL, 0);
1649         if (IS_ERR(ssi->card_pdev)) {
1650             ret = PTR_ERR(ssi->card_pdev);
1651             dev_err(dev, "failed to register %s: %d\n",
1652                 ssi->card_name, ret);
1653             goto error_sound_card;
1654         }
1655     }
1656 
1657     return 0;
1658 
1659 error_sound_card:
1660     fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1661 error_asoc_register:
1662     if (fsl_ssi_is_ac97(ssi))
1663         snd_soc_set_ac97_ops(NULL);
1664 error_ac97_ops:
1665     if (fsl_ssi_is_ac97(ssi))
1666         mutex_destroy(&ssi->ac97_reg_lock);
1667 
1668     if (ssi->soc->imx)
1669         fsl_ssi_imx_clean(pdev, ssi);
1670 
1671     return ret;
1672 }
1673 
1674 static int fsl_ssi_remove(struct platform_device *pdev)
1675 {
1676     struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev);
1677 
1678     fsl_ssi_debugfs_remove(&ssi->dbg_stats);
1679 
1680     if (ssi->card_pdev)
1681         platform_device_unregister(ssi->card_pdev);
1682 
1683     /* Clean up SSI registers */
1684     fsl_ssi_hw_clean(ssi);
1685 
1686     if (ssi->soc->imx)
1687         fsl_ssi_imx_clean(pdev, ssi);
1688 
1689     if (fsl_ssi_is_ac97(ssi)) {
1690         snd_soc_set_ac97_ops(NULL);
1691         mutex_destroy(&ssi->ac97_reg_lock);
1692     }
1693 
1694     return 0;
1695 }
1696 
1697 #ifdef CONFIG_PM_SLEEP
1698 static int fsl_ssi_suspend(struct device *dev)
1699 {
1700     struct fsl_ssi *ssi = dev_get_drvdata(dev);
1701     struct regmap *regs = ssi->regs;
1702 
1703     regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1704     regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1705 
1706     regcache_cache_only(regs, true);
1707     regcache_mark_dirty(regs);
1708 
1709     return 0;
1710 }
1711 
1712 static int fsl_ssi_resume(struct device *dev)
1713 {
1714     struct fsl_ssi *ssi = dev_get_drvdata(dev);
1715     struct regmap *regs = ssi->regs;
1716 
1717     regcache_cache_only(regs, false);
1718 
1719     regmap_update_bits(regs, REG_SSI_SFCSR,
1720                SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
1721                SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
1722                ssi->regcache_sfcsr);
1723     regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1724 
1725     return regcache_sync(regs);
1726 }
1727 #endif /* CONFIG_PM_SLEEP */
1728 
1729 static const struct dev_pm_ops fsl_ssi_pm = {
1730     SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1731 };
1732 
1733 static struct platform_driver fsl_ssi_driver = {
1734     .driver = {
1735         .name = "fsl-ssi-dai",
1736         .of_match_table = fsl_ssi_ids,
1737         .pm = &fsl_ssi_pm,
1738     },
1739     .probe = fsl_ssi_probe,
1740     .remove = fsl_ssi_remove,
1741 };
1742 
1743 module_platform_driver(fsl_ssi_driver);
1744 
1745 MODULE_ALIAS("platform:fsl-ssi-dai");
1746 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1747 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1748 MODULE_LICENSE("GPL v2");
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