soc/fsl/fsl_micfil.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * PDM Microphone Interface for the NXP i.MX SoC
0004  * Copyright 2018 NXP
0005  */
0006
0007 #ifndef _FSL_MICFIL_H
0008 #define _FSL_MICFIL_H
0009
0010 /* MICFIL Register Map */
0011 #define REG_MICFIL_CTRL1        0x00
0012 #define REG_MICFIL_CTRL2        0x04
0013 #define REG_MICFIL_STAT         0x08
0014 #define REG_MICFIL_FIFO_CTRL        0x10
0015 #define REG_MICFIL_FIFO_STAT        0x14
0016 #define REG_MICFIL_DATACH0      0x24
0017 #define REG_MICFIL_DATACH1      0x28
0018 #define REG_MICFIL_DATACH2      0x2C
0019 #define REG_MICFIL_DATACH3      0x30
0020 #define REG_MICFIL_DATACH4      0x34
0021 #define REG_MICFIL_DATACH5      0x38
0022 #define REG_MICFIL_DATACH6      0x3C
0023 #define REG_MICFIL_DATACH7      0x40
0024 #define REG_MICFIL_DC_CTRL      0x64
0025 #define REG_MICFIL_OUT_CTRL     0x74
0026 #define REG_MICFIL_OUT_STAT     0x7C
0027 #define REG_MICFIL_VAD0_CTRL1       0x90
0028 #define REG_MICFIL_VAD0_CTRL2       0x94
0029 #define REG_MICFIL_VAD0_STAT        0x98
0030 #define REG_MICFIL_VAD0_SCONFIG     0x9C
0031 #define REG_MICFIL_VAD0_NCONFIG     0xA0
0032 #define REG_MICFIL_VAD0_NDATA       0xA4
0033 #define REG_MICFIL_VAD0_ZCD     0xA8
0034
0035 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
0036 #define MICFIL_CTRL1_MDIS       BIT(31)
0037 #define MICFIL_CTRL1_DOZEN      BIT(30)
0038 #define MICFIL_CTRL1_PDMIEN     BIT(29)
0039 #define MICFIL_CTRL1_DBG        BIT(28)
0040 #define MICFIL_CTRL1_SRES       BIT(27)
0041 #define MICFIL_CTRL1_DBGE       BIT(26)
0042
0043 #define MICFIL_CTRL1_DISEL_DISABLE  0
0044 #define MICFIL_CTRL1_DISEL_DMA      1
0045 #define MICFIL_CTRL1_DISEL_IRQ      2
0046 #define MICFIL_CTRL1_DISEL      GENMASK(25, 24)
0047 #define MICFIL_CTRL1_ERREN      BIT(23)
0048 #define MICFIL_CTRL1_CHEN(ch)       BIT(ch)
0049
0050 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
0051 #define MICFIL_CTRL2_QSEL_SHIFT     25
0052 #define MICFIL_CTRL2_QSEL       GENMASK(27, 25)
0053 #define MICFIL_QSEL_MEDIUM_QUALITY  0
0054 #define MICFIL_QSEL_HIGH_QUALITY    1
0055 #define MICFIL_QSEL_LOW_QUALITY     7
0056 #define MICFIL_QSEL_VLOW0_QUALITY   6
0057 #define MICFIL_QSEL_VLOW1_QUALITY   5
0058 #define MICFIL_QSEL_VLOW2_QUALITY   4
0059
0060 #define MICFIL_CTRL2_CICOSR     GENMASK(19, 16)
0061 #define MICFIL_CTRL2_CLKDIV     GENMASK(7, 0)
0062
0063 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
0064 #define MICFIL_STAT_BSY_FIL     BIT(31)
0065 #define MICFIL_STAT_FIR_RDY     BIT(30)
0066 #define MICFIL_STAT_LOWFREQF        BIT(29)
0067 #define MICFIL_STAT_CHXF(ch)        BIT(ch)
0068
0069 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
0070 #define MICFIL_FIFO_CTRL_FIFOWMK    GENMASK(2, 0)
0071
0072 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
0073 #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
0074 #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)    BIT((ch) + 8)
0075
0076 /* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
0077 #define MICFIL_DC_CTRL_CONFIG          GENMASK(15, 0)
0078 #define MICFIL_DC_CHX_SHIFT(ch)        ((ch) << 1)
0079 #define MICFIL_DC_CHX(ch)              GENMASK((((ch) << 1) + 1), ((ch) << 1))
0080 #define MICFIL_DC_CUTOFF_21HZ          0
0081 #define MICFIL_DC_CUTOFF_83HZ          1
0082 #define MICFIL_DC_CUTOFF_152Hz         2
0083 #define MICFIL_DC_BYPASS               3
0084
0085 /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
0086 #define MICFIL_VAD0_CTRL1_CHSEL     GENMASK(26, 24)
0087 #define MICFIL_VAD0_CTRL1_CICOSR    GENMASK(19, 16)
0088 #define MICFIL_VAD0_CTRL1_INITT     GENMASK(12, 8)
0089 #define MICFIL_VAD0_CTRL1_ST10      BIT(4)
0090 #define MICFIL_VAD0_CTRL1_ERIE      BIT(3)
0091 #define MICFIL_VAD0_CTRL1_IE        BIT(2)
0092 #define MICFIL_VAD0_CTRL1_RST       BIT(1)
0093 #define MICFIL_VAD0_CTRL1_EN        BIT(0)
0094
0095 /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
0096 #define MICFIL_VAD0_CTRL2_FRENDIS   BIT(31)
0097 #define MICFIL_VAD0_CTRL2_PREFEN    BIT(30)
0098 #define MICFIL_VAD0_CTRL2_FOUTDIS   BIT(28)
0099 #define MICFIL_VAD0_CTRL2_FRAMET    GENMASK(21, 16)
0100 #define MICFIL_VAD0_CTRL2_INPGAIN   GENMASK(11, 8)
0101 #define MICFIL_VAD0_CTRL2_HPF       GENMASK(1, 0)
0102
0103 /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
0104 #define MICFIL_VAD0_SCONFIG_SFILEN      BIT(31)
0105 #define MICFIL_VAD0_SCONFIG_SMAXEN      BIT(30)
0106 #define MICFIL_VAD0_SCONFIG_SGAIN       GENMASK(3, 0)
0107
0108 /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
0109 #define MICFIL_VAD0_NCONFIG_NFILAUT     BIT(31)
0110 #define MICFIL_VAD0_NCONFIG_NMINEN      BIT(30)
0111 #define MICFIL_VAD0_NCONFIG_NDECEN      BIT(29)
0112 #define MICFIL_VAD0_NCONFIG_NOREN       BIT(28)
0113 #define MICFIL_VAD0_NCONFIG_NFILADJ     GENMASK(12, 8)
0114 #define MICFIL_VAD0_NCONFIG_NGAIN       GENMASK(3, 0)
0115
0116 /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
0117 #define MICFIL_VAD0_ZCD_ZCDTH       GENMASK(25, 16)
0118 #define MICFIL_VAD0_ZCD_ZCDADJ      GENMASK(11, 8)
0119 #define MICFIL_VAD0_ZCD_ZCDAND      BIT(4)
0120 #define MICFIL_VAD0_ZCD_ZCDAUT      BIT(2)
0121 #define MICFIL_VAD0_ZCD_ZCDEN       BIT(0)
0122
0123 /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
0124 #define MICFIL_VAD0_STAT_INITF      BIT(31)
0125 #define MICFIL_VAD0_STAT_INSATF     BIT(16)
0126 #define MICFIL_VAD0_STAT_EF     BIT(15)
0127 #define MICFIL_VAD0_STAT_IF     BIT(0)
0128
0129 /* MICFIL Output Control Register */
0130 #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
0131
0132 /* Constants */
0133 #define MICFIL_OUTPUT_CHANNELS      8
0134 #define MICFIL_FIFO_NUM         8
0135
0136 #define FIFO_PTRWID         3
0137 #define FIFO_LEN            BIT(FIFO_PTRWID)
0138
0139 #define MICFIL_IRQ_LINES        2
0140 #define MICFIL_MAX_RETRY        25
0141 #define MICFIL_SLEEP_MIN        90000 /* in us */
0142 #define MICFIL_SLEEP_MAX        100000 /* in us */
0143 #define MICFIL_DMA_MAXBURST_RX      6
0144
0145 #endif /* _FSL_MICFIL_H */