soc/fsl/fsl_dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
0004  */
0005
0006 #ifndef _MPC8610_PCM_H
0007 #define _MPC8610_PCM_H
0008
0009 struct ccsr_dma {
0010     u8 res0[0x100];
0011     struct ccsr_dma_channel {
0012         __be32 mr;      /* Mode register */
0013         __be32 sr;      /* Status register */
0014         __be32 eclndar; /* Current link descriptor extended addr reg */
0015         __be32 clndar;  /* Current link descriptor address register */
0016         __be32 satr;    /* Source attributes register */
0017         __be32 sar;     /* Source address register */
0018         __be32 datr;    /* Destination attributes register */
0019         __be32 dar;     /* Destination address register */
0020         __be32 bcr;     /* Byte count register */
0021         __be32 enlndar; /* Next link descriptor extended address reg */
0022         __be32 nlndar;  /* Next link descriptor address register */
0023         u8 res1[4];
0024         __be32 eclsdar; /* Current list descriptor extended addr reg */
0025         __be32 clsdar;  /* Current list descriptor address register */
0026         __be32 enlsdar; /* Next list descriptor extended address reg */
0027         __be32 nlsdar;  /* Next list descriptor address register */
0028         __be32 ssr;     /* Source stride register */
0029         __be32 dsr;     /* Destination stride register */
0030         u8 res2[0x38];
0031     } channel[4];
0032     __be32 dgsr;
0033 };
0034
0035 #define CCSR_DMA_MR_BWC_DISABLED    0x0F000000
0036 #define CCSR_DMA_MR_BWC_SHIFT       24
0037 #define CCSR_DMA_MR_BWC_MASK        0x0F000000
0038 #define CCSR_DMA_MR_BWC(x) \
0039     ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)
0040 #define CCSR_DMA_MR_EMP_EN          0x00200000
0041 #define CCSR_DMA_MR_EMS_EN          0x00040000
0042 #define CCSR_DMA_MR_DAHTS_MASK      0x00030000
0043 #define CCSR_DMA_MR_DAHTS_1         0x00000000
0044 #define CCSR_DMA_MR_DAHTS_2         0x00010000
0045 #define CCSR_DMA_MR_DAHTS_4         0x00020000
0046 #define CCSR_DMA_MR_DAHTS_8         0x00030000
0047 #define CCSR_DMA_MR_SAHTS_MASK      0x0000C000
0048 #define CCSR_DMA_MR_SAHTS_1         0x00000000
0049 #define CCSR_DMA_MR_SAHTS_2         0x00004000
0050 #define CCSR_DMA_MR_SAHTS_4         0x00008000
0051 #define CCSR_DMA_MR_SAHTS_8         0x0000C000
0052 #define CCSR_DMA_MR_DAHE        0x00002000
0053 #define CCSR_DMA_MR_SAHE        0x00001000
0054 #define CCSR_DMA_MR_SRW         0x00000400
0055 #define CCSR_DMA_MR_EOSIE           0x00000200
0056 #define CCSR_DMA_MR_EOLNIE          0x00000100
0057 #define CCSR_DMA_MR_EOLSIE          0x00000080
0058 #define CCSR_DMA_MR_EIE         0x00000040
0059 #define CCSR_DMA_MR_XFE         0x00000020
0060 #define CCSR_DMA_MR_CDSM_SWSM       0x00000010
0061 #define CCSR_DMA_MR_CA          0x00000008
0062 #define CCSR_DMA_MR_CTM         0x00000004
0063 #define CCSR_DMA_MR_CC          0x00000002
0064 #define CCSR_DMA_MR_CS          0x00000001
0065
0066 #define CCSR_DMA_SR_TE          0x00000080
0067 #define CCSR_DMA_SR_CH          0x00000020
0068 #define CCSR_DMA_SR_PE          0x00000010
0069 #define CCSR_DMA_SR_EOLNI           0x00000008
0070 #define CCSR_DMA_SR_CB          0x00000004
0071 #define CCSR_DMA_SR_EOSI        0x00000002
0072 #define CCSR_DMA_SR_EOLSI           0x00000001
0073
0074 /* ECLNDAR takes bits 32-36 of the CLNDAR register */
0075 static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)
0076 {
0077     return (x >> 32) & 0xf;
0078 }
0079
0080 #define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)
0081 #define CCSR_DMA_CLNDAR_EOSIE       0x00000008
0082
0083 /* SATR and DATR, combined */
0084 #define CCSR_DMA_ATR_PBATMU         0x20000000
0085 #define CCSR_DMA_ATR_TFLOWLVL_0     0x00000000
0086 #define CCSR_DMA_ATR_TFLOWLVL_1     0x06000000
0087 #define CCSR_DMA_ATR_TFLOWLVL_2     0x08000000
0088 #define CCSR_DMA_ATR_TFLOWLVL_3     0x0C000000
0089 #define CCSR_DMA_ATR_PCIORDER       0x02000000
0090 #define CCSR_DMA_ATR_SME        0x01000000
0091 #define CCSR_DMA_ATR_NOSNOOP        0x00040000
0092 #define CCSR_DMA_ATR_SNOOP          0x00050000
0093 #define CCSR_DMA_ATR_ESAD_MASK      0x0000000F
0094
0095 /**
0096  *  List Descriptor for extended chaining mode DMA operations.
0097  *
0098  *  The CLSDAR register points to the first (in a linked-list) List
0099  *  Descriptor.  Each object must be aligned on a 32-byte boundary. Each
0100  *  list descriptor points to a linked-list of link Descriptors.
0101  */
0102 struct fsl_dma_list_descriptor {
0103     __be64 next;        /* Address of next list descriptor */
0104     __be64 first_link;      /* Address of first link descriptor */
0105     __be32 source;      /* Source stride */
0106     __be32 dest;        /* Destination stride */
0107     u8 res[8];          /* Reserved */
0108 } __attribute__ ((aligned(32), packed));
0109
0110 /**
0111  *  Link Descriptor for basic and extended chaining mode DMA operations.
0112  *
0113  *  A Link Descriptor points to a single DMA buffer.  Each link descriptor
0114  *  must be aligned on a 32-byte boundary.
0115  */
0116 struct fsl_dma_link_descriptor {
0117     __be32 source_attr;     /* Programmed into SATR register */
0118     __be32 source_addr;     /* Programmed into SAR register */
0119     __be32 dest_attr;       /* Programmed into DATR register */
0120     __be32 dest_addr;       /* Programmed into DAR register */
0121     __be64 next;    /* Address of next link descriptor */
0122     __be32 count;   /* Byte count */
0123     u8 res[4];      /* Reserved */
0124 } __attribute__ ((aligned(32), packed));
0125
0126 #endif