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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Freescale DMA ALSA SoC PCM driver
0004 //
0005 // Author: Timur Tabi <timur@freescale.com>
0006 //
0007 // Copyright 2007-2010 Freescale Semiconductor, Inc.
0008 //
0009 // This driver implements ASoC support for the Elo DMA controller, which is
0010 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
0011 // the PCM driver is what handles the DMA buffer.
0012 
0013 #include <linux/module.h>
0014 #include <linux/init.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/delay.h>
0019 #include <linux/gfp.h>
0020 #include <linux/of_address.h>
0021 #include <linux/of_irq.h>
0022 #include <linux/of_platform.h>
0023 #include <linux/list.h>
0024 #include <linux/slab.h>
0025 
0026 #include <sound/core.h>
0027 #include <sound/pcm.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/soc.h>
0030 
0031 #include <asm/io.h>
0032 
0033 #include "fsl_dma.h"
0034 #include "fsl_ssi.h"    /* For the offset of stx0 and srx0 */
0035 
0036 #define DRV_NAME "fsl_dma"
0037 
0038 /*
0039  * The formats that the DMA controller supports, which is anything
0040  * that is 8, 16, or 32 bits.
0041  */
0042 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8     | \
0043                 SNDRV_PCM_FMTBIT_U8     | \
0044                 SNDRV_PCM_FMTBIT_S16_LE     | \
0045                 SNDRV_PCM_FMTBIT_S16_BE     | \
0046                 SNDRV_PCM_FMTBIT_U16_LE     | \
0047                 SNDRV_PCM_FMTBIT_U16_BE     | \
0048                 SNDRV_PCM_FMTBIT_S24_LE     | \
0049                 SNDRV_PCM_FMTBIT_S24_BE     | \
0050                 SNDRV_PCM_FMTBIT_U24_LE     | \
0051                 SNDRV_PCM_FMTBIT_U24_BE     | \
0052                 SNDRV_PCM_FMTBIT_S32_LE     | \
0053                 SNDRV_PCM_FMTBIT_S32_BE     | \
0054                 SNDRV_PCM_FMTBIT_U32_LE     | \
0055                 SNDRV_PCM_FMTBIT_U32_BE)
0056 struct dma_object {
0057     struct snd_soc_component_driver dai;
0058     dma_addr_t ssi_stx_phys;
0059     dma_addr_t ssi_srx_phys;
0060     unsigned int ssi_fifo_depth;
0061     struct ccsr_dma_channel __iomem *channel;
0062     unsigned int irq;
0063     bool assigned;
0064 };
0065 
0066 /*
0067  * The number of DMA links to use.  Two is the bare minimum, but if you
0068  * have really small links you might need more.
0069  */
0070 #define NUM_DMA_LINKS   2
0071 
0072 /** fsl_dma_private: p-substream DMA data
0073  *
0074  * Each substream has a 1-to-1 association with a DMA channel.
0075  *
0076  * The link[] array is first because it needs to be aligned on a 32-byte
0077  * boundary, so putting it first will ensure alignment without padding the
0078  * structure.
0079  *
0080  * @link[]: array of link descriptors
0081  * @dma_channel: pointer to the DMA channel's registers
0082  * @irq: IRQ for this DMA channel
0083  * @substream: pointer to the substream object, needed by the ISR
0084  * @ssi_sxx_phys: bus address of the STX or SRX register to use
0085  * @ld_buf_phys: physical address of the LD buffer
0086  * @current_link: index into link[] of the link currently being processed
0087  * @dma_buf_phys: physical address of the DMA buffer
0088  * @dma_buf_next: physical address of the next period to process
0089  * @dma_buf_end: physical address of the byte after the end of the DMA
0090  * @buffer period_size: the size of a single period
0091  * @num_periods: the number of periods in the DMA buffer
0092  */
0093 struct fsl_dma_private {
0094     struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
0095     struct ccsr_dma_channel __iomem *dma_channel;
0096     unsigned int irq;
0097     struct snd_pcm_substream *substream;
0098     dma_addr_t ssi_sxx_phys;
0099     unsigned int ssi_fifo_depth;
0100     dma_addr_t ld_buf_phys;
0101     unsigned int current_link;
0102     dma_addr_t dma_buf_phys;
0103     dma_addr_t dma_buf_next;
0104     dma_addr_t dma_buf_end;
0105     size_t period_size;
0106     unsigned int num_periods;
0107 };
0108 
0109 /**
0110  * fsl_dma_hardare: define characteristics of the PCM hardware.
0111  *
0112  * The PCM hardware is the Freescale DMA controller.  This structure defines
0113  * the capabilities of that hardware.
0114  *
0115  * Since the sampling rate and data format are not controlled by the DMA
0116  * controller, we specify no limits for those values.  The only exception is
0117  * period_bytes_min, which is set to a reasonably low value to prevent the
0118  * DMA controller from generating too many interrupts per second.
0119  *
0120  * Since each link descriptor has a 32-bit byte count field, we set
0121  * period_bytes_max to the largest 32-bit number.  We also have no maximum
0122  * number of periods.
0123  *
0124  * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
0125  * limitation in the SSI driver requires the sample rates for playback and
0126  * capture to be the same.
0127  */
0128 static const struct snd_pcm_hardware fsl_dma_hardware = {
0129 
0130     .info           = SNDRV_PCM_INFO_INTERLEAVED |
0131                   SNDRV_PCM_INFO_MMAP |
0132                   SNDRV_PCM_INFO_MMAP_VALID |
0133                   SNDRV_PCM_INFO_JOINT_DUPLEX |
0134                   SNDRV_PCM_INFO_PAUSE,
0135     .formats        = FSLDMA_PCM_FORMATS,
0136     .period_bytes_min       = 512,      /* A reasonable limit */
0137     .period_bytes_max       = (u32) -1,
0138     .periods_min        = NUM_DMA_LINKS,
0139     .periods_max        = (unsigned int) -1,
0140     .buffer_bytes_max       = 128 * 1024,   /* A reasonable limit */
0141 };
0142 
0143 /**
0144  * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
0145  *
0146  * This function should be called by the ISR whenever the DMA controller
0147  * halts data transfer.
0148  */
0149 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
0150 {
0151     snd_pcm_stop_xrun(substream);
0152 }
0153 
0154 /**
0155  * fsl_dma_update_pointers - update LD pointers to point to the next period
0156  *
0157  * As each period is completed, this function changes the link
0158  * descriptor pointers for that period to point to the next period.
0159  */
0160 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
0161 {
0162     struct fsl_dma_link_descriptor *link =
0163         &dma_private->link[dma_private->current_link];
0164 
0165     /* Update our link descriptors to point to the next period. On a 36-bit
0166      * system, we also need to update the ESAD bits.  We also set (keep) the
0167      * snoop bits.  See the comments in fsl_dma_hw_params() about snooping.
0168      */
0169     if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0170         link->source_addr = cpu_to_be32(dma_private->dma_buf_next);
0171 #ifdef CONFIG_PHYS_64BIT
0172         link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
0173             upper_32_bits(dma_private->dma_buf_next));
0174 #endif
0175     } else {
0176         link->dest_addr = cpu_to_be32(dma_private->dma_buf_next);
0177 #ifdef CONFIG_PHYS_64BIT
0178         link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
0179             upper_32_bits(dma_private->dma_buf_next));
0180 #endif
0181     }
0182 
0183     /* Update our variables for next time */
0184     dma_private->dma_buf_next += dma_private->period_size;
0185 
0186     if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
0187         dma_private->dma_buf_next = dma_private->dma_buf_phys;
0188 
0189     if (++dma_private->current_link >= NUM_DMA_LINKS)
0190         dma_private->current_link = 0;
0191 }
0192 
0193 /**
0194  * fsl_dma_isr: interrupt handler for the DMA controller
0195  *
0196  * @irq: IRQ of the DMA channel
0197  * @dev_id: pointer to the dma_private structure for this DMA channel
0198  */
0199 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
0200 {
0201     struct fsl_dma_private *dma_private = dev_id;
0202     struct snd_pcm_substream *substream = dma_private->substream;
0203     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0204     struct device *dev = rtd->dev;
0205     struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
0206     irqreturn_t ret = IRQ_NONE;
0207     u32 sr, sr2 = 0;
0208 
0209     /* We got an interrupt, so read the status register to see what we
0210        were interrupted for.
0211      */
0212     sr = in_be32(&dma_channel->sr);
0213 
0214     if (sr & CCSR_DMA_SR_TE) {
0215         dev_err(dev, "dma transmit error\n");
0216         fsl_dma_abort_stream(substream);
0217         sr2 |= CCSR_DMA_SR_TE;
0218         ret = IRQ_HANDLED;
0219     }
0220 
0221     if (sr & CCSR_DMA_SR_CH)
0222         ret = IRQ_HANDLED;
0223 
0224     if (sr & CCSR_DMA_SR_PE) {
0225         dev_err(dev, "dma programming error\n");
0226         fsl_dma_abort_stream(substream);
0227         sr2 |= CCSR_DMA_SR_PE;
0228         ret = IRQ_HANDLED;
0229     }
0230 
0231     if (sr & CCSR_DMA_SR_EOLNI) {
0232         sr2 |= CCSR_DMA_SR_EOLNI;
0233         ret = IRQ_HANDLED;
0234     }
0235 
0236     if (sr & CCSR_DMA_SR_CB)
0237         ret = IRQ_HANDLED;
0238 
0239     if (sr & CCSR_DMA_SR_EOSI) {
0240         /* Tell ALSA we completed a period. */
0241         snd_pcm_period_elapsed(substream);
0242 
0243         /*
0244          * Update our link descriptors to point to the next period. We
0245          * only need to do this if the number of periods is not equal to
0246          * the number of links.
0247          */
0248         if (dma_private->num_periods != NUM_DMA_LINKS)
0249             fsl_dma_update_pointers(dma_private);
0250 
0251         sr2 |= CCSR_DMA_SR_EOSI;
0252         ret = IRQ_HANDLED;
0253     }
0254 
0255     if (sr & CCSR_DMA_SR_EOLSI) {
0256         sr2 |= CCSR_DMA_SR_EOLSI;
0257         ret = IRQ_HANDLED;
0258     }
0259 
0260     /* Clear the bits that we set */
0261     if (sr2)
0262         out_be32(&dma_channel->sr, sr2);
0263 
0264     return ret;
0265 }
0266 
0267 /**
0268  * fsl_dma_new: initialize this PCM driver.
0269  *
0270  * This function is called when the codec driver calls snd_soc_new_pcms(),
0271  * once for each .dai_link in the machine driver's snd_soc_card
0272  * structure.
0273  *
0274  * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which
0275  * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM
0276  * is specified. Therefore, any DMA buffers we allocate will always be in low
0277  * memory, but we support for 36-bit physical addresses anyway.
0278  *
0279  * Regardless of where the memory is actually allocated, since the device can
0280  * technically DMA to any 36-bit address, we do need to set the DMA mask to 36.
0281  */
0282 static int fsl_dma_new(struct snd_soc_component *component,
0283                struct snd_soc_pcm_runtime *rtd)
0284 {
0285     struct snd_card *card = rtd->card->snd_card;
0286     struct snd_pcm *pcm = rtd->pcm;
0287     int ret;
0288 
0289     ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(36));
0290     if (ret)
0291         return ret;
0292 
0293     return snd_pcm_set_fixed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
0294                         card->dev,
0295                         fsl_dma_hardware.buffer_bytes_max);
0296 }
0297 
0298 /**
0299  * fsl_dma_open: open a new substream.
0300  *
0301  * Each substream has its own DMA buffer.
0302  *
0303  * ALSA divides the DMA buffer into N periods.  We create NUM_DMA_LINKS link
0304  * descriptors that ping-pong from one period to the next.  For example, if
0305  * there are six periods and two link descriptors, this is how they look
0306  * before playback starts:
0307  *
0308  *             The last link descriptor
0309  *   ____________  points back to the first
0310  *  |        |
0311  *  V        |
0312  *  ___    ___   |
0313  * |   |->|   |->|
0314  * |___|  |___|
0315  *   |      |
0316  *   |      |
0317  *   V      V
0318  *  _________________________________________
0319  * |      |      |      |      |      |      |  The DMA buffer is
0320  * |      |      |      |      |      |      |    divided into 6 parts
0321  * |______|______|______|______|______|______|
0322  *
0323  * and here's how they look after the first period is finished playing:
0324  *
0325  *   ____________
0326  *  |        |
0327  *  V        |
0328  *  ___    ___   |
0329  * |   |->|   |->|
0330  * |___|  |___|
0331  *   |      |
0332  *   |______________
0333  *          |       |
0334  *          V       V
0335  *  _________________________________________
0336  * |      |      |      |      |      |      |
0337  * |      |      |      |      |      |      |
0338  * |______|______|______|______|______|______|
0339  *
0340  * The first link descriptor now points to the third period.  The DMA
0341  * controller is currently playing the second period.  When it finishes, it
0342  * will jump back to the first descriptor and play the third period.
0343  *
0344  * There are four reasons we do this:
0345  *
0346  * 1. The only way to get the DMA controller to automatically restart the
0347  *    transfer when it gets to the end of the buffer is to use chaining
0348  *    mode.  Basic direct mode doesn't offer that feature.
0349  * 2. We need to receive an interrupt at the end of every period.  The DMA
0350  *    controller can generate an interrupt at the end of every link transfer
0351  *    (aka segment).  Making each period into a DMA segment will give us the
0352  *    interrupts we need.
0353  * 3. By creating only two link descriptors, regardless of the number of
0354  *    periods, we do not need to reallocate the link descriptors if the
0355  *    number of periods changes.
0356  * 4. All of the audio data is still stored in a single, contiguous DMA
0357  *    buffer, which is what ALSA expects.  We're just dividing it into
0358  *    contiguous parts, and creating a link descriptor for each one.
0359  */
0360 static int fsl_dma_open(struct snd_soc_component *component,
0361             struct snd_pcm_substream *substream)
0362 {
0363     struct snd_pcm_runtime *runtime = substream->runtime;
0364     struct device *dev = component->dev;
0365     struct dma_object *dma =
0366         container_of(component->driver, struct dma_object, dai);
0367     struct fsl_dma_private *dma_private;
0368     struct ccsr_dma_channel __iomem *dma_channel;
0369     dma_addr_t ld_buf_phys;
0370     u64 temp_link;      /* Pointer to next link descriptor */
0371     u32 mr;
0372     int ret = 0;
0373     unsigned int i;
0374 
0375     /*
0376      * Reject any DMA buffer whose size is not a multiple of the period
0377      * size.  We need to make sure that the DMA buffer can be evenly divided
0378      * into periods.
0379      */
0380     ret = snd_pcm_hw_constraint_integer(runtime,
0381         SNDRV_PCM_HW_PARAM_PERIODS);
0382     if (ret < 0) {
0383         dev_err(dev, "invalid buffer size\n");
0384         return ret;
0385     }
0386 
0387     if (dma->assigned) {
0388         dev_err(dev, "dma channel already assigned\n");
0389         return -EBUSY;
0390     }
0391 
0392     dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private),
0393                      &ld_buf_phys, GFP_KERNEL);
0394     if (!dma_private) {
0395         dev_err(dev, "can't allocate dma private data\n");
0396         return -ENOMEM;
0397     }
0398     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0399         dma_private->ssi_sxx_phys = dma->ssi_stx_phys;
0400     else
0401         dma_private->ssi_sxx_phys = dma->ssi_srx_phys;
0402 
0403     dma_private->ssi_fifo_depth = dma->ssi_fifo_depth;
0404     dma_private->dma_channel = dma->channel;
0405     dma_private->irq = dma->irq;
0406     dma_private->substream = substream;
0407     dma_private->ld_buf_phys = ld_buf_phys;
0408     dma_private->dma_buf_phys = substream->dma_buffer.addr;
0409 
0410     ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "fsldma-audio",
0411               dma_private);
0412     if (ret) {
0413         dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
0414             dma_private->irq, ret);
0415         dma_free_coherent(dev, sizeof(struct fsl_dma_private),
0416             dma_private, dma_private->ld_buf_phys);
0417         return ret;
0418     }
0419 
0420     dma->assigned = true;
0421 
0422     snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
0423     runtime->private_data = dma_private;
0424 
0425     /* Program the fixed DMA controller parameters */
0426 
0427     dma_channel = dma_private->dma_channel;
0428 
0429     temp_link = dma_private->ld_buf_phys +
0430         sizeof(struct fsl_dma_link_descriptor);
0431 
0432     for (i = 0; i < NUM_DMA_LINKS; i++) {
0433         dma_private->link[i].next = cpu_to_be64(temp_link);
0434 
0435         temp_link += sizeof(struct fsl_dma_link_descriptor);
0436     }
0437     /* The last link descriptor points to the first */
0438     dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
0439 
0440     /* Tell the DMA controller where the first link descriptor is */
0441     out_be32(&dma_channel->clndar,
0442         CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
0443     out_be32(&dma_channel->eclndar,
0444         CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
0445 
0446     /* The manual says the BCR must be clear before enabling EMP */
0447     out_be32(&dma_channel->bcr, 0);
0448 
0449     /*
0450      * Program the mode register for interrupts, external master control,
0451      * and source/destination hold.  Also clear the Channel Abort bit.
0452      */
0453     mr = in_be32(&dma_channel->mr) &
0454         ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
0455 
0456     /*
0457      * We want External Master Start and External Master Pause enabled,
0458      * because the SSI is controlling the DMA controller.  We want the DMA
0459      * controller to be set up in advance, and then we signal only the SSI
0460      * to start transferring.
0461      *
0462      * We want End-Of-Segment Interrupts enabled, because this will generate
0463      * an interrupt at the end of each segment (each link descriptor
0464      * represents one segment).  Each DMA segment is the same thing as an
0465      * ALSA period, so this is how we get an interrupt at the end of every
0466      * period.
0467      *
0468      * We want Error Interrupt enabled, so that we can get an error if
0469      * the DMA controller is mis-programmed somehow.
0470      */
0471     mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
0472         CCSR_DMA_MR_EMS_EN;
0473 
0474     /* For playback, we want the destination address to be held.  For
0475        capture, set the source address to be held. */
0476     mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
0477         CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
0478 
0479     out_be32(&dma_channel->mr, mr);
0480 
0481     return 0;
0482 }
0483 
0484 /**
0485  * fsl_dma_hw_params: continue initializing the DMA links
0486  *
0487  * This function obtains hardware parameters about the opened stream and
0488  * programs the DMA controller accordingly.
0489  *
0490  * One drawback of big-endian is that when copying integers of different
0491  * sizes to a fixed-sized register, the address to which the integer must be
0492  * copied is dependent on the size of the integer.
0493  *
0494  * For example, if P is the address of a 32-bit register, and X is a 32-bit
0495  * integer, then X should be copied to address P.  However, if X is a 16-bit
0496  * integer, then it should be copied to P+2.  If X is an 8-bit register,
0497  * then it should be copied to P+3.
0498  *
0499  * So for playback of 8-bit samples, the DMA controller must transfer single
0500  * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
0501  * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
0502  *
0503  * For 24-bit samples, the offset is 1 byte.  However, the DMA controller
0504  * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
0505  * and 8 bytes at a time).  So we do not support packed 24-bit samples.
0506  * 24-bit data must be padded to 32 bits.
0507  */
0508 static int fsl_dma_hw_params(struct snd_soc_component *component,
0509                  struct snd_pcm_substream *substream,
0510                  struct snd_pcm_hw_params *hw_params)
0511 {
0512     struct snd_pcm_runtime *runtime = substream->runtime;
0513     struct fsl_dma_private *dma_private = runtime->private_data;
0514     struct device *dev = component->dev;
0515 
0516     /* Number of bits per sample */
0517     unsigned int sample_bits =
0518         snd_pcm_format_physical_width(params_format(hw_params));
0519 
0520     /* Number of bytes per frame */
0521     unsigned int sample_bytes = sample_bits / 8;
0522 
0523     /* Bus address of SSI STX register */
0524     dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
0525 
0526     /* Size of the DMA buffer, in bytes */
0527     size_t buffer_size = params_buffer_bytes(hw_params);
0528 
0529     /* Number of bytes per period */
0530     size_t period_size = params_period_bytes(hw_params);
0531 
0532     /* Pointer to next period */
0533     dma_addr_t temp_addr = substream->dma_buffer.addr;
0534 
0535     /* Pointer to DMA controller */
0536     struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
0537 
0538     u32 mr; /* DMA Mode Register */
0539 
0540     unsigned int i;
0541 
0542     /* Initialize our DMA tracking variables */
0543     dma_private->period_size = period_size;
0544     dma_private->num_periods = params_periods(hw_params);
0545     dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
0546     dma_private->dma_buf_next = dma_private->dma_buf_phys +
0547         (NUM_DMA_LINKS * period_size);
0548 
0549     if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
0550         /* This happens if the number of periods == NUM_DMA_LINKS */
0551         dma_private->dma_buf_next = dma_private->dma_buf_phys;
0552 
0553     mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
0554           CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
0555 
0556     /* Due to a quirk of the SSI's STX register, the target address
0557      * for the DMA operations depends on the sample size.  So we calculate
0558      * that offset here.  While we're at it, also tell the DMA controller
0559      * how much data to transfer per sample.
0560      */
0561     switch (sample_bits) {
0562     case 8:
0563         mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
0564         ssi_sxx_phys += 3;
0565         break;
0566     case 16:
0567         mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
0568         ssi_sxx_phys += 2;
0569         break;
0570     case 32:
0571         mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
0572         break;
0573     default:
0574         /* We should never get here */
0575         dev_err(dev, "unsupported sample size %u\n", sample_bits);
0576         return -EINVAL;
0577     }
0578 
0579     /*
0580      * BWC determines how many bytes are sent/received before the DMA
0581      * controller checks the SSI to see if it needs to stop. BWC should
0582      * always be a multiple of the frame size, so that we always transmit
0583      * whole frames.  Each frame occupies two slots in the FIFO.  The
0584      * parameter for CCSR_DMA_MR_BWC() is rounded down the next power of two
0585      * (MR[BWC] can only represent even powers of two).
0586      *
0587      * To simplify the process, we set BWC to the largest value that is
0588      * less than or equal to the FIFO watermark.  For playback, this ensures
0589      * that we transfer the maximum amount without overrunning the FIFO.
0590      * For capture, this ensures that we transfer the maximum amount without
0591      * underrunning the FIFO.
0592      *
0593      * f = SSI FIFO depth
0594      * w = SSI watermark value (which equals f - 2)
0595      * b = DMA bandwidth count (in bytes)
0596      * s = sample size (in bytes, which equals frame_size * 2)
0597      *
0598      * For playback, we never transmit more than the transmit FIFO
0599      * watermark, otherwise we might write more data than the FIFO can hold.
0600      * The watermark is equal to the FIFO depth minus two.
0601      *
0602      * For capture, two equations must hold:
0603      *  w > f - (b / s)
0604      *  w >= b / s
0605      *
0606      * So, b > 2 * s, but b must also be <= s * w.  To simplify, we set
0607      * b = s * w, which is equal to
0608      *      (dma_private->ssi_fifo_depth - 2) * sample_bytes.
0609      */
0610     mr |= CCSR_DMA_MR_BWC((dma_private->ssi_fifo_depth - 2) * sample_bytes);
0611 
0612     out_be32(&dma_channel->mr, mr);
0613 
0614     for (i = 0; i < NUM_DMA_LINKS; i++) {
0615         struct fsl_dma_link_descriptor *link = &dma_private->link[i];
0616 
0617         link->count = cpu_to_be32(period_size);
0618 
0619         /* The snoop bit tells the DMA controller whether it should tell
0620          * the ECM to snoop during a read or write to an address. For
0621          * audio, we use DMA to transfer data between memory and an I/O
0622          * device (the SSI's STX0 or SRX0 register). Snooping is only
0623          * needed if there is a cache, so we need to snoop memory
0624          * addresses only.  For playback, that means we snoop the source
0625          * but not the destination.  For capture, we snoop the
0626          * destination but not the source.
0627          *
0628          * Note that failing to snoop properly is unlikely to cause
0629          * cache incoherency if the period size is larger than the
0630          * size of L1 cache.  This is because filling in one period will
0631          * flush out the data for the previous period.  So if you
0632          * increased period_bytes_min to a large enough size, you might
0633          * get more performance by not snooping, and you'll still be
0634          * okay.  You'll need to update fsl_dma_update_pointers() also.
0635          */
0636         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0637             link->source_addr = cpu_to_be32(temp_addr);
0638             link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
0639                 upper_32_bits(temp_addr));
0640 
0641             link->dest_addr = cpu_to_be32(ssi_sxx_phys);
0642             link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
0643                 upper_32_bits(ssi_sxx_phys));
0644         } else {
0645             link->source_addr = cpu_to_be32(ssi_sxx_phys);
0646             link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP |
0647                 upper_32_bits(ssi_sxx_phys));
0648 
0649             link->dest_addr = cpu_to_be32(temp_addr);
0650             link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP |
0651                 upper_32_bits(temp_addr));
0652         }
0653 
0654         temp_addr += period_size;
0655     }
0656 
0657     return 0;
0658 }
0659 
0660 /**
0661  * fsl_dma_pointer: determine the current position of the DMA transfer
0662  *
0663  * This function is called by ALSA when ALSA wants to know where in the
0664  * stream buffer the hardware currently is.
0665  *
0666  * For playback, the SAR register contains the physical address of the most
0667  * recent DMA transfer.  For capture, the value is in the DAR register.
0668  *
0669  * The base address of the buffer is stored in the source_addr field of the
0670  * first link descriptor.
0671  */
0672 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_soc_component *component,
0673                      struct snd_pcm_substream *substream)
0674 {
0675     struct snd_pcm_runtime *runtime = substream->runtime;
0676     struct fsl_dma_private *dma_private = runtime->private_data;
0677     struct device *dev = component->dev;
0678     struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
0679     dma_addr_t position;
0680     snd_pcm_uframes_t frames;
0681 
0682     /* Obtain the current DMA pointer, but don't read the ESAD bits if we
0683      * only have 32-bit DMA addresses.  This function is typically called
0684      * in interrupt context, so we need to optimize it.
0685      */
0686     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0687         position = in_be32(&dma_channel->sar);
0688 #ifdef CONFIG_PHYS_64BIT
0689         position |= (u64)(in_be32(&dma_channel->satr) &
0690                   CCSR_DMA_ATR_ESAD_MASK) << 32;
0691 #endif
0692     } else {
0693         position = in_be32(&dma_channel->dar);
0694 #ifdef CONFIG_PHYS_64BIT
0695         position |= (u64)(in_be32(&dma_channel->datr) &
0696                   CCSR_DMA_ATR_ESAD_MASK) << 32;
0697 #endif
0698     }
0699 
0700     /*
0701      * When capture is started, the SSI immediately starts to fill its FIFO.
0702      * This means that the DMA controller is not started until the FIFO is
0703      * full.  However, ALSA calls this function before that happens, when
0704      * MR.DAR is still zero.  In this case, just return zero to indicate
0705      * that nothing has been received yet.
0706      */
0707     if (!position)
0708         return 0;
0709 
0710     if ((position < dma_private->dma_buf_phys) ||
0711         (position > dma_private->dma_buf_end)) {
0712         dev_err(dev, "dma pointer is out of range, halting stream\n");
0713         return SNDRV_PCM_POS_XRUN;
0714     }
0715 
0716     frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
0717 
0718     /*
0719      * If the current address is just past the end of the buffer, wrap it
0720      * around.
0721      */
0722     if (frames == runtime->buffer_size)
0723         frames = 0;
0724 
0725     return frames;
0726 }
0727 
0728 /**
0729  * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
0730  *
0731  * Release the resources allocated in fsl_dma_hw_params() and de-program the
0732  * registers.
0733  *
0734  * This function can be called multiple times.
0735  */
0736 static int fsl_dma_hw_free(struct snd_soc_component *component,
0737                struct snd_pcm_substream *substream)
0738 {
0739     struct snd_pcm_runtime *runtime = substream->runtime;
0740     struct fsl_dma_private *dma_private = runtime->private_data;
0741 
0742     if (dma_private) {
0743         struct ccsr_dma_channel __iomem *dma_channel;
0744 
0745         dma_channel = dma_private->dma_channel;
0746 
0747         /* Stop the DMA */
0748         out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
0749         out_be32(&dma_channel->mr, 0);
0750 
0751         /* Reset all the other registers */
0752         out_be32(&dma_channel->sr, -1);
0753         out_be32(&dma_channel->clndar, 0);
0754         out_be32(&dma_channel->eclndar, 0);
0755         out_be32(&dma_channel->satr, 0);
0756         out_be32(&dma_channel->sar, 0);
0757         out_be32(&dma_channel->datr, 0);
0758         out_be32(&dma_channel->dar, 0);
0759         out_be32(&dma_channel->bcr, 0);
0760         out_be32(&dma_channel->nlndar, 0);
0761         out_be32(&dma_channel->enlndar, 0);
0762     }
0763 
0764     return 0;
0765 }
0766 
0767 /**
0768  * fsl_dma_close: close the stream.
0769  */
0770 static int fsl_dma_close(struct snd_soc_component *component,
0771              struct snd_pcm_substream *substream)
0772 {
0773     struct snd_pcm_runtime *runtime = substream->runtime;
0774     struct fsl_dma_private *dma_private = runtime->private_data;
0775     struct device *dev = component->dev;
0776     struct dma_object *dma =
0777         container_of(component->driver, struct dma_object, dai);
0778 
0779     if (dma_private) {
0780         if (dma_private->irq)
0781             free_irq(dma_private->irq, dma_private);
0782 
0783         /* Deallocate the fsl_dma_private structure */
0784         dma_free_coherent(dev, sizeof(struct fsl_dma_private),
0785                   dma_private, dma_private->ld_buf_phys);
0786         substream->runtime->private_data = NULL;
0787     }
0788 
0789     dma->assigned = false;
0790 
0791     return 0;
0792 }
0793 
0794 /**
0795  * find_ssi_node -- returns the SSI node that points to its DMA channel node
0796  *
0797  * Although this DMA driver attempts to operate independently of the other
0798  * devices, it still needs to determine some information about the SSI device
0799  * that it's working with.  Unfortunately, the device tree does not contain
0800  * a pointer from the DMA channel node to the SSI node -- the pointer goes the
0801  * other way.  So we need to scan the device tree for SSI nodes until we find
0802  * the one that points to the given DMA channel node.  It's ugly, but at least
0803  * it's contained in this one function.
0804  */
0805 static struct device_node *find_ssi_node(struct device_node *dma_channel_np)
0806 {
0807     struct device_node *ssi_np, *np;
0808 
0809     for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") {
0810         /* Check each DMA phandle to see if it points to us.  We
0811          * assume that device_node pointers are a valid comparison.
0812          */
0813         np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0);
0814         of_node_put(np);
0815         if (np == dma_channel_np)
0816             return ssi_np;
0817 
0818         np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0);
0819         of_node_put(np);
0820         if (np == dma_channel_np)
0821             return ssi_np;
0822     }
0823 
0824     return NULL;
0825 }
0826 
0827 static int fsl_soc_dma_probe(struct platform_device *pdev)
0828 {
0829     struct dma_object *dma;
0830     struct device_node *np = pdev->dev.of_node;
0831     struct device_node *ssi_np;
0832     struct resource res;
0833     const uint32_t *iprop;
0834     int ret;
0835 
0836     /* Find the SSI node that points to us. */
0837     ssi_np = find_ssi_node(np);
0838     if (!ssi_np) {
0839         dev_err(&pdev->dev, "cannot find parent SSI node\n");
0840         return -ENODEV;
0841     }
0842 
0843     ret = of_address_to_resource(ssi_np, 0, &res);
0844     if (ret) {
0845         dev_err(&pdev->dev, "could not determine resources for %pOF\n",
0846             ssi_np);
0847         of_node_put(ssi_np);
0848         return ret;
0849     }
0850 
0851     dma = kzalloc(sizeof(*dma), GFP_KERNEL);
0852     if (!dma) {
0853         of_node_put(ssi_np);
0854         return -ENOMEM;
0855     }
0856 
0857     dma->dai.name = DRV_NAME;
0858     dma->dai.open = fsl_dma_open;
0859     dma->dai.close = fsl_dma_close;
0860     dma->dai.hw_params = fsl_dma_hw_params;
0861     dma->dai.hw_free = fsl_dma_hw_free;
0862     dma->dai.pointer = fsl_dma_pointer;
0863     dma->dai.pcm_construct = fsl_dma_new;
0864 
0865     /* Store the SSI-specific information that we need */
0866     dma->ssi_stx_phys = res.start + REG_SSI_STX0;
0867     dma->ssi_srx_phys = res.start + REG_SSI_SRX0;
0868 
0869     iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
0870     if (iprop)
0871         dma->ssi_fifo_depth = be32_to_cpup(iprop);
0872     else
0873                 /* Older 8610 DTs didn't have the fifo-depth property */
0874         dma->ssi_fifo_depth = 8;
0875 
0876     of_node_put(ssi_np);
0877 
0878     ret = devm_snd_soc_register_component(&pdev->dev, &dma->dai, NULL, 0);
0879     if (ret) {
0880         dev_err(&pdev->dev, "could not register platform\n");
0881         kfree(dma);
0882         return ret;
0883     }
0884 
0885     dma->channel = of_iomap(np, 0);
0886     dma->irq = irq_of_parse_and_map(np, 0);
0887 
0888     dev_set_drvdata(&pdev->dev, dma);
0889 
0890     return 0;
0891 }
0892 
0893 static int fsl_soc_dma_remove(struct platform_device *pdev)
0894 {
0895     struct dma_object *dma = dev_get_drvdata(&pdev->dev);
0896 
0897     iounmap(dma->channel);
0898     irq_dispose_mapping(dma->irq);
0899     kfree(dma);
0900 
0901     return 0;
0902 }
0903 
0904 static const struct of_device_id fsl_soc_dma_ids[] = {
0905     { .compatible = "fsl,ssi-dma-channel", },
0906     {}
0907 };
0908 MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids);
0909 
0910 static struct platform_driver fsl_soc_dma_driver = {
0911     .driver = {
0912         .name = "fsl-pcm-audio",
0913         .of_match_table = fsl_soc_dma_ids,
0914     },
0915     .probe = fsl_soc_dma_probe,
0916     .remove = fsl_soc_dma_remove,
0917 };
0918 
0919 module_platform_driver(fsl_soc_dma_driver);
0920 
0921 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
0922 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver");
0923 MODULE_LICENSE("GPL v2");
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