soc/fsl/fsl_audmix.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
0004  *
0005  * Copyright 2017 NXP
0006  */
0007
0008 #ifndef __FSL_AUDMIX_H
0009 #define __FSL_AUDMIX_H
0010
0011 #define FSL_AUDMIX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0012             SNDRV_PCM_FMTBIT_S24_LE |\
0013             SNDRV_PCM_FMTBIT_S32_LE)
0014 /* AUDMIX Registers */
0015 #define FSL_AUDMIX_CTR      0x200 /* Control */
0016 #define FSL_AUDMIX_STR      0x204 /* Status */
0017
0018 #define FSL_AUDMIX_ATCR0    0x208 /* Attenuation Control */
0019 #define FSL_AUDMIX_ATIVAL0  0x20c /* Attenuation Initial Value */
0020 #define FSL_AUDMIX_ATSTPUP0 0x210 /* Attenuation step up factor */
0021 #define FSL_AUDMIX_ATSTPDN0 0x214 /* Attenuation step down factor */
0022 #define FSL_AUDMIX_ATSTPTGT0    0x218 /* Attenuation step target */
0023 #define FSL_AUDMIX_ATTNVAL0 0x21c /* Attenuation Value */
0024 #define FSL_AUDMIX_ATSTP0   0x220 /* Attenuation step number */
0025
0026 #define FSL_AUDMIX_ATCR1    0x228 /* Attenuation Control */
0027 #define FSL_AUDMIX_ATIVAL1  0x22c /* Attenuation Initial Value */
0028 #define FSL_AUDMIX_ATSTPUP1 0x230 /* Attenuation step up factor */
0029 #define FSL_AUDMIX_ATSTPDN1 0x234 /* Attenuation step down factor */
0030 #define FSL_AUDMIX_ATSTPTGT1    0x238 /* Attenuation step target */
0031 #define FSL_AUDMIX_ATTNVAL1 0x23c /* Attenuation Value */
0032 #define FSL_AUDMIX_ATSTP1   0x240 /* Attenuation step number */
0033
0034 /* AUDMIX Control Register */
0035 #define FSL_AUDMIX_CTR_MIXCLK_SHIFT 0
0036 #define FSL_AUDMIX_CTR_MIXCLK_MASK  BIT(FSL_AUDMIX_CTR_MIXCLK_SHIFT)
0037 #define FSL_AUDMIX_CTR_MIXCLK(i)    ((i) << FSL_AUDMIX_CTR_MIXCLK_SHIFT)
0038 #define FSL_AUDMIX_CTR_OUTSRC_SHIFT 1
0039 #define FSL_AUDMIX_CTR_OUTSRC_MASK  (0x3 << FSL_AUDMIX_CTR_OUTSRC_SHIFT)
0040 #define FSL_AUDMIX_CTR_OUTSRC(i)    (((i) << FSL_AUDMIX_CTR_OUTSRC_SHIFT)\
0041                           & FSL_AUDMIX_CTR_OUTSRC_MASK)
0042 #define FSL_AUDMIX_CTR_OUTWIDTH_SHIFT   3
0043 #define FSL_AUDMIX_CTR_OUTWIDTH_MASK    (0x7 << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)
0044 #define FSL_AUDMIX_CTR_OUTWIDTH(i)  (((i) << FSL_AUDMIX_CTR_OUTWIDTH_SHIFT)\
0045                           & FSL_AUDMIX_CTR_OUTWIDTH_MASK)
0046 #define FSL_AUDMIX_CTR_OUTCKPOL_SHIFT   6
0047 #define FSL_AUDMIX_CTR_OUTCKPOL_MASK    BIT(FSL_AUDMIX_CTR_OUTCKPOL_SHIFT)
0048 #define FSL_AUDMIX_CTR_OUTCKPOL(i)  ((i) << FSL_AUDMIX_CTR_OUTCKPOL_SHIFT)
0049 #define FSL_AUDMIX_CTR_MASKRTDF_SHIFT   7
0050 #define FSL_AUDMIX_CTR_MASKRTDF_MASK    BIT(FSL_AUDMIX_CTR_MASKRTDF_SHIFT)
0051 #define FSL_AUDMIX_CTR_MASKRTDF(i)  ((i) << FSL_AUDMIX_CTR_MASKRTDF_SHIFT)
0052 #define FSL_AUDMIX_CTR_MASKCKDF_SHIFT   8
0053 #define FSL_AUDMIX_CTR_MASKCKDF_MASK    BIT(FSL_AUDMIX_CTR_MASKCKDF_SHIFT)
0054 #define FSL_AUDMIX_CTR_MASKCKDF(i)  ((i) << FSL_AUDMIX_CTR_MASKCKDF_SHIFT)
0055 #define FSL_AUDMIX_CTR_SYNCMODE_SHIFT   9
0056 #define FSL_AUDMIX_CTR_SYNCMODE_MASK    BIT(FSL_AUDMIX_CTR_SYNCMODE_SHIFT)
0057 #define FSL_AUDMIX_CTR_SYNCMODE(i)  ((i) << FSL_AUDMIX_CTR_SYNCMODE_SHIFT)
0058 #define FSL_AUDMIX_CTR_SYNCSRC_SHIFT    10
0059 #define FSL_AUDMIX_CTR_SYNCSRC_MASK BIT(FSL_AUDMIX_CTR_SYNCSRC_SHIFT)
0060 #define FSL_AUDMIX_CTR_SYNCSRC(i)   ((i) << FSL_AUDMIX_CTR_SYNCSRC_SHIFT)
0061
0062 /* AUDMIX Status Register */
0063 #define FSL_AUDMIX_STR_RATEDIFF     BIT(0)
0064 #define FSL_AUDMIX_STR_CLKDIFF      BIT(1)
0065 #define FSL_AUDMIX_STR_MIXSTAT_SHIFT    2
0066 #define FSL_AUDMIX_STR_MIXSTAT_MASK (0x3 << FSL_AUDMIX_STR_MIXSTAT_SHIFT)
0067 #define FSL_AUDMIX_STR_MIXSTAT(i)   (((i) & FSL_AUDMIX_STR_MIXSTAT_MASK) \
0068                        >> FSL_AUDMIX_STR_MIXSTAT_SHIFT)
0069 /* AUDMIX Attenuation Control Register */
0070 #define FSL_AUDMIX_ATCR_AT_EN       BIT(0)
0071 #define FSL_AUDMIX_ATCR_AT_UPDN     BIT(1)
0072 #define FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT  2
0073 #define FSL_AUDMIX_ATCR_ATSTPDFI_MASK   \
0074                 (0xfff << FSL_AUDMIX_ATCR_ATSTPDIF_SHIFT)
0075
0076 /* AUDMIX Attenuation Initial Value Register */
0077 #define FSL_AUDMIX_ATIVAL_ATINVAL_MASK  0x3FFFF
0078
0079 /* AUDMIX Attenuation Step Up Factor Register */
0080 #define FSL_AUDMIX_ATSTPUP_ATSTEPUP_MASK    0x3FFFF
0081
0082 /* AUDMIX Attenuation Step Down Factor Register */
0083 #define FSL_AUDMIX_ATSTPDN_ATSTEPDN_MASK    0x3FFFF
0084
0085 /* AUDMIX Attenuation Step Target Register */
0086 #define FSL_AUDMIX_ATSTPTGT_ATSTPTG_MASK    0x3FFFF
0087
0088 /* AUDMIX Attenuation Value Register */
0089 #define FSL_AUDMIX_ATTNVAL_ATCURVAL_MASK    0x3FFFF
0090
0091 /* AUDMIX Attenuation Step Number Register */
0092 #define FSL_AUDMIX_ATSTP_STPCTR_MASK    0x3FFFF
0093
0094 #define FSL_AUDMIX_MAX_DAIS     2
0095 struct fsl_audmix {
0096     struct platform_device *pdev;
0097     struct regmap *regmap;
0098     struct clk *ipg_clk;
0099     spinlock_t lock; /* Protect tdms */
0100     u8 tdms;
0101 };
0102
0103 #endif /* __FSL_AUDMIX_H */