soc/fsl/fsl_aud2htx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2020 NXP
0004  */
0005
0006 #ifndef _FSL_AUD2HTX_H
0007 #define _FSL_AUD2HTX_H
0008
0009 #define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
0010                  SNDRV_PCM_FMTBIT_S32_LE)
0011
0012 /* AUD2HTX Register Map */
0013 #define AUD2HTX_CTRL          0x0   /* AUD2HTX Control Register */
0014 #define AUD2HTX_CTRL_EXT      0x4   /* AUD2HTX Control Extended Register */
0015 #define AUD2HTX_WR            0x8   /* AUD2HTX Write Register */
0016 #define AUD2HTX_STATUS        0xC   /* AUD2HTX Status Register */
0017 #define AUD2HTX_IRQ_NOMASK    0x10  /* AUD2HTX Nonmasked Interrupt Flags Register */
0018 #define AUD2HTX_IRQ_MASKED    0x14  /* AUD2HTX Masked Interrupt Flags Register */
0019 #define AUD2HTX_IRQ_MASK      0x18  /* AUD2HTX IRQ Masks Register */
0020
0021 /* AUD2HTX Control Register */
0022 #define AUD2HTX_CTRL_EN          BIT(0)
0023
0024 /* AUD2HTX Control Extended Register */
0025 #define AUD2HTX_CTRE_DE          BIT(0)
0026 #define AUD2HTX_CTRE_DT_SHIFT    0x1
0027 #define AUD2HTX_CTRE_DT_WIDTH    0x2
0028 #define AUD2HTX_CTRE_DT_MASK     ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
0029                  << AUD2HTX_CTRE_DT_SHIFT)
0030 #define AUD2HTX_CTRE_WL_SHIFT    16
0031 #define AUD2HTX_CTRE_WL_WIDTH    5
0032 #define AUD2HTX_CTRE_WL_MASK     ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
0033                  << AUD2HTX_CTRE_WL_SHIFT)
0034 #define AUD2HTX_CTRE_WH_SHIFT    24
0035 #define AUD2HTX_CTRE_WH_WIDTH    5
0036 #define AUD2HTX_CTRE_WH_MASK     ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
0037                  << AUD2HTX_CTRE_WH_SHIFT)
0038
0039 /* AUD2HTX IRQ Masks Register */
0040 #define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
0041 #define AUD2HTX_WM_LOW_IRQ_MASK  BIT(1)
0042 #define AUD2HTX_OVF_MASK         BIT(0)
0043
0044 #define AUD2HTX_FIFO_DEPTH       0x20
0045 #define AUD2HTX_WTMK_LOW         0x10
0046 #define AUD2HTX_WTMK_HIGH        0x10
0047 #define AUD2HTX_MAXBURST         0x10
0048
0049 /**
0050  * fsl_aud2htx: AUD2HTX private data
0051  *
0052  * @pdev: platform device pointer
0053  * @regmap: regmap handler
0054  * @bus_clk: clock source to access register
0055  * @dma_params_rx: DMA parameters for receive channel
0056  * @dma_params_tx: DMA parameters for transmit channel
0057  */
0058 struct fsl_aud2htx {
0059     struct platform_device *pdev;
0060     struct regmap *regmap;
0061     struct clk *bus_clk;
0062
0063     struct snd_dmaengine_dai_dma_data dma_params_rx;
0064     struct snd_dmaengine_dai_dma_data dma_params_tx;
0065 };
0066
0067 #endif /* _FSL_AUD2HTX_H */