soc/fsl/fsl_asrc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * fsl_asrc.h - Freescale ASRC ALSA SoC header file
0004  *
0005  * Copyright (C) 2014 Freescale Semiconductor, Inc.
0006  *
0007  * Author: Nicolin Chen <nicoleotsuka@gmail.com>
0008  */
0009
0010 #ifndef _FSL_ASRC_H
0011 #define _FSL_ASRC_H
0012
0013 #include  "fsl_asrc_common.h"
0014
0015 #define ASRC_DMA_BUFFER_NUM     2
0016 #define ASRC_INPUTFIFO_THRESHOLD    32
0017 #define ASRC_OUTPUTFIFO_THRESHOLD   32
0018 #define ASRC_FIFO_THRESHOLD_MIN     0
0019 #define ASRC_FIFO_THRESHOLD_MAX     63
0020 #define ASRC_DMA_BUFFER_SIZE        (1024 * 48 * 4)
0021 #define ASRC_MAX_BUFFER_SIZE        (1024 * 48)
0022 #define ASRC_OUTPUT_LAST_SAMPLE     8
0023
0024 #define IDEAL_RATIO_RATE        1000000
0025
0026 #define REG_ASRCTR          0x00
0027 #define REG_ASRIER          0x04
0028 #define REG_ASRCNCR         0x0C
0029 #define REG_ASRCFG          0x10
0030 #define REG_ASRCSR          0x14
0031
0032 #define REG_ASRCDR1         0x18
0033 #define REG_ASRCDR2         0x1C
0034 #define REG_ASRCDR(i)           ((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
0035
0036 #define REG_ASRSTR          0x20
0037 #define REG_ASRRA           0x24
0038 #define REG_ASRRB           0x28
0039 #define REG_ASRRC           0x2C
0040 #define REG_ASRPM1          0x40
0041 #define REG_ASRPM2          0x44
0042 #define REG_ASRPM3          0x48
0043 #define REG_ASRPM4          0x4C
0044 #define REG_ASRPM5          0x50
0045 #define REG_ASRTFR1         0x54
0046 #define REG_ASRCCR          0x5C
0047
0048 #define REG_ASRDIA          0x60
0049 #define REG_ASRDOA          0x64
0050 #define REG_ASRDIB          0x68
0051 #define REG_ASRDOB          0x6C
0052 #define REG_ASRDIC          0x70
0053 #define REG_ASRDOC          0x74
0054 #define REG_ASRDI(i)            (REG_ASRDIA + (i << 3))
0055 #define REG_ASRDO(i)            (REG_ASRDOA + (i << 3))
0056 #define REG_ASRDx(x, i)         ((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
0057
0058 #define REG_ASRIDRHA            0x80
0059 #define REG_ASRIDRLA            0x84
0060 #define REG_ASRIDRHB            0x88
0061 #define REG_ASRIDRLB            0x8C
0062 #define REG_ASRIDRHC            0x90
0063 #define REG_ASRIDRLC            0x94
0064 #define REG_ASRIDRH(i)          (REG_ASRIDRHA + (i << 3))
0065 #define REG_ASRIDRL(i)          (REG_ASRIDRLA + (i << 3))
0066
0067 #define REG_ASR76K          0x98
0068 #define REG_ASR56K          0x9C
0069
0070 #define REG_ASRMCRA         0xA0
0071 #define REG_ASRFSTA         0xA4
0072 #define REG_ASRMCRB         0xA8
0073 #define REG_ASRFSTB         0xAC
0074 #define REG_ASRMCRC         0xB0
0075 #define REG_ASRFSTC         0xB4
0076 #define REG_ASRMCR(i)           (REG_ASRMCRA + (i << 3))
0077 #define REG_ASRFST(i)           (REG_ASRFSTA + (i << 3))
0078
0079 #define REG_ASRMCR1A            0xC0
0080 #define REG_ASRMCR1B            0xC4
0081 #define REG_ASRMCR1C            0xC8
0082 #define REG_ASRMCR1(i)          (REG_ASRMCR1A + (i << 2))
0083
0084
0085 /* REG0 0x00 REG_ASRCTR */
0086 #define ASRCTR_ATSi_SHIFT(i)        (20 + i)
0087 #define ASRCTR_ATSi_MASK(i)     (1 << ASRCTR_ATSi_SHIFT(i))
0088 #define ASRCTR_ATS(i)           (1 << ASRCTR_ATSi_SHIFT(i))
0089 #define ASRCTR_USRi_SHIFT(i)        (14 + (i << 1))
0090 #define ASRCTR_USRi_MASK(i)     (1 << ASRCTR_USRi_SHIFT(i))
0091 #define ASRCTR_USR(i)           (1 << ASRCTR_USRi_SHIFT(i))
0092 #define ASRCTR_IDRi_SHIFT(i)        (13 + (i << 1))
0093 #define ASRCTR_IDRi_MASK(i)     (1 << ASRCTR_IDRi_SHIFT(i))
0094 #define ASRCTR_IDR(i)           (1 << ASRCTR_IDRi_SHIFT(i))
0095 #define ASRCTR_SRST_SHIFT       4
0096 #define ASRCTR_SRST_MASK        (1 << ASRCTR_SRST_SHIFT)
0097 #define ASRCTR_SRST         (1 << ASRCTR_SRST_SHIFT)
0098 #define ASRCTR_ASRCEi_SHIFT(i)      (1 + i)
0099 #define ASRCTR_ASRCEi_MASK(i)       (1 << ASRCTR_ASRCEi_SHIFT(i))
0100 #define ASRCTR_ASRCE(i)         (1 << ASRCTR_ASRCEi_SHIFT(i))
0101 #define ASRCTR_ASRCEi_ALL_MASK      (0x7 << ASRCTR_ASRCEi_SHIFT(0))
0102 #define ASRCTR_ASRCEN_SHIFT     0
0103 #define ASRCTR_ASRCEN_MASK      (1 << ASRCTR_ASRCEN_SHIFT)
0104 #define ASRCTR_ASRCEN           (1 << ASRCTR_ASRCEN_SHIFT)
0105
0106 /* REG1 0x04 REG_ASRIER */
0107 #define ASRIER_AFPWE_SHIFT      7
0108 #define ASRIER_AFPWE_MASK       (1 << ASRIER_AFPWE_SHIFT)
0109 #define ASRIER_AFPWE            (1 << ASRIER_AFPWE_SHIFT)
0110 #define ASRIER_AOLIE_SHIFT      6
0111 #define ASRIER_AOLIE_MASK       (1 << ASRIER_AOLIE_SHIFT)
0112 #define ASRIER_AOLIE            (1 << ASRIER_AOLIE_SHIFT)
0113 #define ASRIER_ADOEi_SHIFT(i)       (3 + i)
0114 #define ASRIER_ADOEi_MASK(i)        (1 << ASRIER_ADOEi_SHIFT(i))
0115 #define ASRIER_ADOE(i)          (1 << ASRIER_ADOEi_SHIFT(i))
0116 #define ASRIER_ADIEi_SHIFT(i)       (0 + i)
0117 #define ASRIER_ADIEi_MASK(i)        (1 << ASRIER_ADIEi_SHIFT(i))
0118 #define ASRIER_ADIE(i)          (1 << ASRIER_ADIEi_SHIFT(i))
0119
0120 /* REG2 0x0C REG_ASRCNCR */
0121 #define ASRCNCR_ANCi_SHIFT(i, b)    (b * i)
0122 #define ASRCNCR_ANCi_MASK(i, b)     (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
0123 #define ASRCNCR_ANCi(i, v, b)       ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
0124
0125 /* REG3 0x10 REG_ASRCFG */
0126 #define ASRCFG_INIRQi_SHIFT(i)      (21 + i)
0127 #define ASRCFG_INIRQi_MASK(i)       (1 << ASRCFG_INIRQi_SHIFT(i))
0128 #define ASRCFG_INIRQi           (1 << ASRCFG_INIRQi_SHIFT(i))
0129 #define ASRCFG_NDPRi_SHIFT(i)       (18 + i)
0130 #define ASRCFG_NDPRi_MASK(i)        (1 << ASRCFG_NDPRi_SHIFT(i))
0131 #define ASRCFG_NDPRi_ALL_SHIFT      18
0132 #define ASRCFG_NDPRi_ALL_MASK       (7 << ASRCFG_NDPRi_ALL_SHIFT)
0133 #define ASRCFG_NDPRi            (1 << ASRCFG_NDPRi_SHIFT(i))
0134 #define ASRCFG_POSTMODi_SHIFT(i)    (8 + (i << 2))
0135 #define ASRCFG_POSTMODi_WIDTH       2
0136 #define ASRCFG_POSTMODi_MASK(i)     (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
0137 #define ASRCFG_POSTMODi_ALL_MASK    (ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
0138 #define ASRCFG_POSTMOD(i, v)        ((v) << ASRCFG_POSTMODi_SHIFT(i))
0139 #define ASRCFG_POSTMODi_UP(i)       (0 << ASRCFG_POSTMODi_SHIFT(i))
0140 #define ASRCFG_POSTMODi_DCON(i)     (1 << ASRCFG_POSTMODi_SHIFT(i))
0141 #define ASRCFG_POSTMODi_DOWN(i)     (2 << ASRCFG_POSTMODi_SHIFT(i))
0142 #define ASRCFG_PREMODi_SHIFT(i)     (6 + (i << 2))
0143 #define ASRCFG_PREMODi_WIDTH        2
0144 #define ASRCFG_PREMODi_MASK(i)      (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
0145 #define ASRCFG_PREMODi_ALL_MASK     (ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
0146 #define ASRCFG_PREMOD(i, v)     ((v) << ASRCFG_PREMODi_SHIFT(i))
0147 #define ASRCFG_PREMODi_UP(i)        (0 << ASRCFG_PREMODi_SHIFT(i))
0148 #define ASRCFG_PREMODi_DCON(i)      (1 << ASRCFG_PREMODi_SHIFT(i))
0149 #define ASRCFG_PREMODi_DOWN(i)      (2 << ASRCFG_PREMODi_SHIFT(i))
0150 #define ASRCFG_PREMODi_BYPASS(i)    (3 << ASRCFG_PREMODi_SHIFT(i))
0151
0152 /* REG4 0x14 REG_ASRCSR */
0153 #define ASRCSR_AxCSi_WIDTH      4
0154 #define ASRCSR_AxCSi_MASK       ((1 << ASRCSR_AxCSi_WIDTH) - 1)
0155 #define ASRCSR_AOCSi_SHIFT(i)       (12 + (i << 2))
0156 #define ASRCSR_AOCSi_MASK(i)        (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
0157 #define ASRCSR_AOCS(i, v)       ((v) << ASRCSR_AOCSi_SHIFT(i))
0158 #define ASRCSR_AICSi_SHIFT(i)       (i << 2)
0159 #define ASRCSR_AICSi_MASK(i)        (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
0160 #define ASRCSR_AICS(i, v)       ((v) << ASRCSR_AICSi_SHIFT(i))
0161
0162 /* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
0163 #define ASRCDRi_AxCPi_WIDTH     3
0164 #define ASRCDRi_AICPi_SHIFT(i)      (0 + (i % 2) * 6)
0165 #define ASRCDRi_AICPi_MASK(i)       (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
0166 #define ASRCDRi_AICP(i, v)      ((v) << ASRCDRi_AICPi_SHIFT(i))
0167 #define ASRCDRi_AICDi_SHIFT(i)      (3 + (i % 2) * 6)
0168 #define ASRCDRi_AICDi_MASK(i)       (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
0169 #define ASRCDRi_AICD(i, v)      ((v) << ASRCDRi_AICDi_SHIFT(i))
0170 #define ASRCDRi_AOCPi_SHIFT(i)      ((i < 2) ? 12 + i * 6 : 6)
0171 #define ASRCDRi_AOCPi_MASK(i)       (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
0172 #define ASRCDRi_AOCP(i, v)      ((v) << ASRCDRi_AOCPi_SHIFT(i))
0173 #define ASRCDRi_AOCDi_SHIFT(i)      ((i < 2) ? 15 + i * 6 : 9)
0174 #define ASRCDRi_AOCDi_MASK(i)       (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
0175 #define ASRCDRi_AOCD(i, v)      ((v) << ASRCDRi_AOCDi_SHIFT(i))
0176
0177 /* REG7 0x20 REG_ASRSTR */
0178 #define ASRSTR_DSLCNT_SHIFT     21
0179 #define ASRSTR_DSLCNT_MASK      (1 << ASRSTR_DSLCNT_SHIFT)
0180 #define ASRSTR_DSLCNT           (1 << ASRSTR_DSLCNT_SHIFT)
0181 #define ASRSTR_ATQOL_SHIFT      20
0182 #define ASRSTR_ATQOL_MASK       (1 << ASRSTR_ATQOL_SHIFT)
0183 #define ASRSTR_ATQOL            (1 << ASRSTR_ATQOL_SHIFT)
0184 #define ASRSTR_AOOLi_SHIFT(i)       (17 + i)
0185 #define ASRSTR_AOOLi_MASK(i)        (1 << ASRSTR_AOOLi_SHIFT(i))
0186 #define ASRSTR_AOOL(i)          (1 << ASRSTR_AOOLi_SHIFT(i))
0187 #define ASRSTR_AIOLi_SHIFT(i)       (14 + i)
0188 #define ASRSTR_AIOLi_MASK(i)        (1 << ASRSTR_AIOLi_SHIFT(i))
0189 #define ASRSTR_AIOL(i)          (1 << ASRSTR_AIOLi_SHIFT(i))
0190 #define ASRSTR_AODOi_SHIFT(i)       (11 + i)
0191 #define ASRSTR_AODOi_MASK(i)        (1 << ASRSTR_AODOi_SHIFT(i))
0192 #define ASRSTR_AODO(i)          (1 << ASRSTR_AODOi_SHIFT(i))
0193 #define ASRSTR_AIDUi_SHIFT(i)       (8 + i)
0194 #define ASRSTR_AIDUi_MASK(i)        (1 << ASRSTR_AIDUi_SHIFT(i))
0195 #define ASRSTR_AIDU(i)          (1 << ASRSTR_AIDUi_SHIFT(i))
0196 #define ASRSTR_FPWT_SHIFT       7
0197 #define ASRSTR_FPWT_MASK        (1 << ASRSTR_FPWT_SHIFT)
0198 #define ASRSTR_FPWT         (1 << ASRSTR_FPWT_SHIFT)
0199 #define ASRSTR_AOLE_SHIFT       6
0200 #define ASRSTR_AOLE_MASK        (1 << ASRSTR_AOLE_SHIFT)
0201 #define ASRSTR_AOLE         (1 << ASRSTR_AOLE_SHIFT)
0202 #define ASRSTR_AODEi_SHIFT(i)       (3 + i)
0203 #define ASRSTR_AODFi_MASK(i)        (1 << ASRSTR_AODEi_SHIFT(i))
0204 #define ASRSTR_AODF(i)          (1 << ASRSTR_AODEi_SHIFT(i))
0205 #define ASRSTR_AIDEi_SHIFT(i)       (0 + i)
0206 #define ASRSTR_AIDEi_MASK(i)        (1 << ASRSTR_AIDEi_SHIFT(i))
0207 #define ASRSTR_AIDE(i)          (1 << ASRSTR_AIDEi_SHIFT(i))
0208
0209 /* REG10 0x54 REG_ASRTFR1 */
0210 #define ASRTFR1_TF_BASE_WIDTH       7
0211 #define ASRTFR1_TF_BASE_SHIFT       6
0212 #define ASRTFR1_TF_BASE_MASK        (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
0213 #define ASRTFR1_TF_BASE(i)      ((i) << ASRTFR1_TF_BASE_SHIFT)
0214
0215 /*
0216  * REG22 0xA0 REG_ASRMCRA
0217  * REG24 0xA8 REG_ASRMCRB
0218  * REG26 0xB0 REG_ASRMCRC
0219  */
0220 #define ASRMCRi_ZEROBUFi_SHIFT      23
0221 #define ASRMCRi_ZEROBUFi_MASK       (1 << ASRMCRi_ZEROBUFi_SHIFT)
0222 #define ASRMCRi_ZEROBUFi        (1 << ASRMCRi_ZEROBUFi_SHIFT)
0223 #define ASRMCRi_EXTTHRSHi_SHIFT     22
0224 #define ASRMCRi_EXTTHRSHi_MASK      (1 << ASRMCRi_EXTTHRSHi_SHIFT)
0225 #define ASRMCRi_EXTTHRSHi       (1 << ASRMCRi_EXTTHRSHi_SHIFT)
0226 #define ASRMCRi_BUFSTALLi_SHIFT     21
0227 #define ASRMCRi_BUFSTALLi_MASK      (1 << ASRMCRi_BUFSTALLi_SHIFT)
0228 #define ASRMCRi_BUFSTALLi       (1 << ASRMCRi_BUFSTALLi_SHIFT)
0229 #define ASRMCRi_BYPASSPOLYi_SHIFT   20
0230 #define ASRMCRi_BYPASSPOLYi_MASK    (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
0231 #define ASRMCRi_BYPASSPOLYi     (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
0232 #define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH 6
0233 #define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT 12
0234 #define ASRMCRi_OUTFIFO_THRESHOLD_MASK  (((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
0235 #define ASRMCRi_OUTFIFO_THRESHOLD(v)    (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
0236 #define ASRMCRi_RSYNIFi_SHIFT       11
0237 #define ASRMCRi_RSYNIFi_MASK        (1 << ASRMCRi_RSYNIFi_SHIFT)
0238 #define ASRMCRi_RSYNIFi         (1 << ASRMCRi_RSYNIFi_SHIFT)
0239 #define ASRMCRi_RSYNOFi_SHIFT       10
0240 #define ASRMCRi_RSYNOFi_MASK        (1 << ASRMCRi_RSYNOFi_SHIFT)
0241 #define ASRMCRi_RSYNOFi         (1 << ASRMCRi_RSYNOFi_SHIFT)
0242 #define ASRMCRi_INFIFO_THRESHOLD_WIDTH  6
0243 #define ASRMCRi_INFIFO_THRESHOLD_SHIFT  0
0244 #define ASRMCRi_INFIFO_THRESHOLD_MASK   (((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
0245 #define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
0246
0247 /*
0248  * REG23 0xA4 REG_ASRFSTA
0249  * REG25 0xAC REG_ASRFSTB
0250  * REG27 0xB4 REG_ASRFSTC
0251  */
0252 #define ASRFSTi_OAFi_SHIFT      23
0253 #define ASRFSTi_OAFi_MASK       (1 << ASRFSTi_OAFi_SHIFT)
0254 #define ASRFSTi_OAFi            (1 << ASRFSTi_OAFi_SHIFT)
0255 #define ASRFSTi_OUTPUT_FIFO_WIDTH   7
0256 #define ASRFSTi_OUTPUT_FIFO_SHIFT   12
0257 #define ASRFSTi_OUTPUT_FIFO_MASK    (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
0258 #define ASRFSTi_IAEi_SHIFT      11
0259 #define ASRFSTi_IAEi_MASK       (1 << ASRFSTi_IAEi_SHIFT)
0260 #define ASRFSTi_IAEi            (1 << ASRFSTi_IAEi_SHIFT)
0261 #define ASRFSTi_INPUT_FIFO_WIDTH    7
0262 #define ASRFSTi_INPUT_FIFO_SHIFT    0
0263 #define ASRFSTi_INPUT_FIFO_MASK     ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
0264
0265 /* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
0266 #define ASRMCR1i_IWD_WIDTH      3
0267 #define ASRMCR1i_IWD_SHIFT      9
0268 #define ASRMCR1i_IWD_MASK       (((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
0269 #define ASRMCR1i_IWD(v)         ((v) << ASRMCR1i_IWD_SHIFT)
0270 #define ASRMCR1i_IMSB_SHIFT     8
0271 #define ASRMCR1i_IMSB_MASK      (1 << ASRMCR1i_IMSB_SHIFT)
0272 #define ASRMCR1i_IMSB_MSB       (1 << ASRMCR1i_IMSB_SHIFT)
0273 #define ASRMCR1i_IMSB_LSB       (0 << ASRMCR1i_IMSB_SHIFT)
0274 #define ASRMCR1i_OMSB_SHIFT     2
0275 #define ASRMCR1i_OMSB_MASK      (1 << ASRMCR1i_OMSB_SHIFT)
0276 #define ASRMCR1i_OMSB_MSB       (1 << ASRMCR1i_OMSB_SHIFT)
0277 #define ASRMCR1i_OMSB_LSB       (0 << ASRMCR1i_OMSB_SHIFT)
0278 #define ASRMCR1i_OSGN_SHIFT     1
0279 #define ASRMCR1i_OSGN_MASK      (1 << ASRMCR1i_OSGN_SHIFT)
0280 #define ASRMCR1i_OSGN           (1 << ASRMCR1i_OSGN_SHIFT)
0281 #define ASRMCR1i_OW16_SHIFT     0
0282 #define ASRMCR1i_OW16_MASK      (1 << ASRMCR1i_OW16_SHIFT)
0283 #define ASRMCR1i_OW16(v)        ((v) << ASRMCR1i_OW16_SHIFT)
0284
0285 #define ASRC_PAIR_MAX_NUM   (ASRC_PAIR_C + 1)
0286
0287 enum asrc_inclk {
0288     INCLK_NONE = 0x03,
0289     INCLK_ESAI_RX = 0x00,
0290     INCLK_SSI1_RX = 0x01,
0291     INCLK_SSI2_RX = 0x02,
0292     INCLK_SSI3_RX = 0x07,
0293     INCLK_SPDIF_RX = 0x04,
0294     INCLK_MLB_CLK = 0x05,
0295     INCLK_PAD = 0x06,
0296     INCLK_ESAI_TX = 0x08,
0297     INCLK_SSI1_TX = 0x09,
0298     INCLK_SSI2_TX = 0x0a,
0299     INCLK_SSI3_TX = 0x0b,
0300     INCLK_SPDIF_TX = 0x0c,
0301     INCLK_ASRCK1_CLK = 0x0f,
0302
0303     /* clocks for imx8 */
0304     INCLK_AUD_PLL_DIV_CLK0 = 0x10,
0305     INCLK_AUD_PLL_DIV_CLK1 = 0x11,
0306     INCLK_AUD_CLK0         = 0x12,
0307     INCLK_AUD_CLK1         = 0x13,
0308     INCLK_ESAI0_RX_CLK     = 0x14,
0309     INCLK_ESAI0_TX_CLK     = 0x15,
0310     INCLK_SPDIF0_RX        = 0x16,
0311     INCLK_SPDIF1_RX        = 0x17,
0312     INCLK_SAI0_RX_BCLK     = 0x18,
0313     INCLK_SAI0_TX_BCLK     = 0x19,
0314     INCLK_SAI1_RX_BCLK     = 0x1a,
0315     INCLK_SAI1_TX_BCLK     = 0x1b,
0316     INCLK_SAI2_RX_BCLK     = 0x1c,
0317     INCLK_SAI3_RX_BCLK     = 0x1d,
0318     INCLK_ASRC0_MUX_CLK    = 0x1e,
0319
0320     INCLK_ESAI1_RX_CLK     = 0x20,
0321     INCLK_ESAI1_TX_CLK     = 0x21,
0322     INCLK_SAI6_TX_BCLK     = 0x22,
0323     INCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
0324     INCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
0325 };
0326
0327 enum asrc_outclk {
0328     OUTCLK_NONE = 0x03,
0329     OUTCLK_ESAI_TX = 0x00,
0330     OUTCLK_SSI1_TX = 0x01,
0331     OUTCLK_SSI2_TX = 0x02,
0332     OUTCLK_SSI3_TX = 0x07,
0333     OUTCLK_SPDIF_TX = 0x04,
0334     OUTCLK_MLB_CLK = 0x05,
0335     OUTCLK_PAD = 0x06,
0336     OUTCLK_ESAI_RX = 0x08,
0337     OUTCLK_SSI1_RX = 0x09,
0338     OUTCLK_SSI2_RX = 0x0a,
0339     OUTCLK_SSI3_RX = 0x0b,
0340     OUTCLK_SPDIF_RX = 0x0c,
0341     OUTCLK_ASRCK1_CLK = 0x0f,
0342
0343     /* clocks for imx8 */
0344     OUTCLK_AUD_PLL_DIV_CLK0 = 0x10,
0345     OUTCLK_AUD_PLL_DIV_CLK1 = 0x11,
0346     OUTCLK_AUD_CLK0         = 0x12,
0347     OUTCLK_AUD_CLK1         = 0x13,
0348     OUTCLK_ESAI0_RX_CLK     = 0x14,
0349     OUTCLK_ESAI0_TX_CLK     = 0x15,
0350     OUTCLK_SPDIF0_RX        = 0x16,
0351     OUTCLK_SPDIF1_RX        = 0x17,
0352     OUTCLK_SAI0_RX_BCLK     = 0x18,
0353     OUTCLK_SAI0_TX_BCLK     = 0x19,
0354     OUTCLK_SAI1_RX_BCLK     = 0x1a,
0355     OUTCLK_SAI1_TX_BCLK     = 0x1b,
0356     OUTCLK_SAI2_RX_BCLK     = 0x1c,
0357     OUTCLK_SAI3_RX_BCLK     = 0x1d,
0358     OUTCLK_ASRCO_MUX_CLK    = 0x1e,
0359
0360     OUTCLK_ESAI1_RX_CLK     = 0x20,
0361     OUTCLK_ESAI1_TX_CLK     = 0x21,
0362     OUTCLK_SAI6_TX_BCLK     = 0x22,
0363     OUTCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
0364     OUTCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
0365 };
0366
0367 #define ASRC_CLK_MAX_NUM    16
0368 #define ASRC_CLK_MAP_LEN    0x30
0369
0370 enum asrc_word_width {
0371     ASRC_WIDTH_24_BIT = 0,
0372     ASRC_WIDTH_16_BIT = 1,
0373     ASRC_WIDTH_8_BIT = 2,
0374 };
0375
0376 struct asrc_config {
0377     enum asrc_pair_index pair;
0378     unsigned int channel_num;
0379     unsigned int buffer_num;
0380     unsigned int dma_buffer_size;
0381     unsigned int input_sample_rate;
0382     unsigned int output_sample_rate;
0383     snd_pcm_format_t input_format;
0384     snd_pcm_format_t output_format;
0385     enum asrc_inclk inclk;
0386     enum asrc_outclk outclk;
0387 };
0388
0389 struct asrc_req {
0390     unsigned int chn_num;
0391     enum asrc_pair_index index;
0392 };
0393
0394 struct asrc_querybuf {
0395     unsigned int buffer_index;
0396     unsigned int input_length;
0397     unsigned int output_length;
0398     unsigned long input_offset;
0399     unsigned long output_offset;
0400 };
0401
0402 struct asrc_convert_buffer {
0403     void *input_buffer_vaddr;
0404     void *output_buffer_vaddr;
0405     unsigned int input_buffer_length;
0406     unsigned int output_buffer_length;
0407 };
0408
0409 struct asrc_status_flags {
0410     enum asrc_pair_index index;
0411     unsigned int overload_error;
0412 };
0413
0414 enum asrc_error_status {
0415     ASRC_TASK_Q_OVERLOAD        = 0x01,
0416     ASRC_OUTPUT_TASK_OVERLOAD   = 0x02,
0417     ASRC_INPUT_TASK_OVERLOAD    = 0x04,
0418     ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
0419     ASRC_INPUT_BUFFER_UNDERRUN  = 0x10,
0420 };
0421
0422 struct dma_block {
0423     dma_addr_t dma_paddr;
0424     void *dma_vaddr;
0425     unsigned int length;
0426 };
0427
0428 /**
0429  * fsl_asrc_soc_data: soc specific data
0430  *
0431  * @use_edma: using edma as dma device or not
0432  * @channel_bits: width of ASRCNCR register for each pair
0433  */
0434 struct fsl_asrc_soc_data {
0435     bool use_edma;
0436     unsigned int channel_bits;
0437 };
0438
0439 /**
0440  * fsl_asrc_pair_priv: ASRC Pair private data
0441  *
0442  * @config: configuration profile
0443  */
0444 struct fsl_asrc_pair_priv {
0445     struct asrc_config *config;
0446 };
0447
0448 /**
0449  * fsl_asrc_priv: ASRC private data
0450  *
0451  * @asrck_clk: clock sources to driver ASRC internal logic
0452  * @soc: soc specific data
0453  * @clk_map: clock map for input/output clock
0454  * @regcache_cfg: store register value of REG_ASRCFG
0455  */
0456 struct fsl_asrc_priv {
0457     struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
0458     const struct fsl_asrc_soc_data *soc;
0459     unsigned char *clk_map[2];
0460
0461     u32 regcache_cfg;
0462 };
0463
0464 #endif /* _FSL_ASRC_H */