soc/dwc/local.h

0001 /*
0002  * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
0003  *
0004  * This file is licensed under the terms of the GNU General Public
0005  * License version 2. This program is licensed "as is" without any
0006  * warranty of any kind, whether express or implied.
0007  */
0008
0009 #ifndef __DESIGNWARE_LOCAL_H
0010 #define __DESIGNWARE_LOCAL_H
0011
0012 #include <linux/clk.h>
0013 #include <linux/device.h>
0014 #include <linux/types.h>
0015 #include <sound/dmaengine_pcm.h>
0016 #include <sound/pcm.h>
0017 #include <sound/designware_i2s.h>
0018
0019 /* common register for all channel */
0020 #define IER     0x000
0021 #define IRER        0x004
0022 #define ITER        0x008
0023 #define CER     0x00C
0024 #define CCR     0x010
0025 #define RXFFR       0x014
0026 #define TXFFR       0x018
0027
0028 /* Interrupt status register fields */
0029 #define ISR_TXFO    BIT(5)
0030 #define ISR_TXFE    BIT(4)
0031 #define ISR_RXFO    BIT(1)
0032 #define ISR_RXDA    BIT(0)
0033
0034 /* I2STxRxRegisters for all channels */
0035 #define LRBR_LTHR(x)    (0x40 * x + 0x020)
0036 #define RRBR_RTHR(x)    (0x40 * x + 0x024)
0037 #define RER(x)      (0x40 * x + 0x028)
0038 #define TER(x)      (0x40 * x + 0x02C)
0039 #define RCR(x)      (0x40 * x + 0x030)
0040 #define TCR(x)      (0x40 * x + 0x034)
0041 #define ISR(x)      (0x40 * x + 0x038)
0042 #define IMR(x)      (0x40 * x + 0x03C)
0043 #define ROR(x)      (0x40 * x + 0x040)
0044 #define TOR(x)      (0x40 * x + 0x044)
0045 #define RFCR(x)     (0x40 * x + 0x048)
0046 #define TFCR(x)     (0x40 * x + 0x04C)
0047 #define RFF(x)      (0x40 * x + 0x050)
0048 #define TFF(x)      (0x40 * x + 0x054)
0049
0050 /* I2SCOMPRegisters */
0051 #define I2S_COMP_PARAM_2    0x01F0
0052 #define I2S_COMP_PARAM_1    0x01F4
0053 #define I2S_COMP_VERSION    0x01F8
0054 #define I2S_COMP_TYPE       0x01FC
0055
0056 /*
0057  * Component parameter register fields - define the I2S block's
0058  * configuration.
0059  */
0060 #define COMP1_TX_WORDSIZE_3(r)  (((r) & GENMASK(27, 25)) >> 25)
0061 #define COMP1_TX_WORDSIZE_2(r)  (((r) & GENMASK(24, 22)) >> 22)
0062 #define COMP1_TX_WORDSIZE_1(r)  (((r) & GENMASK(21, 19)) >> 19)
0063 #define COMP1_TX_WORDSIZE_0(r)  (((r) & GENMASK(18, 16)) >> 16)
0064 #define COMP1_TX_CHANNELS(r)    (((r) & GENMASK(10, 9)) >> 9)
0065 #define COMP1_RX_CHANNELS(r)    (((r) & GENMASK(8, 7)) >> 7)
0066 #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
0067 #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
0068 #define COMP1_MODE_EN(r)    (((r) & BIT(4)) >> 4)
0069 #define COMP1_FIFO_DEPTH_GLOBAL(r)  (((r) & GENMASK(3, 2)) >> 2)
0070 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
0071
0072 #define COMP2_RX_WORDSIZE_3(r)  (((r) & GENMASK(12, 10)) >> 10)
0073 #define COMP2_RX_WORDSIZE_2(r)  (((r) & GENMASK(9, 7)) >> 7)
0074 #define COMP2_RX_WORDSIZE_1(r)  (((r) & GENMASK(5, 3)) >> 3)
0075 #define COMP2_RX_WORDSIZE_0(r)  (((r) & GENMASK(2, 0)) >> 0)
0076
0077 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
0078 #define COMP_MAX_WORDSIZE   (1 << 3)
0079 #define COMP_MAX_DATA_WIDTH (1 << 2)
0080
0081 #define MAX_CHANNEL_NUM     8
0082 #define MIN_CHANNEL_NUM     2
0083
0084 union dw_i2s_snd_dma_data {
0085     struct i2s_dma_data pd;
0086     struct snd_dmaengine_dai_dma_data dt;
0087 };
0088
0089 struct dw_i2s_dev {
0090     void __iomem *i2s_base;
0091     struct clk *clk;
0092     int active;
0093     unsigned int capability;
0094     unsigned int quirks;
0095     unsigned int i2s_reg_comp1;
0096     unsigned int i2s_reg_comp2;
0097     struct device *dev;
0098     u32 ccr;
0099     u32 xfer_resolution;
0100     u32 fifo_th;
0101
0102     /* data related to DMA transfers b/w i2s and DMAC */
0103     union dw_i2s_snd_dma_data play_dma_data;
0104     union dw_i2s_snd_dma_data capture_dma_data;
0105     struct i2s_clk_config_data config;
0106     int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
0107
0108     /* data related to PIO transfers */
0109     bool use_pio;
0110     struct snd_pcm_substream __rcu *tx_substream;
0111     struct snd_pcm_substream __rcu *rx_substream;
0112     unsigned int (*tx_fn)(struct dw_i2s_dev *dev,
0113             struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
0114             bool *period_elapsed);
0115     unsigned int (*rx_fn)(struct dw_i2s_dev *dev,
0116             struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
0117             bool *period_elapsed);
0118     unsigned int tx_ptr;
0119     unsigned int rx_ptr;
0120 };
0121
0122 #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)
0123 void dw_pcm_push_tx(struct dw_i2s_dev *dev);
0124 void dw_pcm_pop_rx(struct dw_i2s_dev *dev);
0125 int dw_pcm_register(struct platform_device *pdev);
0126 #else
0127 static inline void dw_pcm_push_tx(struct dw_i2s_dev *dev) { }
0128 static inline void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { }
0129 static inline int dw_pcm_register(struct platform_device *pdev)
0130 {
0131     return -EINVAL;
0132 }
0133 #endif
0134
0135 #endif