soc/dwc/dwc-pcm.c

0001 /*
0002  * ALSA SoC Synopsys PIO PCM for I2S driver
0003  *
0004  * sound/soc/dwc/designware_pcm.c
0005  *
0006  * Copyright (C) 2016 Synopsys
0007  * Jose Abreu <joabreu@synopsys.com>
0008  *
0009  * This file is licensed under the terms of the GNU General Public
0010  * License version 2. This program is licensed "as is" without any
0011  * warranty of any kind, whether express or implied.
0012  */
0013
0014 #include <linux/io.h>
0015 #include <linux/rcupdate.h>
0016 #include <sound/pcm.h>
0017 #include <sound/pcm_params.h>
0018 #include "local.h"
0019
0020 #define BUFFER_BYTES_MAX    (3 * 2 * 8 * PERIOD_BYTES_MIN)
0021 #define PERIOD_BYTES_MIN    4096
0022 #define PERIODS_MIN     2
0023
0024 #define dw_pcm_tx_fn(sample_bits) \
0025 static unsigned int dw_pcm_tx_##sample_bits(struct dw_i2s_dev *dev, \
0026         struct snd_pcm_runtime *runtime, unsigned int tx_ptr, \
0027         bool *period_elapsed) \
0028 { \
0029     const u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
0030     unsigned int period_pos = tx_ptr % runtime->period_size; \
0031     int i; \
0032 \
0033     for (i = 0; i < dev->fifo_th; i++) { \
0034         iowrite32(p[tx_ptr][0], dev->i2s_base + LRBR_LTHR(0)); \
0035         iowrite32(p[tx_ptr][1], dev->i2s_base + RRBR_RTHR(0)); \
0036         period_pos++; \
0037         if (++tx_ptr >= runtime->buffer_size) \
0038             tx_ptr = 0; \
0039     } \
0040     *period_elapsed = period_pos >= runtime->period_size; \
0041     return tx_ptr; \
0042 }
0043
0044 #define dw_pcm_rx_fn(sample_bits) \
0045 static unsigned int dw_pcm_rx_##sample_bits(struct dw_i2s_dev *dev, \
0046         struct snd_pcm_runtime *runtime, unsigned int rx_ptr, \
0047         bool *period_elapsed) \
0048 { \
0049     u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
0050     unsigned int period_pos = rx_ptr % runtime->period_size; \
0051     int i; \
0052 \
0053     for (i = 0; i < dev->fifo_th; i++) { \
0054         p[rx_ptr][0] = ioread32(dev->i2s_base + LRBR_LTHR(0)); \
0055         p[rx_ptr][1] = ioread32(dev->i2s_base + RRBR_RTHR(0)); \
0056         period_pos++; \
0057         if (++rx_ptr >= runtime->buffer_size) \
0058             rx_ptr = 0; \
0059     } \
0060     *period_elapsed = period_pos >= runtime->period_size; \
0061     return rx_ptr; \
0062 }
0063
0064 dw_pcm_tx_fn(16);
0065 dw_pcm_tx_fn(32);
0066 dw_pcm_rx_fn(16);
0067 dw_pcm_rx_fn(32);
0068
0069 #undef dw_pcm_tx_fn
0070 #undef dw_pcm_rx_fn
0071
0072 static const struct snd_pcm_hardware dw_pcm_hardware = {
0073     .info = SNDRV_PCM_INFO_INTERLEAVED |
0074         SNDRV_PCM_INFO_MMAP |
0075         SNDRV_PCM_INFO_MMAP_VALID |
0076         SNDRV_PCM_INFO_BLOCK_TRANSFER,
0077     .rates = SNDRV_PCM_RATE_32000 |
0078         SNDRV_PCM_RATE_44100 |
0079         SNDRV_PCM_RATE_48000,
0080     .rate_min = 32000,
0081     .rate_max = 48000,
0082     .formats = SNDRV_PCM_FMTBIT_S16_LE |
0083         SNDRV_PCM_FMTBIT_S24_LE |
0084         SNDRV_PCM_FMTBIT_S32_LE,
0085     .channels_min = 2,
0086     .channels_max = 2,
0087     .buffer_bytes_max = BUFFER_BYTES_MAX,
0088     .period_bytes_min = PERIOD_BYTES_MIN,
0089     .period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
0090     .periods_min = PERIODS_MIN,
0091     .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
0092     .fifo_size = 16,
0093 };
0094
0095 static void dw_pcm_transfer(struct dw_i2s_dev *dev, bool push)
0096 {
0097     struct snd_pcm_substream *substream;
0098     bool active, period_elapsed;
0099
0100     rcu_read_lock();
0101     if (push)
0102         substream = rcu_dereference(dev->tx_substream);
0103     else
0104         substream = rcu_dereference(dev->rx_substream);
0105     active = substream && snd_pcm_running(substream);
0106     if (active) {
0107         unsigned int ptr;
0108         unsigned int new_ptr;
0109
0110         if (push) {
0111             ptr = READ_ONCE(dev->tx_ptr);
0112             new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
0113                     &period_elapsed);
0114             cmpxchg(&dev->tx_ptr, ptr, new_ptr);
0115         } else {
0116             ptr = READ_ONCE(dev->rx_ptr);
0117             new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
0118                     &period_elapsed);
0119             cmpxchg(&dev->rx_ptr, ptr, new_ptr);
0120         }
0121
0122         if (period_elapsed)
0123             snd_pcm_period_elapsed(substream);
0124     }
0125     rcu_read_unlock();
0126 }
0127
0128 void dw_pcm_push_tx(struct dw_i2s_dev *dev)
0129 {
0130     dw_pcm_transfer(dev, true);
0131 }
0132
0133 void dw_pcm_pop_rx(struct dw_i2s_dev *dev)
0134 {
0135     dw_pcm_transfer(dev, false);
0136 }
0137
0138 static int dw_pcm_open(struct snd_soc_component *component,
0139                struct snd_pcm_substream *substream)
0140 {
0141     struct snd_pcm_runtime *runtime = substream->runtime;
0142     struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
0143     struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
0144
0145     snd_soc_set_runtime_hwparams(substream, &dw_pcm_hardware);
0146     snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
0147     runtime->private_data = dev;
0148
0149     return 0;
0150 }
0151
0152 static int dw_pcm_close(struct snd_soc_component *component,
0153             struct snd_pcm_substream *substream)
0154 {
0155     synchronize_rcu();
0156     return 0;
0157 }
0158
0159 static int dw_pcm_hw_params(struct snd_soc_component *component,
0160                 struct snd_pcm_substream *substream,
0161                 struct snd_pcm_hw_params *hw_params)
0162 {
0163     struct snd_pcm_runtime *runtime = substream->runtime;
0164     struct dw_i2s_dev *dev = runtime->private_data;
0165
0166     switch (params_channels(hw_params)) {
0167     case 2:
0168         break;
0169     default:
0170         dev_err(dev->dev, "invalid channels number\n");
0171         return -EINVAL;
0172     }
0173
0174     switch (params_format(hw_params)) {
0175     case SNDRV_PCM_FORMAT_S16_LE:
0176         dev->tx_fn = dw_pcm_tx_16;
0177         dev->rx_fn = dw_pcm_rx_16;
0178         break;
0179     case SNDRV_PCM_FORMAT_S24_LE:
0180     case SNDRV_PCM_FORMAT_S32_LE:
0181         dev->tx_fn = dw_pcm_tx_32;
0182         dev->rx_fn = dw_pcm_rx_32;
0183         break;
0184     default:
0185         dev_err(dev->dev, "invalid format\n");
0186         return -EINVAL;
0187     }
0188
0189     return 0;
0190 }
0191
0192 static int dw_pcm_trigger(struct snd_soc_component *component,
0193               struct snd_pcm_substream *substream, int cmd)
0194 {
0195     struct snd_pcm_runtime *runtime = substream->runtime;
0196     struct dw_i2s_dev *dev = runtime->private_data;
0197     int ret = 0;
0198
0199     switch (cmd) {
0200     case SNDRV_PCM_TRIGGER_START:
0201     case SNDRV_PCM_TRIGGER_RESUME:
0202     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0203         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0204             WRITE_ONCE(dev->tx_ptr, 0);
0205             rcu_assign_pointer(dev->tx_substream, substream);
0206         } else {
0207             WRITE_ONCE(dev->rx_ptr, 0);
0208             rcu_assign_pointer(dev->rx_substream, substream);
0209         }
0210         break;
0211     case SNDRV_PCM_TRIGGER_STOP:
0212     case SNDRV_PCM_TRIGGER_SUSPEND:
0213     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0214         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0215             rcu_assign_pointer(dev->tx_substream, NULL);
0216         else
0217             rcu_assign_pointer(dev->rx_substream, NULL);
0218         break;
0219     default:
0220         ret = -EINVAL;
0221         break;
0222     }
0223
0224     return ret;
0225 }
0226
0227 static snd_pcm_uframes_t dw_pcm_pointer(struct snd_soc_component *component,
0228                     struct snd_pcm_substream *substream)
0229 {
0230     struct snd_pcm_runtime *runtime = substream->runtime;
0231     struct dw_i2s_dev *dev = runtime->private_data;
0232     snd_pcm_uframes_t pos;
0233
0234     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0235         pos = READ_ONCE(dev->tx_ptr);
0236     else
0237         pos = READ_ONCE(dev->rx_ptr);
0238
0239     return pos < runtime->buffer_size ? pos : 0;
0240 }
0241
0242 static int dw_pcm_new(struct snd_soc_component *component,
0243               struct snd_soc_pcm_runtime *rtd)
0244 {
0245     size_t size = dw_pcm_hardware.buffer_bytes_max;
0246
0247     snd_pcm_set_managed_buffer_all(rtd->pcm,
0248             SNDRV_DMA_TYPE_CONTINUOUS,
0249             NULL, size, size);
0250     return 0;
0251 }
0252
0253 static const struct snd_soc_component_driver dw_pcm_component = {
0254     .open       = dw_pcm_open,
0255     .close      = dw_pcm_close,
0256     .hw_params  = dw_pcm_hw_params,
0257     .trigger    = dw_pcm_trigger,
0258     .pointer    = dw_pcm_pointer,
0259     .pcm_construct  = dw_pcm_new,
0260 };
0261
0262 int dw_pcm_register(struct platform_device *pdev)
0263 {
0264     return devm_snd_soc_register_component(&pdev->dev, &dw_pcm_component,
0265                            NULL, 0);
0266 }