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0001 /*
0002  * ALSA SoC Synopsys I2S Audio Layer
0003  *
0004  * sound/soc/dwc/designware_i2s.c
0005  *
0006  * Copyright (C) 2010 ST Microelectronics
0007  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
0008  *
0009  * This file is licensed under the terms of the GNU General Public
0010  * License version 2. This program is licensed "as is" without any
0011  * warranty of any kind, whether express or implied.
0012  */
0013 
0014 #include <linux/clk.h>
0015 #include <linux/device.h>
0016 #include <linux/init.h>
0017 #include <linux/io.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/module.h>
0020 #include <linux/slab.h>
0021 #include <linux/pm_runtime.h>
0022 #include <sound/designware_i2s.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/soc.h>
0026 #include <sound/dmaengine_pcm.h>
0027 #include "local.h"
0028 
0029 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
0030 {
0031     writel(val, io_base + reg);
0032 }
0033 
0034 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
0035 {
0036     return readl(io_base + reg);
0037 }
0038 
0039 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
0040 {
0041     u32 i = 0;
0042 
0043     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0044         for (i = 0; i < 4; i++)
0045             i2s_write_reg(dev->i2s_base, TER(i), 0);
0046     } else {
0047         for (i = 0; i < 4; i++)
0048             i2s_write_reg(dev->i2s_base, RER(i), 0);
0049     }
0050 }
0051 
0052 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
0053 {
0054     u32 i = 0;
0055 
0056     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0057         for (i = 0; i < 4; i++)
0058             i2s_read_reg(dev->i2s_base, TOR(i));
0059     } else {
0060         for (i = 0; i < 4; i++)
0061             i2s_read_reg(dev->i2s_base, ROR(i));
0062     }
0063 }
0064 
0065 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
0066                     int chan_nr)
0067 {
0068     u32 i, irq;
0069 
0070     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0071         for (i = 0; i < (chan_nr / 2); i++) {
0072             irq = i2s_read_reg(dev->i2s_base, IMR(i));
0073             i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
0074         }
0075     } else {
0076         for (i = 0; i < (chan_nr / 2); i++) {
0077             irq = i2s_read_reg(dev->i2s_base, IMR(i));
0078             i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
0079         }
0080     }
0081 }
0082 
0083 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
0084                    int chan_nr)
0085 {
0086     u32 i, irq;
0087 
0088     if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0089         for (i = 0; i < (chan_nr / 2); i++) {
0090             irq = i2s_read_reg(dev->i2s_base, IMR(i));
0091             i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
0092         }
0093     } else {
0094         for (i = 0; i < (chan_nr / 2); i++) {
0095             irq = i2s_read_reg(dev->i2s_base, IMR(i));
0096             i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
0097         }
0098     }
0099 }
0100 
0101 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
0102 {
0103     struct dw_i2s_dev *dev = dev_id;
0104     bool irq_valid = false;
0105     u32 isr[4];
0106     int i;
0107 
0108     for (i = 0; i < 4; i++)
0109         isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
0110 
0111     i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
0112     i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
0113 
0114     for (i = 0; i < 4; i++) {
0115         /*
0116          * Check if TX fifo is empty. If empty fill FIFO with samples
0117          * NOTE: Only two channels supported
0118          */
0119         if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
0120             dw_pcm_push_tx(dev);
0121             irq_valid = true;
0122         }
0123 
0124         /*
0125          * Data available. Retrieve samples from FIFO
0126          * NOTE: Only two channels supported
0127          */
0128         if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
0129             dw_pcm_pop_rx(dev);
0130             irq_valid = true;
0131         }
0132 
0133         /* Error Handling: TX */
0134         if (isr[i] & ISR_TXFO) {
0135             dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
0136             irq_valid = true;
0137         }
0138 
0139         /* Error Handling: TX */
0140         if (isr[i] & ISR_RXFO) {
0141             dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
0142             irq_valid = true;
0143         }
0144     }
0145 
0146     if (irq_valid)
0147         return IRQ_HANDLED;
0148     else
0149         return IRQ_NONE;
0150 }
0151 
0152 static void i2s_start(struct dw_i2s_dev *dev,
0153               struct snd_pcm_substream *substream)
0154 {
0155     struct i2s_clk_config_data *config = &dev->config;
0156 
0157     i2s_write_reg(dev->i2s_base, IER, 1);
0158     i2s_enable_irqs(dev, substream->stream, config->chan_nr);
0159 
0160     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0161         i2s_write_reg(dev->i2s_base, ITER, 1);
0162     else
0163         i2s_write_reg(dev->i2s_base, IRER, 1);
0164 
0165     i2s_write_reg(dev->i2s_base, CER, 1);
0166 }
0167 
0168 static void i2s_stop(struct dw_i2s_dev *dev,
0169         struct snd_pcm_substream *substream)
0170 {
0171 
0172     i2s_clear_irqs(dev, substream->stream);
0173     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0174         i2s_write_reg(dev->i2s_base, ITER, 0);
0175     else
0176         i2s_write_reg(dev->i2s_base, IRER, 0);
0177 
0178     i2s_disable_irqs(dev, substream->stream, 8);
0179 
0180     if (!dev->active) {
0181         i2s_write_reg(dev->i2s_base, CER, 0);
0182         i2s_write_reg(dev->i2s_base, IER, 0);
0183     }
0184 }
0185 
0186 static int dw_i2s_startup(struct snd_pcm_substream *substream,
0187         struct snd_soc_dai *cpu_dai)
0188 {
0189     struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
0190     union dw_i2s_snd_dma_data *dma_data = NULL;
0191 
0192     if (!(dev->capability & DWC_I2S_RECORD) &&
0193             (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
0194         return -EINVAL;
0195 
0196     if (!(dev->capability & DWC_I2S_PLAY) &&
0197             (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
0198         return -EINVAL;
0199 
0200     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0201         dma_data = &dev->play_dma_data;
0202     else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0203         dma_data = &dev->capture_dma_data;
0204 
0205     snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
0206 
0207     return 0;
0208 }
0209 
0210 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
0211 {
0212     u32 ch_reg;
0213     struct i2s_clk_config_data *config = &dev->config;
0214 
0215 
0216     i2s_disable_channels(dev, stream);
0217 
0218     for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
0219         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0220             i2s_write_reg(dev->i2s_base, TCR(ch_reg),
0221                       dev->xfer_resolution);
0222             i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
0223                       dev->fifo_th - 1);
0224             i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
0225         } else {
0226             i2s_write_reg(dev->i2s_base, RCR(ch_reg),
0227                       dev->xfer_resolution);
0228             i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
0229                       dev->fifo_th - 1);
0230             i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
0231         }
0232 
0233     }
0234 }
0235 
0236 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
0237         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
0238 {
0239     struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0240     struct i2s_clk_config_data *config = &dev->config;
0241     int ret;
0242 
0243     switch (params_format(params)) {
0244     case SNDRV_PCM_FORMAT_S16_LE:
0245         config->data_width = 16;
0246         dev->ccr = 0x00;
0247         dev->xfer_resolution = 0x02;
0248         break;
0249 
0250     case SNDRV_PCM_FORMAT_S24_LE:
0251         config->data_width = 24;
0252         dev->ccr = 0x08;
0253         dev->xfer_resolution = 0x04;
0254         break;
0255 
0256     case SNDRV_PCM_FORMAT_S32_LE:
0257         config->data_width = 32;
0258         dev->ccr = 0x10;
0259         dev->xfer_resolution = 0x05;
0260         break;
0261 
0262     default:
0263         dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
0264         return -EINVAL;
0265     }
0266 
0267     config->chan_nr = params_channels(params);
0268 
0269     switch (config->chan_nr) {
0270     case EIGHT_CHANNEL_SUPPORT:
0271     case SIX_CHANNEL_SUPPORT:
0272     case FOUR_CHANNEL_SUPPORT:
0273     case TWO_CHANNEL_SUPPORT:
0274         break;
0275     default:
0276         dev_err(dev->dev, "channel not supported\n");
0277         return -EINVAL;
0278     }
0279 
0280     dw_i2s_config(dev, substream->stream);
0281 
0282     i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
0283 
0284     config->sample_rate = params_rate(params);
0285 
0286     if (dev->capability & DW_I2S_MASTER) {
0287         if (dev->i2s_clk_cfg) {
0288             ret = dev->i2s_clk_cfg(config);
0289             if (ret < 0) {
0290                 dev_err(dev->dev, "runtime audio clk config fail\n");
0291                 return ret;
0292             }
0293         } else {
0294             u32 bitclk = config->sample_rate *
0295                     config->data_width * 2;
0296 
0297             ret = clk_set_rate(dev->clk, bitclk);
0298             if (ret) {
0299                 dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
0300                     ret);
0301                 return ret;
0302             }
0303         }
0304     }
0305     return 0;
0306 }
0307 
0308 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
0309         struct snd_soc_dai *dai)
0310 {
0311     snd_soc_dai_set_dma_data(dai, substream, NULL);
0312 }
0313 
0314 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
0315               struct snd_soc_dai *dai)
0316 {
0317     struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0318 
0319     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0320         i2s_write_reg(dev->i2s_base, TXFFR, 1);
0321     else
0322         i2s_write_reg(dev->i2s_base, RXFFR, 1);
0323 
0324     return 0;
0325 }
0326 
0327 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
0328         int cmd, struct snd_soc_dai *dai)
0329 {
0330     struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
0331     int ret = 0;
0332 
0333     switch (cmd) {
0334     case SNDRV_PCM_TRIGGER_START:
0335     case SNDRV_PCM_TRIGGER_RESUME:
0336     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0337         dev->active++;
0338         i2s_start(dev, substream);
0339         break;
0340 
0341     case SNDRV_PCM_TRIGGER_STOP:
0342     case SNDRV_PCM_TRIGGER_SUSPEND:
0343     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0344         dev->active--;
0345         i2s_stop(dev, substream);
0346         break;
0347     default:
0348         ret = -EINVAL;
0349         break;
0350     }
0351     return ret;
0352 }
0353 
0354 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
0355 {
0356     struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
0357     int ret = 0;
0358 
0359     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
0360     case SND_SOC_DAIFMT_BC_FC:
0361         if (dev->capability & DW_I2S_SLAVE)
0362             ret = 0;
0363         else
0364             ret = -EINVAL;
0365         break;
0366     case SND_SOC_DAIFMT_BP_FP:
0367         if (dev->capability & DW_I2S_MASTER)
0368             ret = 0;
0369         else
0370             ret = -EINVAL;
0371         break;
0372     case SND_SOC_DAIFMT_BC_FP:
0373     case SND_SOC_DAIFMT_BP_FC:
0374         ret = -EINVAL;
0375         break;
0376     default:
0377         dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");
0378         ret = -EINVAL;
0379         break;
0380     }
0381     return ret;
0382 }
0383 
0384 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
0385     .startup    = dw_i2s_startup,
0386     .shutdown   = dw_i2s_shutdown,
0387     .hw_params  = dw_i2s_hw_params,
0388     .prepare    = dw_i2s_prepare,
0389     .trigger    = dw_i2s_trigger,
0390     .set_fmt    = dw_i2s_set_fmt,
0391 };
0392 
0393 #ifdef CONFIG_PM
0394 static int dw_i2s_runtime_suspend(struct device *dev)
0395 {
0396     struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
0397 
0398     if (dw_dev->capability & DW_I2S_MASTER)
0399         clk_disable(dw_dev->clk);
0400     return 0;
0401 }
0402 
0403 static int dw_i2s_runtime_resume(struct device *dev)
0404 {
0405     struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
0406     int ret;
0407 
0408     if (dw_dev->capability & DW_I2S_MASTER) {
0409         ret = clk_enable(dw_dev->clk);
0410         if (ret)
0411             return ret;
0412     }
0413     return 0;
0414 }
0415 
0416 static int dw_i2s_suspend(struct snd_soc_component *component)
0417 {
0418     struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
0419 
0420     if (dev->capability & DW_I2S_MASTER)
0421         clk_disable(dev->clk);
0422     return 0;
0423 }
0424 
0425 static int dw_i2s_resume(struct snd_soc_component *component)
0426 {
0427     struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
0428     struct snd_soc_dai *dai;
0429     int stream, ret;
0430 
0431     if (dev->capability & DW_I2S_MASTER) {
0432         ret = clk_enable(dev->clk);
0433         if (ret)
0434             return ret;
0435     }
0436 
0437     for_each_component_dais(component, dai) {
0438         for_each_pcm_streams(stream)
0439             if (snd_soc_dai_stream_active(dai, stream))
0440                 dw_i2s_config(dev, stream);
0441     }
0442 
0443     return 0;
0444 }
0445 
0446 #else
0447 #define dw_i2s_suspend  NULL
0448 #define dw_i2s_resume   NULL
0449 #endif
0450 
0451 static const struct snd_soc_component_driver dw_i2s_component = {
0452     .name           = "dw-i2s",
0453     .suspend        = dw_i2s_suspend,
0454     .resume         = dw_i2s_resume,
0455     .legacy_dai_naming  = 1,
0456 };
0457 
0458 /*
0459  * The following tables allow a direct lookup of various parameters
0460  * defined in the I2S block's configuration in terms of sound system
0461  * parameters.  Each table is sized to the number of entries possible
0462  * according to the number of configuration bits describing an I2S
0463  * block parameter.
0464  */
0465 
0466 /* Maximum bit resolution of a channel - not uniformly spaced */
0467 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
0468     12, 16, 20, 24, 32, 0, 0, 0
0469 };
0470 
0471 /* Width of (DMA) bus */
0472 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
0473     DMA_SLAVE_BUSWIDTH_1_BYTE,
0474     DMA_SLAVE_BUSWIDTH_2_BYTES,
0475     DMA_SLAVE_BUSWIDTH_4_BYTES,
0476     DMA_SLAVE_BUSWIDTH_UNDEFINED
0477 };
0478 
0479 /* PCM format to support channel resolution */
0480 static const u32 formats[COMP_MAX_WORDSIZE] = {
0481     SNDRV_PCM_FMTBIT_S16_LE,
0482     SNDRV_PCM_FMTBIT_S16_LE,
0483     SNDRV_PCM_FMTBIT_S24_LE,
0484     SNDRV_PCM_FMTBIT_S24_LE,
0485     SNDRV_PCM_FMTBIT_S32_LE,
0486     0,
0487     0,
0488     0
0489 };
0490 
0491 static int dw_configure_dai(struct dw_i2s_dev *dev,
0492                    struct snd_soc_dai_driver *dw_i2s_dai,
0493                    unsigned int rates)
0494 {
0495     /*
0496      * Read component parameter registers to extract
0497      * the I2S block's configuration.
0498      */
0499     u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
0500     u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
0501     u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
0502     u32 idx;
0503 
0504     if (dev->capability & DWC_I2S_RECORD &&
0505             dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
0506         comp1 = comp1 & ~BIT(5);
0507 
0508     if (dev->capability & DWC_I2S_PLAY &&
0509             dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
0510         comp1 = comp1 & ~BIT(6);
0511 
0512     if (COMP1_TX_ENABLED(comp1)) {
0513         dev_dbg(dev->dev, " designware: play supported\n");
0514         idx = COMP1_TX_WORDSIZE_0(comp1);
0515         if (WARN_ON(idx >= ARRAY_SIZE(formats)))
0516             return -EINVAL;
0517         if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
0518             idx = 1;
0519         dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
0520         dw_i2s_dai->playback.channels_max =
0521                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
0522         dw_i2s_dai->playback.formats = formats[idx];
0523         dw_i2s_dai->playback.rates = rates;
0524     }
0525 
0526     if (COMP1_RX_ENABLED(comp1)) {
0527         dev_dbg(dev->dev, "designware: record supported\n");
0528         idx = COMP2_RX_WORDSIZE_0(comp2);
0529         if (WARN_ON(idx >= ARRAY_SIZE(formats)))
0530             return -EINVAL;
0531         if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
0532             idx = 1;
0533         dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
0534         dw_i2s_dai->capture.channels_max =
0535                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
0536         dw_i2s_dai->capture.formats = formats[idx];
0537         dw_i2s_dai->capture.rates = rates;
0538     }
0539 
0540     if (COMP1_MODE_EN(comp1)) {
0541         dev_dbg(dev->dev, "designware: i2s master mode supported\n");
0542         dev->capability |= DW_I2S_MASTER;
0543     } else {
0544         dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
0545         dev->capability |= DW_I2S_SLAVE;
0546     }
0547 
0548     dev->fifo_th = fifo_depth / 2;
0549     return 0;
0550 }
0551 
0552 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
0553                    struct snd_soc_dai_driver *dw_i2s_dai,
0554                    struct resource *res,
0555                    const struct i2s_platform_data *pdata)
0556 {
0557     u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
0558     u32 idx = COMP1_APB_DATA_WIDTH(comp1);
0559     int ret;
0560 
0561     if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
0562         return -EINVAL;
0563 
0564     ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
0565     if (ret < 0)
0566         return ret;
0567 
0568     if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
0569         idx = 1;
0570     /* Set DMA slaves info */
0571     dev->play_dma_data.pd.data = pdata->play_dma_data;
0572     dev->capture_dma_data.pd.data = pdata->capture_dma_data;
0573     dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
0574     dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
0575     dev->play_dma_data.pd.max_burst = 16;
0576     dev->capture_dma_data.pd.max_burst = 16;
0577     dev->play_dma_data.pd.addr_width = bus_widths[idx];
0578     dev->capture_dma_data.pd.addr_width = bus_widths[idx];
0579     dev->play_dma_data.pd.filter = pdata->filter;
0580     dev->capture_dma_data.pd.filter = pdata->filter;
0581 
0582     return 0;
0583 }
0584 
0585 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
0586                    struct snd_soc_dai_driver *dw_i2s_dai,
0587                    struct resource *res)
0588 {
0589     u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
0590     u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
0591     u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
0592     u32 idx = COMP1_APB_DATA_WIDTH(comp1);
0593     u32 idx2;
0594     int ret;
0595 
0596     if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
0597         return -EINVAL;
0598 
0599     ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
0600     if (ret < 0)
0601         return ret;
0602 
0603     if (COMP1_TX_ENABLED(comp1)) {
0604         idx2 = COMP1_TX_WORDSIZE_0(comp1);
0605 
0606         dev->capability |= DWC_I2S_PLAY;
0607         dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
0608         dev->play_dma_data.dt.addr_width = bus_widths[idx];
0609         dev->play_dma_data.dt.fifo_size = fifo_depth *
0610             (fifo_width[idx2]) >> 8;
0611         dev->play_dma_data.dt.maxburst = 16;
0612     }
0613     if (COMP1_RX_ENABLED(comp1)) {
0614         idx2 = COMP2_RX_WORDSIZE_0(comp2);
0615 
0616         dev->capability |= DWC_I2S_RECORD;
0617         dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
0618         dev->capture_dma_data.dt.addr_width = bus_widths[idx];
0619         dev->capture_dma_data.dt.fifo_size = fifo_depth *
0620             (fifo_width[idx2] >> 8);
0621         dev->capture_dma_data.dt.maxburst = 16;
0622     }
0623 
0624     return 0;
0625 
0626 }
0627 
0628 static int dw_i2s_probe(struct platform_device *pdev)
0629 {
0630     const struct i2s_platform_data *pdata = pdev->dev.platform_data;
0631     struct dw_i2s_dev *dev;
0632     struct resource *res;
0633     int ret, irq;
0634     struct snd_soc_dai_driver *dw_i2s_dai;
0635     const char *clk_id;
0636 
0637     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
0638     if (!dev)
0639         return -ENOMEM;
0640 
0641     dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
0642     if (!dw_i2s_dai)
0643         return -ENOMEM;
0644 
0645     dw_i2s_dai->ops = &dw_i2s_dai_ops;
0646 
0647     dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0648     if (IS_ERR(dev->i2s_base))
0649         return PTR_ERR(dev->i2s_base);
0650 
0651     dev->dev = &pdev->dev;
0652 
0653     irq = platform_get_irq_optional(pdev, 0);
0654     if (irq >= 0) {
0655         ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
0656                 pdev->name, dev);
0657         if (ret < 0) {
0658             dev_err(&pdev->dev, "failed to request irq\n");
0659             return ret;
0660         }
0661     }
0662 
0663     dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
0664     dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
0665     if (pdata) {
0666         dev->capability = pdata->cap;
0667         clk_id = NULL;
0668         dev->quirks = pdata->quirks;
0669         if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
0670             dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
0671             dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
0672         }
0673         ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
0674     } else {
0675         clk_id = "i2sclk";
0676         ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
0677     }
0678     if (ret < 0)
0679         return ret;
0680 
0681     if (dev->capability & DW_I2S_MASTER) {
0682         if (pdata) {
0683             dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
0684             if (!dev->i2s_clk_cfg) {
0685                 dev_err(&pdev->dev, "no clock configure method\n");
0686                 return -ENODEV;
0687             }
0688         }
0689         dev->clk = devm_clk_get(&pdev->dev, clk_id);
0690 
0691         if (IS_ERR(dev->clk))
0692             return PTR_ERR(dev->clk);
0693 
0694         ret = clk_prepare_enable(dev->clk);
0695         if (ret < 0)
0696             return ret;
0697     }
0698 
0699     dev_set_drvdata(&pdev->dev, dev);
0700     ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
0701                      dw_i2s_dai, 1);
0702     if (ret != 0) {
0703         dev_err(&pdev->dev, "not able to register dai\n");
0704         goto err_clk_disable;
0705     }
0706 
0707     if (!pdata) {
0708         if (irq >= 0) {
0709             ret = dw_pcm_register(pdev);
0710             dev->use_pio = true;
0711         } else {
0712             ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
0713                     0);
0714             dev->use_pio = false;
0715         }
0716 
0717         if (ret) {
0718             dev_err(&pdev->dev, "could not register pcm: %d\n",
0719                     ret);
0720             goto err_clk_disable;
0721         }
0722     }
0723 
0724     pm_runtime_enable(&pdev->dev);
0725     return 0;
0726 
0727 err_clk_disable:
0728     if (dev->capability & DW_I2S_MASTER)
0729         clk_disable_unprepare(dev->clk);
0730     return ret;
0731 }
0732 
0733 static int dw_i2s_remove(struct platform_device *pdev)
0734 {
0735     struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
0736 
0737     if (dev->capability & DW_I2S_MASTER)
0738         clk_disable_unprepare(dev->clk);
0739 
0740     pm_runtime_disable(&pdev->dev);
0741     return 0;
0742 }
0743 
0744 #ifdef CONFIG_OF
0745 static const struct of_device_id dw_i2s_of_match[] = {
0746     { .compatible = "snps,designware-i2s",   },
0747     {},
0748 };
0749 
0750 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
0751 #endif
0752 
0753 static const struct dev_pm_ops dwc_pm_ops = {
0754     SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
0755 };
0756 
0757 static struct platform_driver dw_i2s_driver = {
0758     .probe      = dw_i2s_probe,
0759     .remove     = dw_i2s_remove,
0760     .driver     = {
0761         .name   = "designware-i2s",
0762         .of_match_table = of_match_ptr(dw_i2s_of_match),
0763         .pm = &dwc_pm_ops,
0764     },
0765 };
0766 
0767 module_platform_driver(dw_i2s_driver);
0768 
0769 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
0770 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
0771 MODULE_LICENSE("GPL");
0772 MODULE_ALIAS("platform:designware_i2s");
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