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0006 #include <linux/bitops.h>
0007 #include <linux/debugfs.h>
0008 #include <linux/delay.h>
0009 #include <linux/device.h>
0010 #include <linux/gpio.h>
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of_gpio.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/printk.h>
0019 #include <linux/regmap.h>
0020 #include <linux/regulator/consumer.h>
0021 #include <linux/slab.h>
0022 #include <linux/soundwire/sdw.h>
0023 #include <linux/soundwire/sdw_registers.h>
0024 #include <linux/soundwire/sdw_type.h>
0025 #include <sound/pcm.h>
0026 #include <sound/pcm_params.h>
0027 #include <sound/soc-dapm.h>
0028 #include <sound/soc.h>
0029 #include <sound/tlv.h>
0030
0031 #define WSA883X_BASE 0x3000
0032 #define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE + 0x00000001)
0033 #define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE + 0x0000)
0034 #define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0001)
0035 #define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0002)
0036 #define WSA883X_OP_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0003)
0037 #define WSA883X_IREF_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0004)
0038 #define WSA883X_ISENS_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0005)
0039 #define WSA883X_CLK_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0006)
0040 #define WSA883X_TEST_CTL_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0007)
0041 #define WSA883X_BIAS_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0008)
0042 #define WSA883X_ADC_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0009)
0043 #define WSA883X_DOUT_MSB (WSA883X_ANA_BG_TSADC_BASE + 0x000A)
0044 #define WSA883X_DOUT_LSB (WSA883X_ANA_BG_TSADC_BASE + 0x000B)
0045 #define WSA883X_VBAT_SNS (WSA883X_ANA_BG_TSADC_BASE + 0x000C)
0046 #define WSA883X_ITRIM_CODE (WSA883X_ANA_BG_TSADC_BASE + 0x000D)
0047
0048 #define WSA883X_ANA_IVSENSE_BASE (WSA883X_BASE + 0x0000000F)
0049 #define WSA883X_EN (WSA883X_ANA_IVSENSE_BASE + 0x0000)
0050 #define WSA883X_OVERRIDE1 (WSA883X_ANA_IVSENSE_BASE + 0x0001)
0051 #define WSA883X_OVERRIDE2 (WSA883X_ANA_IVSENSE_BASE + 0x0002)
0052 #define WSA883X_VSENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0003)
0053 #define WSA883X_ISENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0004)
0054 #define WSA883X_ISENSE2 (WSA883X_ANA_IVSENSE_BASE + 0x0005)
0055 #define WSA883X_ISENSE_CAL (WSA883X_ANA_IVSENSE_BASE + 0x0006)
0056 #define WSA883X_MISC (WSA883X_ANA_IVSENSE_BASE + 0x0007)
0057 #define WSA883X_ADC_0 (WSA883X_ANA_IVSENSE_BASE + 0x0008)
0058 #define WSA883X_ADC_1 (WSA883X_ANA_IVSENSE_BASE + 0x0009)
0059 #define WSA883X_ADC_2 (WSA883X_ANA_IVSENSE_BASE + 0x000A)
0060 #define WSA883X_ADC_3 (WSA883X_ANA_IVSENSE_BASE + 0x000B)
0061 #define WSA883X_ADC_4 (WSA883X_ANA_IVSENSE_BASE + 0x000C)
0062 #define WSA883X_ADC_5 (WSA883X_ANA_IVSENSE_BASE + 0x000D)
0063 #define WSA883X_ADC_6 (WSA883X_ANA_IVSENSE_BASE + 0x000E)
0064 #define WSA883X_ADC_7 (WSA883X_ANA_IVSENSE_BASE + 0x000F)
0065 #define WSA883X_STATUS (WSA883X_ANA_IVSENSE_BASE + 0x0010)
0066
0067 #define WSA883X_ANA_SPK_TOP_BASE (WSA883X_BASE + 0x00000025)
0068 #define WSA883X_DAC_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0000)
0069 #define WSA883X_DAC_EN_DEBUG_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0001)
0070 #define WSA883X_DAC_OPAMP_BIAS1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0002)
0071 #define WSA883X_DAC_OPAMP_BIAS2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0003)
0072 #define WSA883X_DAC_VCM_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0004)
0073 #define WSA883X_DAC_VOLTAGE_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0005)
0074 #define WSA883X_ATEST1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0006)
0075 #define WSA883X_ATEST2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0007)
0076 #define WSA883X_SPKR_TOP_BIAS_REG1 (WSA883X_ANA_SPK_TOP_BASE + 0x0008)
0077 #define WSA883X_SPKR_TOP_BIAS_REG2 (WSA883X_ANA_SPK_TOP_BASE + 0x0009)
0078 #define WSA883X_SPKR_TOP_BIAS_REG3 (WSA883X_ANA_SPK_TOP_BASE + 0x000A)
0079 #define WSA883X_SPKR_TOP_BIAS_REG4 (WSA883X_ANA_SPK_TOP_BASE + 0x000B)
0080 #define WSA883X_SPKR_CLIP_DET_REG (WSA883X_ANA_SPK_TOP_BASE + 0x000C)
0081 #define WSA883X_SPKR_DRV_LF_BLK_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000D)
0082 #define WSA883X_SPKR_DRV_LF_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000E)
0083 #define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F)
0084 #define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0010)
0085 #define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE + 0x0011)
0086 #define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0012)
0087 #define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE + 0x0013)
0088 #define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0014)
0089 #define WSA883X_SPKR_PWM_FREQ_SEL_MASK BIT(3)
0090 #define WSA883X_SPKR_PWM_FREQ_F300KHZ 0
0091 #define WSA883X_SPKR_PWM_FREQ_F600KHZ 1
0092 #define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0015)
0093 #define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0016)
0094 #define WSA883X_SPKR_PWRSTG_DBG (WSA883X_ANA_SPK_TOP_BASE + 0x0017)
0095 #define WSA883X_SPKR_OCP_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0018)
0096 #define WSA883X_SPKR_BBM_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0019)
0097 #define WSA883X_PA_STATUS0 (WSA883X_ANA_SPK_TOP_BASE + 0x001A)
0098 #define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE + 0x001B)
0099 #define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE + 0x001C)
0100
0101 #define WSA883X_ANA_BOOST_BASE (WSA883X_BASE + 0x00000043)
0102 #define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE + 0x0000)
0103 #define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE + 0x0001)
0104 #define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE + 0x0002)
0105 #define WSA883X_IBIAS2 (WSA883X_ANA_BOOST_BASE + 0x0003)
0106 #define WSA883X_IBIAS3 (WSA883X_ANA_BOOST_BASE + 0x0004)
0107 #define WSA883X_LDO_PROG (WSA883X_ANA_BOOST_BASE + 0x0005)
0108 #define WSA883X_STABILITY_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0006)
0109 #define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0007)
0110 #define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0008)
0111 #define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0009)
0112 #define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE + 0x000A)
0113 #define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE + 0x000B)
0114 #define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE + 0x000C)
0115 #define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE + 0x000D)
0116 #define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE + 0x000E)
0117 #define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE + 0x000F)
0118 #define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE + 0x0010)
0119 #define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE + 0x0011)
0120 #define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE + 0x0012)
0121 #define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE + 0x0013)
0122 #define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE + 0x0014)
0123 #define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE + 0x0015)
0124
0125 #define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE + 0x00000059)
0126 #define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0000)
0127 #define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0001)
0128 #define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0002)
0129 #define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE + 0x0003)
0130 #define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0004)
0131 #define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0005)
0132 #define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0006)
0133 #define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0007)
0134 #define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0008)
0135 #define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0009)
0136 #define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000A)
0137 #define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE + 0x000B)
0138 #define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000C)
0139
0140 #define WSA883X_DIG_CTRL_BASE (WSA883X_BASE + 0x00000400)
0141 #define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE + 0x0001)
0142 #define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE + 0x0002)
0143 #define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE + 0x0003)
0144 #define WSA883X_CHIP_ID3 (WSA883X_DIG_CTRL_BASE + 0x0004)
0145 #define WSA883X_BUS_ID (WSA883X_DIG_CTRL_BASE + 0x0005)
0146 #define WSA883X_CDC_RST_CTL (WSA883X_DIG_CTRL_BASE + 0x0006)
0147 #define WSA883X_TOP_CLK_CFG (WSA883X_DIG_CTRL_BASE + 0x0007)
0148 #define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE + 0x0008)
0149 #define WSA883X_RXD_MODE_MASK BIT(1)
0150 #define WSA883X_RXD_MODE_NORMAL 0
0151 #define WSA883X_RXD_MODE_HIFI 1
0152 #define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE + 0x0009)
0153 #define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE + 0x000A)
0154 #define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE + 0x000B)
0155 #define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE + 0x0010)
0156 #define WSA883X_GLOBAL_PA_EN_MASK BIT(0)
0157 #define WSA883X_GLOBAL_PA_ENABLE 1
0158 #define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE + 0x0011)
0159 #define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE + 0x0012)
0160 #define WSA883X_PA_FSM_STA (WSA883X_DIG_CTRL_BASE + 0x0013)
0161 #define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE + 0x0014)
0162 #define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE + 0x0015)
0163 #define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE + 0x0016)
0164 #define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE + 0x0017)
0165 #define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE + 0x0020)
0166 #define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE + 0x0021)
0167 #define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE + 0x0022)
0168 #define WSA883X_TEMP_LSB (WSA883X_DIG_CTRL_BASE + 0x0023)
0169 #define WSA883X_TEMP_CONFIG0 (WSA883X_DIG_CTRL_BASE + 0x0024)
0170 #define WSA883X_TEMP_CONFIG1 (WSA883X_DIG_CTRL_BASE + 0x0025)
0171 #define WSA883X_VBAT_ADC_FLT_CTL (WSA883X_DIG_CTRL_BASE + 0x0026)
0172 #define WSA883X_VBAT_ADC_FLT_EN_MASK BIT(0)
0173 #define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1)
0174 #define WSA883X_VBAT_ADC_COEF_F_1DIV2 0x0
0175 #define WSA883X_VBAT_ADC_COEF_F_1DIV16 0x3
0176 #define WSA883X_VBAT_DIN_MSB (WSA883X_DIG_CTRL_BASE + 0x0027)
0177 #define WSA883X_VBAT_DIN_LSB (WSA883X_DIG_CTRL_BASE + 0x0028)
0178 #define WSA883X_VBAT_DOUT (WSA883X_DIG_CTRL_BASE + 0x0029)
0179 #define WSA883X_SDM_PDM9_LSB (WSA883X_DIG_CTRL_BASE + 0x002A)
0180 #define WSA883X_SDM_PDM9_MSB (WSA883X_DIG_CTRL_BASE + 0x002B)
0181 #define WSA883X_CDC_RX_CTL (WSA883X_DIG_CTRL_BASE + 0x0030)
0182 #define WSA883X_CDC_SPK_DSM_A1_0 (WSA883X_DIG_CTRL_BASE + 0x0031)
0183 #define WSA883X_CDC_SPK_DSM_A1_1 (WSA883X_DIG_CTRL_BASE + 0x0032)
0184 #define WSA883X_CDC_SPK_DSM_A2_0 (WSA883X_DIG_CTRL_BASE + 0x0033)
0185 #define WSA883X_CDC_SPK_DSM_A2_1 (WSA883X_DIG_CTRL_BASE + 0x0034)
0186 #define WSA883X_CDC_SPK_DSM_A3_0 (WSA883X_DIG_CTRL_BASE + 0x0035)
0187 #define WSA883X_CDC_SPK_DSM_A3_1 (WSA883X_DIG_CTRL_BASE + 0x0036)
0188 #define WSA883X_CDC_SPK_DSM_A4_0 (WSA883X_DIG_CTRL_BASE + 0x0037)
0189 #define WSA883X_CDC_SPK_DSM_A4_1 (WSA883X_DIG_CTRL_BASE + 0x0038)
0190 #define WSA883X_CDC_SPK_DSM_A5_0 (WSA883X_DIG_CTRL_BASE + 0x0039)
0191 #define WSA883X_CDC_SPK_DSM_A5_1 (WSA883X_DIG_CTRL_BASE + 0x003A)
0192 #define WSA883X_CDC_SPK_DSM_A6_0 (WSA883X_DIG_CTRL_BASE + 0x003B)
0193 #define WSA883X_CDC_SPK_DSM_A7_0 (WSA883X_DIG_CTRL_BASE + 0x003C)
0194 #define WSA883X_CDC_SPK_DSM_C_0 (WSA883X_DIG_CTRL_BASE + 0x003D)
0195 #define WSA883X_CDC_SPK_DSM_C_1 (WSA883X_DIG_CTRL_BASE + 0x003E)
0196 #define WSA883X_CDC_SPK_DSM_C_2 (WSA883X_DIG_CTRL_BASE + 0x003F)
0197 #define WSA883X_CDC_SPK_DSM_C_3 (WSA883X_DIG_CTRL_BASE + 0x0040)
0198 #define WSA883X_CDC_SPK_DSM_R1 (WSA883X_DIG_CTRL_BASE + 0x0041)
0199 #define WSA883X_CDC_SPK_DSM_R2 (WSA883X_DIG_CTRL_BASE + 0x0042)
0200 #define WSA883X_CDC_SPK_DSM_R3 (WSA883X_DIG_CTRL_BASE + 0x0043)
0201 #define WSA883X_CDC_SPK_DSM_R4 (WSA883X_DIG_CTRL_BASE + 0x0044)
0202 #define WSA883X_CDC_SPK_DSM_R5 (WSA883X_DIG_CTRL_BASE + 0x0045)
0203 #define WSA883X_CDC_SPK_DSM_R6 (WSA883X_DIG_CTRL_BASE + 0x0046)
0204 #define WSA883X_CDC_SPK_DSM_R7 (WSA883X_DIG_CTRL_BASE + 0x0047)
0205 #define WSA883X_CDC_SPK_GAIN_PDM_0 (WSA883X_DIG_CTRL_BASE + 0x0048)
0206 #define WSA883X_CDC_SPK_GAIN_PDM_1 (WSA883X_DIG_CTRL_BASE + 0x0049)
0207 #define WSA883X_CDC_SPK_GAIN_PDM_2 (WSA883X_DIG_CTRL_BASE + 0x004A)
0208 #define WSA883X_PDM_WD_CTL (WSA883X_DIG_CTRL_BASE + 0x004B)
0209 #define WSA883X_PDM_EN_MASK BIT(0)
0210 #define WSA883X_PDM_ENABLE BIT(0)
0211 #define WSA883X_DEM_BYPASS_DATA0 (WSA883X_DIG_CTRL_BASE + 0x004C)
0212 #define WSA883X_DEM_BYPASS_DATA1 (WSA883X_DIG_CTRL_BASE + 0x004D)
0213 #define WSA883X_DEM_BYPASS_DATA2 (WSA883X_DIG_CTRL_BASE + 0x004E)
0214 #define WSA883X_DEM_BYPASS_DATA3 (WSA883X_DIG_CTRL_BASE + 0x004F)
0215 #define WSA883X_WAVG_CTL (WSA883X_DIG_CTRL_BASE + 0x0050)
0216 #define WSA883X_WAVG_LRA_PER_0 (WSA883X_DIG_CTRL_BASE + 0x0051)
0217 #define WSA883X_WAVG_LRA_PER_1 (WSA883X_DIG_CTRL_BASE + 0x0052)
0218 #define WSA883X_WAVG_DELTA_THETA_0 (WSA883X_DIG_CTRL_BASE + 0x0053)
0219 #define WSA883X_WAVG_DELTA_THETA_1 (WSA883X_DIG_CTRL_BASE + 0x0054)
0220 #define WSA883X_WAVG_DIRECT_AMP_0 (WSA883X_DIG_CTRL_BASE + 0x0055)
0221 #define WSA883X_WAVG_DIRECT_AMP_1 (WSA883X_DIG_CTRL_BASE + 0x0056)
0222 #define WSA883X_WAVG_PTRN_AMP0_0 (WSA883X_DIG_CTRL_BASE + 0x0057)
0223 #define WSA883X_WAVG_PTRN_AMP0_1 (WSA883X_DIG_CTRL_BASE + 0x0058)
0224 #define WSA883X_WAVG_PTRN_AMP1_0 (WSA883X_DIG_CTRL_BASE + 0x0059)
0225 #define WSA883X_WAVG_PTRN_AMP1_1 (WSA883X_DIG_CTRL_BASE + 0x005A)
0226 #define WSA883X_WAVG_PTRN_AMP2_0 (WSA883X_DIG_CTRL_BASE + 0x005B)
0227 #define WSA883X_WAVG_PTRN_AMP2_1 (WSA883X_DIG_CTRL_BASE + 0x005C)
0228 #define WSA883X_WAVG_PTRN_AMP3_0 (WSA883X_DIG_CTRL_BASE + 0x005D)
0229 #define WSA883X_WAVG_PTRN_AMP3_1 (WSA883X_DIG_CTRL_BASE + 0x005E)
0230 #define WSA883X_WAVG_PTRN_AMP4_0 (WSA883X_DIG_CTRL_BASE + 0x005F)
0231 #define WSA883X_WAVG_PTRN_AMP4_1 (WSA883X_DIG_CTRL_BASE + 0x0060)
0232 #define WSA883X_WAVG_PTRN_AMP5_0 (WSA883X_DIG_CTRL_BASE + 0x0061)
0233 #define WSA883X_WAVG_PTRN_AMP5_1 (WSA883X_DIG_CTRL_BASE + 0x0062)
0234 #define WSA883X_WAVG_PTRN_AMP6_0 (WSA883X_DIG_CTRL_BASE + 0x0063)
0235 #define WSA883X_WAVG_PTRN_AMP6_1 (WSA883X_DIG_CTRL_BASE + 0x0064)
0236 #define WSA883X_WAVG_PTRN_AMP7_0 (WSA883X_DIG_CTRL_BASE + 0x0065)
0237 #define WSA883X_WAVG_PTRN_AMP7_1 (WSA883X_DIG_CTRL_BASE + 0x0066)
0238 #define WSA883X_WAVG_PER_0_1 (WSA883X_DIG_CTRL_BASE + 0x0067)
0239 #define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE + 0x0068)
0240 #define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE + 0x0069)
0241 #define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE + 0x006A)
0242 #define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE + 0x006B)
0243 #define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x006C)
0244 #define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0)
0245 #define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4)
0246 #define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x006D)
0247 #define WSA883X_DRE_GAIN_EN_MASK BIT(0)
0248 #define WSA883X_DRE_GAIN_FROM_CSR 1
0249 #define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE + 0x006E)
0250 #define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x0070)
0251 #define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x0071)
0252 #define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE + 0x0072)
0253 #define WSA883X_CLSH_V_PA_MIN (WSA883X_DIG_CTRL_BASE + 0x0073)
0254 #define WSA883X_CLSH_OVRD_VAL (WSA883X_DIG_CTRL_BASE + 0x0074)
0255 #define WSA883X_CLSH_HARD_MAX (WSA883X_DIG_CTRL_BASE + 0x0075)
0256 #define WSA883X_CLSH_SOFT_MAX (WSA883X_DIG_CTRL_BASE + 0x0076)
0257 #define WSA883X_CLSH_SIG_DP (WSA883X_DIG_CTRL_BASE + 0x0077)
0258 #define WSA883X_TAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x0078)
0259 #define WSA883X_TAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x0079)
0260 #define WSA883X_TAGC_E2E_GAIN (WSA883X_DIG_CTRL_BASE + 0x007A)
0261 #define WSA883X_TAGC_FORCE_VAL (WSA883X_DIG_CTRL_BASE + 0x007B)
0262 #define WSA883X_VAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x007C)
0263 #define WSA883X_VAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x007D)
0264 #define WSA883X_VAGC_ATTN_LVL_1_2 (WSA883X_DIG_CTRL_BASE + 0x007E)
0265 #define WSA883X_VAGC_ATTN_LVL_3 (WSA883X_DIG_CTRL_BASE + 0x007F)
0266 #define WSA883X_INTR_MODE (WSA883X_DIG_CTRL_BASE + 0x0080)
0267 #define WSA883X_INTR_MASK0 (WSA883X_DIG_CTRL_BASE + 0x0081)
0268 #define WSA883X_INTR_MASK1 (WSA883X_DIG_CTRL_BASE + 0x0082)
0269 #define WSA883X_INTR_STATUS0 (WSA883X_DIG_CTRL_BASE + 0x0083)
0270 #define WSA883X_INTR_STATUS1 (WSA883X_DIG_CTRL_BASE + 0x0084)
0271 #define WSA883X_INTR_CLEAR0 (WSA883X_DIG_CTRL_BASE + 0x0085)
0272 #define WSA883X_INTR_CLEAR1 (WSA883X_DIG_CTRL_BASE + 0x0086)
0273 #define WSA883X_INTR_LEVEL0 (WSA883X_DIG_CTRL_BASE + 0x0087)
0274 #define WSA883X_INTR_LEVEL1 (WSA883X_DIG_CTRL_BASE + 0x0088)
0275 #define WSA883X_INTR_SET0 (WSA883X_DIG_CTRL_BASE + 0x0089)
0276 #define WSA883X_INTR_SET1 (WSA883X_DIG_CTRL_BASE + 0x008A)
0277 #define WSA883X_INTR_TEST0 (WSA883X_DIG_CTRL_BASE + 0x008B)
0278 #define WSA883X_INTR_TEST1 (WSA883X_DIG_CTRL_BASE + 0x008C)
0279 #define WSA883X_OTP_CTRL0 (WSA883X_DIG_CTRL_BASE + 0x0090)
0280 #define WSA883X_OTP_CTRL1 (WSA883X_DIG_CTRL_BASE + 0x0091)
0281 #define WSA883X_HDRIVE_CTL_GROUP1 (WSA883X_DIG_CTRL_BASE + 0x0092)
0282 #define WSA883X_PIN_CTL (WSA883X_DIG_CTRL_BASE + 0x0093)
0283 #define WSA883X_PIN_CTL_OE (WSA883X_DIG_CTRL_BASE + 0x0094)
0284 #define WSA883X_PIN_WDATA_IOPAD (WSA883X_DIG_CTRL_BASE + 0x0095)
0285 #define WSA883X_PIN_STATUS (WSA883X_DIG_CTRL_BASE + 0x0096)
0286 #define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE + 0x0097)
0287 #define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A0)
0288 #define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A1)
0289 #define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE + 0x00A3)
0290 #define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE + 0x00A4)
0291 #define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE + 0x00A5)
0292 #define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE + 0x00A6)
0293 #define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE + 0x00A7)
0294 #define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00A8)
0295 #define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00A9)
0296 #define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE + 0x00AA)
0297 #define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE + 0x00AB)
0298 #define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AC)
0299 #define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AD)
0300 #define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE + 0x00AE)
0301 #define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00AF)
0302 #define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE + 0x00B0)
0303 #define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00B1)
0304 #define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE + 0x00BC)
0305 #define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE + 0x00BD)
0306 #define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE + 0x00BE)
0307 #define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE + 0x00BF)
0308 #define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE + 0x00C0)
0309
0310 #define WSA883X_DIG_TRIM_BASE (WSA883X_BASE + 0x00000500)
0311 #define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE + 0x0080)
0312 #define WSA883X_ID_MASK GENMASK(3, 0)
0313 #define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE + 0x0081)
0314 #define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE + 0x0082)
0315 #define WSA883X_OTP_REG_3 (WSA883X_DIG_TRIM_BASE + 0x0083)
0316 #define WSA883X_OTP_REG_4 (WSA883X_DIG_TRIM_BASE + 0x0084)
0317 #define WSA883X_OTP_REG_5 (WSA883X_DIG_TRIM_BASE + 0x0085)
0318 #define WSA883X_OTP_REG_6 (WSA883X_DIG_TRIM_BASE + 0x0086)
0319 #define WSA883X_OTP_REG_7 (WSA883X_DIG_TRIM_BASE + 0x0087)
0320 #define WSA883X_OTP_REG_8 (WSA883X_DIG_TRIM_BASE + 0x0088)
0321 #define WSA883X_OTP_REG_9 (WSA883X_DIG_TRIM_BASE + 0x0089)
0322 #define WSA883X_OTP_REG_10 (WSA883X_DIG_TRIM_BASE + 0x008A)
0323 #define WSA883X_OTP_REG_11 (WSA883X_DIG_TRIM_BASE + 0x008B)
0324 #define WSA883X_OTP_REG_12 (WSA883X_DIG_TRIM_BASE + 0x008C)
0325 #define WSA883X_OTP_REG_13 (WSA883X_DIG_TRIM_BASE + 0x008D)
0326 #define WSA883X_OTP_REG_14 (WSA883X_DIG_TRIM_BASE + 0x008E)
0327 #define WSA883X_OTP_REG_15 (WSA883X_DIG_TRIM_BASE + 0x008F)
0328 #define WSA883X_OTP_REG_16 (WSA883X_DIG_TRIM_BASE + 0x0090)
0329 #define WSA883X_OTP_REG_17 (WSA883X_DIG_TRIM_BASE + 0x0091)
0330 #define WSA883X_OTP_REG_18 (WSA883X_DIG_TRIM_BASE + 0x0092)
0331 #define WSA883X_OTP_REG_19 (WSA883X_DIG_TRIM_BASE + 0x0093)
0332 #define WSA883X_OTP_REG_20 (WSA883X_DIG_TRIM_BASE + 0x0094)
0333 #define WSA883X_OTP_REG_21 (WSA883X_DIG_TRIM_BASE + 0x0095)
0334 #define WSA883X_OTP_REG_22 (WSA883X_DIG_TRIM_BASE + 0x0096)
0335 #define WSA883X_OTP_REG_23 (WSA883X_DIG_TRIM_BASE + 0x0097)
0336 #define WSA883X_OTP_REG_24 (WSA883X_DIG_TRIM_BASE + 0x0098)
0337 #define WSA883X_OTP_REG_25 (WSA883X_DIG_TRIM_BASE + 0x0099)
0338 #define WSA883X_OTP_REG_26 (WSA883X_DIG_TRIM_BASE + 0x009A)
0339 #define WSA883X_OTP_REG_27 (WSA883X_DIG_TRIM_BASE + 0x009B)
0340 #define WSA883X_OTP_REG_28 (WSA883X_DIG_TRIM_BASE + 0x009C)
0341 #define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE + 0x009D)
0342 #define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE + 0x009E)
0343 #define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE + 0x009F)
0344 #define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE + 0x00A0)
0345 #define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE + 0x00A1)
0346 #define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE + 0x00A2)
0347 #define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE + 0x00A3)
0348 #define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE + 0x00BF)
0349
0350 #define WSA883X_DIG_EMEM_BASE (WSA883X_BASE + 0x000005C0)
0351 #define WSA883X_EMEM_0 (WSA883X_DIG_EMEM_BASE + 0x0000)
0352 #define WSA883X_EMEM_1 (WSA883X_DIG_EMEM_BASE + 0x0001)
0353 #define WSA883X_EMEM_2 (WSA883X_DIG_EMEM_BASE + 0x0002)
0354 #define WSA883X_EMEM_3 (WSA883X_DIG_EMEM_BASE + 0x0003)
0355 #define WSA883X_EMEM_4 (WSA883X_DIG_EMEM_BASE + 0x0004)
0356 #define WSA883X_EMEM_5 (WSA883X_DIG_EMEM_BASE + 0x0005)
0357 #define WSA883X_EMEM_6 (WSA883X_DIG_EMEM_BASE + 0x0006)
0358 #define WSA883X_EMEM_7 (WSA883X_DIG_EMEM_BASE + 0x0007)
0359 #define WSA883X_EMEM_8 (WSA883X_DIG_EMEM_BASE + 0x0008)
0360 #define WSA883X_EMEM_9 (WSA883X_DIG_EMEM_BASE + 0x0009)
0361 #define WSA883X_EMEM_10 (WSA883X_DIG_EMEM_BASE + 0x000A)
0362 #define WSA883X_EMEM_11 (WSA883X_DIG_EMEM_BASE + 0x000B)
0363 #define WSA883X_EMEM_12 (WSA883X_DIG_EMEM_BASE + 0x000C)
0364 #define WSA883X_EMEM_13 (WSA883X_DIG_EMEM_BASE + 0x000D)
0365 #define WSA883X_EMEM_14 (WSA883X_DIG_EMEM_BASE + 0x000E)
0366 #define WSA883X_EMEM_15 (WSA883X_DIG_EMEM_BASE + 0x000F)
0367 #define WSA883X_EMEM_16 (WSA883X_DIG_EMEM_BASE + 0x0010)
0368 #define WSA883X_EMEM_17 (WSA883X_DIG_EMEM_BASE + 0x0011)
0369 #define WSA883X_EMEM_18 (WSA883X_DIG_EMEM_BASE + 0x0012)
0370 #define WSA883X_EMEM_19 (WSA883X_DIG_EMEM_BASE + 0x0013)
0371 #define WSA883X_EMEM_20 (WSA883X_DIG_EMEM_BASE + 0x0014)
0372 #define WSA883X_EMEM_21 (WSA883X_DIG_EMEM_BASE + 0x0015)
0373 #define WSA883X_EMEM_22 (WSA883X_DIG_EMEM_BASE + 0x0016)
0374 #define WSA883X_EMEM_23 (WSA883X_DIG_EMEM_BASE + 0x0017)
0375 #define WSA883X_EMEM_24 (WSA883X_DIG_EMEM_BASE + 0x0018)
0376 #define WSA883X_EMEM_25 (WSA883X_DIG_EMEM_BASE + 0x0019)
0377 #define WSA883X_EMEM_26 (WSA883X_DIG_EMEM_BASE + 0x001A)
0378 #define WSA883X_EMEM_27 (WSA883X_DIG_EMEM_BASE + 0x001B)
0379 #define WSA883X_EMEM_28 (WSA883X_DIG_EMEM_BASE + 0x001C)
0380 #define WSA883X_EMEM_29 (WSA883X_DIG_EMEM_BASE + 0x001D)
0381 #define WSA883X_EMEM_30 (WSA883X_DIG_EMEM_BASE + 0x001E)
0382 #define WSA883X_EMEM_31 (WSA883X_DIG_EMEM_BASE + 0x001F)
0383 #define WSA883X_EMEM_32 (WSA883X_DIG_EMEM_BASE + 0x0020)
0384 #define WSA883X_EMEM_33 (WSA883X_DIG_EMEM_BASE + 0x0021)
0385 #define WSA883X_EMEM_34 (WSA883X_DIG_EMEM_BASE + 0x0022)
0386 #define WSA883X_EMEM_35 (WSA883X_DIG_EMEM_BASE + 0x0023)
0387 #define WSA883X_EMEM_36 (WSA883X_DIG_EMEM_BASE + 0x0024)
0388 #define WSA883X_EMEM_37 (WSA883X_DIG_EMEM_BASE + 0x0025)
0389 #define WSA883X_EMEM_38 (WSA883X_DIG_EMEM_BASE + 0x0026)
0390 #define WSA883X_EMEM_39 (WSA883X_DIG_EMEM_BASE + 0x0027)
0391 #define WSA883X_EMEM_40 (WSA883X_DIG_EMEM_BASE + 0x0028)
0392 #define WSA883X_EMEM_41 (WSA883X_DIG_EMEM_BASE + 0x0029)
0393 #define WSA883X_EMEM_42 (WSA883X_DIG_EMEM_BASE + 0x002A)
0394 #define WSA883X_EMEM_43 (WSA883X_DIG_EMEM_BASE + 0x002B)
0395 #define WSA883X_EMEM_44 (WSA883X_DIG_EMEM_BASE + 0x002C)
0396 #define WSA883X_EMEM_45 (WSA883X_DIG_EMEM_BASE + 0x002D)
0397 #define WSA883X_EMEM_46 (WSA883X_DIG_EMEM_BASE + 0x002E)
0398 #define WSA883X_EMEM_47 (WSA883X_DIG_EMEM_BASE + 0x002F)
0399 #define WSA883X_EMEM_48 (WSA883X_DIG_EMEM_BASE + 0x0030)
0400 #define WSA883X_EMEM_49 (WSA883X_DIG_EMEM_BASE + 0x0031)
0401 #define WSA883X_EMEM_50 (WSA883X_DIG_EMEM_BASE + 0x0032)
0402 #define WSA883X_EMEM_51 (WSA883X_DIG_EMEM_BASE + 0x0033)
0403 #define WSA883X_EMEM_52 (WSA883X_DIG_EMEM_BASE + 0x0034)
0404 #define WSA883X_EMEM_53 (WSA883X_DIG_EMEM_BASE + 0x0035)
0405 #define WSA883X_EMEM_54 (WSA883X_DIG_EMEM_BASE + 0x0036)
0406 #define WSA883X_EMEM_55 (WSA883X_DIG_EMEM_BASE + 0x0037)
0407 #define WSA883X_EMEM_56 (WSA883X_DIG_EMEM_BASE + 0x0038)
0408 #define WSA883X_EMEM_57 (WSA883X_DIG_EMEM_BASE + 0x0039)
0409 #define WSA883X_EMEM_58 (WSA883X_DIG_EMEM_BASE + 0x003A)
0410 #define WSA883X_EMEM_59 (WSA883X_DIG_EMEM_BASE + 0x003B)
0411 #define WSA883X_EMEM_60 (WSA883X_DIG_EMEM_BASE + 0x003C)
0412 #define WSA883X_EMEM_61 (WSA883X_DIG_EMEM_BASE + 0x003D)
0413 #define WSA883X_EMEM_62 (WSA883X_DIG_EMEM_BASE + 0x003E)
0414 #define WSA883X_EMEM_63 (WSA883X_DIG_EMEM_BASE + 0x003F)
0415
0416 #define WSA883X_NUM_REGISTERS (WSA883X_EMEM_63 + 1)
0417 #define WSA883X_MAX_REGISTER (WSA883X_NUM_REGISTERS - 1)
0418 #define WSA883X_PROBE_TIMEOUT 1000
0419
0420 #define WSA883X_VERSION_1_0 0
0421 #define WSA883X_VERSION_1_1 1
0422
0423 #define WSA883X_MAX_SWR_PORTS 4
0424 #define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0425 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
0426 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
0427 SNDRV_PCM_RATE_384000)
0428
0429 #define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
0430 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
0431
0432 #define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
0433 SNDRV_PCM_FMTBIT_S24_LE |\
0434 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
0435
0436 struct wsa883x_priv {
0437 struct regmap *regmap;
0438 struct device *dev;
0439 struct regulator *vdd;
0440 struct sdw_slave *slave;
0441 struct sdw_stream_config sconfig;
0442 struct sdw_stream_runtime *sruntime;
0443 struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS];
0444 struct gpio_desc *sd_n;
0445 bool port_prepared[WSA883X_MAX_SWR_PORTS];
0446 bool port_enable[WSA883X_MAX_SWR_PORTS];
0447 int version;
0448 int variant;
0449 int active_ports;
0450 int dev_mode;
0451 int comp_offset;
0452 };
0453
0454 enum {
0455 WSA8830 = 0,
0456 WSA8835,
0457 WSA8832,
0458 WSA8835_V2 = 5,
0459 };
0460
0461 enum {
0462 COMP_OFFSET0,
0463 COMP_OFFSET1,
0464 COMP_OFFSET2,
0465 COMP_OFFSET3,
0466 COMP_OFFSET4,
0467 };
0468
0469 enum wsa_port_ids {
0470 WSA883X_PORT_DAC,
0471 WSA883X_PORT_COMP,
0472 WSA883X_PORT_BOOST,
0473 WSA883X_PORT_VISENSE,
0474 };
0475
0476 static const char * const wsa_dev_mode_text[] = {
0477 "Speaker", "Receiver", "Ultrasound"
0478 };
0479
0480 enum {
0481 SPEAKER,
0482 RECEIVER,
0483 ULTRASOUND,
0484 };
0485
0486 static const struct soc_enum wsa_dev_mode_enum =
0487 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
0488
0489
0490 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = {
0491 {
0492
0493 .num = 1,
0494 .type = SDW_DPN_SIMPLE,
0495 .min_ch = 1,
0496 .max_ch = 1,
0497 .simple_ch_prep_sm = true,
0498 .read_only_wordlength = true,
0499 }, {
0500
0501 .num = 2,
0502 .type = SDW_DPN_SIMPLE,
0503 .min_ch = 1,
0504 .max_ch = 1,
0505 .simple_ch_prep_sm = true,
0506 .read_only_wordlength = true,
0507 }, {
0508
0509 .num = 3,
0510 .type = SDW_DPN_SIMPLE,
0511 .min_ch = 1,
0512 .max_ch = 1,
0513 .simple_ch_prep_sm = true,
0514 .read_only_wordlength = true,
0515 }, {
0516
0517 .num = 4,
0518 .type = SDW_DPN_SIMPLE,
0519 .min_ch = 1,
0520 .max_ch = 1,
0521 .simple_ch_prep_sm = true,
0522 .read_only_wordlength = true,
0523 }
0524 };
0525
0526 static struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = {
0527 {
0528 .num = 1,
0529 .ch_mask = 0x1,
0530 }, {
0531 .num = 2,
0532 .ch_mask = 0xf,
0533 }, {
0534 .num = 3,
0535 .ch_mask = 0x3,
0536 }, {
0537 .num = 4,
0538 .ch_mask = 0x3,
0539 },
0540 };
0541
0542 static struct reg_default wsa883x_defaults[] = {
0543 { WSA883X_REF_CTRL, 0xD5 },
0544 { WSA883X_TEST_CTL_0, 0x06 },
0545 { WSA883X_BIAS_0, 0xD2 },
0546 { WSA883X_OP_CTL, 0xE0 },
0547 { WSA883X_IREF_CTL, 0x57 },
0548 { WSA883X_ISENS_CTL, 0x47 },
0549 { WSA883X_CLK_CTL, 0x87 },
0550 { WSA883X_TEST_CTL_1, 0x00 },
0551 { WSA883X_BIAS_1, 0x51 },
0552 { WSA883X_ADC_CTL, 0x01 },
0553 { WSA883X_DOUT_MSB, 0x00 },
0554 { WSA883X_DOUT_LSB, 0x00 },
0555 { WSA883X_VBAT_SNS, 0x40 },
0556 { WSA883X_ITRIM_CODE, 0x9F },
0557 { WSA883X_EN, 0x20 },
0558 { WSA883X_OVERRIDE1, 0x00 },
0559 { WSA883X_OVERRIDE2, 0x08 },
0560 { WSA883X_VSENSE1, 0xD3 },
0561 { WSA883X_ISENSE1, 0xD4 },
0562 { WSA883X_ISENSE2, 0x20 },
0563 { WSA883X_ISENSE_CAL, 0x00 },
0564 { WSA883X_MISC, 0x08 },
0565 { WSA883X_ADC_0, 0x00 },
0566 { WSA883X_ADC_1, 0x00 },
0567 { WSA883X_ADC_2, 0x40 },
0568 { WSA883X_ADC_3, 0x80 },
0569 { WSA883X_ADC_4, 0x25 },
0570 { WSA883X_ADC_5, 0x25 },
0571 { WSA883X_ADC_6, 0x08 },
0572 { WSA883X_ADC_7, 0x81 },
0573 { WSA883X_STATUS, 0x00 },
0574 { WSA883X_DAC_CTRL_REG, 0x53 },
0575 { WSA883X_DAC_EN_DEBUG_REG, 0x00 },
0576 { WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 },
0577 { WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 },
0578 { WSA883X_DAC_VCM_CTRL_REG, 0x88 },
0579 { WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 },
0580 { WSA883X_ATEST1_REG, 0x00 },
0581 { WSA883X_ATEST2_REG, 0x00 },
0582 { WSA883X_SPKR_TOP_BIAS_REG1, 0x6A },
0583 { WSA883X_SPKR_TOP_BIAS_REG2, 0x65 },
0584 { WSA883X_SPKR_TOP_BIAS_REG3, 0x55 },
0585 { WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 },
0586 { WSA883X_SPKR_CLIP_DET_REG, 0x9C },
0587 { WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F },
0588 { WSA883X_SPKR_DRV_LF_EN, 0x0A },
0589 { WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 },
0590 { WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A },
0591 { WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 },
0592 { WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 },
0593 { WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 },
0594 { WSA883X_SPKR_PWM_CLK_CTL, 0x00 },
0595 { WSA883X_SPKR_PDRV_HS_CTL, 0x52 },
0596 { WSA883X_SPKR_PDRV_LS_CTL, 0x48 },
0597 { WSA883X_SPKR_PWRSTG_DBG, 0x08 },
0598 { WSA883X_SPKR_OCP_CTL, 0xE2 },
0599 { WSA883X_SPKR_BBM_CTL, 0x92 },
0600 { WSA883X_PA_STATUS0, 0x00 },
0601 { WSA883X_PA_STATUS1, 0x00 },
0602 { WSA883X_PA_STATUS2, 0x80 },
0603 { WSA883X_EN_CTRL, 0x44 },
0604 { WSA883X_CURRENT_LIMIT, 0xCC },
0605 { WSA883X_IBIAS1, 0x00 },
0606 { WSA883X_IBIAS2, 0x00 },
0607 { WSA883X_IBIAS3, 0x00 },
0608 { WSA883X_LDO_PROG, 0x02 },
0609 { WSA883X_STABILITY_CTRL1, 0x8E },
0610 { WSA883X_STABILITY_CTRL2, 0x10 },
0611 { WSA883X_PWRSTAGE_CTRL1, 0x06 },
0612 { WSA883X_PWRSTAGE_CTRL2, 0x00 },
0613 { WSA883X_BYPASS_1, 0x19 },
0614 { WSA883X_BYPASS_2, 0x13 },
0615 { WSA883X_ZX_CTRL_1, 0xF0 },
0616 { WSA883X_ZX_CTRL_2, 0x04 },
0617 { WSA883X_MISC1, 0x06 },
0618 { WSA883X_MISC2, 0xA0 },
0619 { WSA883X_GMAMP_SUP1, 0x82 },
0620 { WSA883X_PWRSTAGE_CTRL3, 0x39 },
0621 { WSA883X_PWRSTAGE_CTRL4, 0x5F },
0622 { WSA883X_TEST1, 0x00 },
0623 { WSA883X_SPARE1, 0x00 },
0624 { WSA883X_SPARE2, 0x00 },
0625 { WSA883X_PON_CTL_0, 0x10 },
0626 { WSA883X_PON_CLT_1, 0xE0 },
0627 { WSA883X_PON_CTL_2, 0x90 },
0628 { WSA883X_PON_CTL_3, 0x70 },
0629 { WSA883X_CKWD_CTL_0, 0x34 },
0630 { WSA883X_CKWD_CTL_1, 0x0F },
0631 { WSA883X_CKWD_CTL_2, 0x00 },
0632 { WSA883X_CKSK_CTL_0, 0x00 },
0633 { WSA883X_PADSW_CTL_0, 0x00 },
0634 { WSA883X_TEST_0, 0x00 },
0635 { WSA883X_TEST_1, 0x00 },
0636 { WSA883X_STATUS_0, 0x00 },
0637 { WSA883X_STATUS_1, 0x00 },
0638 { WSA883X_CHIP_ID0, 0x00 },
0639 { WSA883X_CHIP_ID1, 0x00 },
0640 { WSA883X_CHIP_ID2, 0x02 },
0641 { WSA883X_CHIP_ID3, 0x02 },
0642 { WSA883X_BUS_ID, 0x00 },
0643 { WSA883X_CDC_RST_CTL, 0x01 },
0644 { WSA883X_TOP_CLK_CFG, 0x00 },
0645 { WSA883X_CDC_PATH_MODE, 0x00 },
0646 { WSA883X_CDC_CLK_CTL, 0xFF },
0647 { WSA883X_SWR_RESET_EN, 0x00 },
0648 { WSA883X_RESET_CTL, 0x00 },
0649 { WSA883X_PA_FSM_CTL, 0x00 },
0650 { WSA883X_PA_FSM_TIMER0, 0x80 },
0651 { WSA883X_PA_FSM_TIMER1, 0x80 },
0652 { WSA883X_PA_FSM_STA, 0x00 },
0653 { WSA883X_PA_FSM_ERR_COND, 0x00 },
0654 { WSA883X_PA_FSM_MSK, 0x00 },
0655 { WSA883X_PA_FSM_BYP, 0x01 },
0656 { WSA883X_PA_FSM_DBG, 0x00 },
0657 { WSA883X_TADC_VALUE_CTL, 0x03 },
0658 { WSA883X_TEMP_DETECT_CTL, 0x01 },
0659 { WSA883X_TEMP_MSB, 0x00 },
0660 { WSA883X_TEMP_LSB, 0x00 },
0661 { WSA883X_TEMP_CONFIG0, 0x00 },
0662 { WSA883X_TEMP_CONFIG1, 0x00 },
0663 { WSA883X_VBAT_ADC_FLT_CTL, 0x00 },
0664 { WSA883X_VBAT_DIN_MSB, 0x00 },
0665 { WSA883X_VBAT_DIN_LSB, 0x00 },
0666 { WSA883X_VBAT_DOUT, 0x00 },
0667 { WSA883X_SDM_PDM9_LSB, 0x00 },
0668 { WSA883X_SDM_PDM9_MSB, 0x00 },
0669 { WSA883X_CDC_RX_CTL, 0xFE },
0670 { WSA883X_CDC_SPK_DSM_A1_0, 0x00 },
0671 { WSA883X_CDC_SPK_DSM_A1_1, 0x01 },
0672 { WSA883X_CDC_SPK_DSM_A2_0, 0x96 },
0673 { WSA883X_CDC_SPK_DSM_A2_1, 0x09 },
0674 { WSA883X_CDC_SPK_DSM_A3_0, 0xAB },
0675 { WSA883X_CDC_SPK_DSM_A3_1, 0x05 },
0676 { WSA883X_CDC_SPK_DSM_A4_0, 0x1C },
0677 { WSA883X_CDC_SPK_DSM_A4_1, 0x02 },
0678 { WSA883X_CDC_SPK_DSM_A5_0, 0x17 },
0679 { WSA883X_CDC_SPK_DSM_A5_1, 0x02 },
0680 { WSA883X_CDC_SPK_DSM_A6_0, 0xAA },
0681 { WSA883X_CDC_SPK_DSM_A7_0, 0xE3 },
0682 { WSA883X_CDC_SPK_DSM_C_0, 0x69 },
0683 { WSA883X_CDC_SPK_DSM_C_1, 0x54 },
0684 { WSA883X_CDC_SPK_DSM_C_2, 0x02 },
0685 { WSA883X_CDC_SPK_DSM_C_3, 0x15 },
0686 { WSA883X_CDC_SPK_DSM_R1, 0xA4 },
0687 { WSA883X_CDC_SPK_DSM_R2, 0xB5 },
0688 { WSA883X_CDC_SPK_DSM_R3, 0x86 },
0689 { WSA883X_CDC_SPK_DSM_R4, 0x85 },
0690 { WSA883X_CDC_SPK_DSM_R5, 0xAA },
0691 { WSA883X_CDC_SPK_DSM_R6, 0xE2 },
0692 { WSA883X_CDC_SPK_DSM_R7, 0x62 },
0693 { WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 },
0694 { WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC },
0695 { WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 },
0696 { WSA883X_PDM_WD_CTL, 0x00 },
0697 { WSA883X_DEM_BYPASS_DATA0, 0x00 },
0698 { WSA883X_DEM_BYPASS_DATA1, 0x00 },
0699 { WSA883X_DEM_BYPASS_DATA2, 0x00 },
0700 { WSA883X_DEM_BYPASS_DATA3, 0x00 },
0701 { WSA883X_WAVG_CTL, 0x06 },
0702 { WSA883X_WAVG_LRA_PER_0, 0xD1 },
0703 { WSA883X_WAVG_LRA_PER_1, 0x00 },
0704 { WSA883X_WAVG_DELTA_THETA_0, 0xE6 },
0705 { WSA883X_WAVG_DELTA_THETA_1, 0x04 },
0706 { WSA883X_WAVG_DIRECT_AMP_0, 0x50 },
0707 { WSA883X_WAVG_DIRECT_AMP_1, 0x00 },
0708 { WSA883X_WAVG_PTRN_AMP0_0, 0x50 },
0709 { WSA883X_WAVG_PTRN_AMP0_1, 0x00 },
0710 { WSA883X_WAVG_PTRN_AMP1_0, 0x50 },
0711 { WSA883X_WAVG_PTRN_AMP1_1, 0x00 },
0712 { WSA883X_WAVG_PTRN_AMP2_0, 0x50 },
0713 { WSA883X_WAVG_PTRN_AMP2_1, 0x00 },
0714 { WSA883X_WAVG_PTRN_AMP3_0, 0x50 },
0715 { WSA883X_WAVG_PTRN_AMP3_1, 0x00 },
0716 { WSA883X_WAVG_PTRN_AMP4_0, 0x50 },
0717 { WSA883X_WAVG_PTRN_AMP4_1, 0x00 },
0718 { WSA883X_WAVG_PTRN_AMP5_0, 0x50 },
0719 { WSA883X_WAVG_PTRN_AMP5_1, 0x00 },
0720 { WSA883X_WAVG_PTRN_AMP6_0, 0x50 },
0721 { WSA883X_WAVG_PTRN_AMP6_1, 0x00 },
0722 { WSA883X_WAVG_PTRN_AMP7_0, 0x50 },
0723 { WSA883X_WAVG_PTRN_AMP7_1, 0x00 },
0724 { WSA883X_WAVG_PER_0_1, 0x88 },
0725 { WSA883X_WAVG_PER_2_3, 0x88 },
0726 { WSA883X_WAVG_PER_4_5, 0x88 },
0727 { WSA883X_WAVG_PER_6_7, 0x88 },
0728 { WSA883X_WAVG_STA, 0x00 },
0729 { WSA883X_DRE_CTL_0, 0x70 },
0730 { WSA883X_DRE_CTL_1, 0x08 },
0731 { WSA883X_DRE_IDLE_DET_CTL, 0x1F },
0732 { WSA883X_CLSH_CTL_0, 0x37 },
0733 { WSA883X_CLSH_CTL_1, 0x81 },
0734 { WSA883X_CLSH_V_HD_PA, 0x0F },
0735 { WSA883X_CLSH_V_PA_MIN, 0x00 },
0736 { WSA883X_CLSH_OVRD_VAL, 0x00 },
0737 { WSA883X_CLSH_HARD_MAX, 0xFF },
0738 { WSA883X_CLSH_SOFT_MAX, 0xF5 },
0739 { WSA883X_CLSH_SIG_DP, 0x00 },
0740 { WSA883X_TAGC_CTL, 0x10 },
0741 { WSA883X_TAGC_TIME, 0x20 },
0742 { WSA883X_TAGC_E2E_GAIN, 0x02 },
0743 { WSA883X_TAGC_FORCE_VAL, 0x00 },
0744 { WSA883X_VAGC_CTL, 0x00 },
0745 { WSA883X_VAGC_TIME, 0x08 },
0746 { WSA883X_VAGC_ATTN_LVL_1_2, 0x21 },
0747 { WSA883X_VAGC_ATTN_LVL_3, 0x03 },
0748 { WSA883X_INTR_MODE, 0x00 },
0749 { WSA883X_INTR_MASK0, 0x90 },
0750 { WSA883X_INTR_MASK1, 0x00 },
0751 { WSA883X_INTR_STATUS0, 0x00 },
0752 { WSA883X_INTR_STATUS1, 0x00 },
0753 { WSA883X_INTR_CLEAR0, 0x00 },
0754 { WSA883X_INTR_CLEAR1, 0x00 },
0755 { WSA883X_INTR_LEVEL0, 0x00 },
0756 { WSA883X_INTR_LEVEL1, 0x00 },
0757 { WSA883X_INTR_SET0, 0x00 },
0758 { WSA883X_INTR_SET1, 0x00 },
0759 { WSA883X_INTR_TEST0, 0x00 },
0760 { WSA883X_INTR_TEST1, 0x00 },
0761 { WSA883X_OTP_CTRL0, 0x00 },
0762 { WSA883X_OTP_CTRL1, 0x00 },
0763 { WSA883X_HDRIVE_CTL_GROUP1, 0x00 },
0764 { WSA883X_PIN_CTL, 0x04 },
0765 { WSA883X_PIN_CTL_OE, 0x00 },
0766 { WSA883X_PIN_WDATA_IOPAD, 0x00 },
0767 { WSA883X_PIN_STATUS, 0x00 },
0768 { WSA883X_I2C_SLAVE_CTL, 0x00 },
0769 { WSA883X_PDM_TEST_MODE, 0x00 },
0770 { WSA883X_ATE_TEST_MODE, 0x00 },
0771 { WSA883X_DIG_DEBUG_MODE, 0x00 },
0772 { WSA883X_DIG_DEBUG_SEL, 0x00 },
0773 { WSA883X_DIG_DEBUG_EN, 0x00 },
0774 { WSA883X_SWR_HM_TEST0, 0x08 },
0775 { WSA883X_SWR_HM_TEST1, 0x00 },
0776 { WSA883X_SWR_PAD_CTL, 0x37 },
0777 { WSA883X_TADC_DETECT_DBG_CTL, 0x00 },
0778 { WSA883X_TADC_DEBUG_MSB, 0x00 },
0779 { WSA883X_TADC_DEBUG_LSB, 0x00 },
0780 { WSA883X_SAMPLE_EDGE_SEL, 0x7F },
0781 { WSA883X_SWR_EDGE_SEL, 0x00 },
0782 { WSA883X_TEST_MODE_CTL, 0x04 },
0783 { WSA883X_IOPAD_CTL, 0x00 },
0784 { WSA883X_ANA_CSR_DBG_ADD, 0x00 },
0785 { WSA883X_ANA_CSR_DBG_CTL, 0x12 },
0786 { WSA883X_SPARE_R, 0x00 },
0787 { WSA883X_SPARE_0, 0x00 },
0788 { WSA883X_SPARE_1, 0x00 },
0789 { WSA883X_SPARE_2, 0x00 },
0790 { WSA883X_SCODE, 0x00 },
0791 { WSA883X_OTP_REG_0, 0x05 },
0792 { WSA883X_OTP_REG_1, 0xFF },
0793 { WSA883X_OTP_REG_2, 0xC0 },
0794 { WSA883X_OTP_REG_3, 0xFF },
0795 { WSA883X_OTP_REG_4, 0xC0 },
0796 { WSA883X_OTP_REG_5, 0xFF },
0797 { WSA883X_OTP_REG_6, 0xFF },
0798 { WSA883X_OTP_REG_7, 0xFF },
0799 { WSA883X_OTP_REG_8, 0xFF },
0800 { WSA883X_OTP_REG_9, 0xFF },
0801 { WSA883X_OTP_REG_10, 0xFF },
0802 { WSA883X_OTP_REG_11, 0xFF },
0803 { WSA883X_OTP_REG_12, 0xFF },
0804 { WSA883X_OTP_REG_13, 0xFF },
0805 { WSA883X_OTP_REG_14, 0xFF },
0806 { WSA883X_OTP_REG_15, 0xFF },
0807 { WSA883X_OTP_REG_16, 0xFF },
0808 { WSA883X_OTP_REG_17, 0xFF },
0809 { WSA883X_OTP_REG_18, 0xFF },
0810 { WSA883X_OTP_REG_19, 0xFF },
0811 { WSA883X_OTP_REG_20, 0xFF },
0812 { WSA883X_OTP_REG_21, 0xFF },
0813 { WSA883X_OTP_REG_22, 0xFF },
0814 { WSA883X_OTP_REG_23, 0xFF },
0815 { WSA883X_OTP_REG_24, 0x37 },
0816 { WSA883X_OTP_REG_25, 0x3F },
0817 { WSA883X_OTP_REG_26, 0x03 },
0818 { WSA883X_OTP_REG_27, 0x00 },
0819 { WSA883X_OTP_REG_28, 0x00 },
0820 { WSA883X_OTP_REG_29, 0x00 },
0821 { WSA883X_OTP_REG_30, 0x00 },
0822 { WSA883X_OTP_REG_31, 0x03 },
0823 { WSA883X_OTP_REG_32, 0x00 },
0824 { WSA883X_OTP_REG_33, 0xFF },
0825 { WSA883X_OTP_REG_34, 0x00 },
0826 { WSA883X_OTP_REG_35, 0x00 },
0827 { WSA883X_OTP_REG_63, 0x40 },
0828 { WSA883X_EMEM_0, 0x00 },
0829 { WSA883X_EMEM_1, 0x00 },
0830 { WSA883X_EMEM_2, 0x00 },
0831 { WSA883X_EMEM_3, 0x00 },
0832 { WSA883X_EMEM_4, 0x00 },
0833 { WSA883X_EMEM_5, 0x00 },
0834 { WSA883X_EMEM_6, 0x00 },
0835 { WSA883X_EMEM_7, 0x00 },
0836 { WSA883X_EMEM_8, 0x00 },
0837 { WSA883X_EMEM_9, 0x00 },
0838 { WSA883X_EMEM_10, 0x00 },
0839 { WSA883X_EMEM_11, 0x00 },
0840 { WSA883X_EMEM_12, 0x00 },
0841 { WSA883X_EMEM_13, 0x00 },
0842 { WSA883X_EMEM_14, 0x00 },
0843 { WSA883X_EMEM_15, 0x00 },
0844 { WSA883X_EMEM_16, 0x00 },
0845 { WSA883X_EMEM_17, 0x00 },
0846 { WSA883X_EMEM_18, 0x00 },
0847 { WSA883X_EMEM_19, 0x00 },
0848 { WSA883X_EMEM_20, 0x00 },
0849 { WSA883X_EMEM_21, 0x00 },
0850 { WSA883X_EMEM_22, 0x00 },
0851 { WSA883X_EMEM_23, 0x00 },
0852 { WSA883X_EMEM_24, 0x00 },
0853 { WSA883X_EMEM_25, 0x00 },
0854 { WSA883X_EMEM_26, 0x00 },
0855 { WSA883X_EMEM_27, 0x00 },
0856 { WSA883X_EMEM_28, 0x00 },
0857 { WSA883X_EMEM_29, 0x00 },
0858 { WSA883X_EMEM_30, 0x00 },
0859 { WSA883X_EMEM_31, 0x00 },
0860 { WSA883X_EMEM_32, 0x00 },
0861 { WSA883X_EMEM_33, 0x00 },
0862 { WSA883X_EMEM_34, 0x00 },
0863 { WSA883X_EMEM_35, 0x00 },
0864 { WSA883X_EMEM_36, 0x00 },
0865 { WSA883X_EMEM_37, 0x00 },
0866 { WSA883X_EMEM_38, 0x00 },
0867 { WSA883X_EMEM_39, 0x00 },
0868 { WSA883X_EMEM_40, 0x00 },
0869 { WSA883X_EMEM_41, 0x00 },
0870 { WSA883X_EMEM_42, 0x00 },
0871 { WSA883X_EMEM_43, 0x00 },
0872 { WSA883X_EMEM_44, 0x00 },
0873 { WSA883X_EMEM_45, 0x00 },
0874 { WSA883X_EMEM_46, 0x00 },
0875 { WSA883X_EMEM_47, 0x00 },
0876 { WSA883X_EMEM_48, 0x00 },
0877 { WSA883X_EMEM_49, 0x00 },
0878 { WSA883X_EMEM_50, 0x00 },
0879 { WSA883X_EMEM_51, 0x00 },
0880 { WSA883X_EMEM_52, 0x00 },
0881 { WSA883X_EMEM_53, 0x00 },
0882 { WSA883X_EMEM_54, 0x00 },
0883 { WSA883X_EMEM_55, 0x00 },
0884 { WSA883X_EMEM_56, 0x00 },
0885 { WSA883X_EMEM_57, 0x00 },
0886 { WSA883X_EMEM_58, 0x00 },
0887 { WSA883X_EMEM_59, 0x00 },
0888 { WSA883X_EMEM_60, 0x00 },
0889 { WSA883X_EMEM_61, 0x00 },
0890 { WSA883X_EMEM_62, 0x00 },
0891 { WSA883X_EMEM_63, 0x00 },
0892 };
0893
0894 static bool wsa883x_readonly_register(struct device *dev, unsigned int reg)
0895 {
0896 switch (reg) {
0897 case WSA883X_DOUT_MSB:
0898 case WSA883X_DOUT_LSB:
0899 case WSA883X_STATUS:
0900 case WSA883X_PA_STATUS0:
0901 case WSA883X_PA_STATUS1:
0902 case WSA883X_PA_STATUS2:
0903 case WSA883X_STATUS_0:
0904 case WSA883X_STATUS_1:
0905 case WSA883X_CHIP_ID0:
0906 case WSA883X_CHIP_ID1:
0907 case WSA883X_CHIP_ID2:
0908 case WSA883X_CHIP_ID3:
0909 case WSA883X_BUS_ID:
0910 case WSA883X_PA_FSM_STA:
0911 case WSA883X_PA_FSM_ERR_COND:
0912 case WSA883X_TEMP_MSB:
0913 case WSA883X_TEMP_LSB:
0914 case WSA883X_VBAT_DIN_MSB:
0915 case WSA883X_VBAT_DIN_LSB:
0916 case WSA883X_VBAT_DOUT:
0917 case WSA883X_SDM_PDM9_LSB:
0918 case WSA883X_SDM_PDM9_MSB:
0919 case WSA883X_WAVG_STA:
0920 case WSA883X_INTR_STATUS0:
0921 case WSA883X_INTR_STATUS1:
0922 case WSA883X_OTP_CTRL1:
0923 case WSA883X_PIN_STATUS:
0924 case WSA883X_ATE_TEST_MODE:
0925 case WSA883X_SWR_HM_TEST1:
0926 case WSA883X_SPARE_R:
0927 case WSA883X_OTP_REG_0:
0928 return true;
0929 }
0930 return false;
0931 }
0932
0933 static bool wsa883x_writeable_register(struct device *dev, unsigned int reg)
0934 {
0935 return !wsa883x_readonly_register(dev, reg);
0936 }
0937
0938 static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
0939 {
0940 return wsa883x_readonly_register(dev, reg);
0941 }
0942
0943 static struct regmap_config wsa883x_regmap_config = {
0944 .reg_bits = 32,
0945 .val_bits = 8,
0946 .cache_type = REGCACHE_RBTREE,
0947 .reg_defaults = wsa883x_defaults,
0948 .max_register = WSA883X_MAX_REGISTER,
0949 .num_reg_defaults = ARRAY_SIZE(wsa883x_defaults),
0950 .volatile_reg = wsa883x_volatile_register,
0951 .writeable_reg = wsa883x_writeable_register,
0952 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
0953 .val_format_endian = REGMAP_ENDIAN_NATIVE,
0954 .can_multi_write = true,
0955 .use_single_read = true,
0956 };
0957
0958 static const struct reg_sequence reg_init[] = {
0959 {WSA883X_PA_FSM_BYP, 0x00},
0960 {WSA883X_ADC_6, 0x02},
0961 {WSA883X_CDC_SPK_DSM_A2_0, 0x0A},
0962 {WSA883X_CDC_SPK_DSM_A2_1, 0x08},
0963 {WSA883X_CDC_SPK_DSM_A3_0, 0xF3},
0964 {WSA883X_CDC_SPK_DSM_A3_1, 0x07},
0965 {WSA883X_CDC_SPK_DSM_A4_0, 0x79},
0966 {WSA883X_CDC_SPK_DSM_A4_1, 0x02},
0967 {WSA883X_CDC_SPK_DSM_A5_0, 0x0B},
0968 {WSA883X_CDC_SPK_DSM_A5_1, 0x02},
0969 {WSA883X_CDC_SPK_DSM_A6_0, 0x8A},
0970 {WSA883X_CDC_SPK_DSM_A7_0, 0x9B},
0971 {WSA883X_CDC_SPK_DSM_C_0, 0x68},
0972 {WSA883X_CDC_SPK_DSM_C_1, 0x54},
0973 {WSA883X_CDC_SPK_DSM_C_2, 0xF2},
0974 {WSA883X_CDC_SPK_DSM_C_3, 0x20},
0975 {WSA883X_CDC_SPK_DSM_R1, 0x83},
0976 {WSA883X_CDC_SPK_DSM_R2, 0x7F},
0977 {WSA883X_CDC_SPK_DSM_R3, 0x9D},
0978 {WSA883X_CDC_SPK_DSM_R4, 0x82},
0979 {WSA883X_CDC_SPK_DSM_R5, 0x8B},
0980 {WSA883X_CDC_SPK_DSM_R6, 0x9B},
0981 {WSA883X_CDC_SPK_DSM_R7, 0x3F},
0982 {WSA883X_VBAT_SNS, 0x20},
0983 {WSA883X_DRE_CTL_0, 0x92},
0984 {WSA883X_DRE_IDLE_DET_CTL, 0x0F},
0985 {WSA883X_CURRENT_LIMIT, 0xC4},
0986 {WSA883X_VAGC_TIME, 0x0F},
0987 {WSA883X_VAGC_ATTN_LVL_1_2, 0x00},
0988 {WSA883X_VAGC_ATTN_LVL_3, 0x01},
0989 {WSA883X_VAGC_CTL, 0x01},
0990 {WSA883X_TAGC_CTL, 0x1A},
0991 {WSA883X_TAGC_TIME, 0x2C},
0992 {WSA883X_TEMP_CONFIG0, 0x02},
0993 {WSA883X_TEMP_CONFIG1, 0x02},
0994 {WSA883X_OTP_REG_1, 0x49},
0995 {WSA883X_OTP_REG_2, 0x80},
0996 {WSA883X_OTP_REG_3, 0xC9},
0997 {WSA883X_OTP_REG_4, 0x40},
0998 {WSA883X_TAGC_CTL, 0x1B},
0999 {WSA883X_ADC_2, 0x00},
1000 {WSA883X_ADC_7, 0x85},
1001 {WSA883X_ADC_7, 0x87},
1002 {WSA883X_CKWD_CTL_0, 0x14},
1003 {WSA883X_CKWD_CTL_1, 0x1B},
1004 {WSA883X_GMAMP_SUP1, 0xE2},
1005 };
1006
1007 static void wsa883x_init(struct wsa883x_priv *wsa883x)
1008 {
1009 struct regmap *regmap = wsa883x->regmap;
1010 int variant, version;
1011
1012 regmap_read(regmap, WSA883X_OTP_REG_0, &variant);
1013 wsa883x->variant = variant & WSA883X_ID_MASK;
1014
1015 regmap_read(regmap, WSA883X_CHIP_ID0, &version);
1016 wsa883x->version = version;
1017
1018 switch (wsa883x->variant) {
1019 case WSA8830:
1020 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n",
1021 wsa883x->version);
1022 break;
1023 case WSA8835:
1024 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n",
1025 wsa883x->version);
1026 break;
1027 case WSA8832:
1028 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n",
1029 wsa883x->version);
1030 break;
1031 case WSA8835_V2:
1032 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n",
1033 wsa883x->version);
1034 break;
1035 default:
1036 break;
1037 }
1038
1039 wsa883x->comp_offset = COMP_OFFSET2;
1040
1041
1042 regmap_multi_reg_write(regmap, reg_init, ARRAY_SIZE(reg_init));
1043
1044 if (wsa883x->variant == WSA8830 || wsa883x->variant == WSA8832) {
1045 wsa883x->comp_offset = COMP_OFFSET3;
1046 regmap_update_bits(regmap, WSA883X_DRE_CTL_0,
1047 WSA883X_DRE_OFFSET_MASK,
1048 wsa883x->comp_offset);
1049 }
1050 }
1051
1052 static int wsa883x_update_status(struct sdw_slave *slave,
1053 enum sdw_slave_status status)
1054 {
1055 struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1056
1057 if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1058 wsa883x_init(wsa883x);
1059
1060 return 0;
1061 }
1062
1063 static int wsa883x_port_prep(struct sdw_slave *slave,
1064 struct sdw_prepare_ch *prepare_ch,
1065 enum sdw_port_prep_ops state)
1066 {
1067 struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1068
1069 if (state == SDW_OPS_PORT_POST_PREP)
1070 wsa883x->port_prepared[prepare_ch->num - 1] = true;
1071 else
1072 wsa883x->port_prepared[prepare_ch->num - 1] = false;
1073
1074 return 0;
1075 }
1076
1077 static struct sdw_slave_ops wsa883x_slave_ops = {
1078 .update_status = wsa883x_update_status,
1079 .port_prep = wsa883x_port_prep,
1080 };
1081
1082 static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
1083 struct snd_ctl_elem_value *ucontrol)
1084 {
1085 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1086 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1087
1088 ucontrol->value.enumerated.item[0] = wsa883x->dev_mode;
1089
1090 return 0;
1091 }
1092
1093 static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
1094 struct snd_ctl_elem_value *ucontrol)
1095 {
1096 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1097 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1098
1099 if (wsa883x->dev_mode == ucontrol->value.enumerated.item[0])
1100 return 0;
1101
1102 wsa883x->dev_mode = ucontrol->value.enumerated.item[0];
1103
1104 return 1;
1105 }
1106
1107 static const DECLARE_TLV_DB_SCALE(pa_gain, -300, 150, -300);
1108
1109 static int wsa883x_get_swr_port(struct snd_kcontrol *kcontrol,
1110 struct snd_ctl_elem_value *ucontrol)
1111 {
1112 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1113 struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1114 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1115 int portidx = mixer->reg;
1116
1117 ucontrol->value.integer.value[0] = data->port_enable[portidx];
1118
1119 return 0;
1120 }
1121
1122 static int wsa883x_set_swr_port(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_value *ucontrol)
1124 {
1125 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1126 struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1127 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1128 int portidx = mixer->reg;
1129
1130 if (ucontrol->value.integer.value[0]) {
1131 if (data->port_enable[portidx])
1132 return 0;
1133
1134 data->port_enable[portidx] = true;
1135 } else {
1136 if (!data->port_enable[portidx])
1137 return 0;
1138
1139 data->port_enable[portidx] = false;
1140 }
1141
1142 return 1;
1143 }
1144
1145 static int wsa883x_get_comp_offset(struct snd_kcontrol *kcontrol,
1146 struct snd_ctl_elem_value *ucontrol)
1147 {
1148 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1149 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1150
1151 ucontrol->value.integer.value[0] = wsa883x->comp_offset;
1152
1153 return 0;
1154 }
1155
1156 static int wsa883x_set_comp_offset(struct snd_kcontrol *kcontrol,
1157 struct snd_ctl_elem_value *ucontrol)
1158 {
1159 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1160 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1161
1162 if (wsa883x->comp_offset == ucontrol->value.integer.value[0])
1163 return 0;
1164
1165 wsa883x->comp_offset = ucontrol->value.integer.value[0];
1166
1167 return 1;
1168 }
1169
1170 static int wsa883x_codec_probe(struct snd_soc_component *comp)
1171 {
1172 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(comp);
1173
1174 snd_soc_component_init_regmap(comp, wsa883x->regmap);
1175
1176 return 0;
1177 }
1178
1179 static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
1180 struct snd_kcontrol *kcontrol, int event)
1181 {
1182 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1183 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1184
1185 switch (event) {
1186 case SND_SOC_DAPM_POST_PMU:
1187 switch (wsa883x->dev_mode) {
1188 case RECEIVER:
1189 snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1190 WSA883X_RXD_MODE_MASK,
1191 WSA883X_RXD_MODE_HIFI);
1192 snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1193 WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1194 WSA883X_SPKR_PWM_FREQ_F600KHZ);
1195 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1196 WSA883X_DRE_PROG_DELAY_MASK, 0x0);
1197 break;
1198 case SPEAKER:
1199 snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1200 WSA883X_RXD_MODE_MASK,
1201 WSA883X_RXD_MODE_NORMAL);
1202 snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1203 WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1204 WSA883X_SPKR_PWM_FREQ_F300KHZ);
1205 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1206 WSA883X_DRE_PROG_DELAY_MASK, 0x9);
1207 break;
1208 default:
1209 break;
1210 }
1211
1212 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1213 WSA883X_DRE_GAIN_EN_MASK,
1214 WSA883X_DRE_GAIN_FROM_CSR);
1215 if (wsa883x->port_enable[WSA883X_PORT_COMP])
1216 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1217 WSA883X_DRE_OFFSET_MASK,
1218 wsa883x->comp_offset);
1219 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1220 WSA883X_VBAT_ADC_COEF_SEL_MASK,
1221 WSA883X_VBAT_ADC_COEF_F_1DIV16);
1222 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1223 WSA883X_VBAT_ADC_FLT_EN_MASK, 0x1);
1224 snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1225 WSA883X_PDM_EN_MASK,
1226 WSA883X_PDM_ENABLE);
1227 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1228 WSA883X_GLOBAL_PA_EN_MASK,
1229 WSA883X_GLOBAL_PA_ENABLE);
1230
1231 break;
1232 case SND_SOC_DAPM_PRE_PMD:
1233 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1234 WSA883X_VBAT_ADC_FLT_EN_MASK, 0x0);
1235 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1236 WSA883X_VBAT_ADC_COEF_SEL_MASK,
1237 WSA883X_VBAT_ADC_COEF_F_1DIV2);
1238 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1239 WSA883X_GLOBAL_PA_EN_MASK, 0);
1240 snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1241 WSA883X_PDM_EN_MASK, 0);
1242 break;
1243 }
1244 return 0;
1245 }
1246
1247 static const struct snd_soc_dapm_widget wsa883x_dapm_widgets[] = {
1248 SND_SOC_DAPM_INPUT("IN"),
1249 SND_SOC_DAPM_SPK("SPKR", wsa883x_spkr_event),
1250 };
1251
1252 static const struct snd_kcontrol_new wsa883x_snd_controls[] = {
1253 SOC_SINGLE_RANGE_TLV("PA Volume", WSA883X_DRE_CTL_1, 1,
1254 0x0, 0x1f, 1, pa_gain),
1255 SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
1256 wsa_dev_mode_get, wsa_dev_mode_put),
1257 SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
1258 wsa883x_get_comp_offset, wsa883x_set_comp_offset),
1259 SOC_SINGLE_EXT("DAC Switch", WSA883X_PORT_DAC, 0, 1, 0,
1260 wsa883x_get_swr_port, wsa883x_set_swr_port),
1261 SOC_SINGLE_EXT("COMP Switch", WSA883X_PORT_COMP, 0, 1, 0,
1262 wsa883x_get_swr_port, wsa883x_set_swr_port),
1263 SOC_SINGLE_EXT("BOOST Switch", WSA883X_PORT_BOOST, 0, 1, 0,
1264 wsa883x_get_swr_port, wsa883x_set_swr_port),
1265 SOC_SINGLE_EXT("VISENSE Switch", WSA883X_PORT_VISENSE, 0, 1, 0,
1266 wsa883x_get_swr_port, wsa883x_set_swr_port),
1267 };
1268
1269 static const struct snd_soc_dapm_route wsa883x_audio_map[] = {
1270 {"SPKR", NULL, "IN"},
1271 };
1272
1273 static const struct snd_soc_component_driver wsa883x_component_drv = {
1274 .name = "WSA883x",
1275 .probe = wsa883x_codec_probe,
1276 .controls = wsa883x_snd_controls,
1277 .num_controls = ARRAY_SIZE(wsa883x_snd_controls),
1278 .dapm_widgets = wsa883x_dapm_widgets,
1279 .num_dapm_widgets = ARRAY_SIZE(wsa883x_dapm_widgets),
1280 .dapm_routes = wsa883x_audio_map,
1281 .num_dapm_routes = ARRAY_SIZE(wsa883x_audio_map),
1282 };
1283
1284 static int wsa883x_hw_params(struct snd_pcm_substream *substream,
1285 struct snd_pcm_hw_params *params,
1286 struct snd_soc_dai *dai)
1287 {
1288 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1289 int i;
1290
1291 wsa883x->active_ports = 0;
1292 for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) {
1293 if (!wsa883x->port_enable[i])
1294 continue;
1295
1296 wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i];
1297 wsa883x->active_ports++;
1298 }
1299
1300 wsa883x->sconfig.frame_rate = params_rate(params);
1301
1302 return sdw_stream_add_slave(wsa883x->slave, &wsa883x->sconfig,
1303 wsa883x->port_config, wsa883x->active_ports,
1304 wsa883x->sruntime);
1305 }
1306
1307 static int wsa883x_hw_free(struct snd_pcm_substream *substream,
1308 struct snd_soc_dai *dai)
1309 {
1310 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1311
1312 sdw_stream_remove_slave(wsa883x->slave, wsa883x->sruntime);
1313
1314 return 0;
1315 }
1316
1317 static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai,
1318 void *stream, int direction)
1319 {
1320 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1321
1322 wsa883x->sruntime = stream;
1323
1324 return 0;
1325 }
1326
1327 static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1328 {
1329 struct snd_soc_component *component = dai->component;
1330
1331 if (mute) {
1332 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1333 WSA883X_DRE_GAIN_EN_MASK, 0);
1334 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1335 WSA883X_GLOBAL_PA_EN_MASK, 0);
1336
1337 } else {
1338 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1339 WSA883X_DRE_GAIN_EN_MASK,
1340 WSA883X_DRE_GAIN_FROM_CSR);
1341 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1342 WSA883X_GLOBAL_PA_EN_MASK, 1);
1343
1344 }
1345
1346 return 0;
1347 }
1348
1349 static const struct snd_soc_dai_ops wsa883x_dai_ops = {
1350 .hw_params = wsa883x_hw_params,
1351 .hw_free = wsa883x_hw_free,
1352 .mute_stream = wsa883x_digital_mute,
1353 .set_stream = wsa883x_set_sdw_stream,
1354 };
1355
1356 static struct snd_soc_dai_driver wsa883x_dais[] = {
1357 {
1358 .name = "SPKR",
1359 .playback = {
1360 .stream_name = "SPKR Playback",
1361 .rates = WSA883X_RATES | WSA883X_FRAC_RATES,
1362 .formats = WSA883X_FORMATS,
1363 .rate_max = 8000,
1364 .rate_min = 352800,
1365 .channels_min = 1,
1366 .channels_max = 1,
1367 },
1368 .ops = &wsa883x_dai_ops,
1369 },
1370 };
1371
1372 static int wsa883x_probe(struct sdw_slave *pdev,
1373 const struct sdw_device_id *id)
1374 {
1375 struct wsa883x_priv *wsa883x;
1376 struct device *dev = &pdev->dev;
1377 int ret;
1378
1379 wsa883x = devm_kzalloc(&pdev->dev, sizeof(*wsa883x), GFP_KERNEL);
1380 if (!wsa883x)
1381 return -ENOMEM;
1382
1383 wsa883x->vdd = devm_regulator_get(dev, "vdd");
1384 if (IS_ERR(wsa883x->vdd)) {
1385 dev_err(dev, "No vdd regulator found\n");
1386 return PTR_ERR(wsa883x->vdd);
1387 }
1388
1389 ret = regulator_enable(wsa883x->vdd);
1390 if (ret) {
1391 dev_err(dev, "Failed to enable vdd regulator (%d)\n", ret);
1392 return ret;
1393 }
1394
1395 wsa883x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
1396 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1397 if (IS_ERR(wsa883x->sd_n)) {
1398 dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
1399 ret = PTR_ERR(wsa883x->sd_n);
1400 goto err;
1401 }
1402
1403 dev_set_drvdata(&pdev->dev, wsa883x);
1404 wsa883x->slave = pdev;
1405 wsa883x->dev = &pdev->dev;
1406 wsa883x->sconfig.ch_count = 1;
1407 wsa883x->sconfig.bps = 1;
1408 wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
1409 wsa883x->sconfig.type = SDW_STREAM_PDM;
1410
1411 pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0);
1412 pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1413 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1414 gpiod_direction_output(wsa883x->sd_n, 1);
1415
1416 wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config);
1417 if (IS_ERR(wsa883x->regmap)) {
1418 dev_err(&pdev->dev, "regmap_init failed\n");
1419 ret = PTR_ERR(wsa883x->regmap);
1420 goto err;
1421 }
1422 pm_runtime_set_autosuspend_delay(dev, 3000);
1423 pm_runtime_use_autosuspend(dev);
1424 pm_runtime_mark_last_busy(dev);
1425 pm_runtime_set_active(dev);
1426 pm_runtime_enable(dev);
1427
1428 ret = devm_snd_soc_register_component(&pdev->dev,
1429 &wsa883x_component_drv,
1430 wsa883x_dais,
1431 ARRAY_SIZE(wsa883x_dais));
1432 err:
1433 if (ret)
1434 regulator_disable(wsa883x->vdd);
1435
1436 return ret;
1437
1438 }
1439
1440 static int __maybe_unused wsa883x_runtime_suspend(struct device *dev)
1441 {
1442 struct regmap *regmap = dev_get_regmap(dev, NULL);
1443 struct wsa883x_priv *wsa883x = dev_get_drvdata(dev);
1444
1445 gpiod_direction_output(wsa883x->sd_n, 0);
1446
1447 regcache_cache_only(regmap, true);
1448 regcache_mark_dirty(regmap);
1449
1450 regulator_disable(wsa883x->vdd);
1451 return 0;
1452 }
1453
1454 static int __maybe_unused wsa883x_runtime_resume(struct device *dev)
1455 {
1456 struct sdw_slave *slave = dev_to_sdw_dev(dev);
1457 struct regmap *regmap = dev_get_regmap(dev, NULL);
1458 struct wsa883x_priv *wsa883x = dev_get_drvdata(dev);
1459 unsigned long time;
1460 int ret;
1461
1462 ret = regulator_enable(wsa883x->vdd);
1463 if (ret) {
1464 dev_err(dev, "Failed to enable vdd regulator (%d)\n", ret);
1465 return ret;
1466 }
1467
1468 gpiod_direction_output(wsa883x->sd_n, 1);
1469
1470 time = wait_for_completion_timeout(&slave->initialization_complete,
1471 msecs_to_jiffies(WSA883X_PROBE_TIMEOUT));
1472 if (!time) {
1473 dev_err(dev, "Initialization not complete, timed out\n");
1474 gpiod_direction_output(wsa883x->sd_n, 0);
1475 regulator_disable(wsa883x->vdd);
1476 return -ETIMEDOUT;
1477 }
1478
1479 usleep_range(20000, 20010);
1480 regcache_cache_only(regmap, false);
1481 regcache_sync(regmap);
1482
1483 return 0;
1484 }
1485
1486 static const struct dev_pm_ops wsa883x_pm_ops = {
1487 SET_RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL)
1488 };
1489
1490 static const struct sdw_device_id wsa883x_swr_id[] = {
1491 SDW_SLAVE_ENTRY(0x0217, 0x0202, 0),
1492 {},
1493 };
1494
1495 MODULE_DEVICE_TABLE(sdw, wsa883x_swr_id);
1496
1497 static struct sdw_driver wsa883x_codec_driver = {
1498 .driver = {
1499 .name = "wsa883x-codec",
1500 .pm = &wsa883x_pm_ops,
1501 .suppress_bind_attrs = true,
1502 },
1503 .probe = wsa883x_probe,
1504 .ops = &wsa883x_slave_ops,
1505 .id_table = wsa883x_swr_id,
1506 };
1507
1508 module_sdw_driver(wsa883x_codec_driver);
1509
1510 MODULE_DESCRIPTION("WSA883x codec driver");
1511 MODULE_LICENSE("GPL");
