soc/codecs/wsa881x.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2015-2017, The Linux Foundation.
0003 // Copyright (c) 2019, Linaro Limited
0004
0005 #include <linux/bitops.h>
0006 #include <linux/gpio.h>
0007 #include <linux/gpio/consumer.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/of_gpio.h>
0012 #include <linux/regmap.h>
0013 #include <linux/slab.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/soundwire/sdw.h>
0016 #include <linux/soundwire/sdw_registers.h>
0017 #include <linux/soundwire/sdw_type.h>
0018 #include <sound/soc.h>
0019 #include <sound/tlv.h>
0020
0021 #define WSA881X_DIGITAL_BASE        0x3000
0022 #define WSA881X_ANALOG_BASE     0x3100
0023
0024 /* Digital register address space */
0025 #define WSA881X_CHIP_ID0            (WSA881X_DIGITAL_BASE + 0x0000)
0026 #define WSA881X_CHIP_ID1            (WSA881X_DIGITAL_BASE + 0x0001)
0027 #define WSA881X_CHIP_ID2            (WSA881X_DIGITAL_BASE + 0x0002)
0028 #define WSA881X_CHIP_ID3            (WSA881X_DIGITAL_BASE + 0x0003)
0029 #define WSA881X_BUS_ID              (WSA881X_DIGITAL_BASE + 0x0004)
0030 #define WSA881X_CDC_RST_CTL         (WSA881X_DIGITAL_BASE + 0x0005)
0031 #define WSA881X_CDC_TOP_CLK_CTL         (WSA881X_DIGITAL_BASE + 0x0006)
0032 #define WSA881X_CDC_ANA_CLK_CTL         (WSA881X_DIGITAL_BASE + 0x0007)
0033 #define WSA881X_CDC_DIG_CLK_CTL         (WSA881X_DIGITAL_BASE + 0x0008)
0034 #define WSA881X_CLOCK_CONFIG            (WSA881X_DIGITAL_BASE + 0x0009)
0035 #define WSA881X_ANA_CTL             (WSA881X_DIGITAL_BASE + 0x000A)
0036 #define WSA881X_SWR_RESET_EN            (WSA881X_DIGITAL_BASE + 0x000B)
0037 #define WSA881X_RESET_CTL           (WSA881X_DIGITAL_BASE + 0x000C)
0038 #define WSA881X_TADC_VALUE_CTL          (WSA881X_DIGITAL_BASE + 0x000F)
0039 #define WSA881X_TEMP_DETECT_CTL         (WSA881X_DIGITAL_BASE + 0x0010)
0040 #define WSA881X_TEMP_MSB            (WSA881X_DIGITAL_BASE + 0x0011)
0041 #define WSA881X_TEMP_LSB            (WSA881X_DIGITAL_BASE + 0x0012)
0042 #define WSA881X_TEMP_CONFIG0            (WSA881X_DIGITAL_BASE + 0x0013)
0043 #define WSA881X_TEMP_CONFIG1            (WSA881X_DIGITAL_BASE + 0x0014)
0044 #define WSA881X_CDC_CLIP_CTL            (WSA881X_DIGITAL_BASE + 0x0015)
0045 #define WSA881X_SDM_PDM9_LSB            (WSA881X_DIGITAL_BASE + 0x0016)
0046 #define WSA881X_SDM_PDM9_MSB            (WSA881X_DIGITAL_BASE + 0x0017)
0047 #define WSA881X_CDC_RX_CTL          (WSA881X_DIGITAL_BASE + 0x0018)
0048 #define WSA881X_DEM_BYPASS_DATA0        (WSA881X_DIGITAL_BASE + 0x0019)
0049 #define WSA881X_DEM_BYPASS_DATA1        (WSA881X_DIGITAL_BASE + 0x001A)
0050 #define WSA881X_DEM_BYPASS_DATA2        (WSA881X_DIGITAL_BASE + 0x001B)
0051 #define WSA881X_DEM_BYPASS_DATA3        (WSA881X_DIGITAL_BASE + 0x001C)
0052 #define WSA881X_OTP_CTRL0           (WSA881X_DIGITAL_BASE + 0x001D)
0053 #define WSA881X_OTP_CTRL1           (WSA881X_DIGITAL_BASE + 0x001E)
0054 #define WSA881X_HDRIVE_CTL_GROUP1       (WSA881X_DIGITAL_BASE + 0x001F)
0055 #define WSA881X_INTR_MODE           (WSA881X_DIGITAL_BASE + 0x0020)
0056 #define WSA881X_INTR_MASK           (WSA881X_DIGITAL_BASE + 0x0021)
0057 #define WSA881X_INTR_STATUS         (WSA881X_DIGITAL_BASE + 0x0022)
0058 #define WSA881X_INTR_CLEAR          (WSA881X_DIGITAL_BASE + 0x0023)
0059 #define WSA881X_INTR_LEVEL          (WSA881X_DIGITAL_BASE + 0x0024)
0060 #define WSA881X_INTR_SET            (WSA881X_DIGITAL_BASE + 0x0025)
0061 #define WSA881X_INTR_TEST           (WSA881X_DIGITAL_BASE + 0x0026)
0062 #define WSA881X_PDM_TEST_MODE           (WSA881X_DIGITAL_BASE + 0x0030)
0063 #define WSA881X_ATE_TEST_MODE           (WSA881X_DIGITAL_BASE + 0x0031)
0064 #define WSA881X_PIN_CTL_MODE            (WSA881X_DIGITAL_BASE + 0x0032)
0065 #define WSA881X_PIN_CTL_OE          (WSA881X_DIGITAL_BASE + 0x0033)
0066 #define WSA881X_PIN_WDATA_IOPAD         (WSA881X_DIGITAL_BASE + 0x0034)
0067 #define WSA881X_PIN_STATUS          (WSA881X_DIGITAL_BASE + 0x0035)
0068 #define WSA881X_DIG_DEBUG_MODE          (WSA881X_DIGITAL_BASE + 0x0037)
0069 #define WSA881X_DIG_DEBUG_SEL           (WSA881X_DIGITAL_BASE + 0x0038)
0070 #define WSA881X_DIG_DEBUG_EN            (WSA881X_DIGITAL_BASE + 0x0039)
0071 #define WSA881X_SWR_HM_TEST1            (WSA881X_DIGITAL_BASE + 0x003B)
0072 #define WSA881X_SWR_HM_TEST2            (WSA881X_DIGITAL_BASE + 0x003C)
0073 #define WSA881X_TEMP_DETECT_DBG_CTL     (WSA881X_DIGITAL_BASE + 0x003D)
0074 #define WSA881X_TEMP_DEBUG_MSB          (WSA881X_DIGITAL_BASE + 0x003E)
0075 #define WSA881X_TEMP_DEBUG_LSB          (WSA881X_DIGITAL_BASE + 0x003F)
0076 #define WSA881X_SAMPLE_EDGE_SEL         (WSA881X_DIGITAL_BASE + 0x0044)
0077 #define WSA881X_IOPAD_CTL           (WSA881X_DIGITAL_BASE + 0x0045)
0078 #define WSA881X_SPARE_0             (WSA881X_DIGITAL_BASE + 0x0050)
0079 #define WSA881X_SPARE_1             (WSA881X_DIGITAL_BASE + 0x0051)
0080 #define WSA881X_SPARE_2             (WSA881X_DIGITAL_BASE + 0x0052)
0081 #define WSA881X_OTP_REG_0           (WSA881X_DIGITAL_BASE + 0x0080)
0082 #define WSA881X_OTP_REG_1           (WSA881X_DIGITAL_BASE + 0x0081)
0083 #define WSA881X_OTP_REG_2           (WSA881X_DIGITAL_BASE + 0x0082)
0084 #define WSA881X_OTP_REG_3           (WSA881X_DIGITAL_BASE + 0x0083)
0085 #define WSA881X_OTP_REG_4           (WSA881X_DIGITAL_BASE + 0x0084)
0086 #define WSA881X_OTP_REG_5           (WSA881X_DIGITAL_BASE + 0x0085)
0087 #define WSA881X_OTP_REG_6           (WSA881X_DIGITAL_BASE + 0x0086)
0088 #define WSA881X_OTP_REG_7           (WSA881X_DIGITAL_BASE + 0x0087)
0089 #define WSA881X_OTP_REG_8           (WSA881X_DIGITAL_BASE + 0x0088)
0090 #define WSA881X_OTP_REG_9           (WSA881X_DIGITAL_BASE + 0x0089)
0091 #define WSA881X_OTP_REG_10          (WSA881X_DIGITAL_BASE + 0x008A)
0092 #define WSA881X_OTP_REG_11          (WSA881X_DIGITAL_BASE + 0x008B)
0093 #define WSA881X_OTP_REG_12          (WSA881X_DIGITAL_BASE + 0x008C)
0094 #define WSA881X_OTP_REG_13          (WSA881X_DIGITAL_BASE + 0x008D)
0095 #define WSA881X_OTP_REG_14          (WSA881X_DIGITAL_BASE + 0x008E)
0096 #define WSA881X_OTP_REG_15          (WSA881X_DIGITAL_BASE + 0x008F)
0097 #define WSA881X_OTP_REG_16          (WSA881X_DIGITAL_BASE + 0x0090)
0098 #define WSA881X_OTP_REG_17          (WSA881X_DIGITAL_BASE + 0x0091)
0099 #define WSA881X_OTP_REG_18          (WSA881X_DIGITAL_BASE + 0x0092)
0100 #define WSA881X_OTP_REG_19          (WSA881X_DIGITAL_BASE + 0x0093)
0101 #define WSA881X_OTP_REG_20          (WSA881X_DIGITAL_BASE + 0x0094)
0102 #define WSA881X_OTP_REG_21          (WSA881X_DIGITAL_BASE + 0x0095)
0103 #define WSA881X_OTP_REG_22          (WSA881X_DIGITAL_BASE + 0x0096)
0104 #define WSA881X_OTP_REG_23          (WSA881X_DIGITAL_BASE + 0x0097)
0105 #define WSA881X_OTP_REG_24          (WSA881X_DIGITAL_BASE + 0x0098)
0106 #define WSA881X_OTP_REG_25          (WSA881X_DIGITAL_BASE + 0x0099)
0107 #define WSA881X_OTP_REG_26          (WSA881X_DIGITAL_BASE + 0x009A)
0108 #define WSA881X_OTP_REG_27          (WSA881X_DIGITAL_BASE + 0x009B)
0109 #define WSA881X_OTP_REG_28          (WSA881X_DIGITAL_BASE + 0x009C)
0110 #define WSA881X_OTP_REG_29          (WSA881X_DIGITAL_BASE + 0x009D)
0111 #define WSA881X_OTP_REG_30          (WSA881X_DIGITAL_BASE + 0x009E)
0112 #define WSA881X_OTP_REG_31          (WSA881X_DIGITAL_BASE + 0x009F)
0113 #define WSA881X_OTP_REG_63          (WSA881X_DIGITAL_BASE + 0x00BF)
0114
0115 /* Analog Register address space */
0116 #define WSA881X_BIAS_REF_CTRL           (WSA881X_ANALOG_BASE + 0x0000)
0117 #define WSA881X_BIAS_TEST           (WSA881X_ANALOG_BASE + 0x0001)
0118 #define WSA881X_BIAS_BIAS           (WSA881X_ANALOG_BASE + 0x0002)
0119 #define WSA881X_TEMP_OP             (WSA881X_ANALOG_BASE + 0x0003)
0120 #define WSA881X_TEMP_IREF_CTRL          (WSA881X_ANALOG_BASE + 0x0004)
0121 #define WSA881X_TEMP_ISENS_CTRL         (WSA881X_ANALOG_BASE + 0x0005)
0122 #define WSA881X_TEMP_CLK_CTRL           (WSA881X_ANALOG_BASE + 0x0006)
0123 #define WSA881X_TEMP_TEST           (WSA881X_ANALOG_BASE + 0x0007)
0124 #define WSA881X_TEMP_BIAS           (WSA881X_ANALOG_BASE + 0x0008)
0125 #define WSA881X_TEMP_ADC_CTRL           (WSA881X_ANALOG_BASE + 0x0009)
0126 #define WSA881X_TEMP_DOUT_MSB           (WSA881X_ANALOG_BASE + 0x000A)
0127 #define WSA881X_TEMP_DOUT_LSB           (WSA881X_ANALOG_BASE + 0x000B)
0128 #define WSA881X_ADC_EN_MODU_V           (WSA881X_ANALOG_BASE + 0x0010)
0129 #define WSA881X_ADC_EN_MODU_I           (WSA881X_ANALOG_BASE + 0x0011)
0130 #define WSA881X_ADC_EN_DET_TEST_V       (WSA881X_ANALOG_BASE + 0x0012)
0131 #define WSA881X_ADC_EN_DET_TEST_I       (WSA881X_ANALOG_BASE + 0x0013)
0132 #define WSA881X_ADC_SEL_IBIAS           (WSA881X_ANALOG_BASE + 0x0014)
0133 #define WSA881X_ADC_EN_SEL_IBAIS        (WSA881X_ANALOG_BASE + 0x0015)
0134 #define WSA881X_SPKR_DRV_EN         (WSA881X_ANALOG_BASE + 0x001A)
0135 #define WSA881X_SPKR_DRV_GAIN           (WSA881X_ANALOG_BASE + 0x001B)
0136 #define WSA881X_PA_GAIN_SEL_MASK        BIT(3)
0137 #define WSA881X_PA_GAIN_SEL_REG         BIT(3)
0138 #define WSA881X_PA_GAIN_SEL_DRE         0
0139 #define WSA881X_SPKR_PAG_GAIN_MASK      GENMASK(7, 4)
0140 #define WSA881X_SPKR_DAC_CTL            (WSA881X_ANALOG_BASE + 0x001C)
0141 #define WSA881X_SPKR_DRV_DBG            (WSA881X_ANALOG_BASE + 0x001D)
0142 #define WSA881X_SPKR_PWRSTG_DBG         (WSA881X_ANALOG_BASE + 0x001E)
0143 #define WSA881X_SPKR_OCP_CTL            (WSA881X_ANALOG_BASE + 0x001F)
0144 #define WSA881X_SPKR_OCP_MASK           GENMASK(7, 6)
0145 #define WSA881X_SPKR_OCP_EN         BIT(7)
0146 #define WSA881X_SPKR_OCP_HOLD           BIT(6)
0147 #define WSA881X_SPKR_CLIP_CTL           (WSA881X_ANALOG_BASE + 0x0020)
0148 #define WSA881X_SPKR_BBM_CTL            (WSA881X_ANALOG_BASE + 0x0021)
0149 #define WSA881X_SPKR_MISC_CTL1          (WSA881X_ANALOG_BASE + 0x0022)
0150 #define WSA881X_SPKR_MISC_CTL2          (WSA881X_ANALOG_BASE + 0x0023)
0151 #define WSA881X_SPKR_BIAS_INT           (WSA881X_ANALOG_BASE + 0x0024)
0152 #define WSA881X_SPKR_PA_INT         (WSA881X_ANALOG_BASE + 0x0025)
0153 #define WSA881X_SPKR_BIAS_CAL           (WSA881X_ANALOG_BASE + 0x0026)
0154 #define WSA881X_SPKR_BIAS_PSRR          (WSA881X_ANALOG_BASE + 0x0027)
0155 #define WSA881X_SPKR_STATUS1            (WSA881X_ANALOG_BASE + 0x0028)
0156 #define WSA881X_SPKR_STATUS2            (WSA881X_ANALOG_BASE + 0x0029)
0157 #define WSA881X_BOOST_EN_CTL            (WSA881X_ANALOG_BASE + 0x002A)
0158 #define WSA881X_BOOST_EN_MASK           BIT(7)
0159 #define WSA881X_BOOST_EN            BIT(7)
0160 #define WSA881X_BOOST_CURRENT_LIMIT     (WSA881X_ANALOG_BASE + 0x002B)
0161 #define WSA881X_BOOST_PS_CTL            (WSA881X_ANALOG_BASE + 0x002C)
0162 #define WSA881X_BOOST_PRESET_OUT1       (WSA881X_ANALOG_BASE + 0x002D)
0163 #define WSA881X_BOOST_PRESET_OUT2       (WSA881X_ANALOG_BASE + 0x002E)
0164 #define WSA881X_BOOST_FORCE_OUT         (WSA881X_ANALOG_BASE + 0x002F)
0165 #define WSA881X_BOOST_LDO_PROG          (WSA881X_ANALOG_BASE + 0x0030)
0166 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB  (WSA881X_ANALOG_BASE + 0x0031)
0167 #define WSA881X_BOOST_RON_CTL           (WSA881X_ANALOG_BASE + 0x0032)
0168 #define WSA881X_BOOST_LOOP_STABILITY        (WSA881X_ANALOG_BASE + 0x0033)
0169 #define WSA881X_BOOST_ZX_CTL            (WSA881X_ANALOG_BASE + 0x0034)
0170 #define WSA881X_BOOST_START_CTL         (WSA881X_ANALOG_BASE + 0x0035)
0171 #define WSA881X_BOOST_MISC1_CTL         (WSA881X_ANALOG_BASE + 0x0036)
0172 #define WSA881X_BOOST_MISC2_CTL         (WSA881X_ANALOG_BASE + 0x0037)
0173 #define WSA881X_BOOST_MISC3_CTL         (WSA881X_ANALOG_BASE + 0x0038)
0174 #define WSA881X_BOOST_ATEST_CTL         (WSA881X_ANALOG_BASE + 0x0039)
0175 #define WSA881X_SPKR_PROT_FE_GAIN       (WSA881X_ANALOG_BASE + 0x003A)
0176 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET     (WSA881X_ANALOG_BASE + 0x003B)
0177 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x003C)
0178 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2   (WSA881X_ANALOG_BASE + 0x003D)
0179 #define WSA881X_SPKR_PROT_ATEST1        (WSA881X_ANALOG_BASE + 0x003E)
0180 #define WSA881X_SPKR_PROT_ATEST2        (WSA881X_ANALOG_BASE + 0x003F)
0181 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM     (WSA881X_ANALOG_BASE + 0x0040)
0182 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1   (WSA881X_ANALOG_BASE + 0x0041)
0183 #define WSA881X_BONGO_RESRV_REG1        (WSA881X_ANALOG_BASE + 0x0042)
0184 #define WSA881X_BONGO_RESRV_REG2        (WSA881X_ANALOG_BASE + 0x0043)
0185 #define WSA881X_SPKR_PROT_SAR           (WSA881X_ANALOG_BASE + 0x0044)
0186 #define WSA881X_SPKR_STATUS3            (WSA881X_ANALOG_BASE + 0x0045)
0187
0188 #define SWRS_SCP_FRAME_CTRL_BANK(m)     (0x60 + 0x10 * (m))
0189 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)  (0xE0 + 0x10 * (m))
0190 #define SWR_SLV_MAX_REG_ADDR    0x390
0191 #define SWR_SLV_START_REG_ADDR  0x40
0192 #define SWR_SLV_MAX_BUF_LEN 20
0193 #define BYTES_PER_LINE      12
0194 #define SWR_SLV_RD_BUF_LEN  8
0195 #define SWR_SLV_WR_BUF_LEN  32
0196 #define SWR_SLV_MAX_DEVICES 2
0197 #define WSA881X_MAX_SWR_PORTS   4
0198 #define WSA881X_VERSION_ENTRY_SIZE 27
0199 #define WSA881X_OCP_CTL_TIMER_SEC 2
0200 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25
0201 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
0202 #define WSA881X_PROBE_TIMEOUT 1000
0203
0204 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
0205 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0206     .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
0207          SNDRV_CTL_ELEM_ACCESS_READWRITE,\
0208     .tlv.p = (tlv_array), \
0209     .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
0210     .put = wsa881x_put_pa_gain, \
0211     .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
0212
0213 static struct reg_default wsa881x_defaults[] = {
0214     { WSA881X_CHIP_ID0, 0x00 },
0215     { WSA881X_CHIP_ID1, 0x00 },
0216     { WSA881X_CHIP_ID2, 0x00 },
0217     { WSA881X_CHIP_ID3, 0x02 },
0218     { WSA881X_BUS_ID, 0x00 },
0219     { WSA881X_CDC_RST_CTL, 0x00 },
0220     { WSA881X_CDC_TOP_CLK_CTL, 0x03 },
0221     { WSA881X_CDC_ANA_CLK_CTL, 0x00 },
0222     { WSA881X_CDC_DIG_CLK_CTL, 0x00 },
0223     { WSA881X_CLOCK_CONFIG, 0x00 },
0224     { WSA881X_ANA_CTL, 0x08 },
0225     { WSA881X_SWR_RESET_EN, 0x00 },
0226     { WSA881X_TEMP_DETECT_CTL, 0x01 },
0227     { WSA881X_TEMP_MSB, 0x00 },
0228     { WSA881X_TEMP_LSB, 0x00 },
0229     { WSA881X_TEMP_CONFIG0, 0x00 },
0230     { WSA881X_TEMP_CONFIG1, 0x00 },
0231     { WSA881X_CDC_CLIP_CTL, 0x03 },
0232     { WSA881X_SDM_PDM9_LSB, 0x00 },
0233     { WSA881X_SDM_PDM9_MSB, 0x00 },
0234     { WSA881X_CDC_RX_CTL, 0x7E },
0235     { WSA881X_DEM_BYPASS_DATA0, 0x00 },
0236     { WSA881X_DEM_BYPASS_DATA1, 0x00 },
0237     { WSA881X_DEM_BYPASS_DATA2, 0x00 },
0238     { WSA881X_DEM_BYPASS_DATA3, 0x00 },
0239     { WSA881X_OTP_CTRL0, 0x00 },
0240     { WSA881X_OTP_CTRL1, 0x00 },
0241     { WSA881X_HDRIVE_CTL_GROUP1, 0x00 },
0242     { WSA881X_INTR_MODE, 0x00 },
0243     { WSA881X_INTR_STATUS, 0x00 },
0244     { WSA881X_INTR_CLEAR, 0x00 },
0245     { WSA881X_INTR_LEVEL, 0x00 },
0246     { WSA881X_INTR_SET, 0x00 },
0247     { WSA881X_INTR_TEST, 0x00 },
0248     { WSA881X_PDM_TEST_MODE, 0x00 },
0249     { WSA881X_ATE_TEST_MODE, 0x00 },
0250     { WSA881X_PIN_CTL_MODE, 0x00 },
0251     { WSA881X_PIN_CTL_OE, 0x00 },
0252     { WSA881X_PIN_WDATA_IOPAD, 0x00 },
0253     { WSA881X_PIN_STATUS, 0x00 },
0254     { WSA881X_DIG_DEBUG_MODE, 0x00 },
0255     { WSA881X_DIG_DEBUG_SEL, 0x00 },
0256     { WSA881X_DIG_DEBUG_EN, 0x00 },
0257     { WSA881X_SWR_HM_TEST1, 0x08 },
0258     { WSA881X_SWR_HM_TEST2, 0x00 },
0259     { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 },
0260     { WSA881X_TEMP_DEBUG_MSB, 0x00 },
0261     { WSA881X_TEMP_DEBUG_LSB, 0x00 },
0262     { WSA881X_SAMPLE_EDGE_SEL, 0x0C },
0263     { WSA881X_SPARE_0, 0x00 },
0264     { WSA881X_SPARE_1, 0x00 },
0265     { WSA881X_SPARE_2, 0x00 },
0266     { WSA881X_OTP_REG_0, 0x01 },
0267     { WSA881X_OTP_REG_1, 0xFF },
0268     { WSA881X_OTP_REG_2, 0xC0 },
0269     { WSA881X_OTP_REG_3, 0xFF },
0270     { WSA881X_OTP_REG_4, 0xC0 },
0271     { WSA881X_OTP_REG_5, 0xFF },
0272     { WSA881X_OTP_REG_6, 0xFF },
0273     { WSA881X_OTP_REG_7, 0xFF },
0274     { WSA881X_OTP_REG_8, 0xFF },
0275     { WSA881X_OTP_REG_9, 0xFF },
0276     { WSA881X_OTP_REG_10, 0xFF },
0277     { WSA881X_OTP_REG_11, 0xFF },
0278     { WSA881X_OTP_REG_12, 0xFF },
0279     { WSA881X_OTP_REG_13, 0xFF },
0280     { WSA881X_OTP_REG_14, 0xFF },
0281     { WSA881X_OTP_REG_15, 0xFF },
0282     { WSA881X_OTP_REG_16, 0xFF },
0283     { WSA881X_OTP_REG_17, 0xFF },
0284     { WSA881X_OTP_REG_18, 0xFF },
0285     { WSA881X_OTP_REG_19, 0xFF },
0286     { WSA881X_OTP_REG_20, 0xFF },
0287     { WSA881X_OTP_REG_21, 0xFF },
0288     { WSA881X_OTP_REG_22, 0xFF },
0289     { WSA881X_OTP_REG_23, 0xFF },
0290     { WSA881X_OTP_REG_24, 0x03 },
0291     { WSA881X_OTP_REG_25, 0x01 },
0292     { WSA881X_OTP_REG_26, 0x03 },
0293     { WSA881X_OTP_REG_27, 0x11 },
0294     { WSA881X_OTP_REG_63, 0x40 },
0295     /* WSA881x Analog registers */
0296     { WSA881X_BIAS_REF_CTRL, 0x6C },
0297     { WSA881X_BIAS_TEST, 0x16 },
0298     { WSA881X_BIAS_BIAS, 0xF0 },
0299     { WSA881X_TEMP_OP, 0x00 },
0300     { WSA881X_TEMP_IREF_CTRL, 0x56 },
0301     { WSA881X_TEMP_ISENS_CTRL, 0x47 },
0302     { WSA881X_TEMP_CLK_CTRL, 0x87 },
0303     { WSA881X_TEMP_TEST, 0x00 },
0304     { WSA881X_TEMP_BIAS, 0x51 },
0305     { WSA881X_TEMP_DOUT_MSB, 0x00 },
0306     { WSA881X_TEMP_DOUT_LSB, 0x00 },
0307     { WSA881X_ADC_EN_MODU_V, 0x00 },
0308     { WSA881X_ADC_EN_MODU_I, 0x00 },
0309     { WSA881X_ADC_EN_DET_TEST_V, 0x00 },
0310     { WSA881X_ADC_EN_DET_TEST_I, 0x00 },
0311     { WSA881X_ADC_EN_SEL_IBAIS, 0x10 },
0312     { WSA881X_SPKR_DRV_EN, 0x74 },
0313     { WSA881X_SPKR_DRV_DBG, 0x15 },
0314     { WSA881X_SPKR_PWRSTG_DBG, 0x00 },
0315     { WSA881X_SPKR_OCP_CTL, 0xD4 },
0316     { WSA881X_SPKR_CLIP_CTL, 0x90 },
0317     { WSA881X_SPKR_PA_INT, 0x54 },
0318     { WSA881X_SPKR_BIAS_CAL, 0xAC },
0319     { WSA881X_SPKR_STATUS1, 0x00 },
0320     { WSA881X_SPKR_STATUS2, 0x00 },
0321     { WSA881X_BOOST_EN_CTL, 0x18 },
0322     { WSA881X_BOOST_CURRENT_LIMIT, 0x7A },
0323     { WSA881X_BOOST_PRESET_OUT2, 0x70 },
0324     { WSA881X_BOOST_FORCE_OUT, 0x0E },
0325     { WSA881X_BOOST_LDO_PROG, 0x16 },
0326     { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 },
0327     { WSA881X_BOOST_RON_CTL, 0x0F },
0328     { WSA881X_BOOST_ZX_CTL, 0x34 },
0329     { WSA881X_BOOST_START_CTL, 0x23 },
0330     { WSA881X_BOOST_MISC1_CTL, 0x80 },
0331     { WSA881X_BOOST_MISC2_CTL, 0x00 },
0332     { WSA881X_BOOST_MISC3_CTL, 0x00 },
0333     { WSA881X_BOOST_ATEST_CTL, 0x00 },
0334     { WSA881X_SPKR_PROT_FE_GAIN, 0x46 },
0335     { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B },
0336     { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D },
0337     { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D },
0338     { WSA881X_SPKR_PROT_ATEST1, 0x01 },
0339     { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D },
0340     { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D },
0341     { WSA881X_SPKR_PROT_SAR, 0x00 },
0342     { WSA881X_SPKR_STATUS3, 0x00 },
0343 };
0344
0345 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
0346     { WSA881X_SPKR_DRV_GAIN, 0x41, 0 },
0347     { WSA881X_SPKR_MISC_CTL1, 0x87, 0 },
0348 };
0349
0350 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
0351     { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 },
0352     { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 },
0353     { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 },
0354 };
0355
0356 /* Default register reset values for WSA881x rev 2.0 */
0357 static struct reg_sequence wsa881x_rev_2_0[] = {
0358     { WSA881X_RESET_CTL, 0x00, 0x00 },
0359     { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 },
0360     { WSA881X_INTR_MASK, 0x1B, 0x00 },
0361     { WSA881X_IOPAD_CTL, 0x00, 0x00 },
0362     { WSA881X_OTP_REG_28, 0x3F, 0x00 },
0363     { WSA881X_OTP_REG_29, 0x3F, 0x00 },
0364     { WSA881X_OTP_REG_30, 0x01, 0x00 },
0365     { WSA881X_OTP_REG_31, 0x01, 0x00 },
0366     { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 },
0367     { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 },
0368     { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 },
0369     { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 },
0370     { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 },
0371     { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 },
0372     { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 },
0373     { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 },
0374     { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 },
0375     { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 },
0376     { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 },
0377     { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 },
0378     { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 },
0379     { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 },
0380     { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 },
0381 };
0382
0383 enum wsa_port_ids {
0384     WSA881X_PORT_DAC,
0385     WSA881X_PORT_COMP,
0386     WSA881X_PORT_BOOST,
0387     WSA881X_PORT_VISENSE,
0388 };
0389
0390 /* 4 ports */
0391 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
0392     {
0393         /* DAC */
0394         .num = 1,
0395         .type = SDW_DPN_SIMPLE,
0396         .min_ch = 1,
0397         .max_ch = 1,
0398         .simple_ch_prep_sm = true,
0399         .read_only_wordlength = true,
0400     }, {
0401         /* COMP */
0402         .num = 2,
0403         .type = SDW_DPN_SIMPLE,
0404         .min_ch = 1,
0405         .max_ch = 1,
0406         .simple_ch_prep_sm = true,
0407         .read_only_wordlength = true,
0408     }, {
0409         /* BOOST */
0410         .num = 3,
0411         .type = SDW_DPN_SIMPLE,
0412         .min_ch = 1,
0413         .max_ch = 1,
0414         .simple_ch_prep_sm = true,
0415         .read_only_wordlength = true,
0416     }, {
0417         /* VISENSE */
0418         .num = 4,
0419         .type = SDW_DPN_SIMPLE,
0420         .min_ch = 1,
0421         .max_ch = 1,
0422         .simple_ch_prep_sm = true,
0423         .read_only_wordlength = true,
0424     }
0425 };
0426
0427 static struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = {
0428     {
0429         .num = 1,
0430         .ch_mask = 0x1,
0431     }, {
0432         .num = 2,
0433         .ch_mask = 0xf,
0434     }, {
0435         .num = 3,
0436         .ch_mask = 0x3,
0437     }, {    /* IV feedback */
0438         .num = 4,
0439         .ch_mask = 0x3,
0440     },
0441 };
0442
0443 static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
0444 {
0445     switch (reg) {
0446     case WSA881X_CHIP_ID0:
0447     case WSA881X_CHIP_ID1:
0448     case WSA881X_CHIP_ID2:
0449     case WSA881X_CHIP_ID3:
0450     case WSA881X_BUS_ID:
0451     case WSA881X_CDC_RST_CTL:
0452     case WSA881X_CDC_TOP_CLK_CTL:
0453     case WSA881X_CDC_ANA_CLK_CTL:
0454     case WSA881X_CDC_DIG_CLK_CTL:
0455     case WSA881X_CLOCK_CONFIG:
0456     case WSA881X_ANA_CTL:
0457     case WSA881X_SWR_RESET_EN:
0458     case WSA881X_RESET_CTL:
0459     case WSA881X_TADC_VALUE_CTL:
0460     case WSA881X_TEMP_DETECT_CTL:
0461     case WSA881X_TEMP_MSB:
0462     case WSA881X_TEMP_LSB:
0463     case WSA881X_TEMP_CONFIG0:
0464     case WSA881X_TEMP_CONFIG1:
0465     case WSA881X_CDC_CLIP_CTL:
0466     case WSA881X_SDM_PDM9_LSB:
0467     case WSA881X_SDM_PDM9_MSB:
0468     case WSA881X_CDC_RX_CTL:
0469     case WSA881X_DEM_BYPASS_DATA0:
0470     case WSA881X_DEM_BYPASS_DATA1:
0471     case WSA881X_DEM_BYPASS_DATA2:
0472     case WSA881X_DEM_BYPASS_DATA3:
0473     case WSA881X_OTP_CTRL0:
0474     case WSA881X_OTP_CTRL1:
0475     case WSA881X_HDRIVE_CTL_GROUP1:
0476     case WSA881X_INTR_MODE:
0477     case WSA881X_INTR_MASK:
0478     case WSA881X_INTR_STATUS:
0479     case WSA881X_INTR_CLEAR:
0480     case WSA881X_INTR_LEVEL:
0481     case WSA881X_INTR_SET:
0482     case WSA881X_INTR_TEST:
0483     case WSA881X_PDM_TEST_MODE:
0484     case WSA881X_ATE_TEST_MODE:
0485     case WSA881X_PIN_CTL_MODE:
0486     case WSA881X_PIN_CTL_OE:
0487     case WSA881X_PIN_WDATA_IOPAD:
0488     case WSA881X_PIN_STATUS:
0489     case WSA881X_DIG_DEBUG_MODE:
0490     case WSA881X_DIG_DEBUG_SEL:
0491     case WSA881X_DIG_DEBUG_EN:
0492     case WSA881X_SWR_HM_TEST1:
0493     case WSA881X_SWR_HM_TEST2:
0494     case WSA881X_TEMP_DETECT_DBG_CTL:
0495     case WSA881X_TEMP_DEBUG_MSB:
0496     case WSA881X_TEMP_DEBUG_LSB:
0497     case WSA881X_SAMPLE_EDGE_SEL:
0498     case WSA881X_IOPAD_CTL:
0499     case WSA881X_SPARE_0:
0500     case WSA881X_SPARE_1:
0501     case WSA881X_SPARE_2:
0502     case WSA881X_OTP_REG_0:
0503     case WSA881X_OTP_REG_1:
0504     case WSA881X_OTP_REG_2:
0505     case WSA881X_OTP_REG_3:
0506     case WSA881X_OTP_REG_4:
0507     case WSA881X_OTP_REG_5:
0508     case WSA881X_OTP_REG_6:
0509     case WSA881X_OTP_REG_7:
0510     case WSA881X_OTP_REG_8:
0511     case WSA881X_OTP_REG_9:
0512     case WSA881X_OTP_REG_10:
0513     case WSA881X_OTP_REG_11:
0514     case WSA881X_OTP_REG_12:
0515     case WSA881X_OTP_REG_13:
0516     case WSA881X_OTP_REG_14:
0517     case WSA881X_OTP_REG_15:
0518     case WSA881X_OTP_REG_16:
0519     case WSA881X_OTP_REG_17:
0520     case WSA881X_OTP_REG_18:
0521     case WSA881X_OTP_REG_19:
0522     case WSA881X_OTP_REG_20:
0523     case WSA881X_OTP_REG_21:
0524     case WSA881X_OTP_REG_22:
0525     case WSA881X_OTP_REG_23:
0526     case WSA881X_OTP_REG_24:
0527     case WSA881X_OTP_REG_25:
0528     case WSA881X_OTP_REG_26:
0529     case WSA881X_OTP_REG_27:
0530     case WSA881X_OTP_REG_28:
0531     case WSA881X_OTP_REG_29:
0532     case WSA881X_OTP_REG_30:
0533     case WSA881X_OTP_REG_31:
0534     case WSA881X_OTP_REG_63:
0535     case WSA881X_BIAS_REF_CTRL:
0536     case WSA881X_BIAS_TEST:
0537     case WSA881X_BIAS_BIAS:
0538     case WSA881X_TEMP_OP:
0539     case WSA881X_TEMP_IREF_CTRL:
0540     case WSA881X_TEMP_ISENS_CTRL:
0541     case WSA881X_TEMP_CLK_CTRL:
0542     case WSA881X_TEMP_TEST:
0543     case WSA881X_TEMP_BIAS:
0544     case WSA881X_TEMP_ADC_CTRL:
0545     case WSA881X_TEMP_DOUT_MSB:
0546     case WSA881X_TEMP_DOUT_LSB:
0547     case WSA881X_ADC_EN_MODU_V:
0548     case WSA881X_ADC_EN_MODU_I:
0549     case WSA881X_ADC_EN_DET_TEST_V:
0550     case WSA881X_ADC_EN_DET_TEST_I:
0551     case WSA881X_ADC_SEL_IBIAS:
0552     case WSA881X_ADC_EN_SEL_IBAIS:
0553     case WSA881X_SPKR_DRV_EN:
0554     case WSA881X_SPKR_DRV_GAIN:
0555     case WSA881X_SPKR_DAC_CTL:
0556     case WSA881X_SPKR_DRV_DBG:
0557     case WSA881X_SPKR_PWRSTG_DBG:
0558     case WSA881X_SPKR_OCP_CTL:
0559     case WSA881X_SPKR_CLIP_CTL:
0560     case WSA881X_SPKR_BBM_CTL:
0561     case WSA881X_SPKR_MISC_CTL1:
0562     case WSA881X_SPKR_MISC_CTL2:
0563     case WSA881X_SPKR_BIAS_INT:
0564     case WSA881X_SPKR_PA_INT:
0565     case WSA881X_SPKR_BIAS_CAL:
0566     case WSA881X_SPKR_BIAS_PSRR:
0567     case WSA881X_SPKR_STATUS1:
0568     case WSA881X_SPKR_STATUS2:
0569     case WSA881X_BOOST_EN_CTL:
0570     case WSA881X_BOOST_CURRENT_LIMIT:
0571     case WSA881X_BOOST_PS_CTL:
0572     case WSA881X_BOOST_PRESET_OUT1:
0573     case WSA881X_BOOST_PRESET_OUT2:
0574     case WSA881X_BOOST_FORCE_OUT:
0575     case WSA881X_BOOST_LDO_PROG:
0576     case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB:
0577     case WSA881X_BOOST_RON_CTL:
0578     case WSA881X_BOOST_LOOP_STABILITY:
0579     case WSA881X_BOOST_ZX_CTL:
0580     case WSA881X_BOOST_START_CTL:
0581     case WSA881X_BOOST_MISC1_CTL:
0582     case WSA881X_BOOST_MISC2_CTL:
0583     case WSA881X_BOOST_MISC3_CTL:
0584     case WSA881X_BOOST_ATEST_CTL:
0585     case WSA881X_SPKR_PROT_FE_GAIN:
0586     case WSA881X_SPKR_PROT_FE_CM_LDO_SET:
0587     case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1:
0588     case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2:
0589     case WSA881X_SPKR_PROT_ATEST1:
0590     case WSA881X_SPKR_PROT_ATEST2:
0591     case WSA881X_SPKR_PROT_FE_VSENSE_VCM:
0592     case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1:
0593     case WSA881X_BONGO_RESRV_REG1:
0594     case WSA881X_BONGO_RESRV_REG2:
0595     case WSA881X_SPKR_PROT_SAR:
0596     case WSA881X_SPKR_STATUS3:
0597         return true;
0598     default:
0599         return false;
0600     }
0601 }
0602
0603 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
0604 {
0605     switch (reg) {
0606     case WSA881X_CHIP_ID0:
0607     case WSA881X_CHIP_ID1:
0608     case WSA881X_CHIP_ID2:
0609     case WSA881X_CHIP_ID3:
0610     case WSA881X_BUS_ID:
0611     case WSA881X_TEMP_MSB:
0612     case WSA881X_TEMP_LSB:
0613     case WSA881X_SDM_PDM9_LSB:
0614     case WSA881X_SDM_PDM9_MSB:
0615     case WSA881X_OTP_CTRL1:
0616     case WSA881X_INTR_STATUS:
0617     case WSA881X_ATE_TEST_MODE:
0618     case WSA881X_PIN_STATUS:
0619     case WSA881X_SWR_HM_TEST2:
0620     case WSA881X_SPKR_STATUS1:
0621     case WSA881X_SPKR_STATUS2:
0622     case WSA881X_SPKR_STATUS3:
0623     case WSA881X_OTP_REG_0:
0624     case WSA881X_OTP_REG_1:
0625     case WSA881X_OTP_REG_2:
0626     case WSA881X_OTP_REG_3:
0627     case WSA881X_OTP_REG_4:
0628     case WSA881X_OTP_REG_5:
0629     case WSA881X_OTP_REG_31:
0630     case WSA881X_TEMP_DOUT_MSB:
0631     case WSA881X_TEMP_DOUT_LSB:
0632     case WSA881X_TEMP_OP:
0633     case WSA881X_SPKR_PROT_SAR:
0634         return true;
0635     default:
0636         return false;
0637     }
0638 }
0639
0640 static struct regmap_config wsa881x_regmap_config = {
0641     .reg_bits = 32,
0642     .val_bits = 8,
0643     .cache_type = REGCACHE_RBTREE,
0644     .reg_defaults = wsa881x_defaults,
0645     .max_register = WSA881X_SPKR_STATUS3,
0646     .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
0647     .volatile_reg = wsa881x_volatile_register,
0648     .readable_reg = wsa881x_readable_register,
0649     .reg_format_endian = REGMAP_ENDIAN_NATIVE,
0650     .val_format_endian = REGMAP_ENDIAN_NATIVE,
0651     .can_multi_write = true,
0652 };
0653
0654 enum {
0655     G_18DB = 0,
0656     G_16P5DB,
0657     G_15DB,
0658     G_13P5DB,
0659     G_12DB,
0660     G_10P5DB,
0661     G_9DB,
0662     G_7P5DB,
0663     G_6DB,
0664     G_4P5DB,
0665     G_3DB,
0666     G_1P5DB,
0667     G_0DB,
0668 };
0669
0670 /*
0671  * Private data Structure for wsa881x. All parameters related to
0672  * WSA881X codec needs to be defined here.
0673  */
0674 struct wsa881x_priv {
0675     struct regmap *regmap;
0676     struct device *dev;
0677     struct sdw_slave *slave;
0678     struct sdw_stream_config sconfig;
0679     struct sdw_stream_runtime *sruntime;
0680     struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS];
0681     struct gpio_desc *sd_n;
0682     int version;
0683     int active_ports;
0684     bool port_prepared[WSA881X_MAX_SWR_PORTS];
0685     bool port_enable[WSA881X_MAX_SWR_PORTS];
0686 };
0687
0688 static void wsa881x_init(struct wsa881x_priv *wsa881x)
0689 {
0690     struct regmap *rm = wsa881x->regmap;
0691     unsigned int val = 0;
0692
0693     regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version);
0694     regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0,
0695                   ARRAY_SIZE(wsa881x_rev_2_0));
0696
0697     /* Enable software reset output from soundwire slave */
0698     regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07);
0699
0700     /* Bring out of analog reset */
0701     regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02);
0702
0703     /* Bring out of digital reset */
0704     regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01);
0705     regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
0706     regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
0707     regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
0708     regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
0709     regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
0710     regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
0711     regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
0712     regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03);
0713     regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14);
0714     regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80);
0715     regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00);
0716     regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04);
0717     regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00);
0718
0719     regmap_read(rm, WSA881X_OTP_REG_0, &val);
0720     if (val)
0721         regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70);
0722
0723     regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30);
0724     regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
0725     regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08);
0726     regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
0727     regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
0728     regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A);
0729     regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2);
0730     regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05);
0731 }
0732
0733 static int wsa881x_component_probe(struct snd_soc_component *comp)
0734 {
0735     struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
0736
0737     snd_soc_component_init_regmap(comp, wsa881x->regmap);
0738
0739     return 0;
0740 }
0741
0742 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
0743                    struct snd_ctl_elem_value *ucontrol)
0744 {
0745     struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
0746     struct soc_mixer_control *mc =
0747             (struct soc_mixer_control *)kc->private_value;
0748     int max = mc->max;
0749     unsigned int mask = (1 << fls(max)) - 1;
0750     int val, ret, min_gain, max_gain;
0751
0752     ret = pm_runtime_resume_and_get(comp->dev);
0753     if (ret < 0 && ret != -EACCES)
0754         return ret;
0755
0756     max_gain = (max - ucontrol->value.integer.value[0]) & mask;
0757     /*
0758      * Gain has to set incrementally in 4 steps
0759      * as per HW sequence
0760      */
0761     if (max_gain > G_4P5DB)
0762         min_gain = G_0DB;
0763     else
0764         min_gain = max_gain + 3;
0765     /*
0766      * 1ms delay is needed before change in gain
0767      * as per HW requirement.
0768      */
0769     usleep_range(1000, 1010);
0770
0771     for (val = min_gain; max_gain <= val; val--) {
0772         ret = snd_soc_component_update_bits(comp,
0773                   WSA881X_SPKR_DRV_GAIN,
0774                   WSA881X_SPKR_PAG_GAIN_MASK,
0775                   val << 4);
0776         if (ret < 0)
0777             dev_err(comp->dev, "Failed to change PA gain");
0778
0779         usleep_range(1000, 1010);
0780     }
0781
0782     pm_runtime_mark_last_busy(comp->dev);
0783     pm_runtime_put_autosuspend(comp->dev);
0784
0785     return 1;
0786 }
0787
0788 static int wsa881x_get_port(struct snd_kcontrol *kcontrol,
0789                 struct snd_ctl_elem_value *ucontrol)
0790 {
0791     struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
0792     struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
0793     struct soc_mixer_control *mixer =
0794         (struct soc_mixer_control *)kcontrol->private_value;
0795     int portidx = mixer->reg;
0796
0797     ucontrol->value.integer.value[0] = data->port_enable[portidx];
0798
0799
0800     return 0;
0801 }
0802
0803 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
0804 {
0805     if (enable)
0806         snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
0807                           WSA881X_BOOST_EN_MASK,
0808                           WSA881X_BOOST_EN);
0809     else
0810         snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
0811                           WSA881X_BOOST_EN_MASK, 0);
0812     /*
0813      * 1.5ms sleep is needed after boost enable/disable as per
0814      * HW requirement
0815      */
0816     usleep_range(1500, 1510);
0817     return 0;
0818 }
0819
0820 static int wsa881x_set_port(struct snd_kcontrol *kcontrol,
0821                 struct snd_ctl_elem_value *ucontrol)
0822 {
0823     struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
0824     struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp);
0825     struct soc_mixer_control *mixer =
0826         (struct soc_mixer_control *)kcontrol->private_value;
0827     int portidx = mixer->reg;
0828
0829     if (ucontrol->value.integer.value[0]) {
0830         if (data->port_enable[portidx])
0831             return 0;
0832
0833         data->port_enable[portidx] = true;
0834     } else {
0835         if (!data->port_enable[portidx])
0836             return 0;
0837
0838         data->port_enable[portidx] = false;
0839     }
0840
0841     if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */
0842         wsa881x_boost_ctrl(comp, data->port_enable[portidx]);
0843
0844     return 1;
0845 }
0846
0847 static const char * const smart_boost_lvl_text[] = {
0848     "6.625 V", "6.750 V", "6.875 V", "7.000 V",
0849     "7.125 V", "7.250 V", "7.375 V", "7.500 V",
0850     "7.625 V", "7.750 V", "7.875 V", "8.000 V",
0851     "8.125 V", "8.250 V", "8.375 V", "8.500 V"
0852 };
0853
0854 static const struct soc_enum smart_boost_lvl_enum =
0855     SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
0856             ARRAY_SIZE(smart_boost_lvl_text),
0857             smart_boost_lvl_text);
0858
0859 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
0860
0861 static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
0862     SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
0863     WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN,
0864                 4, 0xC, 1, pa_gain),
0865     SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0,
0866                wsa881x_get_port, wsa881x_set_port),
0867     SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0,
0868                wsa881x_get_port, wsa881x_set_port),
0869     SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0,
0870                wsa881x_get_port, wsa881x_set_port),
0871     SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0,
0872                wsa881x_get_port, wsa881x_set_port),
0873 };
0874
0875 static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
0876     { "RDAC", NULL, "IN" },
0877     { "RDAC", NULL, "DCLK" },
0878     { "RDAC", NULL, "ACLK" },
0879     { "RDAC", NULL, "Bandgap" },
0880     { "SPKR PGA", NULL, "RDAC" },
0881     { "SPKR", NULL, "SPKR PGA" },
0882 };
0883
0884 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
0885                      bool enable)
0886 {
0887     struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
0888
0889     if (enable) {
0890         regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0,
0891                        ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
0892     } else {
0893         snd_soc_component_update_bits(comp,
0894                           WSA881X_SPKR_PROT_FE_VSENSE_VCM,
0895                           0x08, 0x08);
0896         /*
0897          * 200us sleep is needed after visense txfe disable as per
0898          * HW requirement.
0899          */
0900         usleep_range(200, 210);
0901         snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
0902                           0x01, 0x00);
0903     }
0904     return 0;
0905 }
0906
0907 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
0908                     bool enable)
0909 {
0910     snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7),
0911                       (enable << 7));
0912     snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7),
0913                       (enable << 7));
0914     return 0;
0915 }
0916
0917 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
0918                  struct snd_kcontrol *kcontrol, int event)
0919 {
0920     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
0921     struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
0922
0923     switch (event) {
0924     case SND_SOC_DAPM_PRE_PMU:
0925         snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
0926                           WSA881X_SPKR_OCP_MASK,
0927                           WSA881X_SPKR_OCP_EN);
0928         regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0,
0929                        ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
0930
0931         snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
0932                           WSA881X_PA_GAIN_SEL_MASK,
0933                           WSA881X_PA_GAIN_SEL_REG);
0934         break;
0935     case SND_SOC_DAPM_POST_PMU:
0936         if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
0937             wsa881x_visense_txfe_ctrl(comp, true);
0938             snd_soc_component_update_bits(comp,
0939                               WSA881X_ADC_EN_SEL_IBAIS,
0940                               0x07, 0x01);
0941             wsa881x_visense_adc_ctrl(comp, true);
0942         }
0943
0944         break;
0945     case SND_SOC_DAPM_POST_PMD:
0946         if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
0947             wsa881x_visense_adc_ctrl(comp, false);
0948             wsa881x_visense_txfe_ctrl(comp, false);
0949         }
0950
0951         snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
0952                           WSA881X_SPKR_OCP_MASK,
0953                           WSA881X_SPKR_OCP_EN |
0954                           WSA881X_SPKR_OCP_HOLD);
0955         break;
0956     }
0957     return 0;
0958 }
0959
0960 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
0961     SND_SOC_DAPM_INPUT("IN"),
0962     SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
0963                NULL,
0964                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0965     SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
0966                wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
0967                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0968     SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL,
0969                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0970     SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL,
0971                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0972     SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0,
0973                 NULL,
0974                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0975     SND_SOC_DAPM_OUTPUT("SPKR"),
0976 };
0977
0978 static int wsa881x_hw_params(struct snd_pcm_substream *substream,
0979                  struct snd_pcm_hw_params *params,
0980                  struct snd_soc_dai *dai)
0981 {
0982     struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
0983     int i;
0984
0985     wsa881x->active_ports = 0;
0986     for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) {
0987         if (!wsa881x->port_enable[i])
0988             continue;
0989
0990         wsa881x->port_config[wsa881x->active_ports] =
0991                             wsa881x_pconfig[i];
0992         wsa881x->active_ports++;
0993     }
0994
0995     return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig,
0996                     wsa881x->port_config, wsa881x->active_ports,
0997                     wsa881x->sruntime);
0998 }
0999
1000 static int wsa881x_hw_free(struct snd_pcm_substream *substream,
1001                struct snd_soc_dai *dai)
1002 {
1003     struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1004
1005     sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime);
1006
1007     return 0;
1008 }
1009
1010 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai,
1011                   void *stream, int direction)
1012 {
1013     struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1014
1015     wsa881x->sruntime = stream;
1016
1017     return 0;
1018 }
1019
1020 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1021 {
1022     struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev);
1023
1024     if (mute)
1025         regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1026                    0x00);
1027     else
1028         regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80,
1029                    0x80);
1030
1031     return 0;
1032 }
1033
1034 static const struct snd_soc_dai_ops wsa881x_dai_ops = {
1035     .hw_params = wsa881x_hw_params,
1036     .hw_free = wsa881x_hw_free,
1037     .mute_stream = wsa881x_digital_mute,
1038     .set_stream = wsa881x_set_sdw_stream,
1039 };
1040
1041 static struct snd_soc_dai_driver wsa881x_dais[] = {
1042     {
1043         .name = "SPKR",
1044         .id = 0,
1045         .playback = {
1046             .stream_name = "SPKR Playback",
1047             .rates = SNDRV_PCM_RATE_48000,
1048             .formats = SNDRV_PCM_FMTBIT_S16_LE,
1049             .rate_max = 48000,
1050             .rate_min = 48000,
1051             .channels_min = 1,
1052             .channels_max = 1,
1053         },
1054         .ops = &wsa881x_dai_ops,
1055     },
1056 };
1057
1058 static const struct snd_soc_component_driver wsa881x_component_drv = {
1059     .name = "WSA881x",
1060     .probe = wsa881x_component_probe,
1061     .controls = wsa881x_snd_controls,
1062     .num_controls = ARRAY_SIZE(wsa881x_snd_controls),
1063     .dapm_widgets = wsa881x_dapm_widgets,
1064     .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
1065     .dapm_routes = wsa881x_audio_map,
1066     .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
1067     .endianness = 1,
1068 };
1069
1070 static int wsa881x_update_status(struct sdw_slave *slave,
1071                  enum sdw_slave_status status)
1072 {
1073     struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1074
1075     if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1076         wsa881x_init(wsa881x);
1077
1078     return 0;
1079 }
1080
1081 static int wsa881x_port_prep(struct sdw_slave *slave,
1082                  struct sdw_prepare_ch *prepare_ch,
1083                  enum sdw_port_prep_ops state)
1084 {
1085     struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
1086
1087     if (state == SDW_OPS_PORT_POST_PREP)
1088         wsa881x->port_prepared[prepare_ch->num - 1] = true;
1089     else
1090         wsa881x->port_prepared[prepare_ch->num - 1] = false;
1091
1092     return 0;
1093 }
1094
1095 static int wsa881x_bus_config(struct sdw_slave *slave,
1096                   struct sdw_bus_params *params)
1097 {
1098     sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
1099           0x01);
1100
1101     return 0;
1102 }
1103
1104 static struct sdw_slave_ops wsa881x_slave_ops = {
1105     .update_status = wsa881x_update_status,
1106     .bus_config = wsa881x_bus_config,
1107     .port_prep = wsa881x_port_prep,
1108 };
1109
1110 static int wsa881x_probe(struct sdw_slave *pdev,
1111              const struct sdw_device_id *id)
1112 {
1113     struct wsa881x_priv *wsa881x;
1114     struct device *dev = &pdev->dev;
1115
1116     wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
1117     if (!wsa881x)
1118         return -ENOMEM;
1119
1120     wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown",
1121                         GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1122     if (IS_ERR(wsa881x->sd_n)) {
1123         dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
1124         return PTR_ERR(wsa881x->sd_n);
1125     }
1126
1127     dev_set_drvdata(&pdev->dev, wsa881x);
1128     wsa881x->slave = pdev;
1129     wsa881x->dev = &pdev->dev;
1130     wsa881x->sconfig.ch_count = 1;
1131     wsa881x->sconfig.bps = 1;
1132     wsa881x->sconfig.frame_rate = 48000;
1133     wsa881x->sconfig.direction = SDW_DATA_DIR_RX;
1134     wsa881x->sconfig.type = SDW_STREAM_PDM;
1135     pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
1136     pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1137     pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1138     gpiod_direction_output(wsa881x->sd_n, 1);
1139
1140     wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config);
1141     if (IS_ERR(wsa881x->regmap)) {
1142         dev_err(&pdev->dev, "regmap_init failed\n");
1143         return PTR_ERR(wsa881x->regmap);
1144     }
1145
1146     pm_runtime_set_autosuspend_delay(dev, 3000);
1147     pm_runtime_use_autosuspend(dev);
1148     pm_runtime_mark_last_busy(dev);
1149     pm_runtime_set_active(dev);
1150     pm_runtime_enable(dev);
1151
1152     return devm_snd_soc_register_component(&pdev->dev,
1153                            &wsa881x_component_drv,
1154                            wsa881x_dais,
1155                            ARRAY_SIZE(wsa881x_dais));
1156 }
1157
1158 static int __maybe_unused wsa881x_runtime_suspend(struct device *dev)
1159 {
1160     struct regmap *regmap = dev_get_regmap(dev, NULL);
1161     struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1162
1163     gpiod_direction_output(wsa881x->sd_n, 0);
1164
1165     regcache_cache_only(regmap, true);
1166     regcache_mark_dirty(regmap);
1167
1168     return 0;
1169 }
1170
1171 static int __maybe_unused wsa881x_runtime_resume(struct device *dev)
1172 {
1173     struct sdw_slave *slave = dev_to_sdw_dev(dev);
1174     struct regmap *regmap = dev_get_regmap(dev, NULL);
1175     struct wsa881x_priv *wsa881x = dev_get_drvdata(dev);
1176     unsigned long time;
1177
1178     gpiod_direction_output(wsa881x->sd_n, 1);
1179
1180     time = wait_for_completion_timeout(&slave->initialization_complete,
1181                        msecs_to_jiffies(WSA881X_PROBE_TIMEOUT));
1182     if (!time) {
1183         dev_err(dev, "Initialization not complete, timed out\n");
1184         gpiod_direction_output(wsa881x->sd_n, 0);
1185         return -ETIMEDOUT;
1186     }
1187
1188     regcache_cache_only(regmap, false);
1189     regcache_sync(regmap);
1190
1191     return 0;
1192 }
1193
1194 static const struct dev_pm_ops wsa881x_pm_ops = {
1195     SET_RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL)
1196 };
1197
1198 static const struct sdw_device_id wsa881x_slave_id[] = {
1199     SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
1200     SDW_SLAVE_ENTRY(0x0217, 0x2110, 0),
1201     {},
1202 };
1203 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
1204
1205 static struct sdw_driver wsa881x_codec_driver = {
1206     .probe  = wsa881x_probe,
1207     .ops = &wsa881x_slave_ops,
1208     .id_table = wsa881x_slave_id,
1209     .driver = {
1210         .name   = "wsa881x-codec",
1211         .pm = &wsa881x_pm_ops,
1212     }
1213 };
1214 module_sdw_driver(wsa881x_codec_driver);
1215
1216 MODULE_DESCRIPTION("WSA881x codec driver");
1217 MODULE_LICENSE("GPL v2");