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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm9081.c  --  WM9081 ALSA SoC Audio driver
0004  *
0005  * Author: Mark Brown
0006  *
0007  * Copyright 2009-12 Wolfson Microelectronics plc
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/pm.h>
0016 #include <linux/i2c.h>
0017 #include <linux/regmap.h>
0018 #include <linux/slab.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/initval.h>
0024 #include <sound/tlv.h>
0025 
0026 #include <sound/wm9081.h>
0027 #include "wm9081.h"
0028 
0029 static const struct reg_default wm9081_reg[] = {
0030     {  2, 0x00B9 },     /* R2  - Analogue Lineout */
0031     {  3, 0x00B9 },     /* R3  - Analogue Speaker PGA */
0032     {  4, 0x0001 },     /* R4  - VMID Control */
0033     {  5, 0x0068 },     /* R5  - Bias Control 1 */
0034     {  7, 0x0000 },     /* R7  - Analogue Mixer */
0035     {  8, 0x0000 },     /* R8  - Anti Pop Control */
0036     {  9, 0x01DB },     /* R9  - Analogue Speaker 1 */
0037     { 10, 0x0018 },     /* R10 - Analogue Speaker 2 */
0038     { 11, 0x0180 },     /* R11 - Power Management */
0039     { 12, 0x0000 },     /* R12 - Clock Control 1 */
0040     { 13, 0x0038 },     /* R13 - Clock Control 2 */
0041     { 14, 0x4000 },     /* R14 - Clock Control 3 */
0042     { 16, 0x0000 },     /* R16 - FLL Control 1 */
0043     { 17, 0x0200 },     /* R17 - FLL Control 2 */
0044     { 18, 0x0000 },     /* R18 - FLL Control 3 */
0045     { 19, 0x0204 },     /* R19 - FLL Control 4 */
0046     { 20, 0x0000 },     /* R20 - FLL Control 5 */
0047     { 22, 0x0000 },     /* R22 - Audio Interface 1 */
0048     { 23, 0x0002 },     /* R23 - Audio Interface 2 */
0049     { 24, 0x0008 },     /* R24 - Audio Interface 3 */
0050     { 25, 0x0022 },     /* R25 - Audio Interface 4 */
0051     { 27, 0x0006 },     /* R27 - Interrupt Status Mask */
0052     { 28, 0x0000 },     /* R28 - Interrupt Polarity */
0053     { 29, 0x0000 },     /* R29 - Interrupt Control */
0054     { 30, 0x00C0 },     /* R30 - DAC Digital 1 */
0055     { 31, 0x0008 },     /* R31 - DAC Digital 2 */
0056     { 32, 0x09AF },     /* R32 - DRC 1 */
0057     { 33, 0x4201 },     /* R33 - DRC 2 */
0058     { 34, 0x0000 },     /* R34 - DRC 3 */
0059     { 35, 0x0000 },     /* R35 - DRC 4 */
0060     { 38, 0x0000 },     /* R38 - Write Sequencer 1 */
0061     { 39, 0x0000 },     /* R39 - Write Sequencer 2 */
0062     { 40, 0x0002 },     /* R40 - MW Slave 1 */
0063     { 42, 0x0000 },     /* R42 - EQ 1 */
0064     { 43, 0x0000 },     /* R43 - EQ 2 */
0065     { 44, 0x0FCA },     /* R44 - EQ 3 */
0066     { 45, 0x0400 },     /* R45 - EQ 4 */
0067     { 46, 0x00B8 },     /* R46 - EQ 5 */
0068     { 47, 0x1EB5 },     /* R47 - EQ 6 */
0069     { 48, 0xF145 },     /* R48 - EQ 7 */
0070     { 49, 0x0B75 },     /* R49 - EQ 8 */
0071     { 50, 0x01C5 },     /* R50 - EQ 9 */
0072     { 51, 0x169E },     /* R51 - EQ 10 */
0073     { 52, 0xF829 },     /* R52 - EQ 11 */
0074     { 53, 0x07AD },     /* R53 - EQ 12 */
0075     { 54, 0x1103 },     /* R54 - EQ 13 */
0076     { 55, 0x1C58 },     /* R55 - EQ 14 */
0077     { 56, 0xF373 },     /* R56 - EQ 15 */
0078     { 57, 0x0A54 },     /* R57 - EQ 16 */
0079     { 58, 0x0558 },     /* R58 - EQ 17 */
0080     { 59, 0x0564 },     /* R59 - EQ 18 */
0081     { 60, 0x0559 },     /* R60 - EQ 19 */
0082     { 61, 0x4000 },     /* R61 - EQ 20 */
0083 };
0084 
0085 static struct {
0086     int ratio;
0087     int clk_sys_rate;
0088 } clk_sys_rates[] = {
0089     { 64,   0 },
0090     { 128,  1 },
0091     { 192,  2 },
0092     { 256,  3 },
0093     { 384,  4 },
0094     { 512,  5 },
0095     { 768,  6 },
0096     { 1024, 7 },
0097     { 1408, 8 },
0098     { 1536, 9 },
0099 };
0100 
0101 static struct {
0102     int rate;
0103     int sample_rate;
0104 } sample_rates[] = {
0105     { 8000,  0  },
0106     { 11025, 1  },
0107     { 12000, 2  },
0108     { 16000, 3  },
0109     { 22050, 4  },
0110     { 24000, 5  },
0111     { 32000, 6  },
0112     { 44100, 7  },
0113     { 48000, 8  },
0114     { 88200, 9  },
0115     { 96000, 10 },
0116 };
0117 
0118 static struct {
0119     int div; /* *10 due to .5s */
0120     int bclk_div;
0121 } bclk_divs[] = {
0122     { 10,  0  },
0123     { 15,  1  },
0124     { 20,  2  },
0125     { 30,  3  },
0126     { 40,  4  },
0127     { 50,  5  },
0128     { 55,  6  },
0129     { 60,  7  },
0130     { 80,  8  },
0131     { 100, 9  },
0132     { 110, 10 },
0133     { 120, 11 },
0134     { 160, 12 },
0135     { 200, 13 },
0136     { 220, 14 },
0137     { 240, 15 },
0138     { 250, 16 },
0139     { 300, 17 },
0140     { 320, 18 },
0141     { 440, 19 },
0142     { 480, 20 },
0143 };
0144 
0145 struct wm9081_priv {
0146     struct regmap *regmap;
0147     int sysclk_source;
0148     int mclk_rate;
0149     int sysclk_rate;
0150     int fs;
0151     int bclk;
0152     int master;
0153     int fll_fref;
0154     int fll_fout;
0155     int tdm_width;
0156     struct wm9081_pdata pdata;
0157 };
0158 
0159 static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
0160 {
0161     switch (reg) {
0162     case WM9081_SOFTWARE_RESET:
0163     case WM9081_INTERRUPT_STATUS:
0164         return true;
0165     default:
0166         return false;
0167     }
0168 }
0169 
0170 static bool wm9081_readable_register(struct device *dev, unsigned int reg)
0171 {
0172     switch (reg) {
0173     case WM9081_SOFTWARE_RESET:
0174     case WM9081_ANALOGUE_LINEOUT:
0175     case WM9081_ANALOGUE_SPEAKER_PGA:
0176     case WM9081_VMID_CONTROL:
0177     case WM9081_BIAS_CONTROL_1:
0178     case WM9081_ANALOGUE_MIXER:
0179     case WM9081_ANTI_POP_CONTROL:
0180     case WM9081_ANALOGUE_SPEAKER_1:
0181     case WM9081_ANALOGUE_SPEAKER_2:
0182     case WM9081_POWER_MANAGEMENT:
0183     case WM9081_CLOCK_CONTROL_1:
0184     case WM9081_CLOCK_CONTROL_2:
0185     case WM9081_CLOCK_CONTROL_3:
0186     case WM9081_FLL_CONTROL_1:
0187     case WM9081_FLL_CONTROL_2:
0188     case WM9081_FLL_CONTROL_3:
0189     case WM9081_FLL_CONTROL_4:
0190     case WM9081_FLL_CONTROL_5:
0191     case WM9081_AUDIO_INTERFACE_1:
0192     case WM9081_AUDIO_INTERFACE_2:
0193     case WM9081_AUDIO_INTERFACE_3:
0194     case WM9081_AUDIO_INTERFACE_4:
0195     case WM9081_INTERRUPT_STATUS:
0196     case WM9081_INTERRUPT_STATUS_MASK:
0197     case WM9081_INTERRUPT_POLARITY:
0198     case WM9081_INTERRUPT_CONTROL:
0199     case WM9081_DAC_DIGITAL_1:
0200     case WM9081_DAC_DIGITAL_2:
0201     case WM9081_DRC_1:
0202     case WM9081_DRC_2:
0203     case WM9081_DRC_3:
0204     case WM9081_DRC_4:
0205     case WM9081_WRITE_SEQUENCER_1:
0206     case WM9081_WRITE_SEQUENCER_2:
0207     case WM9081_MW_SLAVE_1:
0208     case WM9081_EQ_1:
0209     case WM9081_EQ_2:
0210     case WM9081_EQ_3:
0211     case WM9081_EQ_4:
0212     case WM9081_EQ_5:
0213     case WM9081_EQ_6:
0214     case WM9081_EQ_7:
0215     case WM9081_EQ_8:
0216     case WM9081_EQ_9:
0217     case WM9081_EQ_10:
0218     case WM9081_EQ_11:
0219     case WM9081_EQ_12:
0220     case WM9081_EQ_13:
0221     case WM9081_EQ_14:
0222     case WM9081_EQ_15:
0223     case WM9081_EQ_16:
0224     case WM9081_EQ_17:
0225     case WM9081_EQ_18:
0226     case WM9081_EQ_19:
0227     case WM9081_EQ_20:
0228         return true;
0229     default:
0230         return false;
0231     }
0232 }
0233 
0234 static int wm9081_reset(struct regmap *map)
0235 {
0236     return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
0237 }
0238 
0239 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
0240 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
0241 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
0242 static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
0243     0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
0244     1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
0245     2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
0246     3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
0247 );
0248 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
0249 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
0250 
0251 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0252 
0253 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
0254 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
0255 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
0256 
0257 static const char *drc_high_text[] = {
0258     "1",
0259     "1/2",
0260     "1/4",
0261     "1/8",
0262     "1/16",
0263     "0",
0264 };
0265 
0266 static SOC_ENUM_SINGLE_DECL(drc_high, WM9081_DRC_3, 3, drc_high_text);
0267 
0268 static const char *drc_low_text[] = {
0269     "1",
0270     "1/2",
0271     "1/4",
0272     "1/8",
0273     "0",
0274 };
0275 
0276 static SOC_ENUM_SINGLE_DECL(drc_low, WM9081_DRC_3, 0, drc_low_text);
0277 
0278 static const char *drc_atk_text[] = {
0279     "181us",
0280     "181us",
0281     "363us",
0282     "726us",
0283     "1.45ms",
0284     "2.9ms",
0285     "5.8ms",
0286     "11.6ms",
0287     "23.2ms",
0288     "46.4ms",
0289     "92.8ms",
0290     "185.6ms",
0291 };
0292 
0293 static SOC_ENUM_SINGLE_DECL(drc_atk, WM9081_DRC_2, 12, drc_atk_text);
0294 
0295 static const char *drc_dcy_text[] = {
0296     "186ms",
0297     "372ms",
0298     "743ms",
0299     "1.49s",
0300     "2.97s",
0301     "5.94s",
0302     "11.89s",
0303     "23.78s",
0304     "47.56s",
0305 };
0306 
0307 static SOC_ENUM_SINGLE_DECL(drc_dcy, WM9081_DRC_2, 8, drc_dcy_text);
0308 
0309 static const char *drc_qr_dcy_text[] = {
0310     "0.725ms",
0311     "1.45ms",
0312     "5.8ms",
0313 };
0314 
0315 static SOC_ENUM_SINGLE_DECL(drc_qr_dcy, WM9081_DRC_2, 4, drc_qr_dcy_text);
0316 
0317 static const char *dac_deemph_text[] = {
0318     "None",
0319     "32kHz",
0320     "44.1kHz",
0321     "48kHz",
0322 };
0323 
0324 static SOC_ENUM_SINGLE_DECL(dac_deemph, WM9081_DAC_DIGITAL_2, 1,
0325                 dac_deemph_text);
0326 
0327 static const char *speaker_mode_text[] = {
0328     "Class D",
0329     "Class AB",
0330 };
0331 
0332 static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6,
0333                 speaker_mode_text);
0334 
0335 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
0336                 struct snd_ctl_elem_value *ucontrol)
0337 {
0338     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0339     unsigned int reg;
0340 
0341     reg = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
0342     if (reg & WM9081_SPK_MODE)
0343         ucontrol->value.enumerated.item[0] = 1;
0344     else
0345         ucontrol->value.enumerated.item[0] = 0;
0346 
0347     return 0;
0348 }
0349 
0350 /*
0351  * Stop any attempts to change speaker mode while the speaker is enabled.
0352  *
0353  * We also have some special anti-pop controls dependent on speaker
0354  * mode which must be changed along with the mode.
0355  */
0356 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
0357                 struct snd_ctl_elem_value *ucontrol)
0358 {
0359     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0360     unsigned int reg_pwr = snd_soc_component_read(component, WM9081_POWER_MANAGEMENT);
0361     unsigned int reg2 = snd_soc_component_read(component, WM9081_ANALOGUE_SPEAKER_2);
0362 
0363     /* Are we changing anything? */
0364     if (ucontrol->value.enumerated.item[0] ==
0365         ((reg2 & WM9081_SPK_MODE) != 0))
0366         return 0;
0367 
0368     /* Don't try to change modes while enabled */
0369     if (reg_pwr & WM9081_SPK_ENA)
0370         return -EINVAL;
0371 
0372     if (ucontrol->value.enumerated.item[0]) {
0373         /* Class AB */
0374         reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
0375         reg2 |= WM9081_SPK_MODE;
0376     } else {
0377         /* Class D */
0378         reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
0379         reg2 &= ~WM9081_SPK_MODE;
0380     }
0381 
0382     snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2);
0383 
0384     return 0;
0385 }
0386 
0387 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
0388 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
0389 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
0390 
0391 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
0392 
0393 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
0394 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
0395 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
0396 
0397 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
0398 SOC_ENUM("DRC High Slope", drc_high),
0399 SOC_ENUM("DRC Low Slope", drc_low),
0400 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
0401 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
0402 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
0403 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
0404 SOC_ENUM("DRC Attack", drc_atk),
0405 SOC_ENUM("DRC Decay", drc_dcy),
0406 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
0407 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
0408 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
0409 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
0410 
0411 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
0412 
0413 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
0414 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
0415 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
0416 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
0417 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
0418            out_tlv),
0419 SOC_ENUM("DAC Deemphasis", dac_deemph),
0420 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
0421 };
0422 
0423 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
0424 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
0425 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
0426 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
0427 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
0428 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
0429 };
0430 
0431 static const struct snd_kcontrol_new mixer[] = {
0432 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
0433 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
0434 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
0435 };
0436 
0437 struct _fll_div {
0438     u16 fll_fratio;
0439     u16 fll_outdiv;
0440     u16 fll_clk_ref_div;
0441     u16 n;
0442     u16 k;
0443 };
0444 
0445 /* The size in bits of the FLL divide multiplied by 10
0446  * to allow rounding later */
0447 #define FIXED_FLL_SIZE ((1 << 16) * 10)
0448 
0449 static struct {
0450     unsigned int min;
0451     unsigned int max;
0452     u16 fll_fratio;
0453     int ratio;
0454 } fll_fratios[] = {
0455     {       0,    64000, 4, 16 },
0456     {   64000,   128000, 3,  8 },
0457     {  128000,   256000, 2,  4 },
0458     {  256000,  1000000, 1,  2 },
0459     { 1000000, 13500000, 0,  1 },
0460 };
0461 
0462 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
0463                unsigned int Fout)
0464 {
0465     u64 Kpart;
0466     unsigned int K, Ndiv, Nmod, target;
0467     unsigned int div;
0468     int i;
0469 
0470     /* Fref must be <=13.5MHz */
0471     div = 1;
0472     while ((Fref / div) > 13500000) {
0473         div *= 2;
0474 
0475         if (div > 8) {
0476             pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
0477                    Fref);
0478             return -EINVAL;
0479         }
0480     }
0481     fll_div->fll_clk_ref_div = div / 2;
0482 
0483     pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
0484 
0485     /* Apply the division for our remaining calculations */
0486     Fref /= div;
0487 
0488     /* Fvco should be 90-100MHz; don't check the upper bound */
0489     div = 0;
0490     target = Fout * 2;
0491     while (target < 90000000) {
0492         div++;
0493         target *= 2;
0494         if (div > 7) {
0495             pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
0496                    Fout);
0497             return -EINVAL;
0498         }
0499     }
0500     fll_div->fll_outdiv = div;
0501 
0502     pr_debug("Fvco=%dHz\n", target);
0503 
0504     /* Find an appropriate FLL_FRATIO and factor it out of the target */
0505     for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
0506         if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
0507             fll_div->fll_fratio = fll_fratios[i].fll_fratio;
0508             target /= fll_fratios[i].ratio;
0509             break;
0510         }
0511     }
0512     if (i == ARRAY_SIZE(fll_fratios)) {
0513         pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
0514         return -EINVAL;
0515     }
0516 
0517     /* Now, calculate N.K */
0518     Ndiv = target / Fref;
0519 
0520     fll_div->n = Ndiv;
0521     Nmod = target % Fref;
0522     pr_debug("Nmod=%d\n", Nmod);
0523 
0524     /* Calculate fractional part - scale up so we can round. */
0525     Kpart = FIXED_FLL_SIZE * (long long)Nmod;
0526 
0527     do_div(Kpart, Fref);
0528 
0529     K = Kpart & 0xFFFFFFFF;
0530 
0531     if ((K % 10) >= 5)
0532         K += 5;
0533 
0534     /* Move down to proper range now rounding is done */
0535     fll_div->k = K / 10;
0536 
0537     pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
0538          fll_div->n, fll_div->k,
0539          fll_div->fll_fratio, fll_div->fll_outdiv,
0540          fll_div->fll_clk_ref_div);
0541 
0542     return 0;
0543 }
0544 
0545 static int wm9081_set_fll(struct snd_soc_component *component, int fll_id,
0546               unsigned int Fref, unsigned int Fout)
0547 {
0548     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
0549     u16 reg1, reg4, reg5;
0550     struct _fll_div fll_div;
0551     int ret;
0552     int clk_sys_reg;
0553 
0554     /* Any change? */
0555     if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
0556         return 0;
0557 
0558     /* Disable the FLL */
0559     if (Fout == 0) {
0560         dev_dbg(component->dev, "FLL disabled\n");
0561         wm9081->fll_fref = 0;
0562         wm9081->fll_fout = 0;
0563 
0564         return 0;
0565     }
0566 
0567     ret = fll_factors(&fll_div, Fref, Fout);
0568     if (ret != 0)
0569         return ret;
0570 
0571     reg5 = snd_soc_component_read(component, WM9081_FLL_CONTROL_5);
0572     reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
0573 
0574     switch (fll_id) {
0575     case WM9081_SYSCLK_FLL_MCLK:
0576         reg5 |= 0x1;
0577         break;
0578 
0579     default:
0580         dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
0581         return -EINVAL;
0582     }
0583 
0584     /* Disable CLK_SYS while we reconfigure */
0585     clk_sys_reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
0586     if (clk_sys_reg & WM9081_CLK_SYS_ENA)
0587         snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3,
0588                  clk_sys_reg & ~WM9081_CLK_SYS_ENA);
0589 
0590     /* Any FLL configuration change requires that the FLL be
0591      * disabled first. */
0592     reg1 = snd_soc_component_read(component, WM9081_FLL_CONTROL_1);
0593     reg1 &= ~WM9081_FLL_ENA;
0594     snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
0595 
0596     /* Apply the configuration */
0597     if (fll_div.k)
0598         reg1 |= WM9081_FLL_FRAC_MASK;
0599     else
0600         reg1 &= ~WM9081_FLL_FRAC_MASK;
0601     snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1);
0602 
0603     snd_soc_component_write(component, WM9081_FLL_CONTROL_2,
0604              (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
0605              (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
0606     snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k);
0607 
0608     reg4 = snd_soc_component_read(component, WM9081_FLL_CONTROL_4);
0609     reg4 &= ~WM9081_FLL_N_MASK;
0610     reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
0611     snd_soc_component_write(component, WM9081_FLL_CONTROL_4, reg4);
0612 
0613     reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
0614     reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
0615     snd_soc_component_write(component, WM9081_FLL_CONTROL_5, reg5);
0616 
0617     /* Set gain to the recommended value */
0618     snd_soc_component_update_bits(component, WM9081_FLL_CONTROL_4,
0619                 WM9081_FLL_GAIN_MASK, 0);
0620 
0621     /* Enable the FLL */
0622     snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
0623 
0624     /* Then bring CLK_SYS up again if it was disabled */
0625     if (clk_sys_reg & WM9081_CLK_SYS_ENA)
0626         snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
0627 
0628     dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
0629 
0630     wm9081->fll_fref = Fref;
0631     wm9081->fll_fout = Fout;
0632 
0633     return 0;
0634 }
0635 
0636 static int configure_clock(struct snd_soc_component *component)
0637 {
0638     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
0639     int new_sysclk, i, target;
0640     unsigned int reg;
0641     int ret = 0;
0642     int mclkdiv = 0;
0643     int fll = 0;
0644 
0645     switch (wm9081->sysclk_source) {
0646     case WM9081_SYSCLK_MCLK:
0647         if (wm9081->mclk_rate > 12225000) {
0648             mclkdiv = 1;
0649             wm9081->sysclk_rate = wm9081->mclk_rate / 2;
0650         } else {
0651             wm9081->sysclk_rate = wm9081->mclk_rate;
0652         }
0653         wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK, 0, 0);
0654         break;
0655 
0656     case WM9081_SYSCLK_FLL_MCLK:
0657         /* If we have a sample rate calculate a CLK_SYS that
0658          * gives us a suitable DAC configuration, plus BCLK.
0659          * Ideally we would check to see if we can clock
0660          * directly from MCLK and only use the FLL if this is
0661          * not the case, though care must be taken with free
0662          * running mode.
0663          */
0664         if (wm9081->master && wm9081->bclk) {
0665             /* Make sure we can generate CLK_SYS and BCLK
0666              * and that we've got 3MHz for optimal
0667              * performance. */
0668             for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
0669                 target = wm9081->fs * clk_sys_rates[i].ratio;
0670                 new_sysclk = target;
0671                 if (target >= wm9081->bclk &&
0672                     target > 3000000)
0673                     break;
0674             }
0675 
0676             if (i == ARRAY_SIZE(clk_sys_rates))
0677                 return -EINVAL;
0678 
0679         } else if (wm9081->fs) {
0680             for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
0681                 new_sysclk = clk_sys_rates[i].ratio
0682                     * wm9081->fs;
0683                 if (new_sysclk > 3000000)
0684                     break;
0685             }
0686 
0687             if (i == ARRAY_SIZE(clk_sys_rates))
0688                 return -EINVAL;
0689 
0690         } else {
0691             new_sysclk = 12288000;
0692         }
0693 
0694         ret = wm9081_set_fll(component, WM9081_SYSCLK_FLL_MCLK,
0695                      wm9081->mclk_rate, new_sysclk);
0696         if (ret == 0) {
0697             wm9081->sysclk_rate = new_sysclk;
0698 
0699             /* Switch SYSCLK over to FLL */
0700             fll = 1;
0701         } else {
0702             wm9081->sysclk_rate = wm9081->mclk_rate;
0703         }
0704         break;
0705 
0706     default:
0707         return -EINVAL;
0708     }
0709 
0710     reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_1);
0711     if (mclkdiv)
0712         reg |= WM9081_MCLKDIV2;
0713     else
0714         reg &= ~WM9081_MCLKDIV2;
0715     snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg);
0716 
0717     reg = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_3);
0718     if (fll)
0719         reg |= WM9081_CLK_SRC_SEL;
0720     else
0721         reg &= ~WM9081_CLK_SRC_SEL;
0722     snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg);
0723 
0724     dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
0725 
0726     return ret;
0727 }
0728 
0729 static int clk_sys_event(struct snd_soc_dapm_widget *w,
0730              struct snd_kcontrol *kcontrol, int event)
0731 {
0732     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0733     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
0734 
0735     /* This should be done on init() for bypass paths */
0736     switch (wm9081->sysclk_source) {
0737     case WM9081_SYSCLK_MCLK:
0738         dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
0739         break;
0740     case WM9081_SYSCLK_FLL_MCLK:
0741         dev_dbg(component->dev, "Using %dHz MCLK with FLL\n",
0742             wm9081->mclk_rate);
0743         break;
0744     default:
0745         dev_err(component->dev, "System clock not configured\n");
0746         return -EINVAL;
0747     }
0748 
0749     switch (event) {
0750     case SND_SOC_DAPM_PRE_PMU:
0751         configure_clock(component);
0752         break;
0753 
0754     case SND_SOC_DAPM_POST_PMD:
0755         /* Disable the FLL if it's running */
0756         wm9081_set_fll(component, 0, 0, 0);
0757         break;
0758     }
0759 
0760     return 0;
0761 }
0762 
0763 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
0764 SND_SOC_DAPM_INPUT("IN1"),
0765 SND_SOC_DAPM_INPUT("IN2"),
0766 
0767 SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
0768 
0769 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
0770                  mixer, ARRAY_SIZE(mixer)),
0771 
0772 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
0773 
0774 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
0775 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
0776 
0777 SND_SOC_DAPM_OUTPUT("LINEOUT"),
0778 SND_SOC_DAPM_OUTPUT("SPKN"),
0779 SND_SOC_DAPM_OUTPUT("SPKP"),
0780 
0781 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
0782             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0783 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
0784 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
0785 SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
0786 };
0787 
0788 
0789 static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
0790     { "DAC", NULL, "CLK_SYS" },
0791     { "DAC", NULL, "CLK_DSP" },
0792     { "DAC", NULL, "AIF" },
0793 
0794     { "Mixer", "IN1 Switch", "IN1" },
0795     { "Mixer", "IN2 Switch", "IN2" },
0796     { "Mixer", "Playback Switch", "DAC" },
0797 
0798     { "LINEOUT PGA", NULL, "Mixer" },
0799     { "LINEOUT PGA", NULL, "TOCLK" },
0800     { "LINEOUT PGA", NULL, "CLK_SYS" },
0801 
0802     { "LINEOUT", NULL, "LINEOUT PGA" },
0803 
0804     { "Speaker PGA", NULL, "Mixer" },
0805     { "Speaker PGA", NULL, "TOCLK" },
0806     { "Speaker PGA", NULL, "CLK_SYS" },
0807 
0808     { "Speaker", NULL, "Speaker PGA" },
0809     { "Speaker", NULL, "TSENSE" },
0810 
0811     { "SPKN", NULL, "Speaker" },
0812     { "SPKP", NULL, "Speaker" },
0813 };
0814 
0815 static int wm9081_set_bias_level(struct snd_soc_component *component,
0816                  enum snd_soc_bias_level level)
0817 {
0818     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
0819 
0820     switch (level) {
0821     case SND_SOC_BIAS_ON:
0822         break;
0823 
0824     case SND_SOC_BIAS_PREPARE:
0825         /* VMID=2*40k */
0826         snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
0827                     WM9081_VMID_SEL_MASK, 0x2);
0828 
0829         /* Normal bias current */
0830         snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
0831                     WM9081_STBY_BIAS_ENA, 0);
0832         break;
0833 
0834     case SND_SOC_BIAS_STANDBY:
0835         /* Initial cold start */
0836         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0837             regcache_cache_only(wm9081->regmap, false);
0838             regcache_sync(wm9081->regmap);
0839 
0840             /* Disable LINEOUT discharge */
0841             snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
0842                         WM9081_LINEOUT_DISCH, 0);
0843 
0844             /* Select startup bias source */
0845             snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
0846                         WM9081_BIAS_SRC | WM9081_BIAS_ENA,
0847                         WM9081_BIAS_SRC | WM9081_BIAS_ENA);
0848 
0849             /* VMID 2*4k; Soft VMID ramp enable */
0850             snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
0851                         WM9081_VMID_RAMP |
0852                         WM9081_VMID_SEL_MASK,
0853                         WM9081_VMID_RAMP | 0x6);
0854 
0855             mdelay(100);
0856 
0857             /* Normal bias enable & soft start off */
0858             snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
0859                         WM9081_VMID_RAMP, 0);
0860 
0861             /* Standard bias source */
0862             snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
0863                         WM9081_BIAS_SRC, 0);
0864         }
0865 
0866         /* VMID 2*240k */
0867         snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
0868                     WM9081_VMID_SEL_MASK, 0x04);
0869 
0870         /* Standby bias current on */
0871         snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
0872                     WM9081_STBY_BIAS_ENA,
0873                     WM9081_STBY_BIAS_ENA);
0874         break;
0875 
0876     case SND_SOC_BIAS_OFF:
0877         /* Startup bias source and disable bias */
0878         snd_soc_component_update_bits(component, WM9081_BIAS_CONTROL_1,
0879                     WM9081_BIAS_SRC | WM9081_BIAS_ENA,
0880                     WM9081_BIAS_SRC);
0881 
0882         /* Disable VMID with soft ramping */
0883         snd_soc_component_update_bits(component, WM9081_VMID_CONTROL,
0884                     WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
0885                     WM9081_VMID_RAMP);
0886 
0887         /* Actively discharge LINEOUT */
0888         snd_soc_component_update_bits(component, WM9081_ANTI_POP_CONTROL,
0889                     WM9081_LINEOUT_DISCH,
0890                     WM9081_LINEOUT_DISCH);
0891 
0892         regcache_cache_only(wm9081->regmap, true);
0893         break;
0894     }
0895 
0896     return 0;
0897 }
0898 
0899 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
0900                   unsigned int fmt)
0901 {
0902     struct snd_soc_component *component = dai->component;
0903     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
0904     unsigned int aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
0905 
0906     aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
0907           WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
0908 
0909     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0910     case SND_SOC_DAIFMT_CBS_CFS:
0911         wm9081->master = 0;
0912         break;
0913     case SND_SOC_DAIFMT_CBS_CFM:
0914         aif2 |= WM9081_LRCLK_DIR;
0915         wm9081->master = 1;
0916         break;
0917     case SND_SOC_DAIFMT_CBM_CFS:
0918         aif2 |= WM9081_BCLK_DIR;
0919         wm9081->master = 1;
0920         break;
0921     case SND_SOC_DAIFMT_CBM_CFM:
0922         aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
0923         wm9081->master = 1;
0924         break;
0925     default:
0926         return -EINVAL;
0927     }
0928 
0929     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0930     case SND_SOC_DAIFMT_DSP_B:
0931         aif2 |= WM9081_AIF_LRCLK_INV;
0932         fallthrough;
0933     case SND_SOC_DAIFMT_DSP_A:
0934         aif2 |= 0x3;
0935         break;
0936     case SND_SOC_DAIFMT_I2S:
0937         aif2 |= 0x2;
0938         break;
0939     case SND_SOC_DAIFMT_RIGHT_J:
0940         break;
0941     case SND_SOC_DAIFMT_LEFT_J:
0942         aif2 |= 0x1;
0943         break;
0944     default:
0945         return -EINVAL;
0946     }
0947 
0948     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0949     case SND_SOC_DAIFMT_DSP_A:
0950     case SND_SOC_DAIFMT_DSP_B:
0951         /* frame inversion not valid for DSP modes */
0952         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0953         case SND_SOC_DAIFMT_NB_NF:
0954             break;
0955         case SND_SOC_DAIFMT_IB_NF:
0956             aif2 |= WM9081_AIF_BCLK_INV;
0957             break;
0958         default:
0959             return -EINVAL;
0960         }
0961         break;
0962 
0963     case SND_SOC_DAIFMT_I2S:
0964     case SND_SOC_DAIFMT_RIGHT_J:
0965     case SND_SOC_DAIFMT_LEFT_J:
0966         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0967         case SND_SOC_DAIFMT_NB_NF:
0968             break;
0969         case SND_SOC_DAIFMT_IB_IF:
0970             aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
0971             break;
0972         case SND_SOC_DAIFMT_IB_NF:
0973             aif2 |= WM9081_AIF_BCLK_INV;
0974             break;
0975         case SND_SOC_DAIFMT_NB_IF:
0976             aif2 |= WM9081_AIF_LRCLK_INV;
0977             break;
0978         default:
0979             return -EINVAL;
0980         }
0981         break;
0982     default:
0983         return -EINVAL;
0984     }
0985 
0986     snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
0987 
0988     return 0;
0989 }
0990 
0991 static int wm9081_hw_params(struct snd_pcm_substream *substream,
0992                 struct snd_pcm_hw_params *params,
0993                 struct snd_soc_dai *dai)
0994 {
0995     struct snd_soc_component *component = dai->component;
0996     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
0997     int ret, i, best, best_val, cur_val;
0998     unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
0999 
1000     clk_ctrl2 = snd_soc_component_read(component, WM9081_CLOCK_CONTROL_2);
1001     clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1002 
1003     aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
1004 
1005     aif2 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_2);
1006     aif2 &= ~WM9081_AIF_WL_MASK;
1007 
1008     aif3 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_3);
1009     aif3 &= ~WM9081_BCLK_DIV_MASK;
1010 
1011     aif4 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_4);
1012     aif4 &= ~WM9081_LRCLK_RATE_MASK;
1013 
1014     wm9081->fs = params_rate(params);
1015 
1016     if (wm9081->tdm_width) {
1017         /* If TDM is set up then that fixes our BCLK. */
1018         int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1019                  WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1020 
1021         wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1022     } else {
1023         /* Otherwise work out a BCLK from the sample size */
1024         wm9081->bclk = 2 * wm9081->fs;
1025 
1026         switch (params_width(params)) {
1027         case 16:
1028             wm9081->bclk *= 16;
1029             break;
1030         case 20:
1031             wm9081->bclk *= 20;
1032             aif2 |= 0x4;
1033             break;
1034         case 24:
1035             wm9081->bclk *= 24;
1036             aif2 |= 0x8;
1037             break;
1038         case 32:
1039             wm9081->bclk *= 32;
1040             aif2 |= 0xc;
1041             break;
1042         default:
1043             return -EINVAL;
1044         }
1045     }
1046 
1047     dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1048 
1049     ret = configure_clock(component);
1050     if (ret != 0)
1051         return ret;
1052 
1053     /* Select nearest CLK_SYS_RATE */
1054     best = 0;
1055     best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1056                - wm9081->fs);
1057     for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1058         cur_val = abs((wm9081->sysclk_rate /
1059                    clk_sys_rates[i].ratio) - wm9081->fs);
1060         if (cur_val < best_val) {
1061             best = i;
1062             best_val = cur_val;
1063         }
1064     }
1065     dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1066         clk_sys_rates[best].ratio);
1067     clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1068               << WM9081_CLK_SYS_RATE_SHIFT);
1069 
1070     /* SAMPLE_RATE */
1071     best = 0;
1072     best_val = abs(wm9081->fs - sample_rates[0].rate);
1073     for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1074         /* Closest match */
1075         cur_val = abs(wm9081->fs - sample_rates[i].rate);
1076         if (cur_val < best_val) {
1077             best = i;
1078             best_val = cur_val;
1079         }
1080     }
1081     dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1082         sample_rates[best].rate);
1083     clk_ctrl2 |= (sample_rates[best].sample_rate
1084             << WM9081_SAMPLE_RATE_SHIFT);
1085 
1086     /* BCLK_DIV */
1087     best = 0;
1088     best_val = INT_MAX;
1089     for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1090         cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1091             - wm9081->bclk;
1092         if (cur_val < 0) /* Table is sorted */
1093             break;
1094         if (cur_val < best_val) {
1095             best = i;
1096             best_val = cur_val;
1097         }
1098     }
1099     wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1100     dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1101         bclk_divs[best].div, wm9081->bclk);
1102     aif3 |= bclk_divs[best].bclk_div;
1103 
1104     /* LRCLK is a simple fraction of BCLK */
1105     dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1106     aif4 |= wm9081->bclk / wm9081->fs;
1107 
1108     /* Apply a ReTune Mobile configuration if it's in use */
1109     if (wm9081->pdata.num_retune_configs) {
1110         struct wm9081_pdata *pdata = &wm9081->pdata;
1111         struct wm9081_retune_mobile_setting *s;
1112         int eq1;
1113 
1114         best = 0;
1115         best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1116         for (i = 0; i < pdata->num_retune_configs; i++) {
1117             cur_val = abs(pdata->retune_configs[i].rate -
1118                       wm9081->fs);
1119             if (cur_val < best_val) {
1120                 best_val = cur_val;
1121                 best = i;
1122             }
1123         }
1124         s = &pdata->retune_configs[best];
1125 
1126         dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
1127             s->name, s->rate);
1128 
1129         /* If the EQ is enabled then disable it while we write out */
1130         eq1 = snd_soc_component_read(component, WM9081_EQ_1) & WM9081_EQ_ENA;
1131         if (eq1 & WM9081_EQ_ENA)
1132             snd_soc_component_write(component, WM9081_EQ_1, 0);
1133 
1134         /* Write out the other values */
1135         for (i = 1; i < ARRAY_SIZE(s->config); i++)
1136             snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]);
1137 
1138         eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1139         snd_soc_component_write(component, WM9081_EQ_1, eq1);
1140     }
1141 
1142     snd_soc_component_write(component, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1143     snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2);
1144     snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_3, aif3);
1145     snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_4, aif4);
1146 
1147     return 0;
1148 }
1149 
1150 static int wm9081_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1151 {
1152     struct snd_soc_component *component = codec_dai->component;
1153     unsigned int reg;
1154 
1155     reg = snd_soc_component_read(component, WM9081_DAC_DIGITAL_2);
1156 
1157     if (mute)
1158         reg |= WM9081_DAC_MUTE;
1159     else
1160         reg &= ~WM9081_DAC_MUTE;
1161 
1162     snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg);
1163 
1164     return 0;
1165 }
1166 
1167 static int wm9081_set_sysclk(struct snd_soc_component *component, int clk_id,
1168                  int source, unsigned int freq, int dir)
1169 {
1170     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1171 
1172     switch (clk_id) {
1173     case WM9081_SYSCLK_MCLK:
1174     case WM9081_SYSCLK_FLL_MCLK:
1175         wm9081->sysclk_source = clk_id;
1176         wm9081->mclk_rate = freq;
1177         break;
1178 
1179     default:
1180         return -EINVAL;
1181     }
1182 
1183     return 0;
1184 }
1185 
1186 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1187     unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1188 {
1189     struct snd_soc_component *component = dai->component;
1190     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1191     unsigned int aif1 = snd_soc_component_read(component, WM9081_AUDIO_INTERFACE_1);
1192 
1193     aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1194 
1195     if (slots < 0 || slots > 4)
1196         return -EINVAL;
1197 
1198     wm9081->tdm_width = slot_width;
1199 
1200     if (slots == 0)
1201         slots = 1;
1202 
1203     aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1204 
1205     switch (rx_mask) {
1206     case 1:
1207         break;
1208     case 2:
1209         aif1 |= 0x10;
1210         break;
1211     case 4:
1212         aif1 |= 0x20;
1213         break;
1214     case 8:
1215         aif1 |= 0x30;
1216         break;
1217     default:
1218         return -EINVAL;
1219     }
1220 
1221     snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_1, aif1);
1222 
1223     return 0;
1224 }
1225 
1226 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1227 
1228 #define WM9081_FORMATS \
1229     (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1230      SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1231 
1232 static const struct snd_soc_dai_ops wm9081_dai_ops = {
1233     .hw_params = wm9081_hw_params,
1234     .set_fmt = wm9081_set_dai_fmt,
1235     .mute_stream = wm9081_mute,
1236     .set_tdm_slot = wm9081_set_tdm_slot,
1237     .no_capture_mute = 1,
1238 };
1239 
1240 /* We report two channels because the CODEC processes a stereo signal, even
1241  * though it is only capable of handling a mono output.
1242  */
1243 static struct snd_soc_dai_driver wm9081_dai = {
1244     .name = "wm9081-hifi",
1245     .playback = {
1246         .stream_name = "AIF",
1247         .channels_min = 1,
1248         .channels_max = 2,
1249         .rates = WM9081_RATES,
1250         .formats = WM9081_FORMATS,
1251     },
1252     .ops = &wm9081_dai_ops,
1253 };
1254 
1255 static int wm9081_probe(struct snd_soc_component *component)
1256 {
1257     struct wm9081_priv *wm9081 = snd_soc_component_get_drvdata(component);
1258 
1259     /* Enable zero cross by default */
1260     snd_soc_component_update_bits(component, WM9081_ANALOGUE_LINEOUT,
1261                 WM9081_LINEOUTZC, WM9081_LINEOUTZC);
1262     snd_soc_component_update_bits(component, WM9081_ANALOGUE_SPEAKER_PGA,
1263                 WM9081_SPKPGAZC, WM9081_SPKPGAZC);
1264 
1265     if (!wm9081->pdata.num_retune_configs) {
1266         dev_dbg(component->dev,
1267             "No ReTune Mobile data, using normal EQ\n");
1268         snd_soc_add_component_controls(component, wm9081_eq_controls,
1269                      ARRAY_SIZE(wm9081_eq_controls));
1270     }
1271 
1272     return 0;
1273 }
1274 
1275 static const struct snd_soc_component_driver soc_component_dev_wm9081 = {
1276     .probe          = wm9081_probe,
1277     .set_sysclk     = wm9081_set_sysclk,
1278     .set_bias_level     = wm9081_set_bias_level,
1279     .controls       = wm9081_snd_controls,
1280     .num_controls       = ARRAY_SIZE(wm9081_snd_controls),
1281     .dapm_widgets       = wm9081_dapm_widgets,
1282     .num_dapm_widgets   = ARRAY_SIZE(wm9081_dapm_widgets),
1283     .dapm_routes        = wm9081_audio_paths,
1284     .num_dapm_routes    = ARRAY_SIZE(wm9081_audio_paths),
1285     .use_pmdown_time    = 1,
1286     .endianness     = 1,
1287 };
1288 
1289 static const struct regmap_config wm9081_regmap = {
1290     .reg_bits = 8,
1291     .val_bits = 16,
1292 
1293     .max_register = WM9081_MAX_REGISTER,
1294     .reg_defaults = wm9081_reg,
1295     .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1296     .volatile_reg = wm9081_volatile_register,
1297     .readable_reg = wm9081_readable_register,
1298     .cache_type = REGCACHE_RBTREE,
1299 };
1300 
1301 static int wm9081_i2c_probe(struct i2c_client *i2c)
1302 {
1303     struct wm9081_priv *wm9081;
1304     unsigned int reg;
1305     int ret;
1306 
1307     wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
1308                   GFP_KERNEL);
1309     if (wm9081 == NULL)
1310         return -ENOMEM;
1311 
1312     i2c_set_clientdata(i2c, wm9081);
1313 
1314     wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap);
1315     if (IS_ERR(wm9081->regmap)) {
1316         ret = PTR_ERR(wm9081->regmap);
1317         dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1318         return ret;
1319     }
1320 
1321     ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
1322     if (ret != 0) {
1323         dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1324         return ret;
1325     }
1326     if (reg != 0x9081) {
1327         dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1328         return -EINVAL;
1329     }
1330 
1331     ret = wm9081_reset(wm9081->regmap);
1332     if (ret < 0) {
1333         dev_err(&i2c->dev, "Failed to issue reset\n");
1334         return ret;
1335     }
1336 
1337     if (dev_get_platdata(&i2c->dev))
1338         memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1339                sizeof(wm9081->pdata));
1340 
1341     reg = 0;
1342     if (wm9081->pdata.irq_high)
1343         reg |= WM9081_IRQ_POL;
1344     if (!wm9081->pdata.irq_cmos)
1345         reg |= WM9081_IRQ_OP_CTRL;
1346     regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL,
1347                WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1348 
1349     regcache_cache_only(wm9081->regmap, true);
1350 
1351     ret = devm_snd_soc_register_component(&i2c->dev,
1352             &soc_component_dev_wm9081, &wm9081_dai, 1);
1353     if (ret < 0)
1354         return ret;
1355 
1356     return 0;
1357 }
1358 
1359 static int wm9081_i2c_remove(struct i2c_client *client)
1360 {
1361     return 0;
1362 }
1363 
1364 static const struct i2c_device_id wm9081_i2c_id[] = {
1365     { "wm9081", 0 },
1366     { }
1367 };
1368 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1369 
1370 static struct i2c_driver wm9081_i2c_driver = {
1371     .driver = {
1372         .name = "wm9081",
1373     },
1374     .probe_new = wm9081_i2c_probe,
1375     .remove =   wm9081_i2c_remove,
1376     .id_table = wm9081_i2c_id,
1377 };
1378 
1379 module_i2c_driver(wm9081_i2c_driver);
1380 
1381 MODULE_DESCRIPTION("ASoC WM9081 driver");
1382 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1383 MODULE_LICENSE("GPL");
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