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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8993.c -- WM8993 ALSA SoC audio driver
0004  *
0005  * Copyright 2009-12 Wolfson Microelectronics plc
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/i2c.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/slab.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/tlv.h>
0024 #include <sound/soc.h>
0025 #include <sound/initval.h>
0026 #include <sound/wm8993.h>
0027 
0028 #include "wm8993.h"
0029 #include "wm_hubs.h"
0030 
0031 #define WM8993_NUM_SUPPLIES 6
0032 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
0033     "DCVDD",
0034     "DBVDD",
0035     "AVDD1",
0036     "AVDD2",
0037     "CPVDD",
0038     "SPKVDD",
0039 };
0040 
0041 static const struct reg_default wm8993_reg_defaults[] = {
0042     { 1,   0x0000 },     /* R1   - Power Management (1) */
0043     { 2,   0x6000 },     /* R2   - Power Management (2) */
0044     { 3,   0x0000 },     /* R3   - Power Management (3) */
0045     { 4,   0x4050 },     /* R4   - Audio Interface (1) */
0046     { 5,   0x4000 },     /* R5   - Audio Interface (2) */
0047     { 6,   0x01C8 },     /* R6   - Clocking 1 */
0048     { 7,   0x0000 },     /* R7   - Clocking 2 */
0049     { 8,   0x0000 },     /* R8   - Audio Interface (3) */
0050     { 9,   0x0040 },     /* R9   - Audio Interface (4) */
0051     { 10,  0x0004 },     /* R10  - DAC CTRL */
0052     { 11,  0x00C0 },     /* R11  - Left DAC Digital Volume */
0053     { 12,  0x00C0 },     /* R12  - Right DAC Digital Volume */
0054     { 13,  0x0000 },     /* R13  - Digital Side Tone */
0055     { 14,  0x0300 },     /* R14  - ADC CTRL */
0056     { 15,  0x00C0 },     /* R15  - Left ADC Digital Volume */
0057     { 16,  0x00C0 },     /* R16  - Right ADC Digital Volume */
0058     { 18,  0x0000 },     /* R18  - GPIO CTRL 1 */
0059     { 19,  0x0010 },     /* R19  - GPIO1 */
0060     { 20,  0x0000 },     /* R20  - IRQ_DEBOUNCE */
0061     { 21,  0x0000 },     /* R21  - Inputs Clamp */
0062     { 22,  0x8000 },     /* R22  - GPIOCTRL 2 */
0063     { 23,  0x0800 },     /* R23  - GPIO_POL */
0064     { 24,  0x008B },     /* R24  - Left Line Input 1&2 Volume */
0065     { 25,  0x008B },     /* R25  - Left Line Input 3&4 Volume */
0066     { 26,  0x008B },     /* R26  - Right Line Input 1&2 Volume */
0067     { 27,  0x008B },     /* R27  - Right Line Input 3&4 Volume */
0068     { 28,  0x006D },     /* R28  - Left Output Volume */
0069     { 29,  0x006D },     /* R29  - Right Output Volume */
0070     { 30,  0x0066 },     /* R30  - Line Outputs Volume */
0071     { 31,  0x0020 },     /* R31  - HPOUT2 Volume */
0072     { 32,  0x0079 },     /* R32  - Left OPGA Volume */
0073     { 33,  0x0079 },     /* R33  - Right OPGA Volume */
0074     { 34,  0x0003 },     /* R34  - SPKMIXL Attenuation */
0075     { 35,  0x0003 },     /* R35  - SPKMIXR Attenuation */
0076     { 36,  0x0011 },     /* R36  - SPKOUT Mixers */
0077     { 37,  0x0100 },     /* R37  - SPKOUT Boost */
0078     { 38,  0x0079 },     /* R38  - Speaker Volume Left */
0079     { 39,  0x0079 },     /* R39  - Speaker Volume Right */
0080     { 40,  0x0000 },     /* R40  - Input Mixer2 */
0081     { 41,  0x0000 },     /* R41  - Input Mixer3 */
0082     { 42,  0x0000 },     /* R42  - Input Mixer4 */
0083     { 43,  0x0000 },     /* R43  - Input Mixer5 */
0084     { 44,  0x0000 },     /* R44  - Input Mixer6 */
0085     { 45,  0x0000 },     /* R45  - Output Mixer1 */
0086     { 46,  0x0000 },     /* R46  - Output Mixer2 */
0087     { 47,  0x0000 },     /* R47  - Output Mixer3 */
0088     { 48,  0x0000 },     /* R48  - Output Mixer4 */
0089     { 49,  0x0000 },     /* R49  - Output Mixer5 */
0090     { 50,  0x0000 },     /* R50  - Output Mixer6 */
0091     { 51,  0x0000 },     /* R51  - HPOUT2 Mixer */
0092     { 52,  0x0000 },     /* R52  - Line Mixer1 */
0093     { 53,  0x0000 },     /* R53  - Line Mixer2 */
0094     { 54,  0x0000 },     /* R54  - Speaker Mixer */
0095     { 55,  0x0000 },     /* R55  - Additional Control */
0096     { 56,  0x0000 },     /* R56  - AntiPOP1 */
0097     { 57,  0x0000 },     /* R57  - AntiPOP2 */
0098     { 58,  0x0000 },     /* R58  - MICBIAS */
0099     { 60,  0x0000 },     /* R60  - FLL Control 1 */
0100     { 61,  0x0000 },     /* R61  - FLL Control 2 */
0101     { 62,  0x0000 },     /* R62  - FLL Control 3 */
0102     { 63,  0x2EE0 },     /* R63  - FLL Control 4 */
0103     { 64,  0x0002 },     /* R64  - FLL Control 5 */
0104     { 65,  0x2287 },     /* R65  - Clocking 3 */
0105     { 66,  0x025F },     /* R66  - Clocking 4 */
0106     { 67,  0x0000 },     /* R67  - MW Slave Control */
0107     { 69,  0x0002 },     /* R69  - Bus Control 1 */
0108     { 70,  0x0000 },     /* R70  - Write Sequencer 0 */
0109     { 71,  0x0000 },     /* R71  - Write Sequencer 1 */
0110     { 72,  0x0000 },     /* R72  - Write Sequencer 2 */
0111     { 73,  0x0000 },     /* R73  - Write Sequencer 3 */
0112     { 74,  0x0000 },     /* R74  - Write Sequencer 4 */
0113     { 75,  0x0000 },     /* R75  - Write Sequencer 5 */
0114     { 76,  0x1F25 },     /* R76  - Charge Pump 1 */
0115     { 81,  0x0000 },     /* R81  - Class W 0 */
0116     { 85,  0x054A },     /* R85  - DC Servo 1 */
0117     { 87,  0x0000 },     /* R87  - DC Servo 3 */
0118     { 96,  0x0100 },     /* R96  - Analogue HP 0 */
0119     { 98,  0x0000 },     /* R98  - EQ1 */
0120     { 99,  0x000C },     /* R99  - EQ2 */
0121     { 100, 0x000C },     /* R100 - EQ3 */
0122     { 101, 0x000C },     /* R101 - EQ4 */
0123     { 102, 0x000C },     /* R102 - EQ5 */
0124     { 103, 0x000C },     /* R103 - EQ6 */
0125     { 104, 0x0FCA },     /* R104 - EQ7 */
0126     { 105, 0x0400 },     /* R105 - EQ8 */
0127     { 106, 0x00D8 },     /* R106 - EQ9 */
0128     { 107, 0x1EB5 },     /* R107 - EQ10 */
0129     { 108, 0xF145 },     /* R108 - EQ11 */
0130     { 109, 0x0B75 },     /* R109 - EQ12 */
0131     { 110, 0x01C5 },     /* R110 - EQ13 */
0132     { 111, 0x1C58 },     /* R111 - EQ14 */
0133     { 112, 0xF373 },     /* R112 - EQ15 */
0134     { 113, 0x0A54 },     /* R113 - EQ16 */
0135     { 114, 0x0558 },     /* R114 - EQ17 */
0136     { 115, 0x168E },     /* R115 - EQ18 */
0137     { 116, 0xF829 },     /* R116 - EQ19 */
0138     { 117, 0x07AD },     /* R117 - EQ20 */
0139     { 118, 0x1103 },     /* R118 - EQ21 */
0140     { 119, 0x0564 },     /* R119 - EQ22 */
0141     { 120, 0x0559 },     /* R120 - EQ23 */
0142     { 121, 0x4000 },     /* R121 - EQ24 */
0143     { 122, 0x0000 },     /* R122 - Digital Pulls */
0144     { 123, 0x0F08 },     /* R123 - DRC Control 1 */
0145     { 124, 0x0000 },     /* R124 - DRC Control 2 */
0146     { 125, 0x0080 },     /* R125 - DRC Control 3 */
0147     { 126, 0x0000 },     /* R126 - DRC Control 4 */
0148 };
0149 
0150 static struct {
0151     int ratio;
0152     int clk_sys_rate;
0153 } clk_sys_rates[] = {
0154     { 64,   0 },
0155     { 128,  1 },
0156     { 192,  2 },
0157     { 256,  3 },
0158     { 384,  4 },
0159     { 512,  5 },
0160     { 768,  6 },
0161     { 1024, 7 },
0162     { 1408, 8 },
0163     { 1536, 9 },
0164 };
0165 
0166 static struct {
0167     int rate;
0168     int sample_rate;
0169 } sample_rates[] = {
0170     { 8000,  0  },
0171     { 11025, 1  },
0172     { 12000, 1  },
0173     { 16000, 2  },
0174     { 22050, 3  },
0175     { 24000, 3  },
0176     { 32000, 4  },
0177     { 44100, 5  },
0178     { 48000, 5  },
0179 };
0180 
0181 static struct {
0182     int div; /* *10 due to .5s */
0183     int bclk_div;
0184 } bclk_divs[] = {
0185     { 10,  0  },
0186     { 15,  1  },
0187     { 20,  2  },
0188     { 30,  3  },
0189     { 40,  4  },
0190     { 55,  5  },
0191     { 60,  6  },
0192     { 80,  7  },
0193     { 110, 8  },
0194     { 120, 9  },
0195     { 160, 10 },
0196     { 220, 11 },
0197     { 240, 12 },
0198     { 320, 13 },
0199     { 440, 14 },
0200     { 480, 15 },
0201 };
0202 
0203 struct wm8993_priv {
0204     struct wm_hubs_data hubs_data;
0205     struct device *dev;
0206     struct regmap *regmap;
0207     struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
0208     struct wm8993_platform_data pdata;
0209     struct completion fll_lock;
0210     int master;
0211     int sysclk_source;
0212     int tdm_slots;
0213     int tdm_width;
0214     unsigned int mclk_rate;
0215     unsigned int sysclk_rate;
0216     unsigned int fs;
0217     unsigned int bclk;
0218     unsigned int fll_fref;
0219     unsigned int fll_fout;
0220     int fll_src;
0221 };
0222 
0223 static bool wm8993_volatile(struct device *dev, unsigned int reg)
0224 {
0225     switch (reg) {
0226     case WM8993_SOFTWARE_RESET:
0227     case WM8993_GPIO_CTRL_1:
0228     case WM8993_DC_SERVO_0:
0229     case WM8993_DC_SERVO_READBACK_0:
0230     case WM8993_DC_SERVO_READBACK_1:
0231     case WM8993_DC_SERVO_READBACK_2:
0232         return true;
0233     default:
0234         return false;
0235     }
0236 }
0237 
0238 static bool wm8993_readable(struct device *dev, unsigned int reg)
0239 {
0240     switch (reg) {
0241     case WM8993_SOFTWARE_RESET:
0242     case WM8993_POWER_MANAGEMENT_1:
0243     case WM8993_POWER_MANAGEMENT_2:
0244     case WM8993_POWER_MANAGEMENT_3:
0245     case WM8993_AUDIO_INTERFACE_1:
0246     case WM8993_AUDIO_INTERFACE_2:
0247     case WM8993_CLOCKING_1:
0248     case WM8993_CLOCKING_2:
0249     case WM8993_AUDIO_INTERFACE_3:
0250     case WM8993_AUDIO_INTERFACE_4:
0251     case WM8993_DAC_CTRL:
0252     case WM8993_LEFT_DAC_DIGITAL_VOLUME:
0253     case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
0254     case WM8993_DIGITAL_SIDE_TONE:
0255     case WM8993_ADC_CTRL:
0256     case WM8993_LEFT_ADC_DIGITAL_VOLUME:
0257     case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
0258     case WM8993_GPIO_CTRL_1:
0259     case WM8993_GPIO1:
0260     case WM8993_IRQ_DEBOUNCE:
0261     case WM8993_GPIOCTRL_2:
0262     case WM8993_GPIO_POL:
0263     case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
0264     case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
0265     case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
0266     case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
0267     case WM8993_LEFT_OUTPUT_VOLUME:
0268     case WM8993_RIGHT_OUTPUT_VOLUME:
0269     case WM8993_LINE_OUTPUTS_VOLUME:
0270     case WM8993_HPOUT2_VOLUME:
0271     case WM8993_LEFT_OPGA_VOLUME:
0272     case WM8993_RIGHT_OPGA_VOLUME:
0273     case WM8993_SPKMIXL_ATTENUATION:
0274     case WM8993_SPKMIXR_ATTENUATION:
0275     case WM8993_SPKOUT_MIXERS:
0276     case WM8993_SPKOUT_BOOST:
0277     case WM8993_SPEAKER_VOLUME_LEFT:
0278     case WM8993_SPEAKER_VOLUME_RIGHT:
0279     case WM8993_INPUT_MIXER2:
0280     case WM8993_INPUT_MIXER3:
0281     case WM8993_INPUT_MIXER4:
0282     case WM8993_INPUT_MIXER5:
0283     case WM8993_INPUT_MIXER6:
0284     case WM8993_OUTPUT_MIXER1:
0285     case WM8993_OUTPUT_MIXER2:
0286     case WM8993_OUTPUT_MIXER3:
0287     case WM8993_OUTPUT_MIXER4:
0288     case WM8993_OUTPUT_MIXER5:
0289     case WM8993_OUTPUT_MIXER6:
0290     case WM8993_HPOUT2_MIXER:
0291     case WM8993_LINE_MIXER1:
0292     case WM8993_LINE_MIXER2:
0293     case WM8993_SPEAKER_MIXER:
0294     case WM8993_ADDITIONAL_CONTROL:
0295     case WM8993_ANTIPOP1:
0296     case WM8993_ANTIPOP2:
0297     case WM8993_MICBIAS:
0298     case WM8993_FLL_CONTROL_1:
0299     case WM8993_FLL_CONTROL_2:
0300     case WM8993_FLL_CONTROL_3:
0301     case WM8993_FLL_CONTROL_4:
0302     case WM8993_FLL_CONTROL_5:
0303     case WM8993_CLOCKING_3:
0304     case WM8993_CLOCKING_4:
0305     case WM8993_MW_SLAVE_CONTROL:
0306     case WM8993_BUS_CONTROL_1:
0307     case WM8993_WRITE_SEQUENCER_0:
0308     case WM8993_WRITE_SEQUENCER_1:
0309     case WM8993_WRITE_SEQUENCER_2:
0310     case WM8993_WRITE_SEQUENCER_3:
0311     case WM8993_WRITE_SEQUENCER_4:
0312     case WM8993_WRITE_SEQUENCER_5:
0313     case WM8993_CHARGE_PUMP_1:
0314     case WM8993_CLASS_W_0:
0315     case WM8993_DC_SERVO_0:
0316     case WM8993_DC_SERVO_1:
0317     case WM8993_DC_SERVO_3:
0318     case WM8993_DC_SERVO_READBACK_0:
0319     case WM8993_DC_SERVO_READBACK_1:
0320     case WM8993_DC_SERVO_READBACK_2:
0321     case WM8993_ANALOGUE_HP_0:
0322     case WM8993_EQ1:
0323     case WM8993_EQ2:
0324     case WM8993_EQ3:
0325     case WM8993_EQ4:
0326     case WM8993_EQ5:
0327     case WM8993_EQ6:
0328     case WM8993_EQ7:
0329     case WM8993_EQ8:
0330     case WM8993_EQ9:
0331     case WM8993_EQ10:
0332     case WM8993_EQ11:
0333     case WM8993_EQ12:
0334     case WM8993_EQ13:
0335     case WM8993_EQ14:
0336     case WM8993_EQ15:
0337     case WM8993_EQ16:
0338     case WM8993_EQ17:
0339     case WM8993_EQ18:
0340     case WM8993_EQ19:
0341     case WM8993_EQ20:
0342     case WM8993_EQ21:
0343     case WM8993_EQ22:
0344     case WM8993_EQ23:
0345     case WM8993_EQ24:
0346     case WM8993_DIGITAL_PULLS:
0347     case WM8993_DRC_CONTROL_1:
0348     case WM8993_DRC_CONTROL_2:
0349     case WM8993_DRC_CONTROL_3:
0350     case WM8993_DRC_CONTROL_4:
0351         return true;
0352     default:
0353         return false;
0354     }
0355 }
0356 
0357 struct _fll_div {
0358     u16 fll_fratio;
0359     u16 fll_outdiv;
0360     u16 fll_clk_ref_div;
0361     u16 n;
0362     u16 k;
0363 };
0364 
0365 /* The size in bits of the FLL divide multiplied by 10
0366  * to allow rounding later */
0367 #define FIXED_FLL_SIZE ((1 << 16) * 10)
0368 
0369 static struct {
0370     unsigned int min;
0371     unsigned int max;
0372     u16 fll_fratio;
0373     int ratio;
0374 } fll_fratios[] = {
0375     {       0,    64000, 4, 16 },
0376     {   64000,   128000, 3,  8 },
0377     {  128000,   256000, 2,  4 },
0378     {  256000,  1000000, 1,  2 },
0379     { 1000000, 13500000, 0,  1 },
0380 };
0381 
0382 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
0383                unsigned int Fout)
0384 {
0385     u64 Kpart;
0386     unsigned int K, Ndiv, Nmod, target;
0387     unsigned int div;
0388     int i;
0389 
0390     /* Fref must be <=13.5MHz */
0391     div = 1;
0392     fll_div->fll_clk_ref_div = 0;
0393     while ((Fref / div) > 13500000) {
0394         div *= 2;
0395         fll_div->fll_clk_ref_div++;
0396 
0397         if (div > 8) {
0398             pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
0399                    Fref);
0400             return -EINVAL;
0401         }
0402     }
0403 
0404     pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
0405 
0406     /* Apply the division for our remaining calculations */
0407     Fref /= div;
0408 
0409     /* Fvco should be 90-100MHz; don't check the upper bound */
0410     div = 0;
0411     target = Fout * 2;
0412     while (target < 90000000) {
0413         div++;
0414         target *= 2;
0415         if (div > 7) {
0416             pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
0417                    Fout);
0418             return -EINVAL;
0419         }
0420     }
0421     fll_div->fll_outdiv = div;
0422 
0423     pr_debug("Fvco=%dHz\n", target);
0424 
0425     /* Find an appropriate FLL_FRATIO and factor it out of the target */
0426     for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
0427         if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
0428             fll_div->fll_fratio = fll_fratios[i].fll_fratio;
0429             target /= fll_fratios[i].ratio;
0430             break;
0431         }
0432     }
0433     if (i == ARRAY_SIZE(fll_fratios)) {
0434         pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
0435         return -EINVAL;
0436     }
0437 
0438     /* Now, calculate N.K */
0439     Ndiv = target / Fref;
0440 
0441     fll_div->n = Ndiv;
0442     Nmod = target % Fref;
0443     pr_debug("Nmod=%d\n", Nmod);
0444 
0445     /* Calculate fractional part - scale up so we can round. */
0446     Kpart = FIXED_FLL_SIZE * (long long)Nmod;
0447 
0448     do_div(Kpart, Fref);
0449 
0450     K = Kpart & 0xFFFFFFFF;
0451 
0452     if ((K % 10) >= 5)
0453         K += 5;
0454 
0455     /* Move down to proper range now rounding is done */
0456     fll_div->k = K / 10;
0457 
0458     pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
0459          fll_div->n, fll_div->k,
0460          fll_div->fll_fratio, fll_div->fll_outdiv,
0461          fll_div->fll_clk_ref_div);
0462 
0463     return 0;
0464 }
0465 
0466 static int _wm8993_set_fll(struct snd_soc_component *component, int fll_id, int source,
0467               unsigned int Fref, unsigned int Fout)
0468 {
0469     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
0470     struct i2c_client *i2c = to_i2c_client(component->dev);
0471     u16 reg1, reg4, reg5;
0472     struct _fll_div fll_div;
0473     unsigned int timeout;
0474     int ret;
0475 
0476     /* Any change? */
0477     if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
0478         return 0;
0479 
0480     /* Disable the FLL */
0481     if (Fout == 0) {
0482         dev_dbg(component->dev, "FLL disabled\n");
0483         wm8993->fll_fref = 0;
0484         wm8993->fll_fout = 0;
0485 
0486         reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
0487         reg1 &= ~WM8993_FLL_ENA;
0488         snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
0489 
0490         return 0;
0491     }
0492 
0493     ret = fll_factors(&fll_div, Fref, Fout);
0494     if (ret != 0)
0495         return ret;
0496 
0497     reg5 = snd_soc_component_read(component, WM8993_FLL_CONTROL_5);
0498     reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
0499 
0500     switch (fll_id) {
0501     case WM8993_FLL_MCLK:
0502         break;
0503 
0504     case WM8993_FLL_LRCLK:
0505         reg5 |= 1;
0506         break;
0507 
0508     case WM8993_FLL_BCLK:
0509         reg5 |= 2;
0510         break;
0511 
0512     default:
0513         dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
0514         return -EINVAL;
0515     }
0516 
0517     /* Any FLL configuration change requires that the FLL be
0518      * disabled first. */
0519     reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
0520     reg1 &= ~WM8993_FLL_ENA;
0521     snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
0522 
0523     /* Apply the configuration */
0524     if (fll_div.k)
0525         reg1 |= WM8993_FLL_FRAC_MASK;
0526     else
0527         reg1 &= ~WM8993_FLL_FRAC_MASK;
0528     snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
0529 
0530     snd_soc_component_write(component, WM8993_FLL_CONTROL_2,
0531               (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
0532               (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
0533     snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k);
0534 
0535     reg4 = snd_soc_component_read(component, WM8993_FLL_CONTROL_4);
0536     reg4 &= ~WM8993_FLL_N_MASK;
0537     reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
0538     snd_soc_component_write(component, WM8993_FLL_CONTROL_4, reg4);
0539 
0540     reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
0541     reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
0542     snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5);
0543 
0544     /* If we've got an interrupt wired up make sure we get it */
0545     if (i2c->irq)
0546         timeout = msecs_to_jiffies(20);
0547     else if (Fref < 1000000)
0548         timeout = msecs_to_jiffies(3);
0549     else
0550         timeout = msecs_to_jiffies(1);
0551 
0552     try_wait_for_completion(&wm8993->fll_lock);
0553 
0554     /* Enable the FLL */
0555     snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
0556 
0557     timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout);
0558     if (i2c->irq && !timeout)
0559         dev_warn(component->dev, "Timed out waiting for FLL\n");
0560 
0561     dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
0562 
0563     wm8993->fll_fref = Fref;
0564     wm8993->fll_fout = Fout;
0565     wm8993->fll_src = source;
0566 
0567     return 0;
0568 }
0569 
0570 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
0571               unsigned int Fref, unsigned int Fout)
0572 {
0573     return _wm8993_set_fll(dai->component, fll_id, source, Fref, Fout);
0574 }
0575 
0576 static int configure_clock(struct snd_soc_component *component)
0577 {
0578     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
0579     unsigned int reg;
0580 
0581     /* This should be done on init() for bypass paths */
0582     switch (wm8993->sysclk_source) {
0583     case WM8993_SYSCLK_MCLK:
0584         dev_dbg(component->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
0585 
0586         reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
0587         reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
0588         if (wm8993->mclk_rate > 13500000) {
0589             reg |= WM8993_MCLK_DIV;
0590             wm8993->sysclk_rate = wm8993->mclk_rate / 2;
0591         } else {
0592             reg &= ~WM8993_MCLK_DIV;
0593             wm8993->sysclk_rate = wm8993->mclk_rate;
0594         }
0595         snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
0596         break;
0597 
0598     case WM8993_SYSCLK_FLL:
0599         dev_dbg(component->dev, "Using %dHz FLL clock\n",
0600             wm8993->fll_fout);
0601 
0602         reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
0603         reg |= WM8993_SYSCLK_SRC;
0604         if (wm8993->fll_fout > 13500000) {
0605             reg |= WM8993_MCLK_DIV;
0606             wm8993->sysclk_rate = wm8993->fll_fout / 2;
0607         } else {
0608             reg &= ~WM8993_MCLK_DIV;
0609             wm8993->sysclk_rate = wm8993->fll_fout;
0610         }
0611         snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
0612         break;
0613 
0614     default:
0615         dev_err(component->dev, "System clock not configured\n");
0616         return -EINVAL;
0617     }
0618 
0619     dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
0620 
0621     return 0;
0622 }
0623 
0624 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
0625 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
0626 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
0627 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
0628 static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
0629     0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
0630     3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
0631 );
0632 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
0633 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
0634 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0635 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
0636 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
0637 
0638 static const char *dac_deemph_text[] = {
0639     "None",
0640     "32kHz",
0641     "44.1kHz",
0642     "48kHz",
0643 };
0644 
0645 static SOC_ENUM_SINGLE_DECL(dac_deemph,
0646                 WM8993_DAC_CTRL, 4, dac_deemph_text);
0647 
0648 static const char *adc_hpf_text[] = {
0649     "Hi-Fi",
0650     "Voice 1",
0651     "Voice 2",
0652     "Voice 3",
0653 };
0654 
0655 static SOC_ENUM_SINGLE_DECL(adc_hpf,
0656                 WM8993_ADC_CTRL, 5, adc_hpf_text);
0657 
0658 static const char *drc_path_text[] = {
0659     "ADC",
0660     "DAC"
0661 };
0662 
0663 static SOC_ENUM_SINGLE_DECL(drc_path,
0664                 WM8993_DRC_CONTROL_1, 14, drc_path_text);
0665 
0666 static const char *drc_r0_text[] = {
0667     "1",
0668     "1/2",
0669     "1/4",
0670     "1/8",
0671     "1/16",
0672     "0",
0673 };
0674 
0675 static SOC_ENUM_SINGLE_DECL(drc_r0,
0676                 WM8993_DRC_CONTROL_3, 8, drc_r0_text);
0677 
0678 static const char *drc_r1_text[] = {
0679     "1",
0680     "1/2",
0681     "1/4",
0682     "1/8",
0683     "0",
0684 };
0685 
0686 static SOC_ENUM_SINGLE_DECL(drc_r1,
0687                 WM8993_DRC_CONTROL_4, 13, drc_r1_text);
0688 
0689 static const char *drc_attack_text[] = {
0690     "Reserved",
0691     "181us",
0692     "363us",
0693     "726us",
0694     "1.45ms",
0695     "2.9ms",
0696     "5.8ms",
0697     "11.6ms",
0698     "23.2ms",
0699     "46.4ms",
0700     "92.8ms",
0701     "185.6ms",
0702 };
0703 
0704 static SOC_ENUM_SINGLE_DECL(drc_attack,
0705                 WM8993_DRC_CONTROL_2, 12, drc_attack_text);
0706 
0707 static const char *drc_decay_text[] = {
0708     "186ms",
0709     "372ms",
0710     "743ms",
0711     "1.49s",
0712     "2.97ms",
0713     "5.94ms",
0714     "11.89ms",
0715     "23.78ms",
0716     "47.56ms",
0717 };
0718 
0719 static SOC_ENUM_SINGLE_DECL(drc_decay,
0720                 WM8993_DRC_CONTROL_2, 8, drc_decay_text);
0721 
0722 static const char *drc_ff_text[] = {
0723     "5 samples",
0724     "9 samples",
0725 };
0726 
0727 static SOC_ENUM_SINGLE_DECL(drc_ff,
0728                 WM8993_DRC_CONTROL_3, 7, drc_ff_text);
0729 
0730 static const char *drc_qr_rate_text[] = {
0731     "0.725ms",
0732     "1.45ms",
0733     "5.8ms",
0734 };
0735 
0736 static SOC_ENUM_SINGLE_DECL(drc_qr_rate,
0737                 WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text);
0738 
0739 static const char *drc_smooth_text[] = {
0740     "Low",
0741     "Medium",
0742     "High",
0743 };
0744 
0745 static SOC_ENUM_SINGLE_DECL(drc_smooth,
0746                 WM8993_DRC_CONTROL_1, 4, drc_smooth_text);
0747 
0748 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
0749 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
0750            5, 9, 12, 0, sidetone_tlv),
0751 
0752 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
0753 SOC_ENUM("DRC Path", drc_path),
0754 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
0755            2, 60, 1, drc_comp_threash),
0756 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
0757            11, 30, 1, drc_comp_amp),
0758 SOC_ENUM("DRC R0", drc_r0),
0759 SOC_ENUM("DRC R1", drc_r1),
0760 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
0761            drc_min_tlv),
0762 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
0763            drc_max_tlv),
0764 SOC_ENUM("DRC Attack Rate", drc_attack),
0765 SOC_ENUM("DRC Decay Rate", drc_decay),
0766 SOC_ENUM("DRC FF Delay", drc_ff),
0767 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
0768 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
0769 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
0770            drc_qr_tlv),
0771 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
0772 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
0773 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
0774 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
0775 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
0776            drc_startup_tlv),
0777 
0778 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
0779 
0780 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
0781          WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
0782 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
0783 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
0784 
0785 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
0786          WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
0787 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
0788            dac_boost_tlv),
0789 SOC_ENUM("DAC Deemphasis", dac_deemph),
0790 
0791 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
0792            2, 1, 1, wm_hubs_spkmix_tlv),
0793 
0794 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
0795            2, 1, 1, wm_hubs_spkmix_tlv),
0796 };
0797 
0798 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
0799 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
0800 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
0801 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
0802 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
0803 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
0804 };
0805 
0806 static int clk_sys_event(struct snd_soc_dapm_widget *w,
0807              struct snd_kcontrol *kcontrol, int event)
0808 {
0809     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0810 
0811     switch (event) {
0812     case SND_SOC_DAPM_PRE_PMU:
0813         return configure_clock(component);
0814 
0815     case SND_SOC_DAPM_POST_PMD:
0816         break;
0817     }
0818 
0819     return 0;
0820 }
0821 
0822 static const struct snd_kcontrol_new left_speaker_mixer[] = {
0823 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
0824 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
0825 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
0826 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
0827 };
0828 
0829 static const struct snd_kcontrol_new right_speaker_mixer[] = {
0830 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
0831 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
0832 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
0833 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
0834 };
0835 
0836 static const char *aif_text[] = {
0837     "Left", "Right"
0838 };
0839 
0840 static SOC_ENUM_SINGLE_DECL(aifoutl_enum,
0841                 WM8993_AUDIO_INTERFACE_1, 15, aif_text);
0842 
0843 static const struct snd_kcontrol_new aifoutl_mux =
0844     SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
0845 
0846 static SOC_ENUM_SINGLE_DECL(aifoutr_enum,
0847                 WM8993_AUDIO_INTERFACE_1, 14, aif_text);
0848 
0849 static const struct snd_kcontrol_new aifoutr_mux =
0850     SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
0851 
0852 static SOC_ENUM_SINGLE_DECL(aifinl_enum,
0853                 WM8993_AUDIO_INTERFACE_2, 15, aif_text);
0854 
0855 static const struct snd_kcontrol_new aifinl_mux =
0856     SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
0857 
0858 static SOC_ENUM_SINGLE_DECL(aifinr_enum,
0859                 WM8993_AUDIO_INTERFACE_2, 14, aif_text);
0860 
0861 static const struct snd_kcontrol_new aifinr_mux =
0862     SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
0863 
0864 static const char *sidetone_text[] = {
0865     "None", "Left", "Right"
0866 };
0867 
0868 static SOC_ENUM_SINGLE_DECL(sidetonel_enum,
0869                 WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text);
0870 
0871 static const struct snd_kcontrol_new sidetonel_mux =
0872     SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
0873 
0874 static SOC_ENUM_SINGLE_DECL(sidetoner_enum,
0875                 WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text);
0876 
0877 static const struct snd_kcontrol_new sidetoner_mux =
0878     SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
0879 
0880 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
0881 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
0882             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0883 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
0884 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
0885 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
0886 
0887 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
0888 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
0889 
0890 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
0891 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
0892 
0893 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
0894 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
0895 
0896 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
0897 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
0898 
0899 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
0900 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
0901 
0902 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
0903 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
0904 
0905 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
0906 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
0907 
0908 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
0909 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
0910 
0911 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
0912            left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
0913 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
0914            right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
0915 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
0916 };
0917 
0918 static const struct snd_soc_dapm_route routes[] = {
0919     { "MICBIAS1", NULL, "VMID" },
0920     { "MICBIAS2", NULL, "VMID" },
0921 
0922     { "ADCL", NULL, "CLK_SYS" },
0923     { "ADCL", NULL, "CLK_DSP" },
0924     { "ADCR", NULL, "CLK_SYS" },
0925     { "ADCR", NULL, "CLK_DSP" },
0926 
0927     { "AIFOUTL Mux", "Left", "ADCL" },
0928     { "AIFOUTL Mux", "Right", "ADCR" },
0929     { "AIFOUTR Mux", "Left", "ADCL" },
0930     { "AIFOUTR Mux", "Right", "ADCR" },
0931 
0932     { "AIFOUTL", NULL, "AIFOUTL Mux" },
0933     { "AIFOUTR", NULL, "AIFOUTR Mux" },
0934 
0935     { "DACL Mux", "Left", "AIFINL" },
0936     { "DACL Mux", "Right", "AIFINR" },
0937     { "DACR Mux", "Left", "AIFINL" },
0938     { "DACR Mux", "Right", "AIFINR" },
0939 
0940     { "DACL Sidetone", "Left", "ADCL" },
0941     { "DACL Sidetone", "Right", "ADCR" },
0942     { "DACR Sidetone", "Left", "ADCL" },
0943     { "DACR Sidetone", "Right", "ADCR" },
0944 
0945     { "DACL", NULL, "CLK_SYS" },
0946     { "DACL", NULL, "CLK_DSP" },
0947     { "DACL", NULL, "DACL Mux" },
0948     { "DACL", NULL, "DACL Sidetone" },
0949     { "DACR", NULL, "CLK_SYS" },
0950     { "DACR", NULL, "CLK_DSP" },
0951     { "DACR", NULL, "DACR Mux" },
0952     { "DACR", NULL, "DACR Sidetone" },
0953 
0954     { "Left Output Mixer", "DAC Switch", "DACL" },
0955 
0956     { "Right Output Mixer", "DAC Switch", "DACR" },
0957 
0958     { "Left Output PGA", NULL, "CLK_SYS" },
0959 
0960     { "Right Output PGA", NULL, "CLK_SYS" },
0961 
0962     { "SPKL", "DAC Switch", "DACL" },
0963     { "SPKL", NULL, "CLK_SYS" },
0964 
0965     { "SPKR", "DAC Switch", "DACR" },
0966     { "SPKR", NULL, "CLK_SYS" },
0967 
0968     { "Left Headphone Mux", "DAC", "DACL" },
0969     { "Right Headphone Mux", "DAC", "DACR" },
0970 };
0971 
0972 static int wm8993_set_bias_level(struct snd_soc_component *component,
0973                  enum snd_soc_bias_level level)
0974 {
0975     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
0976     int ret;
0977 
0978     wm_hubs_set_bias_level(component, level);
0979 
0980     switch (level) {
0981     case SND_SOC_BIAS_ON:
0982     case SND_SOC_BIAS_PREPARE:
0983         /* VMID=2*40k */
0984         snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
0985                     WM8993_VMID_SEL_MASK, 0x2);
0986         snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
0987                     WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
0988         break;
0989 
0990     case SND_SOC_BIAS_STANDBY:
0991         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0992             ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
0993                             wm8993->supplies);
0994             if (ret != 0)
0995                 return ret;
0996 
0997             regcache_cache_only(wm8993->regmap, false);
0998             regcache_sync(wm8993->regmap);
0999 
1000             wm_hubs_vmid_ena(component);
1001 
1002             /* Bring up VMID with fast soft start */
1003             snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1004                         WM8993_STARTUP_BIAS_ENA |
1005                         WM8993_VMID_BUF_ENA |
1006                         WM8993_VMID_RAMP_MASK |
1007                         WM8993_BIAS_SRC,
1008                         WM8993_STARTUP_BIAS_ENA |
1009                         WM8993_VMID_BUF_ENA |
1010                         WM8993_VMID_RAMP_MASK |
1011                         WM8993_BIAS_SRC);
1012 
1013             /* If either line output is single ended we
1014              * need the VMID buffer */
1015             if (!wm8993->pdata.lineout1_diff ||
1016                 !wm8993->pdata.lineout2_diff)
1017                 snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1018                          WM8993_LINEOUT_VMID_BUF_ENA,
1019                          WM8993_LINEOUT_VMID_BUF_ENA);
1020 
1021             /* VMID=2*40k */
1022             snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1023                         WM8993_VMID_SEL_MASK |
1024                         WM8993_BIAS_ENA,
1025                         WM8993_BIAS_ENA | 0x2);
1026             msleep(32);
1027 
1028             /* Switch to normal bias */
1029             snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1030                         WM8993_BIAS_SRC |
1031                         WM8993_STARTUP_BIAS_ENA, 0);
1032         }
1033 
1034         /* VMID=2*240k */
1035         snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1036                     WM8993_VMID_SEL_MASK, 0x4);
1037 
1038         snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
1039                     WM8993_TSHUT_ENA, 0);
1040         break;
1041 
1042     case SND_SOC_BIAS_OFF:
1043         snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1044                     WM8993_LINEOUT_VMID_BUF_ENA, 0);
1045 
1046         snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1047                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1048                     0);
1049 
1050         snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1051                     WM8993_STARTUP_BIAS_ENA |
1052                     WM8993_VMID_BUF_ENA |
1053                     WM8993_VMID_RAMP_MASK |
1054                     WM8993_BIAS_SRC, 0);
1055 
1056         regcache_cache_only(wm8993->regmap, true);
1057         regcache_mark_dirty(wm8993->regmap);
1058 
1059         regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1060                        wm8993->supplies);
1061         break;
1062     }
1063 
1064     return 0;
1065 }
1066 
1067 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1068                  int clk_id, unsigned int freq, int dir)
1069 {
1070     struct snd_soc_component *component = codec_dai->component;
1071     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1072 
1073     switch (clk_id) {
1074     case WM8993_SYSCLK_MCLK:
1075         wm8993->mclk_rate = freq;
1076         fallthrough;
1077     case WM8993_SYSCLK_FLL:
1078         wm8993->sysclk_source = clk_id;
1079         break;
1080 
1081     default:
1082         return -EINVAL;
1083     }
1084 
1085     return 0;
1086 }
1087 
1088 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1089                   unsigned int fmt)
1090 {
1091     struct snd_soc_component *component = dai->component;
1092     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1093     unsigned int aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
1094     unsigned int aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
1095 
1096     aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1097           WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1098     aif4 &= ~WM8993_LRCLK_DIR;
1099 
1100     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1101     case SND_SOC_DAIFMT_CBS_CFS:
1102         wm8993->master = 0;
1103         break;
1104     case SND_SOC_DAIFMT_CBS_CFM:
1105         aif4 |= WM8993_LRCLK_DIR;
1106         wm8993->master = 1;
1107         break;
1108     case SND_SOC_DAIFMT_CBM_CFS:
1109         aif1 |= WM8993_BCLK_DIR;
1110         wm8993->master = 1;
1111         break;
1112     case SND_SOC_DAIFMT_CBM_CFM:
1113         aif1 |= WM8993_BCLK_DIR;
1114         aif4 |= WM8993_LRCLK_DIR;
1115         wm8993->master = 1;
1116         break;
1117     default:
1118         return -EINVAL;
1119     }
1120 
1121     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1122     case SND_SOC_DAIFMT_DSP_B:
1123         aif1 |= WM8993_AIF_LRCLK_INV;
1124         fallthrough;
1125     case SND_SOC_DAIFMT_DSP_A:
1126         aif1 |= 0x18;
1127         break;
1128     case SND_SOC_DAIFMT_I2S:
1129         aif1 |= 0x10;
1130         break;
1131     case SND_SOC_DAIFMT_RIGHT_J:
1132         break;
1133     case SND_SOC_DAIFMT_LEFT_J:
1134         aif1 |= 0x8;
1135         break;
1136     default:
1137         return -EINVAL;
1138     }
1139 
1140     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1141     case SND_SOC_DAIFMT_DSP_A:
1142     case SND_SOC_DAIFMT_DSP_B:
1143         /* frame inversion not valid for DSP modes */
1144         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1145         case SND_SOC_DAIFMT_NB_NF:
1146             break;
1147         case SND_SOC_DAIFMT_IB_NF:
1148             aif1 |= WM8993_AIF_BCLK_INV;
1149             break;
1150         default:
1151             return -EINVAL;
1152         }
1153         break;
1154 
1155     case SND_SOC_DAIFMT_I2S:
1156     case SND_SOC_DAIFMT_RIGHT_J:
1157     case SND_SOC_DAIFMT_LEFT_J:
1158         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1159         case SND_SOC_DAIFMT_NB_NF:
1160             break;
1161         case SND_SOC_DAIFMT_IB_IF:
1162             aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1163             break;
1164         case SND_SOC_DAIFMT_IB_NF:
1165             aif1 |= WM8993_AIF_BCLK_INV;
1166             break;
1167         case SND_SOC_DAIFMT_NB_IF:
1168             aif1 |= WM8993_AIF_LRCLK_INV;
1169             break;
1170         default:
1171             return -EINVAL;
1172         }
1173         break;
1174     default:
1175         return -EINVAL;
1176     }
1177 
1178     snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
1179     snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
1180 
1181     return 0;
1182 }
1183 
1184 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1185                 struct snd_pcm_hw_params *params,
1186                 struct snd_soc_dai *dai)
1187 {
1188     struct snd_soc_component *component = dai->component;
1189     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1190     int ret, i, best, best_val, cur_val;
1191     unsigned int clocking1, clocking3, aif1, aif4;
1192 
1193     clocking1 = snd_soc_component_read(component, WM8993_CLOCKING_1);
1194     clocking1 &= ~WM8993_BCLK_DIV_MASK;
1195 
1196     clocking3 = snd_soc_component_read(component, WM8993_CLOCKING_3);
1197     clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1198 
1199     aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
1200     aif1 &= ~WM8993_AIF_WL_MASK;
1201 
1202     aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
1203     aif4 &= ~WM8993_LRCLK_RATE_MASK;
1204 
1205     /* What BCLK do we need? */
1206     wm8993->fs = params_rate(params);
1207     wm8993->bclk = 2 * wm8993->fs;
1208     if (wm8993->tdm_slots) {
1209         dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1210             wm8993->tdm_slots, wm8993->tdm_width);
1211         wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1212     } else {
1213         switch (params_width(params)) {
1214         case 16:
1215             wm8993->bclk *= 16;
1216             break;
1217         case 20:
1218             wm8993->bclk *= 20;
1219             aif1 |= 0x8;
1220             break;
1221         case 24:
1222             wm8993->bclk *= 24;
1223             aif1 |= 0x10;
1224             break;
1225         case 32:
1226             wm8993->bclk *= 32;
1227             aif1 |= 0x18;
1228             break;
1229         default:
1230             return -EINVAL;
1231         }
1232     }
1233 
1234     dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1235 
1236     ret = configure_clock(component);
1237     if (ret != 0)
1238         return ret;
1239 
1240     /* Select nearest CLK_SYS_RATE */
1241     best = 0;
1242     best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1243                - wm8993->fs);
1244     for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1245         cur_val = abs((wm8993->sysclk_rate /
1246                    clk_sys_rates[i].ratio) - wm8993->fs);
1247         if (cur_val < best_val) {
1248             best = i;
1249             best_val = cur_val;
1250         }
1251     }
1252     dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1253         clk_sys_rates[best].ratio);
1254     clocking3 |= (clk_sys_rates[best].clk_sys_rate
1255               << WM8993_CLK_SYS_RATE_SHIFT);
1256 
1257     /* SAMPLE_RATE */
1258     best = 0;
1259     best_val = abs(wm8993->fs - sample_rates[0].rate);
1260     for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1261         /* Closest match */
1262         cur_val = abs(wm8993->fs - sample_rates[i].rate);
1263         if (cur_val < best_val) {
1264             best = i;
1265             best_val = cur_val;
1266         }
1267     }
1268     dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1269         sample_rates[best].rate);
1270     clocking3 |= (sample_rates[best].sample_rate
1271               << WM8993_SAMPLE_RATE_SHIFT);
1272 
1273     /* BCLK_DIV */
1274     best = 0;
1275     best_val = INT_MAX;
1276     for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1277         cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1278             - wm8993->bclk;
1279         if (cur_val < 0) /* Table is sorted */
1280             break;
1281         if (cur_val < best_val) {
1282             best = i;
1283             best_val = cur_val;
1284         }
1285     }
1286     wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1287     dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1288         bclk_divs[best].div, wm8993->bclk);
1289     clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1290 
1291     /* LRCLK is a simple fraction of BCLK */
1292     dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1293     aif4 |= wm8993->bclk / wm8993->fs;
1294 
1295     snd_soc_component_write(component, WM8993_CLOCKING_1, clocking1);
1296     snd_soc_component_write(component, WM8993_CLOCKING_3, clocking3);
1297     snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
1298     snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
1299 
1300     /* ReTune Mobile? */
1301     if (wm8993->pdata.num_retune_configs) {
1302         u16 eq1 = snd_soc_component_read(component, WM8993_EQ1);
1303         struct wm8993_retune_mobile_setting *s;
1304 
1305         best = 0;
1306         best_val = abs(wm8993->pdata.retune_configs[0].rate
1307                    - wm8993->fs);
1308         for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1309             cur_val = abs(wm8993->pdata.retune_configs[i].rate
1310                       - wm8993->fs);
1311             if (cur_val < best_val) {
1312                 best_val = cur_val;
1313                 best = i;
1314             }
1315         }
1316         s = &wm8993->pdata.retune_configs[best];
1317 
1318         dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
1319             s->name, s->rate);
1320 
1321         /* Disable EQ while we reconfigure */
1322         snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, 0);
1323 
1324         for (i = 1; i < ARRAY_SIZE(s->config); i++)
1325             snd_soc_component_write(component, WM8993_EQ1 + i, s->config[i]);
1326 
1327         snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1328     }
1329 
1330     return 0;
1331 }
1332 
1333 static int wm8993_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1334 {
1335     struct snd_soc_component *component = codec_dai->component;
1336     unsigned int reg;
1337 
1338     reg = snd_soc_component_read(component, WM8993_DAC_CTRL);
1339 
1340     if (mute)
1341         reg |= WM8993_DAC_MUTE;
1342     else
1343         reg &= ~WM8993_DAC_MUTE;
1344 
1345     snd_soc_component_write(component, WM8993_DAC_CTRL, reg);
1346 
1347     return 0;
1348 }
1349 
1350 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1351                    unsigned int rx_mask, int slots, int slot_width)
1352 {
1353     struct snd_soc_component *component = dai->component;
1354     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1355     int aif1 = 0;
1356     int aif2 = 0;
1357 
1358     /* Don't need to validate anything if we're turning off TDM */
1359     if (slots == 0) {
1360         wm8993->tdm_slots = 0;
1361         goto out;
1362     }
1363 
1364     /* Note that we allow configurations we can't handle ourselves - 
1365      * for example, we can generate clocks for slots 2 and up even if
1366      * we can't use those slots ourselves.
1367      */
1368     aif1 |= WM8993_AIFADC_TDM;
1369     aif2 |= WM8993_AIFDAC_TDM;
1370 
1371     switch (rx_mask) {
1372     case 3:
1373         break;
1374     case 0xc:
1375         aif1 |= WM8993_AIFADC_TDM_CHAN;
1376         break;
1377     default:
1378         return -EINVAL;
1379     }
1380 
1381 
1382     switch (tx_mask) {
1383     case 3:
1384         break;
1385     case 0xc:
1386         aif2 |= WM8993_AIFDAC_TDM_CHAN;
1387         break;
1388     default:
1389         return -EINVAL;
1390     }
1391 
1392 out:
1393     wm8993->tdm_width = slot_width;
1394     wm8993->tdm_slots = slots / 2;
1395 
1396     snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_1,
1397                 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1398     snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_2,
1399                 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1400 
1401     return 0;
1402 }
1403 
1404 static irqreturn_t wm8993_irq(int irq, void *data)
1405 {
1406     struct wm8993_priv *wm8993 = data;
1407     int mask, val, ret;
1408 
1409     ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
1410     if (ret != 0) {
1411         dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
1412             ret);
1413         return IRQ_NONE;
1414     }
1415 
1416     ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
1417     if (ret != 0) {
1418         dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
1419             ret);
1420         return IRQ_NONE;
1421     }
1422 
1423     /* The IRQ pin status is visible in the register too */
1424     val &= ~(mask | WM8993_IRQ);
1425     if (!val)
1426         return IRQ_NONE;
1427 
1428     if (val & WM8993_TEMPOK_EINT)
1429         dev_crit(wm8993->dev, "Thermal warning\n");
1430 
1431     if (val & WM8993_FLL_LOCK_EINT) {
1432         dev_dbg(wm8993->dev, "FLL locked\n");
1433         complete(&wm8993->fll_lock);
1434     }
1435 
1436     ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
1437     if (ret != 0)
1438         dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
1439 
1440     return IRQ_HANDLED;
1441 }
1442 
1443 static const struct snd_soc_dai_ops wm8993_ops = {
1444     .set_sysclk = wm8993_set_sysclk,
1445     .set_fmt = wm8993_set_dai_fmt,
1446     .hw_params = wm8993_hw_params,
1447     .mute_stream = wm8993_mute,
1448     .set_pll = wm8993_set_fll,
1449     .set_tdm_slot = wm8993_set_tdm_slot,
1450     .no_capture_mute = 1,
1451 };
1452 
1453 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1454 
1455 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1456             SNDRV_PCM_FMTBIT_S20_3LE |\
1457             SNDRV_PCM_FMTBIT_S24_LE |\
1458             SNDRV_PCM_FMTBIT_S32_LE)
1459 
1460 static struct snd_soc_dai_driver wm8993_dai = {
1461     .name = "wm8993-hifi",
1462     .playback = {
1463         .stream_name = "Playback",
1464         .channels_min = 1,
1465         .channels_max = 2,
1466         .rates = WM8993_RATES,
1467         .formats = WM8993_FORMATS,
1468         .sig_bits = 24,
1469     },
1470     .capture = {
1471          .stream_name = "Capture",
1472          .channels_min = 1,
1473          .channels_max = 2,
1474          .rates = WM8993_RATES,
1475          .formats = WM8993_FORMATS,
1476          .sig_bits = 24,
1477      },
1478     .ops = &wm8993_ops,
1479     .symmetric_rate = 1,
1480 };
1481 
1482 static int wm8993_probe(struct snd_soc_component *component)
1483 {
1484     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1485     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1486 
1487     wm8993->hubs_data.hp_startup_mode = 1;
1488     wm8993->hubs_data.dcs_codes_l = -2;
1489     wm8993->hubs_data.dcs_codes_r = -2;
1490     wm8993->hubs_data.series_startup = 1;
1491 
1492     /* Latch volume update bits and default ZC on */
1493     snd_soc_component_update_bits(component, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1494                 WM8993_DAC_VU, WM8993_DAC_VU);
1495     snd_soc_component_update_bits(component, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1496                 WM8993_ADC_VU, WM8993_ADC_VU);
1497 
1498     /* Manualy manage the HPOUT sequencing for independent stereo
1499      * control. */
1500     snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
1501                 WM8993_HPOUT1_AUTO_PU, 0);
1502 
1503     /* Use automatic clock configuration */
1504     snd_soc_component_update_bits(component, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1505 
1506     wm_hubs_handle_analogue_pdata(component, wm8993->pdata.lineout1_diff,
1507                       wm8993->pdata.lineout2_diff,
1508                       wm8993->pdata.lineout1fb,
1509                       wm8993->pdata.lineout2fb,
1510                       wm8993->pdata.jd_scthr,
1511                       wm8993->pdata.jd_thr,
1512                       wm8993->pdata.micbias1_delay,
1513                       wm8993->pdata.micbias2_delay,
1514                       wm8993->pdata.micbias1_lvl,
1515                       wm8993->pdata.micbias2_lvl);
1516 
1517     snd_soc_add_component_controls(component, wm8993_snd_controls,
1518                  ARRAY_SIZE(wm8993_snd_controls));
1519     if (wm8993->pdata.num_retune_configs != 0) {
1520         dev_dbg(component->dev, "Using ReTune Mobile\n");
1521     } else {
1522         dev_dbg(component->dev, "No ReTune Mobile, using normal EQ\n");
1523         snd_soc_add_component_controls(component, wm8993_eq_controls,
1524                      ARRAY_SIZE(wm8993_eq_controls));
1525     }
1526 
1527     snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1528                   ARRAY_SIZE(wm8993_dapm_widgets));
1529     wm_hubs_add_analogue_controls(component);
1530 
1531     snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1532     wm_hubs_add_analogue_routes(component, wm8993->pdata.lineout1_diff,
1533                     wm8993->pdata.lineout2_diff);
1534 
1535     /* If the line outputs are differential then we aren't presenting
1536      * VMID as an output and can disable it.
1537      */
1538     if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
1539         dapm->idle_bias_off = 1;
1540 
1541     return 0;
1542 
1543 }
1544 
1545 #ifdef CONFIG_PM
1546 static int wm8993_suspend(struct snd_soc_component *component)
1547 {
1548     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1549     int fll_fout = wm8993->fll_fout;
1550     int fll_fref  = wm8993->fll_fref;
1551     int ret;
1552 
1553     /* Stop the FLL in an orderly fashion */
1554     ret = _wm8993_set_fll(component, 0, 0, 0, 0);
1555     if (ret != 0) {
1556         dev_err(component->dev, "Failed to stop FLL\n");
1557         return ret;
1558     }
1559 
1560     wm8993->fll_fout = fll_fout;
1561     wm8993->fll_fref = fll_fref;
1562 
1563     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1564 
1565     return 0;
1566 }
1567 
1568 static int wm8993_resume(struct snd_soc_component *component)
1569 {
1570     struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1571     int ret;
1572 
1573     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1574 
1575     /* Restart the FLL? */
1576     if (wm8993->fll_fout) {
1577         int fll_fout = wm8993->fll_fout;
1578         int fll_fref  = wm8993->fll_fref;
1579 
1580         wm8993->fll_fref = 0;
1581         wm8993->fll_fout = 0;
1582 
1583         ret = _wm8993_set_fll(component, 0, wm8993->fll_src,
1584                      fll_fref, fll_fout);
1585         if (ret != 0)
1586             dev_err(component->dev, "Failed to restart FLL\n");
1587     }
1588 
1589     return 0;
1590 }
1591 #else
1592 #define wm8993_suspend NULL
1593 #define wm8993_resume NULL
1594 #endif
1595 
1596 /* Tune DC servo configuration */
1597 static const struct reg_sequence wm8993_regmap_patch[] = {
1598     { 0x44, 3 },
1599     { 0x56, 3 },
1600     { 0x44, 0 },
1601 };
1602 
1603 static const struct regmap_config wm8993_regmap = {
1604     .reg_bits = 8,
1605     .val_bits = 16,
1606 
1607     .max_register = WM8993_MAX_REGISTER,
1608     .volatile_reg = wm8993_volatile,
1609     .readable_reg = wm8993_readable,
1610 
1611     .cache_type = REGCACHE_RBTREE,
1612     .reg_defaults = wm8993_reg_defaults,
1613     .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
1614 };
1615 
1616 static const struct snd_soc_component_driver soc_component_dev_wm8993 = {
1617     .probe          = wm8993_probe,
1618     .suspend        = wm8993_suspend,
1619     .resume         = wm8993_resume,
1620     .set_bias_level     = wm8993_set_bias_level,
1621     .idle_bias_on       = 1,
1622     .use_pmdown_time    = 1,
1623     .endianness     = 1,
1624 };
1625 
1626 static int wm8993_i2c_probe(struct i2c_client *i2c)
1627 {
1628     struct wm8993_priv *wm8993;
1629     unsigned int reg;
1630     int ret, i;
1631 
1632     wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1633                   GFP_KERNEL);
1634     if (wm8993 == NULL)
1635         return -ENOMEM;
1636 
1637     wm8993->dev = &i2c->dev;
1638     init_completion(&wm8993->fll_lock);
1639 
1640     wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap);
1641     if (IS_ERR(wm8993->regmap)) {
1642         ret = PTR_ERR(wm8993->regmap);
1643         dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1644         return ret;
1645     }
1646 
1647     i2c_set_clientdata(i2c, wm8993);
1648 
1649     for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1650         wm8993->supplies[i].supply = wm8993_supply_names[i];
1651 
1652     ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
1653                  wm8993->supplies);
1654     if (ret != 0) {
1655         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1656         return ret;
1657     }
1658 
1659     ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1660                     wm8993->supplies);
1661     if (ret != 0) {
1662         dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1663         return ret;
1664     }
1665 
1666     ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, &reg);
1667     if (ret != 0) {
1668         dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1669         goto err_enable;
1670     }
1671 
1672     if (reg != 0x8993) {
1673         dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
1674         ret = -EINVAL;
1675         goto err_enable;
1676     }
1677 
1678     ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
1679     if (ret != 0)
1680         goto err_enable;
1681 
1682     ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
1683                     ARRAY_SIZE(wm8993_regmap_patch));
1684     if (ret != 0)
1685         dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
1686              ret);
1687 
1688     if (i2c->irq) {
1689         /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
1690         ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
1691                      WM8993_GPIO1_PD |
1692                      WM8993_GPIO1_SEL_MASK, 7);
1693         if (ret != 0)
1694             goto err_enable;
1695 
1696         ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
1697                        IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1698                        "wm8993", wm8993);
1699         if (ret != 0)
1700             goto err_enable;
1701 
1702     }
1703 
1704     regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1705 
1706     regcache_cache_only(wm8993->regmap, true);
1707 
1708     ret = devm_snd_soc_register_component(&i2c->dev,
1709             &soc_component_dev_wm8993, &wm8993_dai, 1);
1710     if (ret != 0) {
1711         dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1712         goto err_irq;
1713     }
1714 
1715     return 0;
1716 
1717 err_irq:
1718     if (i2c->irq)
1719         free_irq(i2c->irq, wm8993);
1720 err_enable:
1721     regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1722     return ret;
1723 }
1724 
1725 static int wm8993_i2c_remove(struct i2c_client *i2c)
1726 {
1727     struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
1728 
1729     if (i2c->irq)
1730         free_irq(i2c->irq, wm8993);
1731     regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1732 
1733     return 0;
1734 }
1735 
1736 static const struct i2c_device_id wm8993_i2c_id[] = {
1737     { "wm8993", 0 },
1738     { }
1739 };
1740 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1741 
1742 static struct i2c_driver wm8993_i2c_driver = {
1743     .driver = {
1744         .name = "wm8993",
1745     },
1746     .probe_new = wm8993_i2c_probe,
1747     .remove =   wm8993_i2c_remove,
1748     .id_table = wm8993_i2c_id,
1749 };
1750 
1751 module_i2c_driver(wm8993_i2c_driver);
1752 
1753 MODULE_DESCRIPTION("ASoC WM8993 driver");
1754 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1755 MODULE_LICENSE("GPL");
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