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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * wm8990.c  --  WM8990 ALSA Soc Audio driver
0004  *
0005  * Copyright 2008 Wolfson Microelectronics PLC.
0006  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/moduleparam.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/i2c.h>
0016 #include <linux/regmap.h>
0017 #include <linux/slab.h>
0018 #include <sound/core.h>
0019 #include <sound/pcm.h>
0020 #include <sound/pcm_params.h>
0021 #include <sound/soc.h>
0022 #include <sound/initval.h>
0023 #include <sound/tlv.h>
0024 #include <asm/div64.h>
0025 
0026 #include "wm8990.h"
0027 
0028 /* codec private data */
0029 struct wm8990_priv {
0030     struct regmap *regmap;
0031     unsigned int sysclk;
0032     unsigned int pcmclk;
0033 };
0034 
0035 #define wm8990_reset(c) snd_soc_component_write(c, WM8990_RESET, 0)
0036 
0037 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
0038 
0039 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
0040 
0041 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
0042 
0043 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
0044 
0045 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
0046 
0047 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
0048 
0049 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
0050     struct snd_ctl_elem_value *ucontrol)
0051 {
0052     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0053     struct soc_mixer_control *mc =
0054         (struct soc_mixer_control *)kcontrol->private_value;
0055     int reg = mc->reg;
0056     int ret;
0057     u16 val;
0058 
0059     ret = snd_soc_put_volsw(kcontrol, ucontrol);
0060     if (ret < 0)
0061         return ret;
0062 
0063     /* now hit the volume update bits (always bit 8) */
0064     val = snd_soc_component_read(component, reg);
0065     return snd_soc_component_write(component, reg, val | 0x0100);
0066 }
0067 
0068 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
0069     tlv_array) \
0070     SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
0071         snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
0072 
0073 
0074 static const char *wm8990_digital_sidetone[] =
0075     {"None", "Left ADC", "Right ADC", "Reserved"};
0076 
0077 static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
0078                 WM8990_DIGITAL_SIDE_TONE,
0079                 WM8990_ADC_TO_DACL_SHIFT,
0080                 wm8990_digital_sidetone);
0081 
0082 static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
0083                 WM8990_DIGITAL_SIDE_TONE,
0084                 WM8990_ADC_TO_DACR_SHIFT,
0085                 wm8990_digital_sidetone);
0086 
0087 static const char *wm8990_adcmode[] =
0088     {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
0089 
0090 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
0091                 WM8990_ADC_CTRL,
0092                 WM8990_ADC_HPF_CUT_SHIFT,
0093                 wm8990_adcmode);
0094 
0095 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
0096 /* INMIXL */
0097 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
0098 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
0099 /* INMIXR */
0100 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
0101 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
0102 
0103 /* LOMIX */
0104 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
0105     WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
0106 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
0107     WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
0108 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
0109     WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
0110 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
0111     WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
0112 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
0113     WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
0114 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
0115     WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
0116 
0117 /* ROMIX */
0118 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
0119     WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
0120 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
0121     WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
0122 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
0123     WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
0124 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
0125     WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
0126 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
0127     WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
0128 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
0129     WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
0130 
0131 /* LOUT */
0132 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
0133     WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
0134 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
0135 
0136 /* ROUT */
0137 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
0138     WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
0139 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
0140 
0141 /* LOPGA */
0142 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
0143     WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
0144 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
0145     WM8990_LOPGAZC_BIT, 1, 0),
0146 
0147 /* ROPGA */
0148 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
0149     WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
0150 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
0151     WM8990_ROPGAZC_BIT, 1, 0),
0152 
0153 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
0154     WM8990_LONMUTE_BIT, 1, 0),
0155 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
0156     WM8990_LOPMUTE_BIT, 1, 0),
0157 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
0158     WM8990_LOATTN_BIT, 1, 0),
0159 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
0160     WM8990_RONMUTE_BIT, 1, 0),
0161 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
0162     WM8990_ROPMUTE_BIT, 1, 0),
0163 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
0164     WM8990_ROATTN_BIT, 1, 0),
0165 
0166 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
0167     WM8990_OUT3MUTE_BIT, 1, 0),
0168 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
0169     WM8990_OUT3ATTN_BIT, 1, 0),
0170 
0171 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
0172     WM8990_OUT4MUTE_BIT, 1, 0),
0173 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
0174     WM8990_OUT4ATTN_BIT, 1, 0),
0175 
0176 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
0177     WM8990_CDMODE_BIT, 1, 0),
0178 
0179 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
0180     WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
0181 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
0182     WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
0183 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
0184     WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
0185 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
0186     WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
0187 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
0188     WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
0189 
0190 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
0191     WM8990_LEFT_DAC_DIGITAL_VOLUME,
0192     WM8990_DACL_VOL_SHIFT,
0193     WM8990_DACL_VOL_MASK,
0194     0,
0195     out_dac_tlv),
0196 
0197 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
0198     WM8990_RIGHT_DAC_DIGITAL_VOLUME,
0199     WM8990_DACR_VOL_SHIFT,
0200     WM8990_DACR_VOL_MASK,
0201     0,
0202     out_dac_tlv),
0203 
0204 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
0205 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
0206 
0207 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
0208     WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
0209     out_sidetone_tlv),
0210 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
0211     WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
0212     out_sidetone_tlv),
0213 
0214 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
0215     WM8990_ADC_HPF_ENA_BIT, 1, 0),
0216 
0217 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
0218 
0219 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
0220     WM8990_LEFT_ADC_DIGITAL_VOLUME,
0221     WM8990_ADCL_VOL_SHIFT,
0222     WM8990_ADCL_VOL_MASK,
0223     0,
0224     in_adc_tlv),
0225 
0226 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
0227     WM8990_RIGHT_ADC_DIGITAL_VOLUME,
0228     WM8990_ADCR_VOL_SHIFT,
0229     WM8990_ADCR_VOL_MASK,
0230     0,
0231     in_adc_tlv),
0232 
0233 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
0234     WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
0235     WM8990_LIN12VOL_SHIFT,
0236     WM8990_LIN12VOL_MASK,
0237     0,
0238     in_pga_tlv),
0239 
0240 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
0241     WM8990_LI12ZC_BIT, 1, 0),
0242 
0243 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
0244     WM8990_LI12MUTE_BIT, 1, 0),
0245 
0246 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
0247     WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
0248     WM8990_LIN34VOL_SHIFT,
0249     WM8990_LIN34VOL_MASK,
0250     0,
0251     in_pga_tlv),
0252 
0253 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
0254     WM8990_LI34ZC_BIT, 1, 0),
0255 
0256 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
0257     WM8990_LI34MUTE_BIT, 1, 0),
0258 
0259 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
0260     WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
0261     WM8990_RIN12VOL_SHIFT,
0262     WM8990_RIN12VOL_MASK,
0263     0,
0264     in_pga_tlv),
0265 
0266 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
0267     WM8990_RI12ZC_BIT, 1, 0),
0268 
0269 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
0270     WM8990_RI12MUTE_BIT, 1, 0),
0271 
0272 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
0273     WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
0274     WM8990_RIN34VOL_SHIFT,
0275     WM8990_RIN34VOL_MASK,
0276     0,
0277     in_pga_tlv),
0278 
0279 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
0280     WM8990_RI34ZC_BIT, 1, 0),
0281 
0282 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
0283     WM8990_RI34MUTE_BIT, 1, 0),
0284 
0285 };
0286 
0287 /*
0288  * _DAPM_ Controls
0289  */
0290 
0291 static int outmixer_event(struct snd_soc_dapm_widget *w,
0292     struct snd_kcontrol *kcontrol, int event)
0293 {
0294     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0295     u32 reg_shift = kcontrol->private_value & 0xfff;
0296     int ret = 0;
0297     u16 reg;
0298 
0299     switch (reg_shift) {
0300     case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
0301         reg = snd_soc_component_read(component, WM8990_OUTPUT_MIXER1);
0302         if (reg & WM8990_LDLO) {
0303             printk(KERN_WARNING
0304             "Cannot set as Output Mixer 1 LDLO Set\n");
0305             ret = -1;
0306         }
0307         break;
0308     case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
0309         reg = snd_soc_component_read(component, WM8990_OUTPUT_MIXER2);
0310         if (reg & WM8990_RDRO) {
0311             printk(KERN_WARNING
0312             "Cannot set as Output Mixer 2 RDRO Set\n");
0313             ret = -1;
0314         }
0315         break;
0316     case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
0317         reg = snd_soc_component_read(component, WM8990_SPEAKER_MIXER);
0318         if (reg & WM8990_LDSPK) {
0319             printk(KERN_WARNING
0320             "Cannot set as Speaker Mixer LDSPK Set\n");
0321             ret = -1;
0322         }
0323         break;
0324     case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
0325         reg = snd_soc_component_read(component, WM8990_SPEAKER_MIXER);
0326         if (reg & WM8990_RDSPK) {
0327             printk(KERN_WARNING
0328             "Cannot set as Speaker Mixer RDSPK Set\n");
0329             ret = -1;
0330         }
0331         break;
0332     }
0333 
0334     return ret;
0335 }
0336 
0337 /* INMIX dB values */
0338 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
0339 
0340 /* Left In PGA Connections */
0341 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
0342 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
0343 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
0344 };
0345 
0346 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
0347 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
0348 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
0349 };
0350 
0351 /* Right In PGA Connections */
0352 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
0353 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
0354 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
0355 };
0356 
0357 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
0358 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
0359 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
0360 };
0361 
0362 /* INMIXL */
0363 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
0364 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
0365     WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
0366 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
0367     7, 0, in_mix_tlv),
0368 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
0369     1, 0),
0370 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
0371     1, 0),
0372 };
0373 
0374 /* INMIXR */
0375 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
0376 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
0377     WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
0378 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
0379     7, 0, in_mix_tlv),
0380 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
0381     1, 0),
0382 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
0383     1, 0),
0384 };
0385 
0386 /* AINLMUX */
0387 static const char *wm8990_ainlmux[] =
0388     {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
0389 
0390 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
0391                 WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
0392                 wm8990_ainlmux);
0393 
0394 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
0395 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
0396 
0397 /* DIFFINL */
0398 
0399 /* AINRMUX */
0400 static const char *wm8990_ainrmux[] =
0401     {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
0402 
0403 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
0404                 WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
0405                 wm8990_ainrmux);
0406 
0407 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
0408 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
0409 
0410 /* LOMIX */
0411 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
0412 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
0413     WM8990_LRBLO_BIT, 1, 0),
0414 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
0415     WM8990_LLBLO_BIT, 1, 0),
0416 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
0417     WM8990_LRI3LO_BIT, 1, 0),
0418 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
0419     WM8990_LLI3LO_BIT, 1, 0),
0420 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
0421     WM8990_LR12LO_BIT, 1, 0),
0422 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
0423     WM8990_LL12LO_BIT, 1, 0),
0424 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
0425     WM8990_LDLO_BIT, 1, 0),
0426 };
0427 
0428 /* ROMIX */
0429 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
0430 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
0431     WM8990_RLBRO_BIT, 1, 0),
0432 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
0433     WM8990_RRBRO_BIT, 1, 0),
0434 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
0435     WM8990_RLI3RO_BIT, 1, 0),
0436 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
0437     WM8990_RRI3RO_BIT, 1, 0),
0438 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
0439     WM8990_RL12RO_BIT, 1, 0),
0440 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
0441     WM8990_RR12RO_BIT, 1, 0),
0442 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
0443     WM8990_RDRO_BIT, 1, 0),
0444 };
0445 
0446 /* LONMIX */
0447 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
0448 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
0449     WM8990_LLOPGALON_BIT, 1, 0),
0450 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
0451     WM8990_LROPGALON_BIT, 1, 0),
0452 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
0453     WM8990_LOPLON_BIT, 1, 0),
0454 };
0455 
0456 /* LOPMIX */
0457 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
0458 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
0459     WM8990_LR12LOP_BIT, 1, 0),
0460 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
0461     WM8990_LL12LOP_BIT, 1, 0),
0462 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
0463     WM8990_LLOPGALOP_BIT, 1, 0),
0464 };
0465 
0466 /* RONMIX */
0467 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
0468 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
0469     WM8990_RROPGARON_BIT, 1, 0),
0470 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
0471     WM8990_RLOPGARON_BIT, 1, 0),
0472 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
0473     WM8990_ROPRON_BIT, 1, 0),
0474 };
0475 
0476 /* ROPMIX */
0477 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
0478 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
0479     WM8990_RL12ROP_BIT, 1, 0),
0480 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
0481     WM8990_RR12ROP_BIT, 1, 0),
0482 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
0483     WM8990_RROPGAROP_BIT, 1, 0),
0484 };
0485 
0486 /* OUT3MIX */
0487 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
0488 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
0489     WM8990_LI4O3_BIT, 1, 0),
0490 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
0491     WM8990_LPGAO3_BIT, 1, 0),
0492 };
0493 
0494 /* OUT4MIX */
0495 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
0496 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
0497     WM8990_RPGAO4_BIT, 1, 0),
0498 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
0499     WM8990_RI4O4_BIT, 1, 0),
0500 };
0501 
0502 /* SPKMIX */
0503 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
0504 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
0505     WM8990_LI2SPK_BIT, 1, 0),
0506 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
0507     WM8990_LB2SPK_BIT, 1, 0),
0508 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
0509     WM8990_LOPGASPK_BIT, 1, 0),
0510 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
0511     WM8990_LDSPK_BIT, 1, 0),
0512 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
0513     WM8990_RDSPK_BIT, 1, 0),
0514 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
0515     WM8990_ROPGASPK_BIT, 1, 0),
0516 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
0517     WM8990_RL12ROP_BIT, 1, 0),
0518 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
0519     WM8990_RI2SPK_BIT, 1, 0),
0520 };
0521 
0522 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
0523 /* Input Side */
0524 /* Input Lines */
0525 SND_SOC_DAPM_INPUT("LIN1"),
0526 SND_SOC_DAPM_INPUT("LIN2"),
0527 SND_SOC_DAPM_INPUT("LIN3"),
0528 SND_SOC_DAPM_INPUT("LIN4/RXN"),
0529 SND_SOC_DAPM_INPUT("RIN3"),
0530 SND_SOC_DAPM_INPUT("RIN4/RXP"),
0531 SND_SOC_DAPM_INPUT("RIN1"),
0532 SND_SOC_DAPM_INPUT("RIN2"),
0533 SND_SOC_DAPM_INPUT("Internal ADC Source"),
0534 
0535 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
0536             NULL, 0),
0537 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
0538             NULL, 0),
0539 
0540 /* DACs */
0541 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
0542     WM8990_ADCL_ENA_BIT, 0),
0543 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
0544     WM8990_ADCR_ENA_BIT, 0),
0545 
0546 /* Input PGAs */
0547 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
0548     0, &wm8990_dapm_lin12_pga_controls[0],
0549     ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
0550 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
0551     0, &wm8990_dapm_lin34_pga_controls[0],
0552     ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
0553 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
0554     0, &wm8990_dapm_rin12_pga_controls[0],
0555     ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
0556 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
0557     0, &wm8990_dapm_rin34_pga_controls[0],
0558     ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
0559 
0560 /* INMIXL */
0561 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
0562     &wm8990_dapm_inmixl_controls[0],
0563     ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
0564 
0565 /* AINLMUX */
0566 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
0567 
0568 /* INMIXR */
0569 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
0570     &wm8990_dapm_inmixr_controls[0],
0571     ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
0572 
0573 /* AINRMUX */
0574 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
0575 
0576 /* Output Side */
0577 /* DACs */
0578 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
0579     WM8990_DACL_ENA_BIT, 0),
0580 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
0581     WM8990_DACR_ENA_BIT, 0),
0582 
0583 /* LOMIX */
0584 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
0585     0, &wm8990_dapm_lomix_controls[0],
0586     ARRAY_SIZE(wm8990_dapm_lomix_controls),
0587     outmixer_event, SND_SOC_DAPM_PRE_REG),
0588 
0589 /* LONMIX */
0590 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
0591     &wm8990_dapm_lonmix_controls[0],
0592     ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
0593 
0594 /* LOPMIX */
0595 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
0596     &wm8990_dapm_lopmix_controls[0],
0597     ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
0598 
0599 /* OUT3MIX */
0600 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
0601     &wm8990_dapm_out3mix_controls[0],
0602     ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
0603 
0604 /* SPKMIX */
0605 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
0606     &wm8990_dapm_spkmix_controls[0],
0607     ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
0608     SND_SOC_DAPM_PRE_REG),
0609 
0610 /* OUT4MIX */
0611 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
0612     &wm8990_dapm_out4mix_controls[0],
0613     ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
0614 
0615 /* ROPMIX */
0616 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
0617     &wm8990_dapm_ropmix_controls[0],
0618     ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
0619 
0620 /* RONMIX */
0621 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
0622     &wm8990_dapm_ronmix_controls[0],
0623     ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
0624 
0625 /* ROMIX */
0626 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
0627     0, &wm8990_dapm_romix_controls[0],
0628     ARRAY_SIZE(wm8990_dapm_romix_controls),
0629     outmixer_event, SND_SOC_DAPM_PRE_REG),
0630 
0631 /* LOUT PGA */
0632 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
0633     NULL, 0),
0634 
0635 /* ROUT PGA */
0636 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
0637     NULL, 0),
0638 
0639 /* LOPGA */
0640 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
0641     NULL, 0),
0642 
0643 /* ROPGA */
0644 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
0645     NULL, 0),
0646 
0647 /* MICBIAS */
0648 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
0649             WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
0650 
0651 SND_SOC_DAPM_OUTPUT("LON"),
0652 SND_SOC_DAPM_OUTPUT("LOP"),
0653 SND_SOC_DAPM_OUTPUT("OUT3"),
0654 SND_SOC_DAPM_OUTPUT("LOUT"),
0655 SND_SOC_DAPM_OUTPUT("SPKN"),
0656 SND_SOC_DAPM_OUTPUT("SPKP"),
0657 SND_SOC_DAPM_OUTPUT("ROUT"),
0658 SND_SOC_DAPM_OUTPUT("OUT4"),
0659 SND_SOC_DAPM_OUTPUT("ROP"),
0660 SND_SOC_DAPM_OUTPUT("RON"),
0661 
0662 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
0663 };
0664 
0665 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
0666     /* Make DACs turn on when playing even if not mixed into any outputs */
0667     {"Internal DAC Sink", NULL, "Left DAC"},
0668     {"Internal DAC Sink", NULL, "Right DAC"},
0669 
0670     /* Make ADCs turn on when recording even if not mixed from any inputs */
0671     {"Left ADC", NULL, "Internal ADC Source"},
0672     {"Right ADC", NULL, "Internal ADC Source"},
0673 
0674     {"AINLMUX", NULL, "INL"},
0675     {"INMIXL", NULL, "INL"},
0676     {"AINRMUX", NULL, "INR"},
0677     {"INMIXR", NULL, "INR"},
0678 
0679     /* Input Side */
0680     /* LIN12 PGA */
0681     {"LIN12 PGA", "LIN1 Switch", "LIN1"},
0682     {"LIN12 PGA", "LIN2 Switch", "LIN2"},
0683     /* LIN34 PGA */
0684     {"LIN34 PGA", "LIN3 Switch", "LIN3"},
0685     {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
0686     /* INMIXL */
0687     {"INMIXL", "Record Left Volume", "LOMIX"},
0688     {"INMIXL", "LIN2 Volume", "LIN2"},
0689     {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
0690     {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
0691     /* AINLMUX */
0692     {"AINLMUX", "INMIXL Mix", "INMIXL"},
0693     {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
0694     {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
0695     {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
0696     {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
0697     /* ADC */
0698     {"Left ADC", NULL, "AINLMUX"},
0699 
0700     /* RIN12 PGA */
0701     {"RIN12 PGA", "RIN1 Switch", "RIN1"},
0702     {"RIN12 PGA", "RIN2 Switch", "RIN2"},
0703     /* RIN34 PGA */
0704     {"RIN34 PGA", "RIN3 Switch", "RIN3"},
0705     {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
0706     /* INMIXL */
0707     {"INMIXR", "Record Right Volume", "ROMIX"},
0708     {"INMIXR", "RIN2 Volume", "RIN2"},
0709     {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
0710     {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
0711     /* AINRMUX */
0712     {"AINRMUX", "INMIXR Mix", "INMIXR"},
0713     {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
0714     {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
0715     {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
0716     {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
0717     /* ADC */
0718     {"Right ADC", NULL, "AINRMUX"},
0719 
0720     /* LOMIX */
0721     {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
0722     {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
0723     {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
0724     {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
0725     {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
0726     {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
0727     {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
0728 
0729     /* ROMIX */
0730     {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
0731     {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
0732     {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
0733     {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
0734     {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
0735     {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
0736     {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
0737 
0738     /* SPKMIX */
0739     {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
0740     {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
0741     {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
0742     {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
0743     {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
0744     {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
0745     {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
0746     {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
0747 
0748     /* LONMIX */
0749     {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
0750     {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
0751     {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
0752 
0753     /* LOPMIX */
0754     {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
0755     {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
0756     {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
0757 
0758     /* OUT3MIX */
0759     {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
0760     {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
0761 
0762     /* OUT4MIX */
0763     {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
0764     {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
0765 
0766     /* RONMIX */
0767     {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
0768     {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
0769     {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
0770 
0771     /* ROPMIX */
0772     {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
0773     {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
0774     {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
0775 
0776     /* Out Mixer PGAs */
0777     {"LOPGA", NULL, "LOMIX"},
0778     {"ROPGA", NULL, "ROMIX"},
0779 
0780     {"LOUT PGA", NULL, "LOMIX"},
0781     {"ROUT PGA", NULL, "ROMIX"},
0782 
0783     /* Output Pins */
0784     {"LON", NULL, "LONMIX"},
0785     {"LOP", NULL, "LOPMIX"},
0786     {"OUT3", NULL, "OUT3MIX"},
0787     {"LOUT", NULL, "LOUT PGA"},
0788     {"SPKN", NULL, "SPKMIX"},
0789     {"ROUT", NULL, "ROUT PGA"},
0790     {"OUT4", NULL, "OUT4MIX"},
0791     {"ROP", NULL, "ROPMIX"},
0792     {"RON", NULL, "RONMIX"},
0793 };
0794 
0795 /* PLL divisors */
0796 struct _pll_div {
0797     u32 div2;
0798     u32 n;
0799     u32 k;
0800 };
0801 
0802 /* The size in bits of the pll divide multiplied by 10
0803  * to allow rounding later */
0804 #define FIXED_PLL_SIZE ((1 << 16) * 10)
0805 
0806 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
0807     unsigned int source)
0808 {
0809     u64 Kpart;
0810     unsigned int K, Ndiv, Nmod;
0811 
0812 
0813     Ndiv = target / source;
0814     if (Ndiv < 6) {
0815         source >>= 1;
0816         pll_div->div2 = 1;
0817         Ndiv = target / source;
0818     } else
0819         pll_div->div2 = 0;
0820 
0821     if ((Ndiv < 6) || (Ndiv > 12))
0822         printk(KERN_WARNING
0823         "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
0824 
0825     pll_div->n = Ndiv;
0826     Nmod = target % source;
0827     Kpart = FIXED_PLL_SIZE * (long long)Nmod;
0828 
0829     do_div(Kpart, source);
0830 
0831     K = Kpart & 0xFFFFFFFF;
0832 
0833     /* Check if we need to round */
0834     if ((K % 10) >= 5)
0835         K += 5;
0836 
0837     /* Move down to proper range now rounding is done */
0838     K /= 10;
0839 
0840     pll_div->k = K;
0841 }
0842 
0843 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
0844         int source, unsigned int freq_in, unsigned int freq_out)
0845 {
0846     struct snd_soc_component *component = codec_dai->component;
0847     struct _pll_div pll_div;
0848 
0849     if (freq_in && freq_out) {
0850         pll_factors(&pll_div, freq_out * 4, freq_in);
0851 
0852         /* Turn on PLL */
0853         snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
0854                     WM8990_PLL_ENA, WM8990_PLL_ENA);
0855 
0856         /* sysclk comes from PLL */
0857         snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
0858                     WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
0859 
0860         /* set up N , fractional mode and pre-divisor if necessary */
0861         snd_soc_component_write(component, WM8990_PLL1, pll_div.n | WM8990_SDM |
0862             (pll_div.div2?WM8990_PRESCALE:0));
0863         snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8));
0864         snd_soc_component_write(component, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
0865     } else {
0866         /* Turn off PLL */
0867         snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
0868                     WM8990_PLL_ENA, 0);
0869     }
0870     return 0;
0871 }
0872 
0873 /*
0874  * Clock after PLL and dividers
0875  */
0876 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0877         int clk_id, unsigned int freq, int dir)
0878 {
0879     struct snd_soc_component *component = codec_dai->component;
0880     struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
0881 
0882     wm8990->sysclk = freq;
0883     return 0;
0884 }
0885 
0886 /*
0887  * Set's ADC and Voice DAC format.
0888  */
0889 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
0890         unsigned int fmt)
0891 {
0892     struct snd_soc_component *component = codec_dai->component;
0893     u16 audio1, audio3;
0894 
0895     audio1 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_1);
0896     audio3 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_3);
0897 
0898     /* set master/slave audio interface */
0899     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0900     case SND_SOC_DAIFMT_CBS_CFS:
0901         audio3 &= ~WM8990_AIF_MSTR1;
0902         break;
0903     case SND_SOC_DAIFMT_CBM_CFM:
0904         audio3 |= WM8990_AIF_MSTR1;
0905         break;
0906     default:
0907         return -EINVAL;
0908     }
0909 
0910     audio1 &= ~WM8990_AIF_FMT_MASK;
0911 
0912     /* interface format */
0913     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0914     case SND_SOC_DAIFMT_I2S:
0915         audio1 |= WM8990_AIF_TMF_I2S;
0916         audio1 &= ~WM8990_AIF_LRCLK_INV;
0917         break;
0918     case SND_SOC_DAIFMT_RIGHT_J:
0919         audio1 |= WM8990_AIF_TMF_RIGHTJ;
0920         audio1 &= ~WM8990_AIF_LRCLK_INV;
0921         break;
0922     case SND_SOC_DAIFMT_LEFT_J:
0923         audio1 |= WM8990_AIF_TMF_LEFTJ;
0924         audio1 &= ~WM8990_AIF_LRCLK_INV;
0925         break;
0926     case SND_SOC_DAIFMT_DSP_A:
0927         audio1 |= WM8990_AIF_TMF_DSP;
0928         audio1 &= ~WM8990_AIF_LRCLK_INV;
0929         break;
0930     case SND_SOC_DAIFMT_DSP_B:
0931         audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
0932         break;
0933     default:
0934         return -EINVAL;
0935     }
0936 
0937     snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
0938     snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_3, audio3);
0939     return 0;
0940 }
0941 
0942 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
0943         int div_id, int div)
0944 {
0945     struct snd_soc_component *component = codec_dai->component;
0946 
0947     switch (div_id) {
0948     case WM8990_MCLK_DIV:
0949         snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
0950                     WM8990_MCLK_DIV_MASK, div);
0951         break;
0952     case WM8990_DACCLK_DIV:
0953         snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
0954                     WM8990_DAC_CLKDIV_MASK, div);
0955         break;
0956     case WM8990_ADCCLK_DIV:
0957         snd_soc_component_update_bits(component, WM8990_CLOCKING_2,
0958                     WM8990_ADC_CLKDIV_MASK, div);
0959         break;
0960     case WM8990_BCLK_DIV:
0961         snd_soc_component_update_bits(component, WM8990_CLOCKING_1,
0962                     WM8990_BCLK_DIV_MASK, div);
0963         break;
0964     default:
0965         return -EINVAL;
0966     }
0967 
0968     return 0;
0969 }
0970 
0971 /*
0972  * Set PCM DAI bit size and sample rate.
0973  */
0974 static int wm8990_hw_params(struct snd_pcm_substream *substream,
0975                 struct snd_pcm_hw_params *params,
0976                 struct snd_soc_dai *dai)
0977 {
0978     struct snd_soc_component *component = dai->component;
0979     u16 audio1 = snd_soc_component_read(component, WM8990_AUDIO_INTERFACE_1);
0980 
0981     audio1 &= ~WM8990_AIF_WL_MASK;
0982     /* bit size */
0983     switch (params_width(params)) {
0984     case 16:
0985         break;
0986     case 20:
0987         audio1 |= WM8990_AIF_WL_20BITS;
0988         break;
0989     case 24:
0990         audio1 |= WM8990_AIF_WL_24BITS;
0991         break;
0992     case 32:
0993         audio1 |= WM8990_AIF_WL_32BITS;
0994         break;
0995     }
0996 
0997     snd_soc_component_write(component, WM8990_AUDIO_INTERFACE_1, audio1);
0998     return 0;
0999 }
1000 
1001 static int wm8990_mute(struct snd_soc_dai *dai, int mute, int direction)
1002 {
1003     struct snd_soc_component *component = dai->component;
1004     u16 val;
1005 
1006     val  = snd_soc_component_read(component, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1007 
1008     if (mute)
1009         snd_soc_component_write(component, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1010     else
1011         snd_soc_component_write(component, WM8990_DAC_CTRL, val);
1012 
1013     return 0;
1014 }
1015 
1016 static int wm8990_set_bias_level(struct snd_soc_component *component,
1017     enum snd_soc_bias_level level)
1018 {
1019     struct wm8990_priv *wm8990 = snd_soc_component_get_drvdata(component);
1020     int ret;
1021 
1022     switch (level) {
1023     case SND_SOC_BIAS_ON:
1024         break;
1025 
1026     case SND_SOC_BIAS_PREPARE:
1027         /* VMID=2*50k */
1028         snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
1029                     WM8990_VMID_MODE_MASK, 0x2);
1030         break;
1031 
1032     case SND_SOC_BIAS_STANDBY:
1033         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1034             ret = regcache_sync(wm8990->regmap);
1035             if (ret < 0) {
1036                 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
1037                 return ret;
1038             }
1039 
1040             /* Enable all output discharge bits */
1041             snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1042                 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1043                 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1044                 WM8990_DIS_ROUT);
1045 
1046             /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1047             snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1048                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1049                      WM8990_VMIDTOG);
1050 
1051             /* Delay to allow output caps to discharge */
1052             msleep(300);
1053 
1054             /* Disable VMIDTOG */
1055             snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1056                      WM8990_BUFDCOPEN | WM8990_POBCTRL);
1057 
1058             /* disable all output discharge bits */
1059             snd_soc_component_write(component, WM8990_ANTIPOP1, 0);
1060 
1061             /* Enable outputs */
1062             snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1063 
1064             msleep(50);
1065 
1066             /* Enable VMID at 2x50k */
1067             snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1068 
1069             msleep(100);
1070 
1071             /* Enable VREF */
1072             snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1073 
1074             msleep(600);
1075 
1076             /* Enable BUFIOEN */
1077             snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1078                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1079                      WM8990_BUFIOEN);
1080 
1081             /* Disable outputs */
1082             snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x3);
1083 
1084             /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1085             snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1086 
1087             /* Enable workaround for ADC clocking issue. */
1088             snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0x2);
1089             snd_soc_component_write(component, WM8990_EXT_CTL1, 0xa003);
1090             snd_soc_component_write(component, WM8990_EXT_ACCESS_ENA, 0);
1091         }
1092 
1093         /* VMID=2*250k */
1094         snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_1,
1095                     WM8990_VMID_MODE_MASK, 0x4);
1096         break;
1097 
1098     case SND_SOC_BIAS_OFF:
1099         /* Enable POBCTRL and SOFT_ST */
1100         snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1101             WM8990_POBCTRL | WM8990_BUFIOEN);
1102 
1103         /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1104         snd_soc_component_write(component, WM8990_ANTIPOP2, WM8990_SOFTST |
1105             WM8990_BUFDCOPEN | WM8990_POBCTRL |
1106             WM8990_BUFIOEN);
1107 
1108         /* mute DAC */
1109         snd_soc_component_update_bits(component, WM8990_DAC_CTRL,
1110                     WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1111 
1112         /* Enable any disabled outputs */
1113         snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1114 
1115         /* Disable VMID */
1116         snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1117 
1118         msleep(300);
1119 
1120         /* Enable all output discharge bits */
1121         snd_soc_component_write(component, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1122             WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1123             WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1124             WM8990_DIS_ROUT);
1125 
1126         /* Disable VREF */
1127         snd_soc_component_write(component, WM8990_POWER_MANAGEMENT_1, 0x0);
1128 
1129         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1130         snd_soc_component_write(component, WM8990_ANTIPOP2, 0x0);
1131 
1132         regcache_mark_dirty(wm8990->regmap);
1133         break;
1134     }
1135 
1136     return 0;
1137 }
1138 
1139 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1140     SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1141     SNDRV_PCM_RATE_48000)
1142 
1143 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1144     SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1145 
1146 /*
1147  * The WM8990 supports 2 different and mutually exclusive DAI
1148  * configurations.
1149  *
1150  * 1. ADC/DAC on Primary Interface
1151  * 2. ADC on Primary Interface/DAC on secondary
1152  */
1153 static const struct snd_soc_dai_ops wm8990_dai_ops = {
1154     .hw_params  = wm8990_hw_params,
1155     .mute_stream    = wm8990_mute,
1156     .set_fmt    = wm8990_set_dai_fmt,
1157     .set_clkdiv = wm8990_set_dai_clkdiv,
1158     .set_pll    = wm8990_set_dai_pll,
1159     .set_sysclk = wm8990_set_dai_sysclk,
1160     .no_capture_mute = 1,
1161 };
1162 
1163 static struct snd_soc_dai_driver wm8990_dai = {
1164 /* ADC/DAC on primary */
1165     .name = "wm8990-hifi",
1166     .playback = {
1167         .stream_name = "Playback",
1168         .channels_min = 1,
1169         .channels_max = 2,
1170         .rates = WM8990_RATES,
1171         .formats = WM8990_FORMATS,},
1172     .capture = {
1173         .stream_name = "Capture",
1174         .channels_min = 1,
1175         .channels_max = 2,
1176         .rates = WM8990_RATES,
1177         .formats = WM8990_FORMATS,},
1178     .ops = &wm8990_dai_ops,
1179 };
1180 
1181 /*
1182  * initialise the WM8990 driver
1183  * register the mixer and dsp interfaces with the kernel
1184  */
1185 static int wm8990_probe(struct snd_soc_component *component)
1186 {
1187     wm8990_reset(component);
1188 
1189     /* charge output caps */
1190     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1191 
1192     snd_soc_component_update_bits(component, WM8990_AUDIO_INTERFACE_4,
1193                 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1194 
1195     snd_soc_component_update_bits(component, WM8990_GPIO1_GPIO2,
1196                 WM8990_GPIO1_SEL_MASK, 1);
1197 
1198     snd_soc_component_update_bits(component, WM8990_POWER_MANAGEMENT_2,
1199                 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1200 
1201     snd_soc_component_write(component, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1202     snd_soc_component_write(component, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1203 
1204     return 0;
1205 }
1206 
1207 static const struct snd_soc_component_driver soc_component_dev_wm8990 = {
1208     .probe          = wm8990_probe,
1209     .set_bias_level     = wm8990_set_bias_level,
1210     .controls       = wm8990_snd_controls,
1211     .num_controls       = ARRAY_SIZE(wm8990_snd_controls),
1212     .dapm_widgets       = wm8990_dapm_widgets,
1213     .num_dapm_widgets   = ARRAY_SIZE(wm8990_dapm_widgets),
1214     .dapm_routes        = wm8990_dapm_routes,
1215     .num_dapm_routes    = ARRAY_SIZE(wm8990_dapm_routes),
1216     .suspend_bias_off   = 1,
1217     .idle_bias_on       = 1,
1218     .use_pmdown_time    = 1,
1219     .endianness     = 1,
1220 };
1221 
1222 static int wm8990_i2c_probe(struct i2c_client *i2c)
1223 {
1224     struct wm8990_priv *wm8990;
1225     int ret;
1226 
1227     wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1228                   GFP_KERNEL);
1229     if (wm8990 == NULL)
1230         return -ENOMEM;
1231 
1232     i2c_set_clientdata(i2c, wm8990);
1233 
1234     ret = devm_snd_soc_register_component(&i2c->dev,
1235             &soc_component_dev_wm8990, &wm8990_dai, 1);
1236 
1237     return ret;
1238 }
1239 
1240 static const struct i2c_device_id wm8990_i2c_id[] = {
1241     { "wm8990", 0 },
1242     { }
1243 };
1244 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1245 
1246 static struct i2c_driver wm8990_i2c_driver = {
1247     .driver = {
1248         .name = "wm8990",
1249     },
1250     .probe_new = wm8990_i2c_probe,
1251     .id_table = wm8990_i2c_id,
1252 };
1253 
1254 module_i2c_driver(wm8990_i2c_driver);
1255 
1256 MODULE_DESCRIPTION("ASoC WM8990 driver");
1257 MODULE_AUTHOR("Liam Girdwood");
1258 MODULE_LICENSE("GPL");
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