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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8985.c  --  WM8985 / WM8758 ALSA SoC Audio driver
0004  *
0005  * Copyright 2010 Wolfson Microelectronics plc
0006  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
0007  *
0008  * WM8758 support:
0009  * Copyright: 2016 Barix AG
0010  * Author: Petr Kulhavy <petr@barix.com>
0011  *
0012  * TODO:
0013  *  o Add OUT3/OUT4 mixer controls.
0014  */
0015 
0016 #include <linux/module.h>
0017 #include <linux/moduleparam.h>
0018 #include <linux/init.h>
0019 #include <linux/delay.h>
0020 #include <linux/pm.h>
0021 #include <linux/i2c.h>
0022 #include <linux/regmap.h>
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/spi/spi.h>
0025 #include <linux/slab.h>
0026 #include <sound/core.h>
0027 #include <sound/pcm.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/soc.h>
0030 #include <sound/initval.h>
0031 #include <sound/tlv.h>
0032 
0033 #include "wm8985.h"
0034 
0035 #define WM8985_NUM_SUPPLIES 4
0036 static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
0037     "DCVDD",
0038     "DBVDD",
0039     "AVDD1",
0040     "AVDD2"
0041 };
0042 
0043 enum wm8985_type {
0044     WM8985,
0045     WM8758,
0046 };
0047 
0048 static const struct reg_default wm8985_reg_defaults[] = {
0049     { 1,  0x0000 },     /* R1  - Power management 1 */
0050     { 2,  0x0000 },     /* R2  - Power management 2 */
0051     { 3,  0x0000 },     /* R3  - Power management 3 */
0052     { 4,  0x0050 },     /* R4  - Audio Interface */
0053     { 5,  0x0000 },     /* R5  - Companding control */
0054     { 6,  0x0140 },     /* R6  - Clock Gen control */
0055     { 7,  0x0000 },     /* R7  - Additional control */
0056     { 8,  0x0000 },     /* R8  - GPIO Control */
0057     { 9,  0x0000 },     /* R9  - Jack Detect Control 1 */
0058     { 10, 0x0000 },     /* R10 - DAC Control */
0059     { 11, 0x00FF },     /* R11 - Left DAC digital Vol */
0060     { 12, 0x00FF },     /* R12 - Right DAC digital vol */
0061     { 13, 0x0000 },     /* R13 - Jack Detect Control 2 */
0062     { 14, 0x0100 },     /* R14 - ADC Control */
0063     { 15, 0x00FF },     /* R15 - Left ADC Digital Vol */
0064     { 16, 0x00FF },     /* R16 - Right ADC Digital Vol */
0065     { 18, 0x012C },     /* R18 - EQ1 - low shelf */
0066     { 19, 0x002C },     /* R19 - EQ2 - peak 1 */
0067     { 20, 0x002C },     /* R20 - EQ3 - peak 2 */
0068     { 21, 0x002C },     /* R21 - EQ4 - peak 3 */
0069     { 22, 0x002C },     /* R22 - EQ5 - high shelf */
0070     { 24, 0x0032 },     /* R24 - DAC Limiter 1 */
0071     { 25, 0x0000 },     /* R25 - DAC Limiter 2 */
0072     { 27, 0x0000 },     /* R27 - Notch Filter 1 */
0073     { 28, 0x0000 },     /* R28 - Notch Filter 2 */
0074     { 29, 0x0000 },     /* R29 - Notch Filter 3 */
0075     { 30, 0x0000 },     /* R30 - Notch Filter 4 */
0076     { 32, 0x0038 },     /* R32 - ALC control 1 */
0077     { 33, 0x000B },     /* R33 - ALC control 2 */
0078     { 34, 0x0032 },     /* R34 - ALC control 3 */
0079     { 35, 0x0000 },     /* R35 - Noise Gate */
0080     { 36, 0x0008 },     /* R36 - PLL N */
0081     { 37, 0x000C },     /* R37 - PLL K 1 */
0082     { 38, 0x0093 },     /* R38 - PLL K 2 */
0083     { 39, 0x00E9 },     /* R39 - PLL K 3 */
0084     { 41, 0x0000 },     /* R41 - 3D control */
0085     { 42, 0x0000 },     /* R42 - OUT4 to ADC */
0086     { 43, 0x0000 },     /* R43 - Beep control */
0087     { 44, 0x0033 },     /* R44 - Input ctrl */
0088     { 45, 0x0010 },     /* R45 - Left INP PGA gain ctrl */
0089     { 46, 0x0010 },     /* R46 - Right INP PGA gain ctrl */
0090     { 47, 0x0100 },     /* R47 - Left ADC BOOST ctrl */
0091     { 48, 0x0100 },     /* R48 - Right ADC BOOST ctrl */
0092     { 49, 0x0002 },     /* R49 - Output ctrl */
0093     { 50, 0x0001 },     /* R50 - Left mixer ctrl */
0094     { 51, 0x0001 },     /* R51 - Right mixer ctrl */
0095     { 52, 0x0039 },     /* R52 - LOUT1 (HP) volume ctrl */
0096     { 53, 0x0039 },     /* R53 - ROUT1 (HP) volume ctrl */
0097     { 54, 0x0039 },     /* R54 - LOUT2 (SPK) volume ctrl */
0098     { 55, 0x0039 },     /* R55 - ROUT2 (SPK) volume ctrl */
0099     { 56, 0x0001 },     /* R56 - OUT3 mixer ctrl */
0100     { 57, 0x0001 },     /* R57 - OUT4 (MONO) mix ctrl */
0101     { 60, 0x0004 },     /* R60 - OUTPUT ctrl */
0102     { 61, 0x0000 },     /* R61 - BIAS CTRL */
0103 };
0104 
0105 static bool wm8985_writeable(struct device *dev, unsigned int reg)
0106 {
0107     switch (reg) {
0108     case WM8985_SOFTWARE_RESET:
0109     case WM8985_POWER_MANAGEMENT_1:
0110     case WM8985_POWER_MANAGEMENT_2:
0111     case WM8985_POWER_MANAGEMENT_3:
0112     case WM8985_AUDIO_INTERFACE:
0113     case WM8985_COMPANDING_CONTROL:
0114     case WM8985_CLOCK_GEN_CONTROL:
0115     case WM8985_ADDITIONAL_CONTROL:
0116     case WM8985_GPIO_CONTROL:
0117     case WM8985_JACK_DETECT_CONTROL_1:
0118     case WM8985_DAC_CONTROL:
0119     case WM8985_LEFT_DAC_DIGITAL_VOL:
0120     case WM8985_RIGHT_DAC_DIGITAL_VOL:
0121     case WM8985_JACK_DETECT_CONTROL_2:
0122     case WM8985_ADC_CONTROL:
0123     case WM8985_LEFT_ADC_DIGITAL_VOL:
0124     case WM8985_RIGHT_ADC_DIGITAL_VOL:
0125     case WM8985_EQ1_LOW_SHELF:
0126     case WM8985_EQ2_PEAK_1:
0127     case WM8985_EQ3_PEAK_2:
0128     case WM8985_EQ4_PEAK_3:
0129     case WM8985_EQ5_HIGH_SHELF:
0130     case WM8985_DAC_LIMITER_1:
0131     case WM8985_DAC_LIMITER_2:
0132     case WM8985_NOTCH_FILTER_1:
0133     case WM8985_NOTCH_FILTER_2:
0134     case WM8985_NOTCH_FILTER_3:
0135     case WM8985_NOTCH_FILTER_4:
0136     case WM8985_ALC_CONTROL_1:
0137     case WM8985_ALC_CONTROL_2:
0138     case WM8985_ALC_CONTROL_3:
0139     case WM8985_NOISE_GATE:
0140     case WM8985_PLL_N:
0141     case WM8985_PLL_K_1:
0142     case WM8985_PLL_K_2:
0143     case WM8985_PLL_K_3:
0144     case WM8985_3D_CONTROL:
0145     case WM8985_OUT4_TO_ADC:
0146     case WM8985_BEEP_CONTROL:
0147     case WM8985_INPUT_CTRL:
0148     case WM8985_LEFT_INP_PGA_GAIN_CTRL:
0149     case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
0150     case WM8985_LEFT_ADC_BOOST_CTRL:
0151     case WM8985_RIGHT_ADC_BOOST_CTRL:
0152     case WM8985_OUTPUT_CTRL0:
0153     case WM8985_LEFT_MIXER_CTRL:
0154     case WM8985_RIGHT_MIXER_CTRL:
0155     case WM8985_LOUT1_HP_VOLUME_CTRL:
0156     case WM8985_ROUT1_HP_VOLUME_CTRL:
0157     case WM8985_LOUT2_SPK_VOLUME_CTRL:
0158     case WM8985_ROUT2_SPK_VOLUME_CTRL:
0159     case WM8985_OUT3_MIXER_CTRL:
0160     case WM8985_OUT4_MONO_MIX_CTRL:
0161     case WM8985_OUTPUT_CTRL1:
0162     case WM8985_BIAS_CTRL:
0163         return true;
0164     default:
0165         return false;
0166     }
0167 }
0168 
0169 /*
0170  * latch bit 8 of these registers to ensure instant
0171  * volume updates
0172  */
0173 static const int volume_update_regs[] = {
0174     WM8985_LEFT_DAC_DIGITAL_VOL,
0175     WM8985_RIGHT_DAC_DIGITAL_VOL,
0176     WM8985_LEFT_ADC_DIGITAL_VOL,
0177     WM8985_RIGHT_ADC_DIGITAL_VOL,
0178     WM8985_LOUT2_SPK_VOLUME_CTRL,
0179     WM8985_ROUT2_SPK_VOLUME_CTRL,
0180     WM8985_LOUT1_HP_VOLUME_CTRL,
0181     WM8985_ROUT1_HP_VOLUME_CTRL,
0182     WM8985_LEFT_INP_PGA_GAIN_CTRL,
0183     WM8985_RIGHT_INP_PGA_GAIN_CTRL
0184 };
0185 
0186 struct wm8985_priv {
0187     struct regmap *regmap;
0188     struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
0189     enum wm8985_type dev_type;
0190     unsigned int sysclk;
0191     unsigned int bclk;
0192 };
0193 
0194 static const struct {
0195     int div;
0196     int ratio;
0197 } fs_ratios[] = {
0198     { 10, 128 },
0199     { 15, 192 },
0200     { 20, 256 },
0201     { 30, 384 },
0202     { 40, 512 },
0203     { 60, 768 },
0204     { 80, 1024 },
0205     { 120, 1536 }
0206 };
0207 
0208 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
0209 
0210 static const int bclk_divs[] = {
0211     1, 2, 4, 8, 16, 32
0212 };
0213 
0214 static int eqmode_get(struct snd_kcontrol *kcontrol,
0215               struct snd_ctl_elem_value *ucontrol);
0216 static int eqmode_put(struct snd_kcontrol *kcontrol,
0217               struct snd_ctl_elem_value *ucontrol);
0218 
0219 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
0220 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
0221 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
0222 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
0223 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
0224 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
0225 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
0226 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
0227 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
0228 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
0229 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0230 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
0231 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
0232 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
0233 
0234 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
0235 static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
0236 
0237 static const char *alc_mode_text[] = { "ALC", "Limiter" };
0238 static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
0239 
0240 static const char *filter_mode_text[] = { "Audio", "Application" };
0241 static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
0242                 filter_mode_text);
0243 
0244 static const char *eq_bw_text[] = { "Narrow", "Wide" };
0245 static const char *eqmode_text[] = { "Capture", "Playback" };
0246 static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
0247 
0248 static const char *eq1_cutoff_text[] = {
0249     "80Hz", "105Hz", "135Hz", "175Hz"
0250 };
0251 static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
0252                 eq1_cutoff_text);
0253 static const char *eq2_cutoff_text[] = {
0254     "230Hz", "300Hz", "385Hz", "500Hz"
0255 };
0256 static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
0257 static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
0258 static const char *eq3_cutoff_text[] = {
0259     "650Hz", "850Hz", "1.1kHz", "1.4kHz"
0260 };
0261 static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
0262 static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
0263                 eq3_cutoff_text);
0264 static const char *eq4_cutoff_text[] = {
0265     "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
0266 };
0267 static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
0268 static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
0269 static const char *eq5_cutoff_text[] = {
0270     "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
0271 };
0272 static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
0273                   eq5_cutoff_text);
0274 
0275 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
0276 static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
0277 
0278 static const char *depth_3d_text[] = {
0279     "Off",
0280     "6.67%",
0281     "13.3%",
0282     "20%",
0283     "26.7%",
0284     "33.3%",
0285     "40%",
0286     "46.6%",
0287     "53.3%",
0288     "60%",
0289     "66.7%",
0290     "73.3%",
0291     "80%",
0292     "86.7%",
0293     "93.3%",
0294     "100%"
0295 };
0296 static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
0297 
0298 static const struct snd_kcontrol_new wm8985_common_snd_controls[] = {
0299     SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
0300         0, 1, 0),
0301 
0302     SOC_ENUM("ALC Capture Function", alc_sel),
0303     SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
0304         3, 7, 0, alc_max_tlv),
0305     SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
0306         0, 7, 0, alc_min_tlv),
0307     SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
0308         0, 15, 0, alc_tar_tlv),
0309     SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
0310     SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
0311     SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
0312     SOC_ENUM("ALC Mode", alc_mode),
0313     SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
0314         3, 1, 0),
0315     SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
0316         0, 7, 1),
0317 
0318     SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
0319         WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
0320     SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
0321         WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
0322     SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
0323         WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
0324 
0325     SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
0326         WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
0327         8, 1, 0, pga_boost_tlv),
0328 
0329     SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
0330     SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
0331 
0332     SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
0333         WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
0334 
0335     SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
0336     SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
0337     SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
0338     SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
0339         4, 7, 1, lim_thresh_tlv),
0340     SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
0341         0, 12, 0, lim_boost_tlv),
0342     SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
0343     SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
0344     SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
0345 
0346     SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
0347         WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
0348     SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
0349         WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
0350     SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
0351         WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
0352 
0353     SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
0354         WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
0355     SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
0356         WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
0357     SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
0358         WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
0359 
0360     SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
0361     SOC_ENUM("High Pass Filter Mode", filter_mode),
0362     SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
0363 
0364     SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
0365         WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
0366         bypass_tlv),
0367 
0368     SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
0369     SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
0370     SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
0371     SOC_ENUM("EQ2 Bandwidth", eq2_bw),
0372     SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
0373     SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
0374     SOC_ENUM("EQ3 Bandwidth", eq3_bw),
0375     SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
0376     SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
0377     SOC_ENUM("EQ4 Bandwidth", eq4_bw),
0378     SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
0379     SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
0380     SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
0381     SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
0382 
0383     SOC_ENUM("3D Depth", depth_3d),
0384 };
0385 
0386 static const struct snd_kcontrol_new wm8985_specific_snd_controls[] = {
0387     SOC_DOUBLE_R_TLV("Aux Bypass Volume",
0388         WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
0389         aux_tlv),
0390 
0391     SOC_ENUM("Speaker Mode", speaker_mode)
0392 };
0393 
0394 static const struct snd_kcontrol_new left_out_mixer[] = {
0395     SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
0396     SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
0397 
0398     /* --- WM8985 only --- */
0399     SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
0400 };
0401 
0402 static const struct snd_kcontrol_new right_out_mixer[] = {
0403     SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
0404     SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
0405 
0406     /* --- WM8985 only --- */
0407     SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
0408 };
0409 
0410 static const struct snd_kcontrol_new left_input_mixer[] = {
0411     SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
0412     SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
0413     SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
0414 };
0415 
0416 static const struct snd_kcontrol_new right_input_mixer[] = {
0417     SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
0418     SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
0419     SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
0420 };
0421 
0422 static const struct snd_kcontrol_new left_boost_mixer[] = {
0423     SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
0424         4, 7, 0, boost_tlv),
0425 
0426     /* --- WM8985 only --- */
0427     SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
0428         0, 7, 0, boost_tlv)
0429 };
0430 
0431 static const struct snd_kcontrol_new right_boost_mixer[] = {
0432     SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
0433         4, 7, 0, boost_tlv),
0434 
0435     /* --- WM8985 only --- */
0436     SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
0437         0, 7, 0, boost_tlv)
0438 };
0439 
0440 static const struct snd_soc_dapm_widget wm8985_common_dapm_widgets[] = {
0441     SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
0442         0, 0),
0443     SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
0444         1, 0),
0445     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
0446         0, 0),
0447     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
0448         1, 0),
0449 
0450     SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
0451         2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
0452     SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
0453         3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
0454 
0455     SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
0456         6, 1, NULL, 0),
0457     SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
0458         6, 1, NULL, 0),
0459 
0460     SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
0461         7, 0, NULL, 0),
0462     SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
0463         8, 0, NULL, 0),
0464 
0465     SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
0466         5, 0, NULL, 0),
0467     SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
0468         6, 0, NULL, 0),
0469 
0470     SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
0471                 NULL, 0),
0472 
0473     SND_SOC_DAPM_INPUT("LIN"),
0474     SND_SOC_DAPM_INPUT("LIP"),
0475     SND_SOC_DAPM_INPUT("RIN"),
0476     SND_SOC_DAPM_INPUT("RIP"),
0477     SND_SOC_DAPM_INPUT("L2"),
0478     SND_SOC_DAPM_INPUT("R2"),
0479     SND_SOC_DAPM_OUTPUT("HPL"),
0480     SND_SOC_DAPM_OUTPUT("HPR"),
0481     SND_SOC_DAPM_OUTPUT("SPKL"),
0482     SND_SOC_DAPM_OUTPUT("SPKR")
0483 };
0484 
0485 static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
0486     SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
0487         2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
0488     SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
0489         3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
0490 
0491     SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
0492         4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
0493     SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
0494         5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
0495 
0496     SND_SOC_DAPM_INPUT("AUXL"),
0497     SND_SOC_DAPM_INPUT("AUXR"),
0498 };
0499 
0500 static const struct snd_soc_dapm_widget wm8758_dapm_widgets[] = {
0501     SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
0502         2, 0, left_out_mixer,
0503         ARRAY_SIZE(left_out_mixer) - 1),
0504     SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
0505         3, 0, right_out_mixer,
0506         ARRAY_SIZE(right_out_mixer) - 1),
0507 
0508     SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
0509         4, 0, left_boost_mixer,
0510         ARRAY_SIZE(left_boost_mixer) - 1),
0511     SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
0512         5, 0, right_boost_mixer,
0513         ARRAY_SIZE(right_boost_mixer) - 1),
0514 };
0515 
0516 static const struct snd_soc_dapm_route wm8985_common_dapm_routes[] = {
0517     { "Right Output Mixer", "PCM Switch", "Right DAC" },
0518     { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
0519 
0520     { "Left Output Mixer", "PCM Switch", "Left DAC" },
0521     { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
0522 
0523     { "Right Headphone Out", NULL, "Right Output Mixer" },
0524     { "HPR", NULL, "Right Headphone Out" },
0525 
0526     { "Left Headphone Out", NULL, "Left Output Mixer" },
0527     { "HPL", NULL, "Left Headphone Out" },
0528 
0529     { "Right Speaker Out", NULL, "Right Output Mixer" },
0530     { "SPKR", NULL, "Right Speaker Out" },
0531 
0532     { "Left Speaker Out", NULL, "Left Output Mixer" },
0533     { "SPKL", NULL, "Left Speaker Out" },
0534 
0535     { "Right ADC", NULL, "Right Boost Mixer" },
0536 
0537     { "Right Boost Mixer", NULL, "Right Capture PGA" },
0538     { "Right Boost Mixer", "R2 Volume", "R2" },
0539 
0540     { "Left ADC", NULL, "Left Boost Mixer" },
0541 
0542     { "Left Boost Mixer", NULL, "Left Capture PGA" },
0543     { "Left Boost Mixer", "L2 Volume", "L2" },
0544 
0545     { "Right Capture PGA", NULL, "Right Input Mixer" },
0546     { "Left Capture PGA", NULL, "Left Input Mixer" },
0547 
0548     { "Right Input Mixer", "R2 Switch", "R2" },
0549     { "Right Input Mixer", "MicN Switch", "RIN" },
0550     { "Right Input Mixer", "MicP Switch", "RIP" },
0551 
0552     { "Left Input Mixer", "L2 Switch", "L2" },
0553     { "Left Input Mixer", "MicN Switch", "LIN" },
0554     { "Left Input Mixer", "MicP Switch", "LIP" },
0555 };
0556 static const struct snd_soc_dapm_route wm8985_aux_dapm_routes[] = {
0557     { "Right Output Mixer", "Aux Switch", "AUXR" },
0558     { "Left Output Mixer", "Aux Switch", "AUXL" },
0559 
0560     { "Right Boost Mixer", "AUXR Volume", "AUXR" },
0561     { "Left Boost Mixer", "AUXL Volume", "AUXL" },
0562 };
0563 
0564 static int wm8985_add_widgets(struct snd_soc_component *component)
0565 {
0566     struct wm8985_priv *wm8985 = snd_soc_component_get_drvdata(component);
0567     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0568 
0569     switch (wm8985->dev_type) {
0570     case WM8758:
0571         snd_soc_dapm_new_controls(dapm, wm8758_dapm_widgets,
0572                       ARRAY_SIZE(wm8758_dapm_widgets));
0573         break;
0574 
0575     case WM8985:
0576         snd_soc_add_component_controls(component, wm8985_specific_snd_controls,
0577             ARRAY_SIZE(wm8985_specific_snd_controls));
0578 
0579         snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
0580             ARRAY_SIZE(wm8985_dapm_widgets));
0581         snd_soc_dapm_add_routes(dapm, wm8985_aux_dapm_routes,
0582             ARRAY_SIZE(wm8985_aux_dapm_routes));
0583         break;
0584     }
0585 
0586     return 0;
0587 }
0588 
0589 static int eqmode_get(struct snd_kcontrol *kcontrol,
0590               struct snd_ctl_elem_value *ucontrol)
0591 {
0592     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0593     unsigned int reg;
0594 
0595     reg = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
0596     if (reg & WM8985_EQ3DMODE)
0597         ucontrol->value.enumerated.item[0] = 1;
0598     else
0599         ucontrol->value.enumerated.item[0] = 0;
0600 
0601     return 0;
0602 }
0603 
0604 static int eqmode_put(struct snd_kcontrol *kcontrol,
0605               struct snd_ctl_elem_value *ucontrol)
0606 {
0607     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0608     unsigned int regpwr2, regpwr3;
0609     unsigned int reg_eq;
0610 
0611     if (ucontrol->value.enumerated.item[0] != 0
0612             && ucontrol->value.enumerated.item[0] != 1)
0613         return -EINVAL;
0614 
0615     reg_eq = snd_soc_component_read(component, WM8985_EQ1_LOW_SHELF);
0616     switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
0617     case 0:
0618         if (!ucontrol->value.enumerated.item[0])
0619             return 0;
0620         break;
0621     case 1:
0622         if (ucontrol->value.enumerated.item[0])
0623             return 0;
0624         break;
0625     }
0626 
0627     regpwr2 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_2);
0628     regpwr3 = snd_soc_component_read(component, WM8985_POWER_MANAGEMENT_3);
0629     /* disable the DACs and ADCs */
0630     snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_2,
0631                 WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
0632     snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_3,
0633                 WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
0634     snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
0635                 WM8985_M128ENB_MASK, WM8985_M128ENB);
0636     /* set the desired eqmode */
0637     snd_soc_component_update_bits(component, WM8985_EQ1_LOW_SHELF,
0638                 WM8985_EQ3DMODE_MASK,
0639                 ucontrol->value.enumerated.item[0]
0640                 << WM8985_EQ3DMODE_SHIFT);
0641     /* restore DAC/ADC configuration */
0642     snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, regpwr2);
0643     snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, regpwr3);
0644     return 0;
0645 }
0646 
0647 static int wm8985_reset(struct snd_soc_component *component)
0648 {
0649     return snd_soc_component_write(component, WM8985_SOFTWARE_RESET, 0x0);
0650 }
0651 
0652 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
0653 {
0654     struct snd_soc_component *component = dai->component;
0655 
0656     return snd_soc_component_update_bits(component, WM8985_DAC_CONTROL,
0657                    WM8985_SOFTMUTE_MASK,
0658                    !!mute << WM8985_SOFTMUTE_SHIFT);
0659 }
0660 
0661 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0662 {
0663     struct snd_soc_component *component;
0664     u16 format, master, bcp, lrp;
0665 
0666     component = dai->component;
0667 
0668     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0669     case SND_SOC_DAIFMT_I2S:
0670         format = 0x2;
0671         break;
0672     case SND_SOC_DAIFMT_RIGHT_J:
0673         format = 0x0;
0674         break;
0675     case SND_SOC_DAIFMT_LEFT_J:
0676         format = 0x1;
0677         break;
0678     case SND_SOC_DAIFMT_DSP_A:
0679     case SND_SOC_DAIFMT_DSP_B:
0680         format = 0x3;
0681         break;
0682     default:
0683         dev_err(dai->dev, "Unknown dai format\n");
0684         return -EINVAL;
0685     }
0686 
0687     snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
0688                 WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
0689 
0690     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0691     case SND_SOC_DAIFMT_CBM_CFM:
0692         master = 1;
0693         break;
0694     case SND_SOC_DAIFMT_CBS_CFS:
0695         master = 0;
0696         break;
0697     default:
0698         dev_err(dai->dev, "Unknown master/slave configuration\n");
0699         return -EINVAL;
0700     }
0701 
0702     snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
0703                 WM8985_MS_MASK, master << WM8985_MS_SHIFT);
0704 
0705     /* frame inversion is not valid for dsp modes */
0706     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0707     case SND_SOC_DAIFMT_DSP_A:
0708     case SND_SOC_DAIFMT_DSP_B:
0709         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0710         case SND_SOC_DAIFMT_IB_IF:
0711         case SND_SOC_DAIFMT_NB_IF:
0712             return -EINVAL;
0713         default:
0714             break;
0715         }
0716         break;
0717     default:
0718         break;
0719     }
0720 
0721     bcp = lrp = 0;
0722     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0723     case SND_SOC_DAIFMT_NB_NF:
0724         break;
0725     case SND_SOC_DAIFMT_IB_IF:
0726         bcp = lrp = 1;
0727         break;
0728     case SND_SOC_DAIFMT_IB_NF:
0729         bcp = 1;
0730         break;
0731     case SND_SOC_DAIFMT_NB_IF:
0732         lrp = 1;
0733         break;
0734     default:
0735         dev_err(dai->dev, "Unknown polarity configuration\n");
0736         return -EINVAL;
0737     }
0738 
0739     snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
0740                 WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
0741     snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
0742                 WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
0743     return 0;
0744 }
0745 
0746 static int wm8985_hw_params(struct snd_pcm_substream *substream,
0747                 struct snd_pcm_hw_params *params,
0748                 struct snd_soc_dai *dai)
0749 {
0750     int i;
0751     struct snd_soc_component *component;
0752     struct wm8985_priv *wm8985;
0753     u16 blen, srate_idx;
0754     unsigned int tmp;
0755     int srate_best;
0756 
0757     component = dai->component;
0758     wm8985 = snd_soc_component_get_drvdata(component);
0759 
0760     wm8985->bclk = snd_soc_params_to_bclk(params);
0761     if ((int)wm8985->bclk < 0)
0762         return wm8985->bclk;
0763 
0764     switch (params_width(params)) {
0765     case 16:
0766         blen = 0x0;
0767         break;
0768     case 20:
0769         blen = 0x1;
0770         break;
0771     case 24:
0772         blen = 0x2;
0773         break;
0774     case 32:
0775         blen = 0x3;
0776         break;
0777     default:
0778         dev_err(dai->dev, "Unsupported word length %u\n",
0779             params_width(params));
0780         return -EINVAL;
0781     }
0782 
0783     snd_soc_component_update_bits(component, WM8985_AUDIO_INTERFACE,
0784                 WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
0785 
0786     /*
0787      * match to the nearest possible sample rate and rely
0788      * on the array index to configure the SR register
0789      */
0790     srate_idx = 0;
0791     srate_best = abs(srates[0] - params_rate(params));
0792     for (i = 1; i < ARRAY_SIZE(srates); ++i) {
0793         if (abs(srates[i] - params_rate(params)) >= srate_best)
0794             continue;
0795         srate_idx = i;
0796         srate_best = abs(srates[i] - params_rate(params));
0797     }
0798 
0799     dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
0800     snd_soc_component_update_bits(component, WM8985_ADDITIONAL_CONTROL,
0801                 WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
0802 
0803     dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
0804     dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
0805 
0806     for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
0807         if (wm8985->sysclk / params_rate(params)
0808                 == fs_ratios[i].ratio)
0809             break;
0810     }
0811 
0812     if (i == ARRAY_SIZE(fs_ratios)) {
0813         dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
0814             wm8985->sysclk, params_rate(params));
0815         return -EINVAL;
0816     }
0817 
0818     dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
0819     snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
0820                 WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
0821 
0822     /* select the appropriate bclk divider */
0823     tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
0824     for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
0825         if (wm8985->bclk == tmp / bclk_divs[i])
0826             break;
0827     }
0828 
0829     if (i == ARRAY_SIZE(bclk_divs)) {
0830         dev_err(dai->dev, "No matching BCLK divider found\n");
0831         return -EINVAL;
0832     }
0833 
0834     dev_dbg(dai->dev, "BCLK div = %d\n", i);
0835     snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
0836                 WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
0837     return 0;
0838 }
0839 
0840 struct pll_div {
0841     u32 div2:1;
0842     u32 n:4;
0843     u32 k:24;
0844 };
0845 
0846 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
0847 static int pll_factors(struct pll_div *pll_div, unsigned int target,
0848                unsigned int source)
0849 {
0850     u64 Kpart;
0851     unsigned long int K, Ndiv, Nmod;
0852 
0853     pll_div->div2 = 0;
0854     Ndiv = target / source;
0855     if (Ndiv < 6) {
0856         source >>= 1;
0857         pll_div->div2 = 1;
0858         Ndiv = target / source;
0859     }
0860 
0861     if (Ndiv < 6 || Ndiv > 12) {
0862         printk(KERN_ERR "%s: WM8985 N value is not within"
0863                " the recommended range: %lu\n", __func__, Ndiv);
0864         return -EINVAL;
0865     }
0866     pll_div->n = Ndiv;
0867 
0868     Nmod = target % source;
0869     Kpart = FIXED_PLL_SIZE * (u64)Nmod;
0870 
0871     do_div(Kpart, source);
0872 
0873     K = Kpart & 0xffffffff;
0874     if ((K % 10) >= 5)
0875         K += 5;
0876     K /= 10;
0877     pll_div->k = K;
0878 
0879     return 0;
0880 }
0881 
0882 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
0883               int source, unsigned int freq_in,
0884               unsigned int freq_out)
0885 {
0886     int ret;
0887     struct snd_soc_component *component;
0888     struct pll_div pll_div;
0889 
0890     component = dai->component;
0891     if (!freq_in || !freq_out) {
0892         /* disable the PLL */
0893         snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0894                     WM8985_PLLEN_MASK, 0);
0895     } else {
0896         ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
0897         if (ret)
0898             return ret;
0899 
0900         /* set PLLN and PRESCALE */
0901         snd_soc_component_write(component, WM8985_PLL_N,
0902                   (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
0903                   | pll_div.n);
0904         /* set PLLK */
0905         snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff);
0906         snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
0907         snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18));
0908         /* set the source of the clock to be the PLL */
0909         snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
0910                     WM8985_CLKSEL_MASK, WM8985_CLKSEL);
0911         /* enable the PLL */
0912         snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0913                     WM8985_PLLEN_MASK, WM8985_PLLEN);
0914     }
0915     return 0;
0916 }
0917 
0918 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
0919                  int clk_id, unsigned int freq, int dir)
0920 {
0921     struct snd_soc_component *component;
0922     struct wm8985_priv *wm8985;
0923 
0924     component = dai->component;
0925     wm8985 = snd_soc_component_get_drvdata(component);
0926 
0927     switch (clk_id) {
0928     case WM8985_CLKSRC_MCLK:
0929         snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
0930                     WM8985_CLKSEL_MASK, 0);
0931         snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0932                     WM8985_PLLEN_MASK, 0);
0933         break;
0934     case WM8985_CLKSRC_PLL:
0935         snd_soc_component_update_bits(component, WM8985_CLOCK_GEN_CONTROL,
0936                     WM8985_CLKSEL_MASK, WM8985_CLKSEL);
0937         break;
0938     default:
0939         dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
0940         return -EINVAL;
0941     }
0942 
0943     wm8985->sysclk = freq;
0944     return 0;
0945 }
0946 
0947 static int wm8985_set_bias_level(struct snd_soc_component *component,
0948                  enum snd_soc_bias_level level)
0949 {
0950     int ret;
0951     struct wm8985_priv *wm8985;
0952 
0953     wm8985 = snd_soc_component_get_drvdata(component);
0954     switch (level) {
0955     case SND_SOC_BIAS_ON:
0956     case SND_SOC_BIAS_PREPARE:
0957         /* VMID at 75k */
0958         snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0959                     WM8985_VMIDSEL_MASK,
0960                     1 << WM8985_VMIDSEL_SHIFT);
0961         break;
0962     case SND_SOC_BIAS_STANDBY:
0963         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0964             ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
0965                             wm8985->supplies);
0966             if (ret) {
0967                 dev_err(component->dev,
0968                     "Failed to enable supplies: %d\n",
0969                     ret);
0970                 return ret;
0971             }
0972 
0973             regcache_sync(wm8985->regmap);
0974 
0975             /* enable anti-pop features */
0976             snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
0977                         WM8985_POBCTRL_MASK,
0978                         WM8985_POBCTRL);
0979             /* enable thermal shutdown */
0980             snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
0981                         WM8985_TSDEN_MASK, WM8985_TSDEN);
0982             snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
0983                         WM8985_TSOPCTRL_MASK,
0984                         WM8985_TSOPCTRL);
0985             /* enable BIASEN */
0986             snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0987                         WM8985_BIASEN_MASK, WM8985_BIASEN);
0988             /* VMID at 75k */
0989             snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0990                         WM8985_VMIDSEL_MASK,
0991                         1 << WM8985_VMIDSEL_SHIFT);
0992             msleep(500);
0993             /* disable anti-pop features */
0994             snd_soc_component_update_bits(component, WM8985_OUT4_TO_ADC,
0995                         WM8985_POBCTRL_MASK, 0);
0996         }
0997         /* VMID at 300k */
0998         snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
0999                     WM8985_VMIDSEL_MASK,
1000                     2 << WM8985_VMIDSEL_SHIFT);
1001         break;
1002     case SND_SOC_BIAS_OFF:
1003         /* disable thermal shutdown */
1004         snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
1005                     WM8985_TSOPCTRL_MASK, 0);
1006         snd_soc_component_update_bits(component, WM8985_OUTPUT_CTRL0,
1007                     WM8985_TSDEN_MASK, 0);
1008         /* disable VMIDSEL and BIASEN */
1009         snd_soc_component_update_bits(component, WM8985_POWER_MANAGEMENT_1,
1010                     WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
1011                     0);
1012         snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_1, 0);
1013         snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_2, 0);
1014         snd_soc_component_write(component, WM8985_POWER_MANAGEMENT_3, 0);
1015 
1016         regcache_mark_dirty(wm8985->regmap);
1017 
1018         regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
1019                        wm8985->supplies);
1020         break;
1021     }
1022 
1023     return 0;
1024 }
1025 
1026 static int wm8985_probe(struct snd_soc_component *component)
1027 {
1028     size_t i;
1029     struct wm8985_priv *wm8985;
1030     int ret;
1031 
1032     wm8985 = snd_soc_component_get_drvdata(component);
1033 
1034     for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
1035         wm8985->supplies[i].supply = wm8985_supply_names[i];
1036 
1037     ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8985->supplies),
1038                  wm8985->supplies);
1039     if (ret) {
1040         dev_err(component->dev, "Failed to request supplies: %d\n", ret);
1041         return ret;
1042     }
1043 
1044     ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
1045                     wm8985->supplies);
1046     if (ret) {
1047         dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
1048         return ret;
1049     }
1050 
1051     ret = wm8985_reset(component);
1052     if (ret < 0) {
1053         dev_err(component->dev, "Failed to issue reset: %d\n", ret);
1054         goto err_reg_enable;
1055     }
1056 
1057     /* latch volume update bits */
1058     for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
1059         snd_soc_component_update_bits(component, volume_update_regs[i],
1060                     0x100, 0x100);
1061     /* enable BIASCUT */
1062     snd_soc_component_update_bits(component, WM8985_BIAS_CTRL, WM8985_BIASCUT,
1063                 WM8985_BIASCUT);
1064 
1065     wm8985_add_widgets(component);
1066 
1067     return 0;
1068 
1069 err_reg_enable:
1070     regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1071     return ret;
1072 }
1073 
1074 static const struct snd_soc_dai_ops wm8985_dai_ops = {
1075     .mute_stream = wm8985_dac_mute,
1076     .hw_params = wm8985_hw_params,
1077     .set_fmt = wm8985_set_fmt,
1078     .set_sysclk = wm8985_set_sysclk,
1079     .set_pll = wm8985_set_pll,
1080     .no_capture_mute = 1,
1081 };
1082 
1083 #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1084             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1085 
1086 static struct snd_soc_dai_driver wm8985_dai = {
1087     .name = "wm8985-hifi",
1088     .playback = {
1089         .stream_name = "Playback",
1090         .channels_min = 2,
1091         .channels_max = 2,
1092         .rates = SNDRV_PCM_RATE_8000_48000,
1093         .formats = WM8985_FORMATS,
1094     },
1095     .capture = {
1096         .stream_name = "Capture",
1097         .channels_min = 2,
1098         .channels_max = 2,
1099         .rates = SNDRV_PCM_RATE_8000_48000,
1100         .formats = WM8985_FORMATS,
1101     },
1102     .ops = &wm8985_dai_ops,
1103     .symmetric_rate = 1
1104 };
1105 
1106 static const struct snd_soc_component_driver soc_component_dev_wm8985 = {
1107     .probe          = wm8985_probe,
1108     .set_bias_level     = wm8985_set_bias_level,
1109     .controls       = wm8985_common_snd_controls,
1110     .num_controls       = ARRAY_SIZE(wm8985_common_snd_controls),
1111     .dapm_widgets       = wm8985_common_dapm_widgets,
1112     .num_dapm_widgets   = ARRAY_SIZE(wm8985_common_dapm_widgets),
1113     .dapm_routes        = wm8985_common_dapm_routes,
1114     .num_dapm_routes    = ARRAY_SIZE(wm8985_common_dapm_routes),
1115     .suspend_bias_off   = 1,
1116     .idle_bias_on       = 1,
1117     .use_pmdown_time    = 1,
1118     .endianness     = 1,
1119 };
1120 
1121 static const struct regmap_config wm8985_regmap = {
1122     .reg_bits = 7,
1123     .val_bits = 9,
1124 
1125     .max_register = WM8985_MAX_REGISTER,
1126     .writeable_reg = wm8985_writeable,
1127 
1128     .cache_type = REGCACHE_RBTREE,
1129     .reg_defaults = wm8985_reg_defaults,
1130     .num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
1131 };
1132 
1133 #if defined(CONFIG_SPI_MASTER)
1134 static int wm8985_spi_probe(struct spi_device *spi)
1135 {
1136     struct wm8985_priv *wm8985;
1137     int ret;
1138 
1139     wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
1140     if (!wm8985)
1141         return -ENOMEM;
1142 
1143     spi_set_drvdata(spi, wm8985);
1144 
1145     wm8985->dev_type = WM8985;
1146 
1147     wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
1148     if (IS_ERR(wm8985->regmap)) {
1149         ret = PTR_ERR(wm8985->regmap);
1150         dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1151             ret);
1152         return ret;
1153     }
1154 
1155     ret = devm_snd_soc_register_component(&spi->dev,
1156                      &soc_component_dev_wm8985, &wm8985_dai, 1);
1157     return ret;
1158 }
1159 
1160 static struct spi_driver wm8985_spi_driver = {
1161     .driver = {
1162         .name = "wm8985",
1163     },
1164     .probe = wm8985_spi_probe,
1165 };
1166 #endif
1167 
1168 #if IS_ENABLED(CONFIG_I2C)
1169 static const struct i2c_device_id wm8985_i2c_id[];
1170 
1171 static int wm8985_i2c_probe(struct i2c_client *i2c)
1172 {
1173     struct wm8985_priv *wm8985;
1174     const struct i2c_device_id *id = i2c_match_id(wm8985_i2c_id, i2c);
1175     int ret;
1176 
1177     wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
1178     if (!wm8985)
1179         return -ENOMEM;
1180 
1181     i2c_set_clientdata(i2c, wm8985);
1182 
1183     wm8985->dev_type = id->driver_data;
1184 
1185     wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
1186     if (IS_ERR(wm8985->regmap)) {
1187         ret = PTR_ERR(wm8985->regmap);
1188         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1189             ret);
1190         return ret;
1191     }
1192 
1193     ret = devm_snd_soc_register_component(&i2c->dev,
1194                      &soc_component_dev_wm8985, &wm8985_dai, 1);
1195     return ret;
1196 }
1197 
1198 static const struct i2c_device_id wm8985_i2c_id[] = {
1199     { "wm8985", WM8985 },
1200     { "wm8758", WM8758 },
1201     { }
1202 };
1203 MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1204 
1205 static struct i2c_driver wm8985_i2c_driver = {
1206     .driver = {
1207         .name = "wm8985",
1208     },
1209     .probe_new = wm8985_i2c_probe,
1210     .id_table = wm8985_i2c_id
1211 };
1212 #endif
1213 
1214 static int __init wm8985_modinit(void)
1215 {
1216     int ret = 0;
1217 
1218 #if IS_ENABLED(CONFIG_I2C)
1219     ret = i2c_add_driver(&wm8985_i2c_driver);
1220     if (ret) {
1221         printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1222                ret);
1223     }
1224 #endif
1225 #if defined(CONFIG_SPI_MASTER)
1226     ret = spi_register_driver(&wm8985_spi_driver);
1227     if (ret != 0) {
1228         printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1229                ret);
1230     }
1231 #endif
1232     return ret;
1233 }
1234 module_init(wm8985_modinit);
1235 
1236 static void __exit wm8985_exit(void)
1237 {
1238 #if IS_ENABLED(CONFIG_I2C)
1239     i2c_del_driver(&wm8985_i2c_driver);
1240 #endif
1241 #if defined(CONFIG_SPI_MASTER)
1242     spi_unregister_driver(&wm8985_spi_driver);
1243 #endif
1244 }
1245 module_exit(wm8985_exit);
1246 
1247 MODULE_DESCRIPTION("ASoC WM8985 / WM8758 driver");
1248 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1249 MODULE_LICENSE("GPL");
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