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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8983.c  --  WM8983 ALSA SoC Audio driver
0004  *
0005  * Copyright 2011 Wolfson Microelectronics plc
0006  *
0007  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/i2c.h>
0016 #include <linux/regmap.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/slab.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/initval.h>
0024 #include <sound/tlv.h>
0025 
0026 #include "wm8983.h"
0027 
0028 static const struct reg_default wm8983_defaults[] = {
0029     { 0x01, 0x0000 },     /* R1  - Power management 1 */
0030     { 0x02, 0x0000 },     /* R2  - Power management 2 */
0031     { 0x03, 0x0000 },     /* R3  - Power management 3 */
0032     { 0x04, 0x0050 },     /* R4  - Audio Interface */
0033     { 0x05, 0x0000 },     /* R5  - Companding control */
0034     { 0x06, 0x0140 },     /* R6  - Clock Gen control */
0035     { 0x07, 0x0000 },     /* R7  - Additional control */
0036     { 0x08, 0x0000 },     /* R8  - GPIO Control */
0037     { 0x09, 0x0000 },     /* R9  - Jack Detect Control 1 */
0038     { 0x0A, 0x0000 },     /* R10 - DAC Control */
0039     { 0x0B, 0x00FF },     /* R11 - Left DAC digital Vol */
0040     { 0x0C, 0x00FF },     /* R12 - Right DAC digital vol */
0041     { 0x0D, 0x0000 },     /* R13 - Jack Detect Control 2 */
0042     { 0x0E, 0x0100 },     /* R14 - ADC Control */
0043     { 0x0F, 0x00FF },     /* R15 - Left ADC Digital Vol */
0044     { 0x10, 0x00FF },     /* R16 - Right ADC Digital Vol */
0045     { 0x12, 0x012C },     /* R18 - EQ1 - low shelf */
0046     { 0x13, 0x002C },     /* R19 - EQ2 - peak 1 */
0047     { 0x14, 0x002C },     /* R20 - EQ3 - peak 2 */
0048     { 0x15, 0x002C },     /* R21 - EQ4 - peak 3 */
0049     { 0x16, 0x002C },     /* R22 - EQ5 - high shelf */
0050     { 0x18, 0x0032 },     /* R24 - DAC Limiter 1 */
0051     { 0x19, 0x0000 },     /* R25 - DAC Limiter 2 */
0052     { 0x1B, 0x0000 },     /* R27 - Notch Filter 1 */
0053     { 0x1C, 0x0000 },     /* R28 - Notch Filter 2 */
0054     { 0x1D, 0x0000 },     /* R29 - Notch Filter 3 */
0055     { 0x1E, 0x0000 },     /* R30 - Notch Filter 4 */
0056     { 0x20, 0x0038 },     /* R32 - ALC control 1 */
0057     { 0x21, 0x000B },     /* R33 - ALC control 2 */
0058     { 0x22, 0x0032 },     /* R34 - ALC control 3 */
0059     { 0x23, 0x0000 },     /* R35 - Noise Gate */
0060     { 0x24, 0x0008 },     /* R36 - PLL N */
0061     { 0x25, 0x000C },     /* R37 - PLL K 1 */
0062     { 0x26, 0x0093 },     /* R38 - PLL K 2 */
0063     { 0x27, 0x00E9 },     /* R39 - PLL K 3 */
0064     { 0x29, 0x0000 },     /* R41 - 3D control */
0065     { 0x2A, 0x0000 },     /* R42 - OUT4 to ADC */
0066     { 0x2B, 0x0000 },     /* R43 - Beep control */
0067     { 0x2C, 0x0033 },     /* R44 - Input ctrl */
0068     { 0x2D, 0x0010 },     /* R45 - Left INP PGA gain ctrl */
0069     { 0x2E, 0x0010 },     /* R46 - Right INP PGA gain ctrl */
0070     { 0x2F, 0x0100 },     /* R47 - Left ADC BOOST ctrl */
0071     { 0x30, 0x0100 },     /* R48 - Right ADC BOOST ctrl */
0072     { 0x31, 0x0002 },     /* R49 - Output ctrl */
0073     { 0x32, 0x0001 },     /* R50 - Left mixer ctrl */
0074     { 0x33, 0x0001 },     /* R51 - Right mixer ctrl */
0075     { 0x34, 0x0039 },     /* R52 - LOUT1 (HP) volume ctrl */
0076     { 0x35, 0x0039 },     /* R53 - ROUT1 (HP) volume ctrl */
0077     { 0x36, 0x0039 },     /* R54 - LOUT2 (SPK) volume ctrl */
0078     { 0x37, 0x0039 },     /* R55 - ROUT2 (SPK) volume ctrl */
0079     { 0x38, 0x0001 },     /* R56 - OUT3 mixer ctrl */
0080     { 0x39, 0x0001 },     /* R57 - OUT4 (MONO) mix ctrl */
0081     { 0x3D, 0x0000 },      /* R61 - BIAS CTRL */
0082 };
0083 
0084 /* vol/gain update regs */
0085 static const int vol_update_regs[] = {
0086     WM8983_LEFT_DAC_DIGITAL_VOL,
0087     WM8983_RIGHT_DAC_DIGITAL_VOL,
0088     WM8983_LEFT_ADC_DIGITAL_VOL,
0089     WM8983_RIGHT_ADC_DIGITAL_VOL,
0090     WM8983_LOUT1_HP_VOLUME_CTRL,
0091     WM8983_ROUT1_HP_VOLUME_CTRL,
0092     WM8983_LOUT2_SPK_VOLUME_CTRL,
0093     WM8983_ROUT2_SPK_VOLUME_CTRL,
0094     WM8983_LEFT_INP_PGA_GAIN_CTRL,
0095     WM8983_RIGHT_INP_PGA_GAIN_CTRL
0096 };
0097 
0098 struct wm8983_priv {
0099     struct regmap *regmap;
0100     u32 sysclk;
0101     u32 bclk;
0102 };
0103 
0104 static const struct {
0105     int div;
0106     int ratio;
0107 } fs_ratios[] = {
0108     { 10, 128 },
0109     { 15, 192 },
0110     { 20, 256 },
0111     { 30, 384 },
0112     { 40, 512 },
0113     { 60, 768 },
0114     { 80, 1024 },
0115     { 120, 1536 }
0116 };
0117 
0118 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
0119 
0120 static const int bclk_divs[] = {
0121     1, 2, 4, 8, 16, 32
0122 };
0123 
0124 static int eqmode_get(struct snd_kcontrol *kcontrol,
0125               struct snd_ctl_elem_value *ucontrol);
0126 static int eqmode_put(struct snd_kcontrol *kcontrol,
0127               struct snd_ctl_elem_value *ucontrol);
0128 
0129 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
0130 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
0131 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
0132 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
0133 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
0134 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
0135 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
0136 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
0137 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
0138 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
0139 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0140 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
0141 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
0142 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
0143 
0144 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
0145 static SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, alc_sel_text);
0146 
0147 static const char *alc_mode_text[] = { "ALC", "Limiter" };
0148 static SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, alc_mode_text);
0149 
0150 static const char *filter_mode_text[] = { "Audio", "Application" };
0151 static SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
0152                 filter_mode_text);
0153 
0154 static const char *eq_bw_text[] = { "Narrow", "Wide" };
0155 static const char *eqmode_text[] = { "Capture", "Playback" };
0156 static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
0157 
0158 static const char *eq1_cutoff_text[] = {
0159     "80Hz", "105Hz", "135Hz", "175Hz"
0160 };
0161 static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
0162                 eq1_cutoff_text);
0163 static const char *eq2_cutoff_text[] = {
0164     "230Hz", "300Hz", "385Hz", "500Hz"
0165 };
0166 static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
0167 static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, eq2_cutoff_text);
0168 static const char *eq3_cutoff_text[] = {
0169     "650Hz", "850Hz", "1.1kHz", "1.4kHz"
0170 };
0171 static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
0172 static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, eq3_cutoff_text);
0173 static const char *eq4_cutoff_text[] = {
0174     "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
0175 };
0176 static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
0177 static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, eq4_cutoff_text);
0178 static const char *eq5_cutoff_text[] = {
0179     "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
0180 };
0181 static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
0182                 eq5_cutoff_text);
0183 
0184 static const char *depth_3d_text[] = {
0185     "Off",
0186     "6.67%",
0187     "13.3%",
0188     "20%",
0189     "26.7%",
0190     "33.3%",
0191     "40%",
0192     "46.6%",
0193     "53.3%",
0194     "60%",
0195     "66.7%",
0196     "73.3%",
0197     "80%",
0198     "86.7%",
0199     "93.3%",
0200     "100%"
0201 };
0202 static SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
0203                 depth_3d_text);
0204 
0205 static const struct snd_kcontrol_new wm8983_snd_controls[] = {
0206     SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
0207            0, 1, 0),
0208 
0209     SOC_ENUM("ALC Capture Function", alc_sel),
0210     SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
0211                3, 7, 0, alc_max_tlv),
0212     SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
0213                0, 7, 0, alc_min_tlv),
0214     SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
0215                0, 15, 0, alc_tar_tlv),
0216     SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
0217     SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
0218     SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
0219     SOC_ENUM("ALC Mode", alc_mode),
0220     SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
0221            3, 1, 0),
0222     SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
0223            0, 7, 1),
0224 
0225     SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
0226              WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
0227     SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
0228              WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
0229     SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
0230              WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
0231 
0232     SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
0233              WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
0234              8, 1, 0, pga_boost_tlv),
0235 
0236     SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
0237     SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
0238 
0239     SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
0240              WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
0241 
0242     SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
0243     SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
0244     SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
0245     SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
0246                4, 7, 1, lim_thresh_tlv),
0247     SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
0248                0, 12, 0, lim_boost_tlv),
0249     SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
0250     SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
0251     SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
0252 
0253     SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
0254              WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
0255     SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
0256              WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
0257     SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
0258              WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
0259 
0260     SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
0261              WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
0262     SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
0263              WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
0264     SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
0265              WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
0266 
0267     SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
0268            6, 1, 1),
0269 
0270     SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
0271            6, 1, 1),
0272 
0273     SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
0274     SOC_ENUM("High Pass Filter Mode", filter_mode),
0275     SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
0276 
0277     SOC_DOUBLE_R_TLV("Aux Bypass Volume",
0278              WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
0279              aux_tlv),
0280 
0281     SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
0282              WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
0283              bypass_tlv),
0284 
0285     SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
0286     SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
0287     SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
0288     SOC_ENUM("EQ2 Bandwidth", eq2_bw),
0289     SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
0290     SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
0291     SOC_ENUM("EQ3 Bandwidth", eq3_bw),
0292     SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
0293     SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
0294     SOC_ENUM("EQ4 Bandwidth", eq4_bw),
0295     SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
0296     SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
0297     SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
0298     SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
0299 
0300     SOC_ENUM("3D Depth", depth_3d),
0301 };
0302 
0303 static const struct snd_kcontrol_new left_out_mixer[] = {
0304     SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
0305     SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
0306     SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
0307 };
0308 
0309 static const struct snd_kcontrol_new right_out_mixer[] = {
0310     SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
0311     SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
0312     SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
0313 };
0314 
0315 static const struct snd_kcontrol_new left_input_mixer[] = {
0316     SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
0317     SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
0318     SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
0319 };
0320 
0321 static const struct snd_kcontrol_new right_input_mixer[] = {
0322     SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
0323     SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
0324     SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
0325 };
0326 
0327 static const struct snd_kcontrol_new left_boost_mixer[] = {
0328     SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
0329                 4, 7, 0, boost_tlv),
0330     SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
0331                 0, 7, 0, boost_tlv)
0332 };
0333 
0334 static const struct snd_kcontrol_new out3_mixer[] = {
0335     SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
0336             1, 1, 0),
0337     SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
0338             0, 1, 0),
0339 };
0340 
0341 static const struct snd_kcontrol_new out4_mixer[] = {
0342     SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
0343             4, 1, 0),
0344     SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
0345             1, 1, 0),
0346     SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
0347             3, 1, 0),
0348     SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
0349             0, 1, 0),
0350 };
0351 
0352 static const struct snd_kcontrol_new right_boost_mixer[] = {
0353     SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
0354                 4, 7, 0, boost_tlv),
0355     SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
0356                 0, 7, 0, boost_tlv)
0357 };
0358 
0359 static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
0360     SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
0361              0, 0),
0362     SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
0363              1, 0),
0364     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
0365              0, 0),
0366     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
0367              1, 0),
0368 
0369     SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
0370                2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
0371     SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
0372                3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
0373 
0374     SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
0375                2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
0376     SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
0377                3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
0378 
0379     SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
0380                4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
0381     SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
0382                5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
0383 
0384     SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
0385                6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
0386 
0387     SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
0388                7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
0389 
0390     SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
0391              6, 1, NULL, 0),
0392     SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
0393              6, 1, NULL, 0),
0394 
0395     SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
0396              7, 0, NULL, 0),
0397     SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
0398              8, 0, NULL, 0),
0399 
0400     SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
0401              5, 0, NULL, 0),
0402     SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
0403              6, 0, NULL, 0),
0404 
0405     SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
0406              7, 0, NULL, 0),
0407 
0408     SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
0409              8, 0, NULL, 0),
0410 
0411     SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0,
0412                 NULL, 0),
0413 
0414     SND_SOC_DAPM_INPUT("LIN"),
0415     SND_SOC_DAPM_INPUT("LIP"),
0416     SND_SOC_DAPM_INPUT("RIN"),
0417     SND_SOC_DAPM_INPUT("RIP"),
0418     SND_SOC_DAPM_INPUT("AUXL"),
0419     SND_SOC_DAPM_INPUT("AUXR"),
0420     SND_SOC_DAPM_INPUT("L2"),
0421     SND_SOC_DAPM_INPUT("R2"),
0422     SND_SOC_DAPM_OUTPUT("HPL"),
0423     SND_SOC_DAPM_OUTPUT("HPR"),
0424     SND_SOC_DAPM_OUTPUT("SPKL"),
0425     SND_SOC_DAPM_OUTPUT("SPKR"),
0426     SND_SOC_DAPM_OUTPUT("OUT3"),
0427     SND_SOC_DAPM_OUTPUT("OUT4")
0428 };
0429 
0430 static const struct snd_soc_dapm_route wm8983_audio_map[] = {
0431     { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
0432     { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
0433 
0434     { "OUT3 Out", NULL, "OUT3 Mixer" },
0435     { "OUT3", NULL, "OUT3 Out" },
0436 
0437     { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
0438     { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
0439     { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
0440     { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
0441 
0442     { "OUT4 Out", NULL, "OUT4 Mixer" },
0443     { "OUT4", NULL, "OUT4 Out" },
0444 
0445     { "Right Output Mixer", "PCM Switch", "Right DAC" },
0446     { "Right Output Mixer", "Aux Switch", "AUXR" },
0447     { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
0448 
0449     { "Left Output Mixer", "PCM Switch", "Left DAC" },
0450     { "Left Output Mixer", "Aux Switch", "AUXL" },
0451     { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
0452 
0453     { "Right Headphone Out", NULL, "Right Output Mixer" },
0454     { "HPR", NULL, "Right Headphone Out" },
0455 
0456     { "Left Headphone Out", NULL, "Left Output Mixer" },
0457     { "HPL", NULL, "Left Headphone Out" },
0458 
0459     { "Right Speaker Out", NULL, "Right Output Mixer" },
0460     { "SPKR", NULL, "Right Speaker Out" },
0461 
0462     { "Left Speaker Out", NULL, "Left Output Mixer" },
0463     { "SPKL", NULL, "Left Speaker Out" },
0464 
0465     { "Right ADC", NULL, "Right Boost Mixer" },
0466 
0467     { "Right Boost Mixer", "AUXR Volume", "AUXR" },
0468     { "Right Boost Mixer", NULL, "Right Capture PGA" },
0469     { "Right Boost Mixer", "R2 Volume", "R2" },
0470 
0471     { "Left ADC", NULL, "Left Boost Mixer" },
0472 
0473     { "Left Boost Mixer", "AUXL Volume", "AUXL" },
0474     { "Left Boost Mixer", NULL, "Left Capture PGA" },
0475     { "Left Boost Mixer", "L2 Volume", "L2" },
0476 
0477     { "Right Capture PGA", NULL, "Right Input Mixer" },
0478     { "Left Capture PGA", NULL, "Left Input Mixer" },
0479 
0480     { "Right Input Mixer", "R2 Switch", "R2" },
0481     { "Right Input Mixer", "MicN Switch", "RIN" },
0482     { "Right Input Mixer", "MicP Switch", "RIP" },
0483 
0484     { "Left Input Mixer", "L2 Switch", "L2" },
0485     { "Left Input Mixer", "MicN Switch", "LIN" },
0486     { "Left Input Mixer", "MicP Switch", "LIP" },
0487 };
0488 
0489 static int eqmode_get(struct snd_kcontrol *kcontrol,
0490               struct snd_ctl_elem_value *ucontrol)
0491 {
0492     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0493     unsigned int reg;
0494 
0495     reg = snd_soc_component_read(component, WM8983_EQ1_LOW_SHELF);
0496     if (reg & WM8983_EQ3DMODE)
0497         ucontrol->value.enumerated.item[0] = 1;
0498     else
0499         ucontrol->value.enumerated.item[0] = 0;
0500 
0501     return 0;
0502 }
0503 
0504 static int eqmode_put(struct snd_kcontrol *kcontrol,
0505               struct snd_ctl_elem_value *ucontrol)
0506 {
0507     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0508     unsigned int regpwr2, regpwr3;
0509     unsigned int reg_eq;
0510 
0511     if (ucontrol->value.enumerated.item[0] != 0
0512         && ucontrol->value.enumerated.item[0] != 1)
0513         return -EINVAL;
0514 
0515     reg_eq = snd_soc_component_read(component, WM8983_EQ1_LOW_SHELF);
0516     switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
0517     case 0:
0518         if (!ucontrol->value.enumerated.item[0])
0519             return 0;
0520         break;
0521     case 1:
0522         if (ucontrol->value.enumerated.item[0])
0523             return 0;
0524         break;
0525     }
0526 
0527     regpwr2 = snd_soc_component_read(component, WM8983_POWER_MANAGEMENT_2);
0528     regpwr3 = snd_soc_component_read(component, WM8983_POWER_MANAGEMENT_3);
0529     /* disable the DACs and ADCs */
0530     snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_2,
0531                 WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
0532     snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_3,
0533                 WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
0534     /* set the desired eqmode */
0535     snd_soc_component_update_bits(component, WM8983_EQ1_LOW_SHELF,
0536                 WM8983_EQ3DMODE_MASK,
0537                 ucontrol->value.enumerated.item[0]
0538                 << WM8983_EQ3DMODE_SHIFT);
0539     /* restore DAC/ADC configuration */
0540     snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_2, regpwr2);
0541     snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_3, regpwr3);
0542     return 0;
0543 }
0544 
0545 static bool wm8983_writeable(struct device *dev, unsigned int reg)
0546 {
0547     switch (reg) {
0548     case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL:
0549     case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2:
0550     case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4:
0551     case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3:
0552     case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL:
0553     case WM8983_BIAS_CTRL:
0554         return true;
0555     default:
0556         return false;
0557     }
0558 }
0559 
0560 static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute, int direction)
0561 {
0562     struct snd_soc_component *component = dai->component;
0563 
0564     return snd_soc_component_update_bits(component, WM8983_DAC_CONTROL,
0565                    WM8983_SOFTMUTE_MASK,
0566                    !!mute << WM8983_SOFTMUTE_SHIFT);
0567 }
0568 
0569 static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0570 {
0571     struct snd_soc_component *component = dai->component;
0572     u16 format, master, bcp, lrp;
0573 
0574     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0575     case SND_SOC_DAIFMT_I2S:
0576         format = 0x2;
0577         break;
0578     case SND_SOC_DAIFMT_RIGHT_J:
0579         format = 0x0;
0580         break;
0581     case SND_SOC_DAIFMT_LEFT_J:
0582         format = 0x1;
0583         break;
0584     case SND_SOC_DAIFMT_DSP_A:
0585     case SND_SOC_DAIFMT_DSP_B:
0586         format = 0x3;
0587         break;
0588     default:
0589         dev_err(dai->dev, "Unknown dai format\n");
0590         return -EINVAL;
0591     }
0592 
0593     snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
0594                 WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
0595 
0596     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0597     case SND_SOC_DAIFMT_CBM_CFM:
0598         master = 1;
0599         break;
0600     case SND_SOC_DAIFMT_CBS_CFS:
0601         master = 0;
0602         break;
0603     default:
0604         dev_err(dai->dev, "Unknown master/slave configuration\n");
0605         return -EINVAL;
0606     }
0607 
0608     snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
0609                 WM8983_MS_MASK, master << WM8983_MS_SHIFT);
0610 
0611     /* FIXME: We don't currently support DSP A/B modes */
0612     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0613     case SND_SOC_DAIFMT_DSP_A:
0614     case SND_SOC_DAIFMT_DSP_B:
0615         dev_err(dai->dev, "DSP A/B modes are not supported\n");
0616         return -EINVAL;
0617     default:
0618         break;
0619     }
0620 
0621     bcp = lrp = 0;
0622     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0623     case SND_SOC_DAIFMT_NB_NF:
0624         break;
0625     case SND_SOC_DAIFMT_IB_IF:
0626         bcp = lrp = 1;
0627         break;
0628     case SND_SOC_DAIFMT_IB_NF:
0629         bcp = 1;
0630         break;
0631     case SND_SOC_DAIFMT_NB_IF:
0632         lrp = 1;
0633         break;
0634     default:
0635         dev_err(dai->dev, "Unknown polarity configuration\n");
0636         return -EINVAL;
0637     }
0638 
0639     snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
0640                 WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
0641     snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
0642                 WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
0643     return 0;
0644 }
0645 
0646 static int wm8983_hw_params(struct snd_pcm_substream *substream,
0647                 struct snd_pcm_hw_params *params,
0648                 struct snd_soc_dai *dai)
0649 {
0650     int i;
0651     struct snd_soc_component *component = dai->component;
0652     struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
0653     u16 blen, srate_idx;
0654     u32 tmp;
0655     int srate_best;
0656     int ret;
0657 
0658     ret = snd_soc_params_to_bclk(params);
0659     if (ret < 0) {
0660         dev_err(component->dev, "Failed to convert params to bclk: %d\n", ret);
0661         return ret;
0662     }
0663 
0664     wm8983->bclk = ret;
0665 
0666     switch (params_width(params)) {
0667     case 16:
0668         blen = 0x0;
0669         break;
0670     case 20:
0671         blen = 0x1;
0672         break;
0673     case 24:
0674         blen = 0x2;
0675         break;
0676     case 32:
0677         blen = 0x3;
0678         break;
0679     default:
0680         dev_err(dai->dev, "Unsupported word length %u\n",
0681             params_width(params));
0682         return -EINVAL;
0683     }
0684 
0685     snd_soc_component_update_bits(component, WM8983_AUDIO_INTERFACE,
0686                 WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
0687 
0688     /*
0689      * match to the nearest possible sample rate and rely
0690      * on the array index to configure the SR register
0691      */
0692     srate_idx = 0;
0693     srate_best = abs(srates[0] - params_rate(params));
0694     for (i = 1; i < ARRAY_SIZE(srates); ++i) {
0695         if (abs(srates[i] - params_rate(params)) >= srate_best)
0696             continue;
0697         srate_idx = i;
0698         srate_best = abs(srates[i] - params_rate(params));
0699     }
0700 
0701     dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
0702     snd_soc_component_update_bits(component, WM8983_ADDITIONAL_CONTROL,
0703                 WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
0704 
0705     dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
0706     dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
0707 
0708     for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
0709         if (wm8983->sysclk / params_rate(params)
0710             == fs_ratios[i].ratio)
0711             break;
0712     }
0713 
0714     if (i == ARRAY_SIZE(fs_ratios)) {
0715         dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
0716             wm8983->sysclk, params_rate(params));
0717         return -EINVAL;
0718     }
0719 
0720     dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
0721     snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
0722                 WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
0723 
0724     /* select the appropriate bclk divider */
0725     tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
0726     for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
0727         if (wm8983->bclk == tmp / bclk_divs[i])
0728             break;
0729     }
0730 
0731     if (i == ARRAY_SIZE(bclk_divs)) {
0732         dev_err(dai->dev, "No matching BCLK divider found\n");
0733         return -EINVAL;
0734     }
0735 
0736     dev_dbg(dai->dev, "BCLK div = %d\n", i);
0737     snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
0738                 WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
0739 
0740     return 0;
0741 }
0742 
0743 struct pll_div {
0744     u32 div2:1;
0745     u32 n:4;
0746     u32 k:24;
0747 };
0748 
0749 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
0750 static int pll_factors(struct pll_div *pll_div, unsigned int target,
0751                unsigned int source)
0752 {
0753     u64 Kpart;
0754     unsigned long int K, Ndiv, Nmod;
0755 
0756     pll_div->div2 = 0;
0757     Ndiv = target / source;
0758     if (Ndiv < 6) {
0759         source >>= 1;
0760         pll_div->div2 = 1;
0761         Ndiv = target / source;
0762     }
0763 
0764     if (Ndiv < 6 || Ndiv > 12) {
0765         printk(KERN_ERR "%s: WM8983 N value is not within"
0766                " the recommended range: %lu\n", __func__, Ndiv);
0767         return -EINVAL;
0768     }
0769     pll_div->n = Ndiv;
0770 
0771     Nmod = target % source;
0772     Kpart = FIXED_PLL_SIZE * (u64)Nmod;
0773 
0774     do_div(Kpart, source);
0775 
0776     K = Kpart & 0xffffffff;
0777     if ((K % 10) >= 5)
0778         K += 5;
0779     K /= 10;
0780     pll_div->k = K;
0781     return 0;
0782 }
0783 
0784 static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
0785               int source, unsigned int freq_in,
0786               unsigned int freq_out)
0787 {
0788     int ret;
0789     struct snd_soc_component *component;
0790     struct pll_div pll_div;
0791 
0792     component = dai->component;
0793     if (!freq_in || !freq_out) {
0794         /* disable the PLL */
0795         snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0796                     WM8983_PLLEN_MASK, 0);
0797         return 0;
0798     } else {
0799         ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
0800         if (ret)
0801             return ret;
0802 
0803         /* disable the PLL before re-programming it */
0804         snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0805                     WM8983_PLLEN_MASK, 0);
0806 
0807         /* set PLLN and PRESCALE */
0808         snd_soc_component_write(component, WM8983_PLL_N,
0809             (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
0810             | pll_div.n);
0811         /* set PLLK */
0812         snd_soc_component_write(component, WM8983_PLL_K_3, pll_div.k & 0x1ff);
0813         snd_soc_component_write(component, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
0814         snd_soc_component_write(component, WM8983_PLL_K_1, (pll_div.k >> 18));
0815         /* enable the PLL */
0816         snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0817                     WM8983_PLLEN_MASK, WM8983_PLLEN);
0818     }
0819 
0820     return 0;
0821 }
0822 
0823 static int wm8983_set_sysclk(struct snd_soc_dai *dai,
0824                  int clk_id, unsigned int freq, int dir)
0825 {
0826     struct snd_soc_component *component = dai->component;
0827     struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
0828 
0829     switch (clk_id) {
0830     case WM8983_CLKSRC_MCLK:
0831         snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
0832                     WM8983_CLKSEL_MASK, 0);
0833         break;
0834     case WM8983_CLKSRC_PLL:
0835         snd_soc_component_update_bits(component, WM8983_CLOCK_GEN_CONTROL,
0836                     WM8983_CLKSEL_MASK, WM8983_CLKSEL);
0837         break;
0838     default:
0839         dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
0840         return -EINVAL;
0841     }
0842 
0843     wm8983->sysclk = freq;
0844     return 0;
0845 }
0846 
0847 static int wm8983_set_bias_level(struct snd_soc_component *component,
0848                  enum snd_soc_bias_level level)
0849 {
0850     struct wm8983_priv *wm8983 = snd_soc_component_get_drvdata(component);
0851     int ret;
0852 
0853     switch (level) {
0854     case SND_SOC_BIAS_ON:
0855     case SND_SOC_BIAS_PREPARE:
0856         /* VMID at 100k */
0857         snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0858                     WM8983_VMIDSEL_MASK,
0859                     1 << WM8983_VMIDSEL_SHIFT);
0860         break;
0861     case SND_SOC_BIAS_STANDBY:
0862         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0863             ret = regcache_sync(wm8983->regmap);
0864             if (ret < 0) {
0865                 dev_err(component->dev, "Failed to sync cache: %d\n", ret);
0866                 return ret;
0867             }
0868             /* enable anti-pop features */
0869             snd_soc_component_update_bits(component, WM8983_OUT4_TO_ADC,
0870                         WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
0871                         WM8983_POBCTRL | WM8983_DELEN);
0872             /* enable thermal shutdown */
0873             snd_soc_component_update_bits(component, WM8983_OUTPUT_CTRL,
0874                         WM8983_TSDEN_MASK, WM8983_TSDEN);
0875             /* enable BIASEN */
0876             snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0877                         WM8983_BIASEN_MASK, WM8983_BIASEN);
0878             /* VMID at 100k */
0879             snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0880                         WM8983_VMIDSEL_MASK,
0881                         1 << WM8983_VMIDSEL_SHIFT);
0882             msleep(250);
0883             /* disable anti-pop features */
0884             snd_soc_component_update_bits(component, WM8983_OUT4_TO_ADC,
0885                         WM8983_POBCTRL_MASK |
0886                         WM8983_DELEN_MASK, 0);
0887         }
0888 
0889         /* VMID at 500k */
0890         snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0891                     WM8983_VMIDSEL_MASK,
0892                     2 << WM8983_VMIDSEL_SHIFT);
0893         break;
0894     case SND_SOC_BIAS_OFF:
0895         /* disable thermal shutdown */
0896         snd_soc_component_update_bits(component, WM8983_OUTPUT_CTRL,
0897                     WM8983_TSDEN_MASK, 0);
0898         /* disable VMIDSEL and BIASEN */
0899         snd_soc_component_update_bits(component, WM8983_POWER_MANAGEMENT_1,
0900                     WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
0901                     0);
0902         /* wait for VMID to discharge */
0903         msleep(100);
0904         snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_1, 0);
0905         snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_2, 0);
0906         snd_soc_component_write(component, WM8983_POWER_MANAGEMENT_3, 0);
0907         break;
0908     }
0909 
0910     return 0;
0911 }
0912 
0913 static int wm8983_probe(struct snd_soc_component *component)
0914 {
0915     int ret;
0916     int i;
0917 
0918     ret = snd_soc_component_write(component, WM8983_SOFTWARE_RESET, 0);
0919     if (ret < 0) {
0920         dev_err(component->dev, "Failed to issue reset: %d\n", ret);
0921         return ret;
0922     }
0923 
0924     /* set the vol/gain update bits */
0925     for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
0926         snd_soc_component_update_bits(component, vol_update_regs[i],
0927                     0x100, 0x100);
0928 
0929     /* mute all outputs and set PGAs to minimum gain */
0930     for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
0931          i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
0932         snd_soc_component_update_bits(component, i, 0x40, 0x40);
0933 
0934     /* enable soft mute */
0935     snd_soc_component_update_bits(component, WM8983_DAC_CONTROL,
0936                 WM8983_SOFTMUTE_MASK,
0937                 WM8983_SOFTMUTE);
0938 
0939     /* enable BIASCUT */
0940     snd_soc_component_update_bits(component, WM8983_BIAS_CTRL,
0941                 WM8983_BIASCUT, WM8983_BIASCUT);
0942     return 0;
0943 }
0944 
0945 static const struct snd_soc_dai_ops wm8983_dai_ops = {
0946     .mute_stream = wm8983_dac_mute,
0947     .hw_params = wm8983_hw_params,
0948     .set_fmt = wm8983_set_fmt,
0949     .set_sysclk = wm8983_set_sysclk,
0950     .set_pll = wm8983_set_pll,
0951     .no_capture_mute = 1,
0952 };
0953 
0954 #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0955             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0956 
0957 static struct snd_soc_dai_driver wm8983_dai = {
0958     .name = "wm8983-hifi",
0959     .playback = {
0960         .stream_name = "Playback",
0961         .channels_min = 2,
0962         .channels_max = 2,
0963         .rates = SNDRV_PCM_RATE_8000_48000,
0964         .formats = WM8983_FORMATS,
0965     },
0966     .capture = {
0967         .stream_name = "Capture",
0968         .channels_min = 2,
0969         .channels_max = 2,
0970         .rates = SNDRV_PCM_RATE_8000_48000,
0971         .formats = WM8983_FORMATS,
0972     },
0973     .ops = &wm8983_dai_ops,
0974     .symmetric_rate = 1
0975 };
0976 
0977 static const struct snd_soc_component_driver soc_component_dev_wm8983 = {
0978     .probe          = wm8983_probe,
0979     .set_bias_level     = wm8983_set_bias_level,
0980     .controls       = wm8983_snd_controls,
0981     .num_controls       = ARRAY_SIZE(wm8983_snd_controls),
0982     .dapm_widgets       = wm8983_dapm_widgets,
0983     .num_dapm_widgets   = ARRAY_SIZE(wm8983_dapm_widgets),
0984     .dapm_routes        = wm8983_audio_map,
0985     .num_dapm_routes    = ARRAY_SIZE(wm8983_audio_map),
0986     .suspend_bias_off   = 1,
0987     .idle_bias_on       = 1,
0988     .use_pmdown_time    = 1,
0989     .endianness     = 1,
0990 };
0991 
0992 static const struct regmap_config wm8983_regmap = {
0993     .reg_bits = 7,
0994     .val_bits = 9,
0995 
0996     .reg_defaults = wm8983_defaults,
0997     .num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
0998     .cache_type = REGCACHE_RBTREE,
0999     .max_register = WM8983_MAX_REGISTER,
1000 
1001     .writeable_reg = wm8983_writeable,
1002 };
1003 
1004 #if defined(CONFIG_SPI_MASTER)
1005 static int wm8983_spi_probe(struct spi_device *spi)
1006 {
1007     struct wm8983_priv *wm8983;
1008     int ret;
1009 
1010     wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL);
1011     if (!wm8983)
1012         return -ENOMEM;
1013 
1014     wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap);
1015     if (IS_ERR(wm8983->regmap)) {
1016         ret = PTR_ERR(wm8983->regmap);
1017         dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
1018         return ret;
1019     }
1020 
1021     spi_set_drvdata(spi, wm8983);
1022 
1023     ret = devm_snd_soc_register_component(&spi->dev,
1024                 &soc_component_dev_wm8983, &wm8983_dai, 1);
1025     return ret;
1026 }
1027 
1028 static struct spi_driver wm8983_spi_driver = {
1029     .driver = {
1030         .name = "wm8983",
1031     },
1032     .probe = wm8983_spi_probe,
1033 };
1034 #endif
1035 
1036 #if IS_ENABLED(CONFIG_I2C)
1037 static int wm8983_i2c_probe(struct i2c_client *i2c)
1038 {
1039     struct wm8983_priv *wm8983;
1040     int ret;
1041 
1042     wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL);
1043     if (!wm8983)
1044         return -ENOMEM;
1045 
1046     wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap);
1047     if (IS_ERR(wm8983->regmap)) {
1048         ret = PTR_ERR(wm8983->regmap);
1049         dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1050         return ret;
1051     }
1052 
1053     i2c_set_clientdata(i2c, wm8983);
1054 
1055     ret = devm_snd_soc_register_component(&i2c->dev,
1056                 &soc_component_dev_wm8983, &wm8983_dai, 1);
1057 
1058     return ret;
1059 }
1060 
1061 static const struct i2c_device_id wm8983_i2c_id[] = {
1062     { "wm8983", 0 },
1063     { }
1064 };
1065 MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
1066 
1067 static struct i2c_driver wm8983_i2c_driver = {
1068     .driver = {
1069         .name = "wm8983",
1070     },
1071     .probe_new = wm8983_i2c_probe,
1072     .id_table = wm8983_i2c_id
1073 };
1074 #endif
1075 
1076 static int __init wm8983_modinit(void)
1077 {
1078     int ret = 0;
1079 
1080 #if IS_ENABLED(CONFIG_I2C)
1081     ret = i2c_add_driver(&wm8983_i2c_driver);
1082     if (ret) {
1083         printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
1084                ret);
1085     }
1086 #endif
1087 #if defined(CONFIG_SPI_MASTER)
1088     ret = spi_register_driver(&wm8983_spi_driver);
1089     if (ret != 0) {
1090         printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
1091                ret);
1092     }
1093 #endif
1094     return ret;
1095 }
1096 module_init(wm8983_modinit);
1097 
1098 static void __exit wm8983_exit(void)
1099 {
1100 #if IS_ENABLED(CONFIG_I2C)
1101     i2c_del_driver(&wm8983_i2c_driver);
1102 #endif
1103 #if defined(CONFIG_SPI_MASTER)
1104     spi_unregister_driver(&wm8983_spi_driver);
1105 #endif
1106 }
1107 module_exit(wm8983_exit);
1108 
1109 MODULE_DESCRIPTION("ASoC WM8983 driver");
1110 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1111 MODULE_LICENSE("GPL");
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