soc/codecs/wm8974.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * wm8974.h  --  WM8974 Soc Audio driver
0004  */
0005
0006 #ifndef _WM8974_H
0007 #define _WM8974_H
0008
0009 /* WM8974 register space */
0010
0011 #define WM8974_RESET        0x0
0012 #define WM8974_POWER1       0x1
0013 #define WM8974_POWER2       0x2
0014 #define WM8974_POWER3       0x3
0015 #define WM8974_IFACE        0x4
0016 #define WM8974_COMP     0x5
0017 #define WM8974_CLOCK        0x6
0018 #define WM8974_ADD      0x7
0019 #define WM8974_GPIO     0x8
0020 #define WM8974_DAC      0xa
0021 #define WM8974_DACVOL       0xb
0022 #define WM8974_ADC      0xe
0023 #define WM8974_ADCVOL       0xf
0024 #define WM8974_EQ1      0x12
0025 #define WM8974_EQ2      0x13
0026 #define WM8974_EQ3      0x14
0027 #define WM8974_EQ4      0x15
0028 #define WM8974_EQ5      0x16
0029 #define WM8974_DACLIM1      0x18
0030 #define WM8974_DACLIM2      0x19
0031 #define WM8974_NOTCH1       0x1b
0032 #define WM8974_NOTCH2       0x1c
0033 #define WM8974_NOTCH3       0x1d
0034 #define WM8974_NOTCH4       0x1e
0035 #define WM8974_ALC1     0x20
0036 #define WM8974_ALC2     0x21
0037 #define WM8974_ALC3     0x22
0038 #define WM8974_NGATE        0x23
0039 #define WM8974_PLLN     0x24
0040 #define WM8974_PLLK1        0x25
0041 #define WM8974_PLLK2        0x26
0042 #define WM8974_PLLK3        0x27
0043 #define WM8974_ATTEN        0x28
0044 #define WM8974_INPUT        0x2c
0045 #define WM8974_INPPGA       0x2d
0046 #define WM8974_ADCBOOST     0x2f
0047 #define WM8974_OUTPUT       0x31
0048 #define WM8974_SPKMIX       0x32
0049 #define WM8974_SPKVOL       0x36
0050 #define WM8974_MONOMIX      0x38
0051
0052 #define WM8974_CACHEREGNUM  57
0053
0054 /* Clock divider Id's */
0055 #define WM8974_OPCLKDIV     0
0056 #define WM8974_MCLKDIV      1
0057 #define WM8974_BCLKDIV      2
0058
0059 /* PLL Out dividers */
0060 #define WM8974_OPCLKDIV_1   (0 << 4)
0061 #define WM8974_OPCLKDIV_2   (1 << 4)
0062 #define WM8974_OPCLKDIV_3   (2 << 4)
0063 #define WM8974_OPCLKDIV_4   (3 << 4)
0064
0065 /* BCLK clock dividers */
0066 #define WM8974_BCLKDIV_1    (0 << 2)
0067 #define WM8974_BCLKDIV_2    (1 << 2)
0068 #define WM8974_BCLKDIV_4    (2 << 2)
0069 #define WM8974_BCLKDIV_8    (3 << 2)
0070 #define WM8974_BCLKDIV_16   (4 << 2)
0071 #define WM8974_BCLKDIV_32   (5 << 2)
0072
0073 /* MCLK clock dividers */
0074 #define WM8974_MCLKDIV_1    (0 << 5)
0075 #define WM8974_MCLKDIV_1_5  (1 << 5)
0076 #define WM8974_MCLKDIV_2    (2 << 5)
0077 #define WM8974_MCLKDIV_3    (3 << 5)
0078 #define WM8974_MCLKDIV_4    (4 << 5)
0079 #define WM8974_MCLKDIV_6    (5 << 5)
0080 #define WM8974_MCLKDIV_8    (6 << 5)
0081 #define WM8974_MCLKDIV_12   (7 << 5)
0082
0083 #endif