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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8962.c  --  WM8962 ALSA SoC Audio driver
0004  *
0005  * Copyright 2010-2 Wolfson Microelectronics plc
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/pm.h>
0016 #include <linux/gcd.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/i2c.h>
0019 #include <linux/input.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/regmap.h>
0022 #include <linux/regulator/consumer.h>
0023 #include <linux/slab.h>
0024 #include <linux/workqueue.h>
0025 #include <linux/mutex.h>
0026 #include <sound/core.h>
0027 #include <sound/jack.h>
0028 #include <sound/pcm.h>
0029 #include <sound/pcm_params.h>
0030 #include <sound/soc.h>
0031 #include <sound/initval.h>
0032 #include <sound/tlv.h>
0033 #include <sound/wm8962.h>
0034 #include <trace/events/asoc.h>
0035 
0036 #include "wm8962.h"
0037 
0038 #define WM8962_NUM_SUPPLIES 8
0039 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
0040     "DCVDD",
0041     "DBVDD",
0042     "AVDD",
0043     "CPVDD",
0044     "MICVDD",
0045     "PLLVDD",
0046     "SPKVDD1",
0047     "SPKVDD2",
0048 };
0049 
0050 /* codec private data */
0051 struct wm8962_priv {
0052     struct wm8962_pdata pdata;
0053     struct regmap *regmap;
0054     struct snd_soc_component *component;
0055 
0056     int sysclk;
0057     int sysclk_rate;
0058 
0059     int bclk;  /* Desired BCLK */
0060     int lrclk;
0061 
0062     struct completion fll_lock;
0063     int fll_src;
0064     int fll_fref;
0065     int fll_fout;
0066 
0067     struct mutex dsp2_ena_lock;
0068     u16 dsp2_ena;
0069 
0070     struct delayed_work mic_work;
0071     struct snd_soc_jack *jack;
0072 
0073     struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
0074     struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
0075 
0076     struct input_dev *beep;
0077     struct work_struct beep_work;
0078     int beep_rate;
0079 
0080 #ifdef CONFIG_GPIOLIB
0081     struct gpio_chip gpio_chip;
0082 #endif
0083 
0084     int irq;
0085 };
0086 
0087 /* We can't use the same notifier block for more than one supply and
0088  * there's no way I can see to get from a callback to the caller
0089  * except container_of().
0090  */
0091 #define WM8962_REGULATOR_EVENT(n) \
0092 static int wm8962_regulator_event_##n(struct notifier_block *nb, \
0093                     unsigned long event, void *data)    \
0094 { \
0095     struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
0096                           disable_nb[n]); \
0097     if (event & REGULATOR_EVENT_DISABLE) { \
0098         regcache_mark_dirty(wm8962->regmap);    \
0099     } \
0100     return 0; \
0101 }
0102 
0103 WM8962_REGULATOR_EVENT(0)
0104 WM8962_REGULATOR_EVENT(1)
0105 WM8962_REGULATOR_EVENT(2)
0106 WM8962_REGULATOR_EVENT(3)
0107 WM8962_REGULATOR_EVENT(4)
0108 WM8962_REGULATOR_EVENT(5)
0109 WM8962_REGULATOR_EVENT(6)
0110 WM8962_REGULATOR_EVENT(7)
0111 
0112 static const struct reg_default wm8962_reg[] = {
0113     { 0, 0x009F },   /* R0     - Left Input volume */
0114     { 1, 0x049F },   /* R1     - Right Input volume */
0115     { 2, 0x0000 },   /* R2     - HPOUTL volume */
0116     { 3, 0x0000 },   /* R3     - HPOUTR volume */
0117 
0118     { 5, 0x0018 },   /* R5     - ADC & DAC Control 1 */
0119     { 6, 0x2008 },   /* R6     - ADC & DAC Control 2 */
0120     { 7, 0x000A },   /* R7     - Audio Interface 0 */
0121     { 8, 0x01E4 },   /* R8     - Clocking2 */
0122     { 9, 0x0300 },   /* R9     - Audio Interface 1 */
0123     { 10, 0x00C0 },  /* R10    - Left DAC volume */
0124     { 11, 0x00C0 },  /* R11    - Right DAC volume */
0125 
0126     { 14, 0x0040 },   /* R14    - Audio Interface 2 */
0127     { 15, 0x6243 },   /* R15    - Software Reset */
0128 
0129     { 17, 0x007B },   /* R17    - ALC1 */
0130     { 18, 0x0000 },   /* R18    - ALC2 */
0131     { 19, 0x1C32 },   /* R19    - ALC3 */
0132     { 20, 0x3200 },   /* R20    - Noise Gate */
0133     { 21, 0x00C0 },   /* R21    - Left ADC volume */
0134     { 22, 0x00C0 },   /* R22    - Right ADC volume */
0135     { 23, 0x0160 },   /* R23    - Additional control(1) */
0136     { 24, 0x0000 },   /* R24    - Additional control(2) */
0137     { 25, 0x0000 },   /* R25    - Pwr Mgmt (1) */
0138     { 26, 0x0000 },   /* R26    - Pwr Mgmt (2) */
0139     { 27, 0x0010 },   /* R27    - Additional Control (3) */
0140     { 28, 0x0000 },   /* R28    - Anti-pop */
0141 
0142     { 30, 0x005E },   /* R30    - Clocking 3 */
0143     { 31, 0x0000 },   /* R31    - Input mixer control (1) */
0144     { 32, 0x0145 },   /* R32    - Left input mixer volume */
0145     { 33, 0x0145 },   /* R33    - Right input mixer volume */
0146     { 34, 0x0009 },   /* R34    - Input mixer control (2) */
0147     { 35, 0x0003 },   /* R35    - Input bias control */
0148     { 37, 0x0008 },   /* R37    - Left input PGA control */
0149     { 38, 0x0008 },   /* R38    - Right input PGA control */
0150 
0151     { 40, 0x0000 },   /* R40    - SPKOUTL volume */
0152     { 41, 0x0000 },   /* R41    - SPKOUTR volume */
0153 
0154     { 49, 0x0010 },   /* R49    - Class D Control 1 */
0155     { 51, 0x0003 },   /* R51    - Class D Control 2 */
0156 
0157     { 56, 0x0506 },   /* R56    - Clocking 4 */
0158     { 57, 0x0000 },   /* R57    - DAC DSP Mixing (1) */
0159     { 58, 0x0000 },   /* R58    - DAC DSP Mixing (2) */
0160 
0161     { 60, 0x0300 },   /* R60    - DC Servo 0 */
0162     { 61, 0x0300 },   /* R61    - DC Servo 1 */
0163 
0164     { 64, 0x0810 },   /* R64    - DC Servo 4 */
0165 
0166     { 68, 0x001B },   /* R68    - Analogue PGA Bias */
0167     { 69, 0x0000 },   /* R69    - Analogue HP 0 */
0168 
0169     { 71, 0x01FB },   /* R71    - Analogue HP 2 */
0170     { 72, 0x0000 },   /* R72    - Charge Pump 1 */
0171 
0172     { 82, 0x0004 },   /* R82    - Charge Pump B */
0173 
0174     { 87, 0x0000 },   /* R87    - Write Sequencer Control 1 */
0175 
0176     { 90, 0x0000 },   /* R90    - Write Sequencer Control 2 */
0177 
0178     { 93, 0x0000 },   /* R93    - Write Sequencer Control 3 */
0179     { 94, 0x0000 },   /* R94    - Control Interface */
0180 
0181     { 99, 0x0000 },   /* R99    - Mixer Enables */
0182     { 100, 0x0000 },   /* R100   - Headphone Mixer (1) */
0183     { 101, 0x0000 },   /* R101   - Headphone Mixer (2) */
0184     { 102, 0x013F },   /* R102   - Headphone Mixer (3) */
0185     { 103, 0x013F },   /* R103   - Headphone Mixer (4) */
0186 
0187     { 105, 0x0000 },   /* R105   - Speaker Mixer (1) */
0188     { 106, 0x0000 },   /* R106   - Speaker Mixer (2) */
0189     { 107, 0x013F },   /* R107   - Speaker Mixer (3) */
0190     { 108, 0x013F },   /* R108   - Speaker Mixer (4) */
0191     { 109, 0x0003 },   /* R109   - Speaker Mixer (5) */
0192     { 110, 0x0002 },   /* R110   - Beep Generator (1) */
0193 
0194     { 115, 0x0006 },   /* R115   - Oscillator Trim (3) */
0195     { 116, 0x0026 },   /* R116   - Oscillator Trim (4) */
0196 
0197     { 119, 0x0000 },   /* R119   - Oscillator Trim (7) */
0198 
0199     { 124, 0x0011 },   /* R124   - Analogue Clocking1 */
0200     { 125, 0x004B },   /* R125   - Analogue Clocking2 */
0201     { 126, 0x000D },   /* R126   - Analogue Clocking3 */
0202     { 127, 0x0000 },   /* R127   - PLL Software Reset */
0203 
0204     { 131, 0x0000 },   /* R131   - PLL 4 */
0205 
0206     { 136, 0x0067 },   /* R136   - PLL 9 */
0207     { 137, 0x001C },   /* R137   - PLL 10 */
0208     { 138, 0x0071 },   /* R138   - PLL 11 */
0209     { 139, 0x00C7 },   /* R139   - PLL 12 */
0210     { 140, 0x0067 },   /* R140   - PLL 13 */
0211     { 141, 0x0048 },   /* R141   - PLL 14 */
0212     { 142, 0x0022 },   /* R142   - PLL 15 */
0213     { 143, 0x0097 },   /* R143   - PLL 16 */
0214 
0215     { 155, 0x000C },   /* R155   - FLL Control (1) */
0216     { 156, 0x0039 },   /* R156   - FLL Control (2) */
0217     { 157, 0x0180 },   /* R157   - FLL Control (3) */
0218 
0219     { 159, 0x0032 },   /* R159   - FLL Control (5) */
0220     { 160, 0x0018 },   /* R160   - FLL Control (6) */
0221     { 161, 0x007D },   /* R161   - FLL Control (7) */
0222     { 162, 0x0008 },   /* R162   - FLL Control (8) */
0223 
0224     { 252, 0x0005 },   /* R252   - General test 1 */
0225 
0226     { 256, 0x0000 },   /* R256   - DF1 */
0227     { 257, 0x0000 },   /* R257   - DF2 */
0228     { 258, 0x0000 },   /* R258   - DF3 */
0229     { 259, 0x0000 },   /* R259   - DF4 */
0230     { 260, 0x0000 },   /* R260   - DF5 */
0231     { 261, 0x0000 },   /* R261   - DF6 */
0232     { 262, 0x0000 },   /* R262   - DF7 */
0233 
0234     { 264, 0x0000 },   /* R264   - LHPF1 */
0235     { 265, 0x0000 },   /* R265   - LHPF2 */
0236 
0237     { 268, 0x0000 },   /* R268   - THREED1 */
0238     { 269, 0x0000 },   /* R269   - THREED2 */
0239     { 270, 0x0000 },   /* R270   - THREED3 */
0240     { 271, 0x0000 },   /* R271   - THREED4 */
0241 
0242     { 276, 0x000C },   /* R276   - DRC 1 */
0243     { 277, 0x0925 },   /* R277   - DRC 2 */
0244     { 278, 0x0000 },   /* R278   - DRC 3 */
0245     { 279, 0x0000 },   /* R279   - DRC 4 */
0246     { 280, 0x0000 },   /* R280   - DRC 5 */
0247 
0248     { 285, 0x0000 },   /* R285   - Tloopback */
0249 
0250     { 335, 0x0004 },   /* R335   - EQ1 */
0251     { 336, 0x6318 },   /* R336   - EQ2 */
0252     { 337, 0x6300 },   /* R337   - EQ3 */
0253     { 338, 0x0FCA },   /* R338   - EQ4 */
0254     { 339, 0x0400 },   /* R339   - EQ5 */
0255     { 340, 0x00D8 },   /* R340   - EQ6 */
0256     { 341, 0x1EB5 },   /* R341   - EQ7 */
0257     { 342, 0xF145 },   /* R342   - EQ8 */
0258     { 343, 0x0B75 },   /* R343   - EQ9 */
0259     { 344, 0x01C5 },   /* R344   - EQ10 */
0260     { 345, 0x1C58 },   /* R345   - EQ11 */
0261     { 346, 0xF373 },   /* R346   - EQ12 */
0262     { 347, 0x0A54 },   /* R347   - EQ13 */
0263     { 348, 0x0558 },   /* R348   - EQ14 */
0264     { 349, 0x168E },   /* R349   - EQ15 */
0265     { 350, 0xF829 },   /* R350   - EQ16 */
0266     { 351, 0x07AD },   /* R351   - EQ17 */
0267     { 352, 0x1103 },   /* R352   - EQ18 */
0268     { 353, 0x0564 },   /* R353   - EQ19 */
0269     { 354, 0x0559 },   /* R354   - EQ20 */
0270     { 355, 0x4000 },   /* R355   - EQ21 */
0271     { 356, 0x6318 },   /* R356   - EQ22 */
0272     { 357, 0x6300 },   /* R357   - EQ23 */
0273     { 358, 0x0FCA },   /* R358   - EQ24 */
0274     { 359, 0x0400 },   /* R359   - EQ25 */
0275     { 360, 0x00D8 },   /* R360   - EQ26 */
0276     { 361, 0x1EB5 },   /* R361   - EQ27 */
0277     { 362, 0xF145 },   /* R362   - EQ28 */
0278     { 363, 0x0B75 },   /* R363   - EQ29 */
0279     { 364, 0x01C5 },   /* R364   - EQ30 */
0280     { 365, 0x1C58 },   /* R365   - EQ31 */
0281     { 366, 0xF373 },   /* R366   - EQ32 */
0282     { 367, 0x0A54 },   /* R367   - EQ33 */
0283     { 368, 0x0558 },   /* R368   - EQ34 */
0284     { 369, 0x168E },   /* R369   - EQ35 */
0285     { 370, 0xF829 },   /* R370   - EQ36 */
0286     { 371, 0x07AD },   /* R371   - EQ37 */
0287     { 372, 0x1103 },   /* R372   - EQ38 */
0288     { 373, 0x0564 },   /* R373   - EQ39 */
0289     { 374, 0x0559 },   /* R374   - EQ40 */
0290     { 375, 0x4000 },   /* R375   - EQ41 */
0291 
0292     { 513, 0x0000 },   /* R513   - GPIO 2 */
0293     { 514, 0x0000 },   /* R514   - GPIO 3 */
0294 
0295     { 516, 0x8100 },   /* R516   - GPIO 5 */
0296     { 517, 0x8100 },   /* R517   - GPIO 6 */
0297 
0298     { 568, 0x0030 },   /* R568   - Interrupt Status 1 Mask */
0299     { 569, 0xFFED },   /* R569   - Interrupt Status 2 Mask */
0300 
0301     { 576, 0x0000 },   /* R576   - Interrupt Control */
0302 
0303     { 584, 0x002D },   /* R584   - IRQ Debounce */
0304 
0305     { 586, 0x0000 },   /* R586   -  MICINT Source Pol */
0306 
0307     { 768, 0x1C00 },   /* R768   - DSP2 Power Management */
0308 
0309     { 8192, 0x0000 },   /* R8192  - DSP2 Instruction RAM 0 */
0310 
0311     { 9216, 0x0030 },   /* R9216  - DSP2 Address RAM 2 */
0312     { 9217, 0x0000 },   /* R9217  - DSP2 Address RAM 1 */
0313     { 9218, 0x0000 },   /* R9218  - DSP2 Address RAM 0 */
0314 
0315     { 12288, 0x0000 },   /* R12288 - DSP2 Data1 RAM 1 */
0316     { 12289, 0x0000 },   /* R12289 - DSP2 Data1 RAM 0 */
0317 
0318     { 13312, 0x0000 },   /* R13312 - DSP2 Data2 RAM 1 */
0319     { 13313, 0x0000 },   /* R13313 - DSP2 Data2 RAM 0 */
0320 
0321     { 14336, 0x0000 },   /* R14336 - DSP2 Data3 RAM 1 */
0322     { 14337, 0x0000 },   /* R14337 - DSP2 Data3 RAM 0 */
0323 
0324     { 15360, 0x000A },   /* R15360 - DSP2 Coeff RAM 0 */
0325 
0326     { 16384, 0x0000 },   /* R16384 - RETUNEADC_SHARED_COEFF_1 */
0327     { 16385, 0x0000 },   /* R16385 - RETUNEADC_SHARED_COEFF_0 */
0328     { 16386, 0x0000 },   /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
0329     { 16387, 0x0000 },   /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
0330     { 16388, 0x0000 },   /* R16388 - SOUNDSTAGE_ENABLES_1 */
0331     { 16389, 0x0000 },   /* R16389 - SOUNDSTAGE_ENABLES_0 */
0332 
0333     { 16896, 0x0002 },   /* R16896 - HDBASS_AI_1 */
0334     { 16897, 0xBD12 },   /* R16897 - HDBASS_AI_0 */
0335     { 16898, 0x007C },   /* R16898 - HDBASS_AR_1 */
0336     { 16899, 0x586C },   /* R16899 - HDBASS_AR_0 */
0337     { 16900, 0x0053 },   /* R16900 - HDBASS_B_1 */
0338     { 16901, 0x8121 },   /* R16901 - HDBASS_B_0 */
0339     { 16902, 0x003F },   /* R16902 - HDBASS_K_1 */
0340     { 16903, 0x8BD8 },   /* R16903 - HDBASS_K_0 */
0341     { 16904, 0x0032 },   /* R16904 - HDBASS_N1_1 */
0342     { 16905, 0xF52D },   /* R16905 - HDBASS_N1_0 */
0343     { 16906, 0x0065 },   /* R16906 - HDBASS_N2_1 */
0344     { 16907, 0xAC8C },   /* R16907 - HDBASS_N2_0 */
0345     { 16908, 0x006B },   /* R16908 - HDBASS_N3_1 */
0346     { 16909, 0xE087 },   /* R16909 - HDBASS_N3_0 */
0347     { 16910, 0x0072 },   /* R16910 - HDBASS_N4_1 */
0348     { 16911, 0x1483 },   /* R16911 - HDBASS_N4_0 */
0349     { 16912, 0x0072 },   /* R16912 - HDBASS_N5_1 */
0350     { 16913, 0x1483 },   /* R16913 - HDBASS_N5_0 */
0351     { 16914, 0x0043 },   /* R16914 - HDBASS_X1_1 */
0352     { 16915, 0x3525 },   /* R16915 - HDBASS_X1_0 */
0353     { 16916, 0x0006 },   /* R16916 - HDBASS_X2_1 */
0354     { 16917, 0x6A4A },   /* R16917 - HDBASS_X2_0 */
0355     { 16918, 0x0043 },   /* R16918 - HDBASS_X3_1 */
0356     { 16919, 0x6079 },   /* R16919 - HDBASS_X3_0 */
0357     { 16920, 0x0008 },   /* R16920 - HDBASS_ATK_1 */
0358     { 16921, 0x0000 },   /* R16921 - HDBASS_ATK_0 */
0359     { 16922, 0x0001 },   /* R16922 - HDBASS_DCY_1 */
0360     { 16923, 0x0000 },   /* R16923 - HDBASS_DCY_0 */
0361     { 16924, 0x0059 },   /* R16924 - HDBASS_PG_1 */
0362     { 16925, 0x999A },   /* R16925 - HDBASS_PG_0 */
0363 
0364     { 17408, 0x0083 },   /* R17408 - HPF_C_1 */
0365     { 17409, 0x98AD },   /* R17409 - HPF_C_0 */
0366 
0367     { 17920, 0x007F },   /* R17920 - ADCL_RETUNE_C1_1 */
0368     { 17921, 0xFFFF },   /* R17921 - ADCL_RETUNE_C1_0 */
0369     { 17922, 0x0000 },   /* R17922 - ADCL_RETUNE_C2_1 */
0370     { 17923, 0x0000 },   /* R17923 - ADCL_RETUNE_C2_0 */
0371     { 17924, 0x0000 },   /* R17924 - ADCL_RETUNE_C3_1 */
0372     { 17925, 0x0000 },   /* R17925 - ADCL_RETUNE_C3_0 */
0373     { 17926, 0x0000 },   /* R17926 - ADCL_RETUNE_C4_1 */
0374     { 17927, 0x0000 },   /* R17927 - ADCL_RETUNE_C4_0 */
0375     { 17928, 0x0000 },   /* R17928 - ADCL_RETUNE_C5_1 */
0376     { 17929, 0x0000 },   /* R17929 - ADCL_RETUNE_C5_0 */
0377     { 17930, 0x0000 },   /* R17930 - ADCL_RETUNE_C6_1 */
0378     { 17931, 0x0000 },   /* R17931 - ADCL_RETUNE_C6_0 */
0379     { 17932, 0x0000 },   /* R17932 - ADCL_RETUNE_C7_1 */
0380     { 17933, 0x0000 },   /* R17933 - ADCL_RETUNE_C7_0 */
0381     { 17934, 0x0000 },   /* R17934 - ADCL_RETUNE_C8_1 */
0382     { 17935, 0x0000 },   /* R17935 - ADCL_RETUNE_C8_0 */
0383     { 17936, 0x0000 },   /* R17936 - ADCL_RETUNE_C9_1 */
0384     { 17937, 0x0000 },   /* R17937 - ADCL_RETUNE_C9_0 */
0385     { 17938, 0x0000 },   /* R17938 - ADCL_RETUNE_C10_1 */
0386     { 17939, 0x0000 },   /* R17939 - ADCL_RETUNE_C10_0 */
0387     { 17940, 0x0000 },   /* R17940 - ADCL_RETUNE_C11_1 */
0388     { 17941, 0x0000 },   /* R17941 - ADCL_RETUNE_C11_0 */
0389     { 17942, 0x0000 },   /* R17942 - ADCL_RETUNE_C12_1 */
0390     { 17943, 0x0000 },   /* R17943 - ADCL_RETUNE_C12_0 */
0391     { 17944, 0x0000 },   /* R17944 - ADCL_RETUNE_C13_1 */
0392     { 17945, 0x0000 },   /* R17945 - ADCL_RETUNE_C13_0 */
0393     { 17946, 0x0000 },   /* R17946 - ADCL_RETUNE_C14_1 */
0394     { 17947, 0x0000 },   /* R17947 - ADCL_RETUNE_C14_0 */
0395     { 17948, 0x0000 },   /* R17948 - ADCL_RETUNE_C15_1 */
0396     { 17949, 0x0000 },   /* R17949 - ADCL_RETUNE_C15_0 */
0397     { 17950, 0x0000 },   /* R17950 - ADCL_RETUNE_C16_1 */
0398     { 17951, 0x0000 },   /* R17951 - ADCL_RETUNE_C16_0 */
0399     { 17952, 0x0000 },   /* R17952 - ADCL_RETUNE_C17_1 */
0400     { 17953, 0x0000 },   /* R17953 - ADCL_RETUNE_C17_0 */
0401     { 17954, 0x0000 },   /* R17954 - ADCL_RETUNE_C18_1 */
0402     { 17955, 0x0000 },   /* R17955 - ADCL_RETUNE_C18_0 */
0403     { 17956, 0x0000 },   /* R17956 - ADCL_RETUNE_C19_1 */
0404     { 17957, 0x0000 },   /* R17957 - ADCL_RETUNE_C19_0 */
0405     { 17958, 0x0000 },   /* R17958 - ADCL_RETUNE_C20_1 */
0406     { 17959, 0x0000 },   /* R17959 - ADCL_RETUNE_C20_0 */
0407     { 17960, 0x0000 },   /* R17960 - ADCL_RETUNE_C21_1 */
0408     { 17961, 0x0000 },   /* R17961 - ADCL_RETUNE_C21_0 */
0409     { 17962, 0x0000 },   /* R17962 - ADCL_RETUNE_C22_1 */
0410     { 17963, 0x0000 },   /* R17963 - ADCL_RETUNE_C22_0 */
0411     { 17964, 0x0000 },   /* R17964 - ADCL_RETUNE_C23_1 */
0412     { 17965, 0x0000 },   /* R17965 - ADCL_RETUNE_C23_0 */
0413     { 17966, 0x0000 },   /* R17966 - ADCL_RETUNE_C24_1 */
0414     { 17967, 0x0000 },   /* R17967 - ADCL_RETUNE_C24_0 */
0415     { 17968, 0x0000 },   /* R17968 - ADCL_RETUNE_C25_1 */
0416     { 17969, 0x0000 },   /* R17969 - ADCL_RETUNE_C25_0 */
0417     { 17970, 0x0000 },   /* R17970 - ADCL_RETUNE_C26_1 */
0418     { 17971, 0x0000 },   /* R17971 - ADCL_RETUNE_C26_0 */
0419     { 17972, 0x0000 },   /* R17972 - ADCL_RETUNE_C27_1 */
0420     { 17973, 0x0000 },   /* R17973 - ADCL_RETUNE_C27_0 */
0421     { 17974, 0x0000 },   /* R17974 - ADCL_RETUNE_C28_1 */
0422     { 17975, 0x0000 },   /* R17975 - ADCL_RETUNE_C28_0 */
0423     { 17976, 0x0000 },   /* R17976 - ADCL_RETUNE_C29_1 */
0424     { 17977, 0x0000 },   /* R17977 - ADCL_RETUNE_C29_0 */
0425     { 17978, 0x0000 },   /* R17978 - ADCL_RETUNE_C30_1 */
0426     { 17979, 0x0000 },   /* R17979 - ADCL_RETUNE_C30_0 */
0427     { 17980, 0x0000 },   /* R17980 - ADCL_RETUNE_C31_1 */
0428     { 17981, 0x0000 },   /* R17981 - ADCL_RETUNE_C31_0 */
0429     { 17982, 0x0000 },   /* R17982 - ADCL_RETUNE_C32_1 */
0430     { 17983, 0x0000 },   /* R17983 - ADCL_RETUNE_C32_0 */
0431 
0432     { 18432, 0x0020 },   /* R18432 - RETUNEADC_PG2_1 */
0433     { 18433, 0x0000 },   /* R18433 - RETUNEADC_PG2_0 */
0434     { 18434, 0x0040 },   /* R18434 - RETUNEADC_PG_1 */
0435     { 18435, 0x0000 },   /* R18435 - RETUNEADC_PG_0 */
0436 
0437     { 18944, 0x007F },   /* R18944 - ADCR_RETUNE_C1_1 */
0438     { 18945, 0xFFFF },   /* R18945 - ADCR_RETUNE_C1_0 */
0439     { 18946, 0x0000 },   /* R18946 - ADCR_RETUNE_C2_1 */
0440     { 18947, 0x0000 },   /* R18947 - ADCR_RETUNE_C2_0 */
0441     { 18948, 0x0000 },   /* R18948 - ADCR_RETUNE_C3_1 */
0442     { 18949, 0x0000 },   /* R18949 - ADCR_RETUNE_C3_0 */
0443     { 18950, 0x0000 },   /* R18950 - ADCR_RETUNE_C4_1 */
0444     { 18951, 0x0000 },   /* R18951 - ADCR_RETUNE_C4_0 */
0445     { 18952, 0x0000 },   /* R18952 - ADCR_RETUNE_C5_1 */
0446     { 18953, 0x0000 },   /* R18953 - ADCR_RETUNE_C5_0 */
0447     { 18954, 0x0000 },   /* R18954 - ADCR_RETUNE_C6_1 */
0448     { 18955, 0x0000 },   /* R18955 - ADCR_RETUNE_C6_0 */
0449     { 18956, 0x0000 },   /* R18956 - ADCR_RETUNE_C7_1 */
0450     { 18957, 0x0000 },   /* R18957 - ADCR_RETUNE_C7_0 */
0451     { 18958, 0x0000 },   /* R18958 - ADCR_RETUNE_C8_1 */
0452     { 18959, 0x0000 },   /* R18959 - ADCR_RETUNE_C8_0 */
0453     { 18960, 0x0000 },   /* R18960 - ADCR_RETUNE_C9_1 */
0454     { 18961, 0x0000 },   /* R18961 - ADCR_RETUNE_C9_0 */
0455     { 18962, 0x0000 },   /* R18962 - ADCR_RETUNE_C10_1 */
0456     { 18963, 0x0000 },   /* R18963 - ADCR_RETUNE_C10_0 */
0457     { 18964, 0x0000 },   /* R18964 - ADCR_RETUNE_C11_1 */
0458     { 18965, 0x0000 },   /* R18965 - ADCR_RETUNE_C11_0 */
0459     { 18966, 0x0000 },   /* R18966 - ADCR_RETUNE_C12_1 */
0460     { 18967, 0x0000 },   /* R18967 - ADCR_RETUNE_C12_0 */
0461     { 18968, 0x0000 },   /* R18968 - ADCR_RETUNE_C13_1 */
0462     { 18969, 0x0000 },   /* R18969 - ADCR_RETUNE_C13_0 */
0463     { 18970, 0x0000 },   /* R18970 - ADCR_RETUNE_C14_1 */
0464     { 18971, 0x0000 },   /* R18971 - ADCR_RETUNE_C14_0 */
0465     { 18972, 0x0000 },   /* R18972 - ADCR_RETUNE_C15_1 */
0466     { 18973, 0x0000 },   /* R18973 - ADCR_RETUNE_C15_0 */
0467     { 18974, 0x0000 },   /* R18974 - ADCR_RETUNE_C16_1 */
0468     { 18975, 0x0000 },   /* R18975 - ADCR_RETUNE_C16_0 */
0469     { 18976, 0x0000 },   /* R18976 - ADCR_RETUNE_C17_1 */
0470     { 18977, 0x0000 },   /* R18977 - ADCR_RETUNE_C17_0 */
0471     { 18978, 0x0000 },   /* R18978 - ADCR_RETUNE_C18_1 */
0472     { 18979, 0x0000 },   /* R18979 - ADCR_RETUNE_C18_0 */
0473     { 18980, 0x0000 },   /* R18980 - ADCR_RETUNE_C19_1 */
0474     { 18981, 0x0000 },   /* R18981 - ADCR_RETUNE_C19_0 */
0475     { 18982, 0x0000 },   /* R18982 - ADCR_RETUNE_C20_1 */
0476     { 18983, 0x0000 },   /* R18983 - ADCR_RETUNE_C20_0 */
0477     { 18984, 0x0000 },   /* R18984 - ADCR_RETUNE_C21_1 */
0478     { 18985, 0x0000 },   /* R18985 - ADCR_RETUNE_C21_0 */
0479     { 18986, 0x0000 },   /* R18986 - ADCR_RETUNE_C22_1 */
0480     { 18987, 0x0000 },   /* R18987 - ADCR_RETUNE_C22_0 */
0481     { 18988, 0x0000 },   /* R18988 - ADCR_RETUNE_C23_1 */
0482     { 18989, 0x0000 },   /* R18989 - ADCR_RETUNE_C23_0 */
0483     { 18990, 0x0000 },   /* R18990 - ADCR_RETUNE_C24_1 */
0484     { 18991, 0x0000 },   /* R18991 - ADCR_RETUNE_C24_0 */
0485     { 18992, 0x0000 },   /* R18992 - ADCR_RETUNE_C25_1 */
0486     { 18993, 0x0000 },   /* R18993 - ADCR_RETUNE_C25_0 */
0487     { 18994, 0x0000 },   /* R18994 - ADCR_RETUNE_C26_1 */
0488     { 18995, 0x0000 },   /* R18995 - ADCR_RETUNE_C26_0 */
0489     { 18996, 0x0000 },   /* R18996 - ADCR_RETUNE_C27_1 */
0490     { 18997, 0x0000 },   /* R18997 - ADCR_RETUNE_C27_0 */
0491     { 18998, 0x0000 },   /* R18998 - ADCR_RETUNE_C28_1 */
0492     { 18999, 0x0000 },   /* R18999 - ADCR_RETUNE_C28_0 */
0493     { 19000, 0x0000 },   /* R19000 - ADCR_RETUNE_C29_1 */
0494     { 19001, 0x0000 },   /* R19001 - ADCR_RETUNE_C29_0 */
0495     { 19002, 0x0000 },   /* R19002 - ADCR_RETUNE_C30_1 */
0496     { 19003, 0x0000 },   /* R19003 - ADCR_RETUNE_C30_0 */
0497     { 19004, 0x0000 },   /* R19004 - ADCR_RETUNE_C31_1 */
0498     { 19005, 0x0000 },   /* R19005 - ADCR_RETUNE_C31_0 */
0499     { 19006, 0x0000 },   /* R19006 - ADCR_RETUNE_C32_1 */
0500     { 19007, 0x0000 },   /* R19007 - ADCR_RETUNE_C32_0 */
0501 
0502     { 19456, 0x007F },   /* R19456 - DACL_RETUNE_C1_1 */
0503     { 19457, 0xFFFF },   /* R19457 - DACL_RETUNE_C1_0 */
0504     { 19458, 0x0000 },   /* R19458 - DACL_RETUNE_C2_1 */
0505     { 19459, 0x0000 },   /* R19459 - DACL_RETUNE_C2_0 */
0506     { 19460, 0x0000 },   /* R19460 - DACL_RETUNE_C3_1 */
0507     { 19461, 0x0000 },   /* R19461 - DACL_RETUNE_C3_0 */
0508     { 19462, 0x0000 },   /* R19462 - DACL_RETUNE_C4_1 */
0509     { 19463, 0x0000 },   /* R19463 - DACL_RETUNE_C4_0 */
0510     { 19464, 0x0000 },   /* R19464 - DACL_RETUNE_C5_1 */
0511     { 19465, 0x0000 },   /* R19465 - DACL_RETUNE_C5_0 */
0512     { 19466, 0x0000 },   /* R19466 - DACL_RETUNE_C6_1 */
0513     { 19467, 0x0000 },   /* R19467 - DACL_RETUNE_C6_0 */
0514     { 19468, 0x0000 },   /* R19468 - DACL_RETUNE_C7_1 */
0515     { 19469, 0x0000 },   /* R19469 - DACL_RETUNE_C7_0 */
0516     { 19470, 0x0000 },   /* R19470 - DACL_RETUNE_C8_1 */
0517     { 19471, 0x0000 },   /* R19471 - DACL_RETUNE_C8_0 */
0518     { 19472, 0x0000 },   /* R19472 - DACL_RETUNE_C9_1 */
0519     { 19473, 0x0000 },   /* R19473 - DACL_RETUNE_C9_0 */
0520     { 19474, 0x0000 },   /* R19474 - DACL_RETUNE_C10_1 */
0521     { 19475, 0x0000 },   /* R19475 - DACL_RETUNE_C10_0 */
0522     { 19476, 0x0000 },   /* R19476 - DACL_RETUNE_C11_1 */
0523     { 19477, 0x0000 },   /* R19477 - DACL_RETUNE_C11_0 */
0524     { 19478, 0x0000 },   /* R19478 - DACL_RETUNE_C12_1 */
0525     { 19479, 0x0000 },   /* R19479 - DACL_RETUNE_C12_0 */
0526     { 19480, 0x0000 },   /* R19480 - DACL_RETUNE_C13_1 */
0527     { 19481, 0x0000 },   /* R19481 - DACL_RETUNE_C13_0 */
0528     { 19482, 0x0000 },   /* R19482 - DACL_RETUNE_C14_1 */
0529     { 19483, 0x0000 },   /* R19483 - DACL_RETUNE_C14_0 */
0530     { 19484, 0x0000 },   /* R19484 - DACL_RETUNE_C15_1 */
0531     { 19485, 0x0000 },   /* R19485 - DACL_RETUNE_C15_0 */
0532     { 19486, 0x0000 },   /* R19486 - DACL_RETUNE_C16_1 */
0533     { 19487, 0x0000 },   /* R19487 - DACL_RETUNE_C16_0 */
0534     { 19488, 0x0000 },   /* R19488 - DACL_RETUNE_C17_1 */
0535     { 19489, 0x0000 },   /* R19489 - DACL_RETUNE_C17_0 */
0536     { 19490, 0x0000 },   /* R19490 - DACL_RETUNE_C18_1 */
0537     { 19491, 0x0000 },   /* R19491 - DACL_RETUNE_C18_0 */
0538     { 19492, 0x0000 },   /* R19492 - DACL_RETUNE_C19_1 */
0539     { 19493, 0x0000 },   /* R19493 - DACL_RETUNE_C19_0 */
0540     { 19494, 0x0000 },   /* R19494 - DACL_RETUNE_C20_1 */
0541     { 19495, 0x0000 },   /* R19495 - DACL_RETUNE_C20_0 */
0542     { 19496, 0x0000 },   /* R19496 - DACL_RETUNE_C21_1 */
0543     { 19497, 0x0000 },   /* R19497 - DACL_RETUNE_C21_0 */
0544     { 19498, 0x0000 },   /* R19498 - DACL_RETUNE_C22_1 */
0545     { 19499, 0x0000 },   /* R19499 - DACL_RETUNE_C22_0 */
0546     { 19500, 0x0000 },   /* R19500 - DACL_RETUNE_C23_1 */
0547     { 19501, 0x0000 },   /* R19501 - DACL_RETUNE_C23_0 */
0548     { 19502, 0x0000 },   /* R19502 - DACL_RETUNE_C24_1 */
0549     { 19503, 0x0000 },   /* R19503 - DACL_RETUNE_C24_0 */
0550     { 19504, 0x0000 },   /* R19504 - DACL_RETUNE_C25_1 */
0551     { 19505, 0x0000 },   /* R19505 - DACL_RETUNE_C25_0 */
0552     { 19506, 0x0000 },   /* R19506 - DACL_RETUNE_C26_1 */
0553     { 19507, 0x0000 },   /* R19507 - DACL_RETUNE_C26_0 */
0554     { 19508, 0x0000 },   /* R19508 - DACL_RETUNE_C27_1 */
0555     { 19509, 0x0000 },   /* R19509 - DACL_RETUNE_C27_0 */
0556     { 19510, 0x0000 },   /* R19510 - DACL_RETUNE_C28_1 */
0557     { 19511, 0x0000 },   /* R19511 - DACL_RETUNE_C28_0 */
0558     { 19512, 0x0000 },   /* R19512 - DACL_RETUNE_C29_1 */
0559     { 19513, 0x0000 },   /* R19513 - DACL_RETUNE_C29_0 */
0560     { 19514, 0x0000 },   /* R19514 - DACL_RETUNE_C30_1 */
0561     { 19515, 0x0000 },   /* R19515 - DACL_RETUNE_C30_0 */
0562     { 19516, 0x0000 },   /* R19516 - DACL_RETUNE_C31_1 */
0563     { 19517, 0x0000 },   /* R19517 - DACL_RETUNE_C31_0 */
0564     { 19518, 0x0000 },   /* R19518 - DACL_RETUNE_C32_1 */
0565     { 19519, 0x0000 },   /* R19519 - DACL_RETUNE_C32_0 */
0566 
0567     { 19968, 0x0020 },   /* R19968 - RETUNEDAC_PG2_1 */
0568     { 19969, 0x0000 },   /* R19969 - RETUNEDAC_PG2_0 */
0569     { 19970, 0x0040 },   /* R19970 - RETUNEDAC_PG_1 */
0570     { 19971, 0x0000 },   /* R19971 - RETUNEDAC_PG_0 */
0571 
0572     { 20480, 0x007F },   /* R20480 - DACR_RETUNE_C1_1 */
0573     { 20481, 0xFFFF },   /* R20481 - DACR_RETUNE_C1_0 */
0574     { 20482, 0x0000 },   /* R20482 - DACR_RETUNE_C2_1 */
0575     { 20483, 0x0000 },   /* R20483 - DACR_RETUNE_C2_0 */
0576     { 20484, 0x0000 },   /* R20484 - DACR_RETUNE_C3_1 */
0577     { 20485, 0x0000 },   /* R20485 - DACR_RETUNE_C3_0 */
0578     { 20486, 0x0000 },   /* R20486 - DACR_RETUNE_C4_1 */
0579     { 20487, 0x0000 },   /* R20487 - DACR_RETUNE_C4_0 */
0580     { 20488, 0x0000 },   /* R20488 - DACR_RETUNE_C5_1 */
0581     { 20489, 0x0000 },   /* R20489 - DACR_RETUNE_C5_0 */
0582     { 20490, 0x0000 },   /* R20490 - DACR_RETUNE_C6_1 */
0583     { 20491, 0x0000 },   /* R20491 - DACR_RETUNE_C6_0 */
0584     { 20492, 0x0000 },   /* R20492 - DACR_RETUNE_C7_1 */
0585     { 20493, 0x0000 },   /* R20493 - DACR_RETUNE_C7_0 */
0586     { 20494, 0x0000 },   /* R20494 - DACR_RETUNE_C8_1 */
0587     { 20495, 0x0000 },   /* R20495 - DACR_RETUNE_C8_0 */
0588     { 20496, 0x0000 },   /* R20496 - DACR_RETUNE_C9_1 */
0589     { 20497, 0x0000 },   /* R20497 - DACR_RETUNE_C9_0 */
0590     { 20498, 0x0000 },   /* R20498 - DACR_RETUNE_C10_1 */
0591     { 20499, 0x0000 },   /* R20499 - DACR_RETUNE_C10_0 */
0592     { 20500, 0x0000 },   /* R20500 - DACR_RETUNE_C11_1 */
0593     { 20501, 0x0000 },   /* R20501 - DACR_RETUNE_C11_0 */
0594     { 20502, 0x0000 },   /* R20502 - DACR_RETUNE_C12_1 */
0595     { 20503, 0x0000 },   /* R20503 - DACR_RETUNE_C12_0 */
0596     { 20504, 0x0000 },   /* R20504 - DACR_RETUNE_C13_1 */
0597     { 20505, 0x0000 },   /* R20505 - DACR_RETUNE_C13_0 */
0598     { 20506, 0x0000 },   /* R20506 - DACR_RETUNE_C14_1 */
0599     { 20507, 0x0000 },   /* R20507 - DACR_RETUNE_C14_0 */
0600     { 20508, 0x0000 },   /* R20508 - DACR_RETUNE_C15_1 */
0601     { 20509, 0x0000 },   /* R20509 - DACR_RETUNE_C15_0 */
0602     { 20510, 0x0000 },   /* R20510 - DACR_RETUNE_C16_1 */
0603     { 20511, 0x0000 },   /* R20511 - DACR_RETUNE_C16_0 */
0604     { 20512, 0x0000 },   /* R20512 - DACR_RETUNE_C17_1 */
0605     { 20513, 0x0000 },   /* R20513 - DACR_RETUNE_C17_0 */
0606     { 20514, 0x0000 },   /* R20514 - DACR_RETUNE_C18_1 */
0607     { 20515, 0x0000 },   /* R20515 - DACR_RETUNE_C18_0 */
0608     { 20516, 0x0000 },   /* R20516 - DACR_RETUNE_C19_1 */
0609     { 20517, 0x0000 },   /* R20517 - DACR_RETUNE_C19_0 */
0610     { 20518, 0x0000 },   /* R20518 - DACR_RETUNE_C20_1 */
0611     { 20519, 0x0000 },   /* R20519 - DACR_RETUNE_C20_0 */
0612     { 20520, 0x0000 },   /* R20520 - DACR_RETUNE_C21_1 */
0613     { 20521, 0x0000 },   /* R20521 - DACR_RETUNE_C21_0 */
0614     { 20522, 0x0000 },   /* R20522 - DACR_RETUNE_C22_1 */
0615     { 20523, 0x0000 },   /* R20523 - DACR_RETUNE_C22_0 */
0616     { 20524, 0x0000 },   /* R20524 - DACR_RETUNE_C23_1 */
0617     { 20525, 0x0000 },   /* R20525 - DACR_RETUNE_C23_0 */
0618     { 20526, 0x0000 },   /* R20526 - DACR_RETUNE_C24_1 */
0619     { 20527, 0x0000 },   /* R20527 - DACR_RETUNE_C24_0 */
0620     { 20528, 0x0000 },   /* R20528 - DACR_RETUNE_C25_1 */
0621     { 20529, 0x0000 },   /* R20529 - DACR_RETUNE_C25_0 */
0622     { 20530, 0x0000 },   /* R20530 - DACR_RETUNE_C26_1 */
0623     { 20531, 0x0000 },   /* R20531 - DACR_RETUNE_C26_0 */
0624     { 20532, 0x0000 },   /* R20532 - DACR_RETUNE_C27_1 */
0625     { 20533, 0x0000 },   /* R20533 - DACR_RETUNE_C27_0 */
0626     { 20534, 0x0000 },   /* R20534 - DACR_RETUNE_C28_1 */
0627     { 20535, 0x0000 },   /* R20535 - DACR_RETUNE_C28_0 */
0628     { 20536, 0x0000 },   /* R20536 - DACR_RETUNE_C29_1 */
0629     { 20537, 0x0000 },   /* R20537 - DACR_RETUNE_C29_0 */
0630     { 20538, 0x0000 },   /* R20538 - DACR_RETUNE_C30_1 */
0631     { 20539, 0x0000 },   /* R20539 - DACR_RETUNE_C30_0 */
0632     { 20540, 0x0000 },   /* R20540 - DACR_RETUNE_C31_1 */
0633     { 20541, 0x0000 },   /* R20541 - DACR_RETUNE_C31_0 */
0634     { 20542, 0x0000 },   /* R20542 - DACR_RETUNE_C32_1 */
0635     { 20543, 0x0000 },   /* R20543 - DACR_RETUNE_C32_0 */
0636 
0637     { 20992, 0x008C },   /* R20992 - VSS_XHD2_1 */
0638     { 20993, 0x0200 },   /* R20993 - VSS_XHD2_0 */
0639     { 20994, 0x0035 },   /* R20994 - VSS_XHD3_1 */
0640     { 20995, 0x0700 },   /* R20995 - VSS_XHD3_0 */
0641     { 20996, 0x003A },   /* R20996 - VSS_XHN1_1 */
0642     { 20997, 0x4100 },   /* R20997 - VSS_XHN1_0 */
0643     { 20998, 0x008B },   /* R20998 - VSS_XHN2_1 */
0644     { 20999, 0x7D00 },   /* R20999 - VSS_XHN2_0 */
0645     { 21000, 0x003A },   /* R21000 - VSS_XHN3_1 */
0646     { 21001, 0x4100 },   /* R21001 - VSS_XHN3_0 */
0647     { 21002, 0x008C },   /* R21002 - VSS_XLA_1 */
0648     { 21003, 0xFEE8 },   /* R21003 - VSS_XLA_0 */
0649     { 21004, 0x0078 },   /* R21004 - VSS_XLB_1 */
0650     { 21005, 0x0000 },   /* R21005 - VSS_XLB_0 */
0651     { 21006, 0x003F },   /* R21006 - VSS_XLG_1 */
0652     { 21007, 0xB260 },   /* R21007 - VSS_XLG_0 */
0653     { 21008, 0x002D },   /* R21008 - VSS_PG2_1 */
0654     { 21009, 0x1818 },   /* R21009 - VSS_PG2_0 */
0655     { 21010, 0x0020 },   /* R21010 - VSS_PG_1 */
0656     { 21011, 0x0000 },   /* R21011 - VSS_PG_0 */
0657     { 21012, 0x00F1 },   /* R21012 - VSS_XTD1_1 */
0658     { 21013, 0x8340 },   /* R21013 - VSS_XTD1_0 */
0659     { 21014, 0x00FB },   /* R21014 - VSS_XTD2_1 */
0660     { 21015, 0x8300 },   /* R21015 - VSS_XTD2_0 */
0661     { 21016, 0x00EE },   /* R21016 - VSS_XTD3_1 */
0662     { 21017, 0xAEC0 },   /* R21017 - VSS_XTD3_0 */
0663     { 21018, 0x00FB },   /* R21018 - VSS_XTD4_1 */
0664     { 21019, 0xAC40 },   /* R21019 - VSS_XTD4_0 */
0665     { 21020, 0x00F1 },   /* R21020 - VSS_XTD5_1 */
0666     { 21021, 0x7F80 },   /* R21021 - VSS_XTD5_0 */
0667     { 21022, 0x00F4 },   /* R21022 - VSS_XTD6_1 */
0668     { 21023, 0x3B40 },   /* R21023 - VSS_XTD6_0 */
0669     { 21024, 0x00F5 },   /* R21024 - VSS_XTD7_1 */
0670     { 21025, 0xFB00 },   /* R21025 - VSS_XTD7_0 */
0671     { 21026, 0x00EA },   /* R21026 - VSS_XTD8_1 */
0672     { 21027, 0x10C0 },   /* R21027 - VSS_XTD8_0 */
0673     { 21028, 0x00FC },   /* R21028 - VSS_XTD9_1 */
0674     { 21029, 0xC580 },   /* R21029 - VSS_XTD9_0 */
0675     { 21030, 0x00E2 },   /* R21030 - VSS_XTD10_1 */
0676     { 21031, 0x75C0 },   /* R21031 - VSS_XTD10_0 */
0677     { 21032, 0x0004 },   /* R21032 - VSS_XTD11_1 */
0678     { 21033, 0xB480 },   /* R21033 - VSS_XTD11_0 */
0679     { 21034, 0x00D4 },   /* R21034 - VSS_XTD12_1 */
0680     { 21035, 0xF980 },   /* R21035 - VSS_XTD12_0 */
0681     { 21036, 0x0004 },   /* R21036 - VSS_XTD13_1 */
0682     { 21037, 0x9140 },   /* R21037 - VSS_XTD13_0 */
0683     { 21038, 0x00D8 },   /* R21038 - VSS_XTD14_1 */
0684     { 21039, 0xA480 },   /* R21039 - VSS_XTD14_0 */
0685     { 21040, 0x0002 },   /* R21040 - VSS_XTD15_1 */
0686     { 21041, 0x3DC0 },   /* R21041 - VSS_XTD15_0 */
0687     { 21042, 0x00CF },   /* R21042 - VSS_XTD16_1 */
0688     { 21043, 0x7A80 },   /* R21043 - VSS_XTD16_0 */
0689     { 21044, 0x00DC },   /* R21044 - VSS_XTD17_1 */
0690     { 21045, 0x0600 },   /* R21045 - VSS_XTD17_0 */
0691     { 21046, 0x00F2 },   /* R21046 - VSS_XTD18_1 */
0692     { 21047, 0xDAC0 },   /* R21047 - VSS_XTD18_0 */
0693     { 21048, 0x00BA },   /* R21048 - VSS_XTD19_1 */
0694     { 21049, 0xF340 },   /* R21049 - VSS_XTD19_0 */
0695     { 21050, 0x000A },   /* R21050 - VSS_XTD20_1 */
0696     { 21051, 0x7940 },   /* R21051 - VSS_XTD20_0 */
0697     { 21052, 0x001C },   /* R21052 - VSS_XTD21_1 */
0698     { 21053, 0x0680 },   /* R21053 - VSS_XTD21_0 */
0699     { 21054, 0x00FD },   /* R21054 - VSS_XTD22_1 */
0700     { 21055, 0x2D00 },   /* R21055 - VSS_XTD22_0 */
0701     { 21056, 0x001C },   /* R21056 - VSS_XTD23_1 */
0702     { 21057, 0xE840 },   /* R21057 - VSS_XTD23_0 */
0703     { 21058, 0x000D },   /* R21058 - VSS_XTD24_1 */
0704     { 21059, 0xDC40 },   /* R21059 - VSS_XTD24_0 */
0705     { 21060, 0x00FC },   /* R21060 - VSS_XTD25_1 */
0706     { 21061, 0x9D00 },   /* R21061 - VSS_XTD25_0 */
0707     { 21062, 0x0009 },   /* R21062 - VSS_XTD26_1 */
0708     { 21063, 0x5580 },   /* R21063 - VSS_XTD26_0 */
0709     { 21064, 0x00FE },   /* R21064 - VSS_XTD27_1 */
0710     { 21065, 0x7E80 },   /* R21065 - VSS_XTD27_0 */
0711     { 21066, 0x000E },   /* R21066 - VSS_XTD28_1 */
0712     { 21067, 0xAB40 },   /* R21067 - VSS_XTD28_0 */
0713     { 21068, 0x00F9 },   /* R21068 - VSS_XTD29_1 */
0714     { 21069, 0x9880 },   /* R21069 - VSS_XTD29_0 */
0715     { 21070, 0x0009 },   /* R21070 - VSS_XTD30_1 */
0716     { 21071, 0x87C0 },   /* R21071 - VSS_XTD30_0 */
0717     { 21072, 0x00FD },   /* R21072 - VSS_XTD31_1 */
0718     { 21073, 0x2C40 },   /* R21073 - VSS_XTD31_0 */
0719     { 21074, 0x0009 },   /* R21074 - VSS_XTD32_1 */
0720     { 21075, 0x4800 },   /* R21075 - VSS_XTD32_0 */
0721     { 21076, 0x0003 },   /* R21076 - VSS_XTS1_1 */
0722     { 21077, 0x5F40 },   /* R21077 - VSS_XTS1_0 */
0723     { 21078, 0x0000 },   /* R21078 - VSS_XTS2_1 */
0724     { 21079, 0x8700 },   /* R21079 - VSS_XTS2_0 */
0725     { 21080, 0x00FA },   /* R21080 - VSS_XTS3_1 */
0726     { 21081, 0xE4C0 },   /* R21081 - VSS_XTS3_0 */
0727     { 21082, 0x0000 },   /* R21082 - VSS_XTS4_1 */
0728     { 21083, 0x0B40 },   /* R21083 - VSS_XTS4_0 */
0729     { 21084, 0x0004 },   /* R21084 - VSS_XTS5_1 */
0730     { 21085, 0xE180 },   /* R21085 - VSS_XTS5_0 */
0731     { 21086, 0x0001 },   /* R21086 - VSS_XTS6_1 */
0732     { 21087, 0x1F40 },   /* R21087 - VSS_XTS6_0 */
0733     { 21088, 0x00F8 },   /* R21088 - VSS_XTS7_1 */
0734     { 21089, 0xB000 },   /* R21089 - VSS_XTS7_0 */
0735     { 21090, 0x00FB },   /* R21090 - VSS_XTS8_1 */
0736     { 21091, 0xCBC0 },   /* R21091 - VSS_XTS8_0 */
0737     { 21092, 0x0004 },   /* R21092 - VSS_XTS9_1 */
0738     { 21093, 0xF380 },   /* R21093 - VSS_XTS9_0 */
0739     { 21094, 0x0007 },   /* R21094 - VSS_XTS10_1 */
0740     { 21095, 0xDF40 },   /* R21095 - VSS_XTS10_0 */
0741     { 21096, 0x00FF },   /* R21096 - VSS_XTS11_1 */
0742     { 21097, 0x0700 },   /* R21097 - VSS_XTS11_0 */
0743     { 21098, 0x00EF },   /* R21098 - VSS_XTS12_1 */
0744     { 21099, 0xD700 },   /* R21099 - VSS_XTS12_0 */
0745     { 21100, 0x00FB },   /* R21100 - VSS_XTS13_1 */
0746     { 21101, 0xAF40 },   /* R21101 - VSS_XTS13_0 */
0747     { 21102, 0x0010 },   /* R21102 - VSS_XTS14_1 */
0748     { 21103, 0x8A80 },   /* R21103 - VSS_XTS14_0 */
0749     { 21104, 0x0011 },   /* R21104 - VSS_XTS15_1 */
0750     { 21105, 0x07C0 },   /* R21105 - VSS_XTS15_0 */
0751     { 21106, 0x00E0 },   /* R21106 - VSS_XTS16_1 */
0752     { 21107, 0x0800 },   /* R21107 - VSS_XTS16_0 */
0753     { 21108, 0x00D2 },   /* R21108 - VSS_XTS17_1 */
0754     { 21109, 0x7600 },   /* R21109 - VSS_XTS17_0 */
0755     { 21110, 0x0020 },   /* R21110 - VSS_XTS18_1 */
0756     { 21111, 0xCF40 },   /* R21111 - VSS_XTS18_0 */
0757     { 21112, 0x0030 },   /* R21112 - VSS_XTS19_1 */
0758     { 21113, 0x2340 },   /* R21113 - VSS_XTS19_0 */
0759     { 21114, 0x00FD },   /* R21114 - VSS_XTS20_1 */
0760     { 21115, 0x69C0 },   /* R21115 - VSS_XTS20_0 */
0761     { 21116, 0x0028 },   /* R21116 - VSS_XTS21_1 */
0762     { 21117, 0x3500 },   /* R21117 - VSS_XTS21_0 */
0763     { 21118, 0x0006 },   /* R21118 - VSS_XTS22_1 */
0764     { 21119, 0x3300 },   /* R21119 - VSS_XTS22_0 */
0765     { 21120, 0x00D9 },   /* R21120 - VSS_XTS23_1 */
0766     { 21121, 0xF6C0 },   /* R21121 - VSS_XTS23_0 */
0767     { 21122, 0x00F3 },   /* R21122 - VSS_XTS24_1 */
0768     { 21123, 0x3340 },   /* R21123 - VSS_XTS24_0 */
0769     { 21124, 0x000F },   /* R21124 - VSS_XTS25_1 */
0770     { 21125, 0x4200 },   /* R21125 - VSS_XTS25_0 */
0771     { 21126, 0x0004 },   /* R21126 - VSS_XTS26_1 */
0772     { 21127, 0x0C80 },   /* R21127 - VSS_XTS26_0 */
0773     { 21128, 0x00FB },   /* R21128 - VSS_XTS27_1 */
0774     { 21129, 0x3F80 },   /* R21129 - VSS_XTS27_0 */
0775     { 21130, 0x00F7 },   /* R21130 - VSS_XTS28_1 */
0776     { 21131, 0x57C0 },   /* R21131 - VSS_XTS28_0 */
0777     { 21132, 0x0003 },   /* R21132 - VSS_XTS29_1 */
0778     { 21133, 0x5400 },   /* R21133 - VSS_XTS29_0 */
0779     { 21134, 0x0000 },   /* R21134 - VSS_XTS30_1 */
0780     { 21135, 0xC6C0 },   /* R21135 - VSS_XTS30_0 */
0781     { 21136, 0x0003 },   /* R21136 - VSS_XTS31_1 */
0782     { 21137, 0x12C0 },   /* R21137 - VSS_XTS31_0 */
0783     { 21138, 0x00FD },   /* R21138 - VSS_XTS32_1 */
0784     { 21139, 0x8580 },   /* R21139 - VSS_XTS32_0 */
0785 };
0786 
0787 static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
0788 {
0789     switch (reg) {
0790     case WM8962_CLOCKING1:
0791     case WM8962_SOFTWARE_RESET:
0792     case WM8962_THERMAL_SHUTDOWN_STATUS:
0793     case WM8962_ADDITIONAL_CONTROL_4:
0794     case WM8962_DC_SERVO_6:
0795     case WM8962_INTERRUPT_STATUS_1:
0796     case WM8962_INTERRUPT_STATUS_2:
0797     case WM8962_DSP2_EXECCONTROL:
0798         return true;
0799     default:
0800         return false;
0801     }
0802 }
0803 
0804 static bool wm8962_readable_register(struct device *dev, unsigned int reg)
0805 {
0806     switch (reg) {
0807     case WM8962_LEFT_INPUT_VOLUME:
0808     case WM8962_RIGHT_INPUT_VOLUME:
0809     case WM8962_HPOUTL_VOLUME:
0810     case WM8962_HPOUTR_VOLUME:
0811     case WM8962_CLOCKING1:
0812     case WM8962_ADC_DAC_CONTROL_1:
0813     case WM8962_ADC_DAC_CONTROL_2:
0814     case WM8962_AUDIO_INTERFACE_0:
0815     case WM8962_CLOCKING2:
0816     case WM8962_AUDIO_INTERFACE_1:
0817     case WM8962_LEFT_DAC_VOLUME:
0818     case WM8962_RIGHT_DAC_VOLUME:
0819     case WM8962_AUDIO_INTERFACE_2:
0820     case WM8962_SOFTWARE_RESET:
0821     case WM8962_ALC1:
0822     case WM8962_ALC2:
0823     case WM8962_ALC3:
0824     case WM8962_NOISE_GATE:
0825     case WM8962_LEFT_ADC_VOLUME:
0826     case WM8962_RIGHT_ADC_VOLUME:
0827     case WM8962_ADDITIONAL_CONTROL_1:
0828     case WM8962_ADDITIONAL_CONTROL_2:
0829     case WM8962_PWR_MGMT_1:
0830     case WM8962_PWR_MGMT_2:
0831     case WM8962_ADDITIONAL_CONTROL_3:
0832     case WM8962_ANTI_POP:
0833     case WM8962_CLOCKING_3:
0834     case WM8962_INPUT_MIXER_CONTROL_1:
0835     case WM8962_LEFT_INPUT_MIXER_VOLUME:
0836     case WM8962_RIGHT_INPUT_MIXER_VOLUME:
0837     case WM8962_INPUT_MIXER_CONTROL_2:
0838     case WM8962_INPUT_BIAS_CONTROL:
0839     case WM8962_LEFT_INPUT_PGA_CONTROL:
0840     case WM8962_RIGHT_INPUT_PGA_CONTROL:
0841     case WM8962_SPKOUTL_VOLUME:
0842     case WM8962_SPKOUTR_VOLUME:
0843     case WM8962_THERMAL_SHUTDOWN_STATUS:
0844     case WM8962_ADDITIONAL_CONTROL_4:
0845     case WM8962_CLASS_D_CONTROL_1:
0846     case WM8962_CLASS_D_CONTROL_2:
0847     case WM8962_CLOCKING_4:
0848     case WM8962_DAC_DSP_MIXING_1:
0849     case WM8962_DAC_DSP_MIXING_2:
0850     case WM8962_DC_SERVO_0:
0851     case WM8962_DC_SERVO_1:
0852     case WM8962_DC_SERVO_4:
0853     case WM8962_DC_SERVO_6:
0854     case WM8962_ANALOGUE_PGA_BIAS:
0855     case WM8962_ANALOGUE_HP_0:
0856     case WM8962_ANALOGUE_HP_2:
0857     case WM8962_CHARGE_PUMP_1:
0858     case WM8962_CHARGE_PUMP_B:
0859     case WM8962_WRITE_SEQUENCER_CONTROL_1:
0860     case WM8962_WRITE_SEQUENCER_CONTROL_2:
0861     case WM8962_WRITE_SEQUENCER_CONTROL_3:
0862     case WM8962_CONTROL_INTERFACE:
0863     case WM8962_MIXER_ENABLES:
0864     case WM8962_HEADPHONE_MIXER_1:
0865     case WM8962_HEADPHONE_MIXER_2:
0866     case WM8962_HEADPHONE_MIXER_3:
0867     case WM8962_HEADPHONE_MIXER_4:
0868     case WM8962_SPEAKER_MIXER_1:
0869     case WM8962_SPEAKER_MIXER_2:
0870     case WM8962_SPEAKER_MIXER_3:
0871     case WM8962_SPEAKER_MIXER_4:
0872     case WM8962_SPEAKER_MIXER_5:
0873     case WM8962_BEEP_GENERATOR_1:
0874     case WM8962_OSCILLATOR_TRIM_3:
0875     case WM8962_OSCILLATOR_TRIM_4:
0876     case WM8962_OSCILLATOR_TRIM_7:
0877     case WM8962_ANALOGUE_CLOCKING1:
0878     case WM8962_ANALOGUE_CLOCKING2:
0879     case WM8962_ANALOGUE_CLOCKING3:
0880     case WM8962_PLL_SOFTWARE_RESET:
0881     case WM8962_PLL2:
0882     case WM8962_PLL_4:
0883     case WM8962_PLL_9:
0884     case WM8962_PLL_10:
0885     case WM8962_PLL_11:
0886     case WM8962_PLL_12:
0887     case WM8962_PLL_13:
0888     case WM8962_PLL_14:
0889     case WM8962_PLL_15:
0890     case WM8962_PLL_16:
0891     case WM8962_FLL_CONTROL_1:
0892     case WM8962_FLL_CONTROL_2:
0893     case WM8962_FLL_CONTROL_3:
0894     case WM8962_FLL_CONTROL_5:
0895     case WM8962_FLL_CONTROL_6:
0896     case WM8962_FLL_CONTROL_7:
0897     case WM8962_FLL_CONTROL_8:
0898     case WM8962_GENERAL_TEST_1:
0899     case WM8962_DF1:
0900     case WM8962_DF2:
0901     case WM8962_DF3:
0902     case WM8962_DF4:
0903     case WM8962_DF5:
0904     case WM8962_DF6:
0905     case WM8962_DF7:
0906     case WM8962_LHPF1:
0907     case WM8962_LHPF2:
0908     case WM8962_THREED1:
0909     case WM8962_THREED2:
0910     case WM8962_THREED3:
0911     case WM8962_THREED4:
0912     case WM8962_DRC_1:
0913     case WM8962_DRC_2:
0914     case WM8962_DRC_3:
0915     case WM8962_DRC_4:
0916     case WM8962_DRC_5:
0917     case WM8962_TLOOPBACK:
0918     case WM8962_EQ1:
0919     case WM8962_EQ2:
0920     case WM8962_EQ3:
0921     case WM8962_EQ4:
0922     case WM8962_EQ5:
0923     case WM8962_EQ6:
0924     case WM8962_EQ7:
0925     case WM8962_EQ8:
0926     case WM8962_EQ9:
0927     case WM8962_EQ10:
0928     case WM8962_EQ11:
0929     case WM8962_EQ12:
0930     case WM8962_EQ13:
0931     case WM8962_EQ14:
0932     case WM8962_EQ15:
0933     case WM8962_EQ16:
0934     case WM8962_EQ17:
0935     case WM8962_EQ18:
0936     case WM8962_EQ19:
0937     case WM8962_EQ20:
0938     case WM8962_EQ21:
0939     case WM8962_EQ22:
0940     case WM8962_EQ23:
0941     case WM8962_EQ24:
0942     case WM8962_EQ25:
0943     case WM8962_EQ26:
0944     case WM8962_EQ27:
0945     case WM8962_EQ28:
0946     case WM8962_EQ29:
0947     case WM8962_EQ30:
0948     case WM8962_EQ31:
0949     case WM8962_EQ32:
0950     case WM8962_EQ33:
0951     case WM8962_EQ34:
0952     case WM8962_EQ35:
0953     case WM8962_EQ36:
0954     case WM8962_EQ37:
0955     case WM8962_EQ38:
0956     case WM8962_EQ39:
0957     case WM8962_EQ40:
0958     case WM8962_EQ41:
0959     case WM8962_GPIO_2:
0960     case WM8962_GPIO_3:
0961     case WM8962_GPIO_5:
0962     case WM8962_GPIO_6:
0963     case WM8962_INTERRUPT_STATUS_1:
0964     case WM8962_INTERRUPT_STATUS_2:
0965     case WM8962_INTERRUPT_STATUS_1_MASK:
0966     case WM8962_INTERRUPT_STATUS_2_MASK:
0967     case WM8962_INTERRUPT_CONTROL:
0968     case WM8962_IRQ_DEBOUNCE:
0969     case WM8962_MICINT_SOURCE_POL:
0970     case WM8962_DSP2_POWER_MANAGEMENT:
0971     case WM8962_DSP2_EXECCONTROL:
0972     case WM8962_DSP2_INSTRUCTION_RAM_0:
0973     case WM8962_DSP2_ADDRESS_RAM_2:
0974     case WM8962_DSP2_ADDRESS_RAM_1:
0975     case WM8962_DSP2_ADDRESS_RAM_0:
0976     case WM8962_DSP2_DATA1_RAM_1:
0977     case WM8962_DSP2_DATA1_RAM_0:
0978     case WM8962_DSP2_DATA2_RAM_1:
0979     case WM8962_DSP2_DATA2_RAM_0:
0980     case WM8962_DSP2_DATA3_RAM_1:
0981     case WM8962_DSP2_DATA3_RAM_0:
0982     case WM8962_DSP2_COEFF_RAM_0:
0983     case WM8962_RETUNEADC_SHARED_COEFF_1:
0984     case WM8962_RETUNEADC_SHARED_COEFF_0:
0985     case WM8962_RETUNEDAC_SHARED_COEFF_1:
0986     case WM8962_RETUNEDAC_SHARED_COEFF_0:
0987     case WM8962_SOUNDSTAGE_ENABLES_1:
0988     case WM8962_SOUNDSTAGE_ENABLES_0:
0989     case WM8962_HDBASS_AI_1:
0990     case WM8962_HDBASS_AI_0:
0991     case WM8962_HDBASS_AR_1:
0992     case WM8962_HDBASS_AR_0:
0993     case WM8962_HDBASS_B_1:
0994     case WM8962_HDBASS_B_0:
0995     case WM8962_HDBASS_K_1:
0996     case WM8962_HDBASS_K_0:
0997     case WM8962_HDBASS_N1_1:
0998     case WM8962_HDBASS_N1_0:
0999     case WM8962_HDBASS_N2_1:
1000     case WM8962_HDBASS_N2_0:
1001     case WM8962_HDBASS_N3_1:
1002     case WM8962_HDBASS_N3_0:
1003     case WM8962_HDBASS_N4_1:
1004     case WM8962_HDBASS_N4_0:
1005     case WM8962_HDBASS_N5_1:
1006     case WM8962_HDBASS_N5_0:
1007     case WM8962_HDBASS_X1_1:
1008     case WM8962_HDBASS_X1_0:
1009     case WM8962_HDBASS_X2_1:
1010     case WM8962_HDBASS_X2_0:
1011     case WM8962_HDBASS_X3_1:
1012     case WM8962_HDBASS_X3_0:
1013     case WM8962_HDBASS_ATK_1:
1014     case WM8962_HDBASS_ATK_0:
1015     case WM8962_HDBASS_DCY_1:
1016     case WM8962_HDBASS_DCY_0:
1017     case WM8962_HDBASS_PG_1:
1018     case WM8962_HDBASS_PG_0:
1019     case WM8962_HPF_C_1:
1020     case WM8962_HPF_C_0:
1021     case WM8962_ADCL_RETUNE_C1_1:
1022     case WM8962_ADCL_RETUNE_C1_0:
1023     case WM8962_ADCL_RETUNE_C2_1:
1024     case WM8962_ADCL_RETUNE_C2_0:
1025     case WM8962_ADCL_RETUNE_C3_1:
1026     case WM8962_ADCL_RETUNE_C3_0:
1027     case WM8962_ADCL_RETUNE_C4_1:
1028     case WM8962_ADCL_RETUNE_C4_0:
1029     case WM8962_ADCL_RETUNE_C5_1:
1030     case WM8962_ADCL_RETUNE_C5_0:
1031     case WM8962_ADCL_RETUNE_C6_1:
1032     case WM8962_ADCL_RETUNE_C6_0:
1033     case WM8962_ADCL_RETUNE_C7_1:
1034     case WM8962_ADCL_RETUNE_C7_0:
1035     case WM8962_ADCL_RETUNE_C8_1:
1036     case WM8962_ADCL_RETUNE_C8_0:
1037     case WM8962_ADCL_RETUNE_C9_1:
1038     case WM8962_ADCL_RETUNE_C9_0:
1039     case WM8962_ADCL_RETUNE_C10_1:
1040     case WM8962_ADCL_RETUNE_C10_0:
1041     case WM8962_ADCL_RETUNE_C11_1:
1042     case WM8962_ADCL_RETUNE_C11_0:
1043     case WM8962_ADCL_RETUNE_C12_1:
1044     case WM8962_ADCL_RETUNE_C12_0:
1045     case WM8962_ADCL_RETUNE_C13_1:
1046     case WM8962_ADCL_RETUNE_C13_0:
1047     case WM8962_ADCL_RETUNE_C14_1:
1048     case WM8962_ADCL_RETUNE_C14_0:
1049     case WM8962_ADCL_RETUNE_C15_1:
1050     case WM8962_ADCL_RETUNE_C15_0:
1051     case WM8962_ADCL_RETUNE_C16_1:
1052     case WM8962_ADCL_RETUNE_C16_0:
1053     case WM8962_ADCL_RETUNE_C17_1:
1054     case WM8962_ADCL_RETUNE_C17_0:
1055     case WM8962_ADCL_RETUNE_C18_1:
1056     case WM8962_ADCL_RETUNE_C18_0:
1057     case WM8962_ADCL_RETUNE_C19_1:
1058     case WM8962_ADCL_RETUNE_C19_0:
1059     case WM8962_ADCL_RETUNE_C20_1:
1060     case WM8962_ADCL_RETUNE_C20_0:
1061     case WM8962_ADCL_RETUNE_C21_1:
1062     case WM8962_ADCL_RETUNE_C21_0:
1063     case WM8962_ADCL_RETUNE_C22_1:
1064     case WM8962_ADCL_RETUNE_C22_0:
1065     case WM8962_ADCL_RETUNE_C23_1:
1066     case WM8962_ADCL_RETUNE_C23_0:
1067     case WM8962_ADCL_RETUNE_C24_1:
1068     case WM8962_ADCL_RETUNE_C24_0:
1069     case WM8962_ADCL_RETUNE_C25_1:
1070     case WM8962_ADCL_RETUNE_C25_0:
1071     case WM8962_ADCL_RETUNE_C26_1:
1072     case WM8962_ADCL_RETUNE_C26_0:
1073     case WM8962_ADCL_RETUNE_C27_1:
1074     case WM8962_ADCL_RETUNE_C27_0:
1075     case WM8962_ADCL_RETUNE_C28_1:
1076     case WM8962_ADCL_RETUNE_C28_0:
1077     case WM8962_ADCL_RETUNE_C29_1:
1078     case WM8962_ADCL_RETUNE_C29_0:
1079     case WM8962_ADCL_RETUNE_C30_1:
1080     case WM8962_ADCL_RETUNE_C30_0:
1081     case WM8962_ADCL_RETUNE_C31_1:
1082     case WM8962_ADCL_RETUNE_C31_0:
1083     case WM8962_ADCL_RETUNE_C32_1:
1084     case WM8962_ADCL_RETUNE_C32_0:
1085     case WM8962_RETUNEADC_PG2_1:
1086     case WM8962_RETUNEADC_PG2_0:
1087     case WM8962_RETUNEADC_PG_1:
1088     case WM8962_RETUNEADC_PG_0:
1089     case WM8962_ADCR_RETUNE_C1_1:
1090     case WM8962_ADCR_RETUNE_C1_0:
1091     case WM8962_ADCR_RETUNE_C2_1:
1092     case WM8962_ADCR_RETUNE_C2_0:
1093     case WM8962_ADCR_RETUNE_C3_1:
1094     case WM8962_ADCR_RETUNE_C3_0:
1095     case WM8962_ADCR_RETUNE_C4_1:
1096     case WM8962_ADCR_RETUNE_C4_0:
1097     case WM8962_ADCR_RETUNE_C5_1:
1098     case WM8962_ADCR_RETUNE_C5_0:
1099     case WM8962_ADCR_RETUNE_C6_1:
1100     case WM8962_ADCR_RETUNE_C6_0:
1101     case WM8962_ADCR_RETUNE_C7_1:
1102     case WM8962_ADCR_RETUNE_C7_0:
1103     case WM8962_ADCR_RETUNE_C8_1:
1104     case WM8962_ADCR_RETUNE_C8_0:
1105     case WM8962_ADCR_RETUNE_C9_1:
1106     case WM8962_ADCR_RETUNE_C9_0:
1107     case WM8962_ADCR_RETUNE_C10_1:
1108     case WM8962_ADCR_RETUNE_C10_0:
1109     case WM8962_ADCR_RETUNE_C11_1:
1110     case WM8962_ADCR_RETUNE_C11_0:
1111     case WM8962_ADCR_RETUNE_C12_1:
1112     case WM8962_ADCR_RETUNE_C12_0:
1113     case WM8962_ADCR_RETUNE_C13_1:
1114     case WM8962_ADCR_RETUNE_C13_0:
1115     case WM8962_ADCR_RETUNE_C14_1:
1116     case WM8962_ADCR_RETUNE_C14_0:
1117     case WM8962_ADCR_RETUNE_C15_1:
1118     case WM8962_ADCR_RETUNE_C15_0:
1119     case WM8962_ADCR_RETUNE_C16_1:
1120     case WM8962_ADCR_RETUNE_C16_0:
1121     case WM8962_ADCR_RETUNE_C17_1:
1122     case WM8962_ADCR_RETUNE_C17_0:
1123     case WM8962_ADCR_RETUNE_C18_1:
1124     case WM8962_ADCR_RETUNE_C18_0:
1125     case WM8962_ADCR_RETUNE_C19_1:
1126     case WM8962_ADCR_RETUNE_C19_0:
1127     case WM8962_ADCR_RETUNE_C20_1:
1128     case WM8962_ADCR_RETUNE_C20_0:
1129     case WM8962_ADCR_RETUNE_C21_1:
1130     case WM8962_ADCR_RETUNE_C21_0:
1131     case WM8962_ADCR_RETUNE_C22_1:
1132     case WM8962_ADCR_RETUNE_C22_0:
1133     case WM8962_ADCR_RETUNE_C23_1:
1134     case WM8962_ADCR_RETUNE_C23_0:
1135     case WM8962_ADCR_RETUNE_C24_1:
1136     case WM8962_ADCR_RETUNE_C24_0:
1137     case WM8962_ADCR_RETUNE_C25_1:
1138     case WM8962_ADCR_RETUNE_C25_0:
1139     case WM8962_ADCR_RETUNE_C26_1:
1140     case WM8962_ADCR_RETUNE_C26_0:
1141     case WM8962_ADCR_RETUNE_C27_1:
1142     case WM8962_ADCR_RETUNE_C27_0:
1143     case WM8962_ADCR_RETUNE_C28_1:
1144     case WM8962_ADCR_RETUNE_C28_0:
1145     case WM8962_ADCR_RETUNE_C29_1:
1146     case WM8962_ADCR_RETUNE_C29_0:
1147     case WM8962_ADCR_RETUNE_C30_1:
1148     case WM8962_ADCR_RETUNE_C30_0:
1149     case WM8962_ADCR_RETUNE_C31_1:
1150     case WM8962_ADCR_RETUNE_C31_0:
1151     case WM8962_ADCR_RETUNE_C32_1:
1152     case WM8962_ADCR_RETUNE_C32_0:
1153     case WM8962_DACL_RETUNE_C1_1:
1154     case WM8962_DACL_RETUNE_C1_0:
1155     case WM8962_DACL_RETUNE_C2_1:
1156     case WM8962_DACL_RETUNE_C2_0:
1157     case WM8962_DACL_RETUNE_C3_1:
1158     case WM8962_DACL_RETUNE_C3_0:
1159     case WM8962_DACL_RETUNE_C4_1:
1160     case WM8962_DACL_RETUNE_C4_0:
1161     case WM8962_DACL_RETUNE_C5_1:
1162     case WM8962_DACL_RETUNE_C5_0:
1163     case WM8962_DACL_RETUNE_C6_1:
1164     case WM8962_DACL_RETUNE_C6_0:
1165     case WM8962_DACL_RETUNE_C7_1:
1166     case WM8962_DACL_RETUNE_C7_0:
1167     case WM8962_DACL_RETUNE_C8_1:
1168     case WM8962_DACL_RETUNE_C8_0:
1169     case WM8962_DACL_RETUNE_C9_1:
1170     case WM8962_DACL_RETUNE_C9_0:
1171     case WM8962_DACL_RETUNE_C10_1:
1172     case WM8962_DACL_RETUNE_C10_0:
1173     case WM8962_DACL_RETUNE_C11_1:
1174     case WM8962_DACL_RETUNE_C11_0:
1175     case WM8962_DACL_RETUNE_C12_1:
1176     case WM8962_DACL_RETUNE_C12_0:
1177     case WM8962_DACL_RETUNE_C13_1:
1178     case WM8962_DACL_RETUNE_C13_0:
1179     case WM8962_DACL_RETUNE_C14_1:
1180     case WM8962_DACL_RETUNE_C14_0:
1181     case WM8962_DACL_RETUNE_C15_1:
1182     case WM8962_DACL_RETUNE_C15_0:
1183     case WM8962_DACL_RETUNE_C16_1:
1184     case WM8962_DACL_RETUNE_C16_0:
1185     case WM8962_DACL_RETUNE_C17_1:
1186     case WM8962_DACL_RETUNE_C17_0:
1187     case WM8962_DACL_RETUNE_C18_1:
1188     case WM8962_DACL_RETUNE_C18_0:
1189     case WM8962_DACL_RETUNE_C19_1:
1190     case WM8962_DACL_RETUNE_C19_0:
1191     case WM8962_DACL_RETUNE_C20_1:
1192     case WM8962_DACL_RETUNE_C20_0:
1193     case WM8962_DACL_RETUNE_C21_1:
1194     case WM8962_DACL_RETUNE_C21_0:
1195     case WM8962_DACL_RETUNE_C22_1:
1196     case WM8962_DACL_RETUNE_C22_0:
1197     case WM8962_DACL_RETUNE_C23_1:
1198     case WM8962_DACL_RETUNE_C23_0:
1199     case WM8962_DACL_RETUNE_C24_1:
1200     case WM8962_DACL_RETUNE_C24_0:
1201     case WM8962_DACL_RETUNE_C25_1:
1202     case WM8962_DACL_RETUNE_C25_0:
1203     case WM8962_DACL_RETUNE_C26_1:
1204     case WM8962_DACL_RETUNE_C26_0:
1205     case WM8962_DACL_RETUNE_C27_1:
1206     case WM8962_DACL_RETUNE_C27_0:
1207     case WM8962_DACL_RETUNE_C28_1:
1208     case WM8962_DACL_RETUNE_C28_0:
1209     case WM8962_DACL_RETUNE_C29_1:
1210     case WM8962_DACL_RETUNE_C29_0:
1211     case WM8962_DACL_RETUNE_C30_1:
1212     case WM8962_DACL_RETUNE_C30_0:
1213     case WM8962_DACL_RETUNE_C31_1:
1214     case WM8962_DACL_RETUNE_C31_0:
1215     case WM8962_DACL_RETUNE_C32_1:
1216     case WM8962_DACL_RETUNE_C32_0:
1217     case WM8962_RETUNEDAC_PG2_1:
1218     case WM8962_RETUNEDAC_PG2_0:
1219     case WM8962_RETUNEDAC_PG_1:
1220     case WM8962_RETUNEDAC_PG_0:
1221     case WM8962_DACR_RETUNE_C1_1:
1222     case WM8962_DACR_RETUNE_C1_0:
1223     case WM8962_DACR_RETUNE_C2_1:
1224     case WM8962_DACR_RETUNE_C2_0:
1225     case WM8962_DACR_RETUNE_C3_1:
1226     case WM8962_DACR_RETUNE_C3_0:
1227     case WM8962_DACR_RETUNE_C4_1:
1228     case WM8962_DACR_RETUNE_C4_0:
1229     case WM8962_DACR_RETUNE_C5_1:
1230     case WM8962_DACR_RETUNE_C5_0:
1231     case WM8962_DACR_RETUNE_C6_1:
1232     case WM8962_DACR_RETUNE_C6_0:
1233     case WM8962_DACR_RETUNE_C7_1:
1234     case WM8962_DACR_RETUNE_C7_0:
1235     case WM8962_DACR_RETUNE_C8_1:
1236     case WM8962_DACR_RETUNE_C8_0:
1237     case WM8962_DACR_RETUNE_C9_1:
1238     case WM8962_DACR_RETUNE_C9_0:
1239     case WM8962_DACR_RETUNE_C10_1:
1240     case WM8962_DACR_RETUNE_C10_0:
1241     case WM8962_DACR_RETUNE_C11_1:
1242     case WM8962_DACR_RETUNE_C11_0:
1243     case WM8962_DACR_RETUNE_C12_1:
1244     case WM8962_DACR_RETUNE_C12_0:
1245     case WM8962_DACR_RETUNE_C13_1:
1246     case WM8962_DACR_RETUNE_C13_0:
1247     case WM8962_DACR_RETUNE_C14_1:
1248     case WM8962_DACR_RETUNE_C14_0:
1249     case WM8962_DACR_RETUNE_C15_1:
1250     case WM8962_DACR_RETUNE_C15_0:
1251     case WM8962_DACR_RETUNE_C16_1:
1252     case WM8962_DACR_RETUNE_C16_0:
1253     case WM8962_DACR_RETUNE_C17_1:
1254     case WM8962_DACR_RETUNE_C17_0:
1255     case WM8962_DACR_RETUNE_C18_1:
1256     case WM8962_DACR_RETUNE_C18_0:
1257     case WM8962_DACR_RETUNE_C19_1:
1258     case WM8962_DACR_RETUNE_C19_0:
1259     case WM8962_DACR_RETUNE_C20_1:
1260     case WM8962_DACR_RETUNE_C20_0:
1261     case WM8962_DACR_RETUNE_C21_1:
1262     case WM8962_DACR_RETUNE_C21_0:
1263     case WM8962_DACR_RETUNE_C22_1:
1264     case WM8962_DACR_RETUNE_C22_0:
1265     case WM8962_DACR_RETUNE_C23_1:
1266     case WM8962_DACR_RETUNE_C23_0:
1267     case WM8962_DACR_RETUNE_C24_1:
1268     case WM8962_DACR_RETUNE_C24_0:
1269     case WM8962_DACR_RETUNE_C25_1:
1270     case WM8962_DACR_RETUNE_C25_0:
1271     case WM8962_DACR_RETUNE_C26_1:
1272     case WM8962_DACR_RETUNE_C26_0:
1273     case WM8962_DACR_RETUNE_C27_1:
1274     case WM8962_DACR_RETUNE_C27_0:
1275     case WM8962_DACR_RETUNE_C28_1:
1276     case WM8962_DACR_RETUNE_C28_0:
1277     case WM8962_DACR_RETUNE_C29_1:
1278     case WM8962_DACR_RETUNE_C29_0:
1279     case WM8962_DACR_RETUNE_C30_1:
1280     case WM8962_DACR_RETUNE_C30_0:
1281     case WM8962_DACR_RETUNE_C31_1:
1282     case WM8962_DACR_RETUNE_C31_0:
1283     case WM8962_DACR_RETUNE_C32_1:
1284     case WM8962_DACR_RETUNE_C32_0:
1285     case WM8962_VSS_XHD2_1:
1286     case WM8962_VSS_XHD2_0:
1287     case WM8962_VSS_XHD3_1:
1288     case WM8962_VSS_XHD3_0:
1289     case WM8962_VSS_XHN1_1:
1290     case WM8962_VSS_XHN1_0:
1291     case WM8962_VSS_XHN2_1:
1292     case WM8962_VSS_XHN2_0:
1293     case WM8962_VSS_XHN3_1:
1294     case WM8962_VSS_XHN3_0:
1295     case WM8962_VSS_XLA_1:
1296     case WM8962_VSS_XLA_0:
1297     case WM8962_VSS_XLB_1:
1298     case WM8962_VSS_XLB_0:
1299     case WM8962_VSS_XLG_1:
1300     case WM8962_VSS_XLG_0:
1301     case WM8962_VSS_PG2_1:
1302     case WM8962_VSS_PG2_0:
1303     case WM8962_VSS_PG_1:
1304     case WM8962_VSS_PG_0:
1305     case WM8962_VSS_XTD1_1:
1306     case WM8962_VSS_XTD1_0:
1307     case WM8962_VSS_XTD2_1:
1308     case WM8962_VSS_XTD2_0:
1309     case WM8962_VSS_XTD3_1:
1310     case WM8962_VSS_XTD3_0:
1311     case WM8962_VSS_XTD4_1:
1312     case WM8962_VSS_XTD4_0:
1313     case WM8962_VSS_XTD5_1:
1314     case WM8962_VSS_XTD5_0:
1315     case WM8962_VSS_XTD6_1:
1316     case WM8962_VSS_XTD6_0:
1317     case WM8962_VSS_XTD7_1:
1318     case WM8962_VSS_XTD7_0:
1319     case WM8962_VSS_XTD8_1:
1320     case WM8962_VSS_XTD8_0:
1321     case WM8962_VSS_XTD9_1:
1322     case WM8962_VSS_XTD9_0:
1323     case WM8962_VSS_XTD10_1:
1324     case WM8962_VSS_XTD10_0:
1325     case WM8962_VSS_XTD11_1:
1326     case WM8962_VSS_XTD11_0:
1327     case WM8962_VSS_XTD12_1:
1328     case WM8962_VSS_XTD12_0:
1329     case WM8962_VSS_XTD13_1:
1330     case WM8962_VSS_XTD13_0:
1331     case WM8962_VSS_XTD14_1:
1332     case WM8962_VSS_XTD14_0:
1333     case WM8962_VSS_XTD15_1:
1334     case WM8962_VSS_XTD15_0:
1335     case WM8962_VSS_XTD16_1:
1336     case WM8962_VSS_XTD16_0:
1337     case WM8962_VSS_XTD17_1:
1338     case WM8962_VSS_XTD17_0:
1339     case WM8962_VSS_XTD18_1:
1340     case WM8962_VSS_XTD18_0:
1341     case WM8962_VSS_XTD19_1:
1342     case WM8962_VSS_XTD19_0:
1343     case WM8962_VSS_XTD20_1:
1344     case WM8962_VSS_XTD20_0:
1345     case WM8962_VSS_XTD21_1:
1346     case WM8962_VSS_XTD21_0:
1347     case WM8962_VSS_XTD22_1:
1348     case WM8962_VSS_XTD22_0:
1349     case WM8962_VSS_XTD23_1:
1350     case WM8962_VSS_XTD23_0:
1351     case WM8962_VSS_XTD24_1:
1352     case WM8962_VSS_XTD24_0:
1353     case WM8962_VSS_XTD25_1:
1354     case WM8962_VSS_XTD25_0:
1355     case WM8962_VSS_XTD26_1:
1356     case WM8962_VSS_XTD26_0:
1357     case WM8962_VSS_XTD27_1:
1358     case WM8962_VSS_XTD27_0:
1359     case WM8962_VSS_XTD28_1:
1360     case WM8962_VSS_XTD28_0:
1361     case WM8962_VSS_XTD29_1:
1362     case WM8962_VSS_XTD29_0:
1363     case WM8962_VSS_XTD30_1:
1364     case WM8962_VSS_XTD30_0:
1365     case WM8962_VSS_XTD31_1:
1366     case WM8962_VSS_XTD31_0:
1367     case WM8962_VSS_XTD32_1:
1368     case WM8962_VSS_XTD32_0:
1369     case WM8962_VSS_XTS1_1:
1370     case WM8962_VSS_XTS1_0:
1371     case WM8962_VSS_XTS2_1:
1372     case WM8962_VSS_XTS2_0:
1373     case WM8962_VSS_XTS3_1:
1374     case WM8962_VSS_XTS3_0:
1375     case WM8962_VSS_XTS4_1:
1376     case WM8962_VSS_XTS4_0:
1377     case WM8962_VSS_XTS5_1:
1378     case WM8962_VSS_XTS5_0:
1379     case WM8962_VSS_XTS6_1:
1380     case WM8962_VSS_XTS6_0:
1381     case WM8962_VSS_XTS7_1:
1382     case WM8962_VSS_XTS7_0:
1383     case WM8962_VSS_XTS8_1:
1384     case WM8962_VSS_XTS8_0:
1385     case WM8962_VSS_XTS9_1:
1386     case WM8962_VSS_XTS9_0:
1387     case WM8962_VSS_XTS10_1:
1388     case WM8962_VSS_XTS10_0:
1389     case WM8962_VSS_XTS11_1:
1390     case WM8962_VSS_XTS11_0:
1391     case WM8962_VSS_XTS12_1:
1392     case WM8962_VSS_XTS12_0:
1393     case WM8962_VSS_XTS13_1:
1394     case WM8962_VSS_XTS13_0:
1395     case WM8962_VSS_XTS14_1:
1396     case WM8962_VSS_XTS14_0:
1397     case WM8962_VSS_XTS15_1:
1398     case WM8962_VSS_XTS15_0:
1399     case WM8962_VSS_XTS16_1:
1400     case WM8962_VSS_XTS16_0:
1401     case WM8962_VSS_XTS17_1:
1402     case WM8962_VSS_XTS17_0:
1403     case WM8962_VSS_XTS18_1:
1404     case WM8962_VSS_XTS18_0:
1405     case WM8962_VSS_XTS19_1:
1406     case WM8962_VSS_XTS19_0:
1407     case WM8962_VSS_XTS20_1:
1408     case WM8962_VSS_XTS20_0:
1409     case WM8962_VSS_XTS21_1:
1410     case WM8962_VSS_XTS21_0:
1411     case WM8962_VSS_XTS22_1:
1412     case WM8962_VSS_XTS22_0:
1413     case WM8962_VSS_XTS23_1:
1414     case WM8962_VSS_XTS23_0:
1415     case WM8962_VSS_XTS24_1:
1416     case WM8962_VSS_XTS24_0:
1417     case WM8962_VSS_XTS25_1:
1418     case WM8962_VSS_XTS25_0:
1419     case WM8962_VSS_XTS26_1:
1420     case WM8962_VSS_XTS26_0:
1421     case WM8962_VSS_XTS27_1:
1422     case WM8962_VSS_XTS27_0:
1423     case WM8962_VSS_XTS28_1:
1424     case WM8962_VSS_XTS28_0:
1425     case WM8962_VSS_XTS29_1:
1426     case WM8962_VSS_XTS29_0:
1427     case WM8962_VSS_XTS30_1:
1428     case WM8962_VSS_XTS30_0:
1429     case WM8962_VSS_XTS31_1:
1430     case WM8962_VSS_XTS31_0:
1431     case WM8962_VSS_XTS32_1:
1432     case WM8962_VSS_XTS32_0:
1433         return true;
1434     default:
1435         return false;
1436     }
1437 }
1438 
1439 static int wm8962_reset(struct wm8962_priv *wm8962)
1440 {
1441     int ret;
1442 
1443     ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1444     if (ret != 0)
1445         return ret;
1446 
1447     return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1448 }
1449 
1450 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1451 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1452 static const DECLARE_TLV_DB_RANGE(mixinpga_tlv,
1453     0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1454     2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1455     3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1456     5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1457     6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0)
1458 );
1459 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1460 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1461 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1462 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1463 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1464 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1465 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1466 static const DECLARE_TLV_DB_RANGE(classd_tlv,
1467     0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1468     7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0)
1469 );
1470 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1471 
1472 static int wm8962_dsp2_write_config(struct snd_soc_component *component)
1473 {
1474     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1475 
1476     return regcache_sync_region(wm8962->regmap,
1477                     WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1478 }
1479 
1480 static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val)
1481 {
1482     u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME);
1483     u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME);
1484     u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1);
1485 
1486     /* Mute the ADCs and DACs */
1487     snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, 0);
1488     snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1489     snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1490                 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1491 
1492     snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val);
1493 
1494     /* Restore the ADCs and DACs */
1495     snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, adcl);
1496     snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, adcr);
1497     snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
1498                 WM8962_DAC_MUTE, dac);
1499 
1500     return 0;
1501 }
1502 
1503 static int wm8962_dsp2_start(struct snd_soc_component *component)
1504 {
1505     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1506 
1507     wm8962_dsp2_write_config(component);
1508 
1509     snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1510 
1511     wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1512 
1513     return 0;
1514 }
1515 
1516 static int wm8962_dsp2_stop(struct snd_soc_component *component)
1517 {
1518     wm8962_dsp2_set_enable(component, 0);
1519 
1520     snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1521 
1522     return 0;
1523 }
1524 
1525 #define WM8962_DSP2_ENABLE(xname, xshift) \
1526 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1527     .info = wm8962_dsp2_ena_info, \
1528     .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1529     .private_value = xshift }
1530 
1531 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1532                 struct snd_ctl_elem_info *uinfo)
1533 {
1534     uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1535 
1536     uinfo->count = 1;
1537     uinfo->value.integer.min = 0;
1538     uinfo->value.integer.max = 1;
1539 
1540     return 0;
1541 }
1542 
1543 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1544                    struct snd_ctl_elem_value *ucontrol)
1545 {
1546     int shift = kcontrol->private_value;
1547     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1548     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1549 
1550     ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1551 
1552     return 0;
1553 }
1554 
1555 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1556                    struct snd_ctl_elem_value *ucontrol)
1557 {
1558     int shift = kcontrol->private_value;
1559     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1560     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1561     int old = wm8962->dsp2_ena;
1562     int ret = 0;
1563     int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) &
1564         WM8962_DSP2_ENA;
1565 
1566     mutex_lock(&wm8962->dsp2_ena_lock);
1567 
1568     if (ucontrol->value.integer.value[0])
1569         wm8962->dsp2_ena |= 1 << shift;
1570     else
1571         wm8962->dsp2_ena &= ~(1 << shift);
1572 
1573     if (wm8962->dsp2_ena == old)
1574         goto out;
1575 
1576     ret = 1;
1577 
1578     if (dsp2_running) {
1579         if (wm8962->dsp2_ena)
1580             wm8962_dsp2_set_enable(component, wm8962->dsp2_ena);
1581         else
1582             wm8962_dsp2_stop(component);
1583     }
1584 
1585 out:
1586     mutex_unlock(&wm8962->dsp2_ena_lock);
1587 
1588     return ret;
1589 }
1590 
1591 /* The VU bits for the headphones are in a different register to the mute
1592  * bits and only take effect on the PGA if it is actually powered.
1593  */
1594 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1595                 struct snd_ctl_elem_value *ucontrol)
1596 {
1597     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1598     int ret;
1599 
1600     /* Apply the update (if any) */
1601         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1602     if (ret == 0)
1603         return 0;
1604 
1605     /* If the left PGA is enabled hit that VU bit... */
1606     ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
1607     if (ret & WM8962_HPOUTL_PGA_ENA) {
1608         snd_soc_component_write(component, WM8962_HPOUTL_VOLUME,
1609                   snd_soc_component_read(component, WM8962_HPOUTL_VOLUME));
1610         return 1;
1611     }
1612 
1613     /* ...otherwise the right.  The VU is stereo. */
1614     if (ret & WM8962_HPOUTR_PGA_ENA)
1615         snd_soc_component_write(component, WM8962_HPOUTR_VOLUME,
1616                   snd_soc_component_read(component, WM8962_HPOUTR_VOLUME));
1617 
1618     return 1;
1619 }
1620 
1621 /* The VU bits for the speakers are in a different register to the mute
1622  * bits and only take effect on the PGA if it is actually powered.
1623  */
1624 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1625                 struct snd_ctl_elem_value *ucontrol)
1626 {
1627     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1628     int ret;
1629 
1630     /* Apply the update (if any) */
1631         ret = snd_soc_put_volsw(kcontrol, ucontrol);
1632     if (ret == 0)
1633         return 0;
1634 
1635     /* If the left PGA is enabled hit that VU bit... */
1636     ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2);
1637     if (ret & WM8962_SPKOUTL_PGA_ENA) {
1638         snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME,
1639                   snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME));
1640         return 1;
1641     }
1642 
1643     /* ...otherwise the right.  The VU is stereo. */
1644     if (ret & WM8962_SPKOUTR_PGA_ENA)
1645         snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME,
1646                   snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME));
1647 
1648     return 1;
1649 }
1650 
1651 static const char *cap_hpf_mode_text[] = {
1652     "Hi-fi", "Application"
1653 };
1654 
1655 static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1656                 WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
1657 
1658 
1659 static const char *cap_lhpf_mode_text[] = {
1660     "LPF", "HPF"
1661 };
1662 
1663 static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1664                 WM8962_LHPF1, 1, cap_lhpf_mode_text);
1665 
1666 static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1667 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1668 
1669 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1670            mixin_tlv),
1671 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1672            mixinpga_tlv),
1673 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1674            mixin_tlv),
1675 
1676 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1677            mixin_tlv),
1678 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1679            mixinpga_tlv),
1680 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1681            mixin_tlv),
1682 
1683 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1684          WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1685 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1686          WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1687 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1688          WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1689 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1690          WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1691 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1692 SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1693 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1694 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1695 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1696 
1697 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1698          WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1699 
1700 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1701          WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1702 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1703 SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1704 SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1705 SOC_SINGLE("DAC Monomix Switch", WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0),
1706 SOC_SINGLE("ADC Monomix Switch", WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0),
1707 
1708 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1709        5, 1, 0),
1710 
1711 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1712 
1713 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1714          WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1715 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1716            snd_soc_get_volsw, wm8962_put_hp_sw),
1717 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1718          7, 1, 0),
1719 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1720            hp_tlv),
1721 
1722 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1723          WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1724 
1725 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1726            3, 7, 0, bypass_tlv),
1727 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1728            0, 7, 0, bypass_tlv),
1729 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1730            7, 1, 1, inmix_tlv),
1731 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1732            6, 1, 1, inmix_tlv),
1733 
1734 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1735            3, 7, 0, bypass_tlv),
1736 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1737            0, 7, 0, bypass_tlv),
1738 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1739            7, 1, 1, inmix_tlv),
1740 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1741            6, 1, 1, inmix_tlv),
1742 
1743 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1744            classd_tlv),
1745 
1746 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1747 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1748          WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1749 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1750          WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1751 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1752          WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1753 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1754          WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1755 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1756          WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1757 SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1758 SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1759 
1760 
1761 SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1762 SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1763 
1764 SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1765 SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1766 
1767 SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1768 SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1769 
1770 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1771 SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1772 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1773 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1774 SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1775 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1776 SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1777 
1778 SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1779         WM8962_ALCR_ENA_SHIFT, 1, 0),
1780 SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1781         WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
1782 };
1783 
1784 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1785 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1786 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1787            snd_soc_get_volsw, wm8962_put_spk_sw),
1788 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1789 
1790 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1791 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1792            3, 7, 0, bypass_tlv),
1793 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1794            0, 7, 0, bypass_tlv),
1795 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1796            7, 1, 1, inmix_tlv),
1797 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1798            6, 1, 1, inmix_tlv),
1799 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1800            7, 1, 0, inmix_tlv),
1801 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1802            6, 1, 0, inmix_tlv),
1803 };
1804 
1805 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1806 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1807          WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1808 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1809            snd_soc_get_volsw, wm8962_put_spk_sw),
1810 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1811          7, 1, 0),
1812 
1813 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1814          WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1815 
1816 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1817            3, 7, 0, bypass_tlv),
1818 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1819            0, 7, 0, bypass_tlv),
1820 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1821            7, 1, 1, inmix_tlv),
1822 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1823            6, 1, 1, inmix_tlv),
1824 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1825            7, 1, 0, inmix_tlv),
1826 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1827            6, 1, 0, inmix_tlv),
1828 
1829 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1830            3, 7, 0, bypass_tlv),
1831 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1832            0, 7, 0, bypass_tlv),
1833 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1834            7, 1, 1, inmix_tlv),
1835 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1836            6, 1, 1, inmix_tlv),
1837 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1838            5, 1, 0, inmix_tlv),
1839 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1840            4, 1, 0, inmix_tlv),
1841 };
1842 
1843 static int cp_event(struct snd_soc_dapm_widget *w,
1844             struct snd_kcontrol *kcontrol, int event)
1845 {
1846     switch (event) {
1847     case SND_SOC_DAPM_POST_PMU:
1848         msleep(5);
1849         break;
1850 
1851     default:
1852         WARN(1, "Invalid event %d\n", event);
1853         return -EINVAL;
1854     }
1855 
1856     return 0;
1857 }
1858 
1859 static int hp_event(struct snd_soc_dapm_widget *w,
1860             struct snd_kcontrol *kcontrol, int event)
1861 {
1862     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1863     int timeout;
1864     int reg;
1865     int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1866             WM8962_DCS_STARTUP_DONE_HP1R);
1867 
1868     switch (event) {
1869     case SND_SOC_DAPM_POST_PMU:
1870         snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1871                     WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1872                     WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1873         udelay(20);
1874 
1875         snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1876                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1877                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1878 
1879         /* Start the DC servo */
1880         snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1881                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1882                     WM8962_HP1L_DCS_STARTUP |
1883                     WM8962_HP1R_DCS_STARTUP,
1884                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1885                     WM8962_HP1L_DCS_STARTUP |
1886                     WM8962_HP1R_DCS_STARTUP);
1887 
1888         /* Wait for it to complete, should be well under 100ms */
1889         timeout = 0;
1890         do {
1891             msleep(1);
1892             reg = snd_soc_component_read(component, WM8962_DC_SERVO_6);
1893             if (reg < 0) {
1894                 dev_err(component->dev,
1895                     "Failed to read DCS status: %d\n",
1896                     reg);
1897                 continue;
1898             }
1899             dev_dbg(component->dev, "DCS status: %x\n", reg);
1900         } while (++timeout < 200 && (reg & expected) != expected);
1901 
1902         if ((reg & expected) != expected)
1903             dev_err(component->dev, "DC servo timed out\n");
1904         else
1905             dev_dbg(component->dev, "DC servo complete after %dms\n",
1906                 timeout);
1907 
1908         snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1909                     WM8962_HP1L_ENA_OUTP |
1910                     WM8962_HP1R_ENA_OUTP,
1911                     WM8962_HP1L_ENA_OUTP |
1912                     WM8962_HP1R_ENA_OUTP);
1913         udelay(20);
1914 
1915         snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1916                     WM8962_HP1L_RMV_SHORT |
1917                     WM8962_HP1R_RMV_SHORT,
1918                     WM8962_HP1L_RMV_SHORT |
1919                     WM8962_HP1R_RMV_SHORT);
1920         break;
1921 
1922     case SND_SOC_DAPM_PRE_PMD:
1923         snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1924                     WM8962_HP1L_RMV_SHORT |
1925                     WM8962_HP1R_RMV_SHORT, 0);
1926 
1927         udelay(20);
1928 
1929         snd_soc_component_update_bits(component, WM8962_DC_SERVO_1,
1930                     WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1931                     WM8962_HP1L_DCS_STARTUP |
1932                     WM8962_HP1R_DCS_STARTUP,
1933                     0);
1934 
1935         snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0,
1936                     WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1937                     WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1938                     WM8962_HP1L_ENA_OUTP |
1939                     WM8962_HP1R_ENA_OUTP, 0);
1940                     
1941         break;
1942 
1943     default:
1944         WARN(1, "Invalid event %d\n", event);
1945         return -EINVAL;
1946     
1947     }
1948 
1949     return 0;
1950 }
1951 
1952 /* VU bits for the output PGAs only take effect while the PGA is powered */
1953 static int out_pga_event(struct snd_soc_dapm_widget *w,
1954              struct snd_kcontrol *kcontrol, int event)
1955 {
1956     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1957     int reg;
1958 
1959     switch (w->shift) {
1960     case WM8962_HPOUTR_PGA_ENA_SHIFT:
1961         reg = WM8962_HPOUTR_VOLUME;
1962         break;
1963     case WM8962_HPOUTL_PGA_ENA_SHIFT:
1964         reg = WM8962_HPOUTL_VOLUME;
1965         break;
1966     case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1967         reg = WM8962_SPKOUTR_VOLUME;
1968         break;
1969     case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1970         reg = WM8962_SPKOUTL_VOLUME;
1971         break;
1972     default:
1973         WARN(1, "Invalid shift %d\n", w->shift);
1974         return -EINVAL;
1975     }
1976 
1977     switch (event) {
1978     case SND_SOC_DAPM_POST_PMU:
1979         return snd_soc_component_write(component, reg,
1980             snd_soc_component_read(component, reg));
1981     default:
1982         WARN(1, "Invalid event %d\n", event);
1983         return -EINVAL;
1984     }
1985 }
1986 
1987 static int dsp2_event(struct snd_soc_dapm_widget *w,
1988               struct snd_kcontrol *kcontrol, int event)
1989 {
1990     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1991     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
1992 
1993     switch (event) {
1994     case SND_SOC_DAPM_POST_PMU:
1995         if (wm8962->dsp2_ena)
1996             wm8962_dsp2_start(component);
1997         break;
1998 
1999     case SND_SOC_DAPM_PRE_PMD:
2000         if (wm8962->dsp2_ena)
2001             wm8962_dsp2_stop(component);
2002         break;
2003 
2004     default:
2005         WARN(1, "Invalid event %d\n", event);
2006         return -EINVAL;
2007     }
2008 
2009     return 0;
2010 }
2011 
2012 static const char *st_text[] = { "None", "Left", "Right" };
2013 
2014 static SOC_ENUM_SINGLE_DECL(str_enum,
2015                 WM8962_DAC_DSP_MIXING_1, 2, st_text);
2016 
2017 static const struct snd_kcontrol_new str_mux =
2018     SOC_DAPM_ENUM("Right Sidetone", str_enum);
2019 
2020 static SOC_ENUM_SINGLE_DECL(stl_enum,
2021                 WM8962_DAC_DSP_MIXING_2, 2, st_text);
2022 
2023 static const struct snd_kcontrol_new stl_mux =
2024     SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2025 
2026 static const char *outmux_text[] = { "DAC", "Mixer" };
2027 
2028 static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2029                 WM8962_SPEAKER_MIXER_2, 7, outmux_text);
2030 
2031 static const struct snd_kcontrol_new spkoutr_mux =
2032     SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2033 
2034 static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2035                 WM8962_SPEAKER_MIXER_1, 7, outmux_text);
2036 
2037 static const struct snd_kcontrol_new spkoutl_mux =
2038     SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2039 
2040 static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2041                 WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
2042 
2043 static const struct snd_kcontrol_new hpoutr_mux =
2044     SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2045 
2046 static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2047                 WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
2048 
2049 static const struct snd_kcontrol_new hpoutl_mux =
2050     SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2051 
2052 static const char * const input_mode_text[] = { "Analog", "Digital" };
2053 
2054 static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text);
2055 
2056 static const struct snd_kcontrol_new input_mode_mux =
2057     SOC_DAPM_ENUM("Input Mode", input_mode_enum);
2058 
2059 static const struct snd_kcontrol_new inpgal[] = {
2060 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2061 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2062 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2063 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2064 };
2065 
2066 static const struct snd_kcontrol_new inpgar[] = {
2067 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2068 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2069 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2070 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2071 };
2072 
2073 static const struct snd_kcontrol_new mixinl[] = {
2074 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2075 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2076 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2077 };
2078 
2079 static const struct snd_kcontrol_new mixinr[] = {
2080 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2081 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2082 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2083 };
2084 
2085 static const struct snd_kcontrol_new hpmixl[] = {
2086 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2087 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2088 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2089 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2090 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2091 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2092 };
2093 
2094 static const struct snd_kcontrol_new hpmixr[] = {
2095 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2096 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2097 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2098 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2099 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2100 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2101 };
2102 
2103 static const struct snd_kcontrol_new spkmixl[] = {
2104 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2105 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2106 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2107 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2108 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2109 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2110 };
2111 
2112 static const struct snd_kcontrol_new spkmixr[] = {
2113 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2114 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2115 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2116 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2117 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2118 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2119 };
2120 
2121 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2122 SND_SOC_DAPM_INPUT("IN1L"),
2123 SND_SOC_DAPM_INPUT("IN1R"),
2124 SND_SOC_DAPM_INPUT("IN2L"),
2125 SND_SOC_DAPM_INPUT("IN2R"),
2126 SND_SOC_DAPM_INPUT("IN3L"),
2127 SND_SOC_DAPM_INPUT("IN3R"),
2128 SND_SOC_DAPM_INPUT("IN4L"),
2129 SND_SOC_DAPM_INPUT("IN4R"),
2130 SND_SOC_DAPM_SIGGEN("Beep"),
2131 SND_SOC_DAPM_INPUT("DMICDAT"),
2132 
2133 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2134 
2135 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2136 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2137 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2138             SND_SOC_DAPM_POST_PMU),
2139 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2140 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2141               WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2142               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2143 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2144 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2145 
2146 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2147            inpgal, ARRAY_SIZE(inpgal)),
2148 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2149            inpgar, ARRAY_SIZE(inpgar)),
2150 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2151            mixinl, ARRAY_SIZE(mixinl)),
2152 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2153            mixinr, ARRAY_SIZE(mixinr)),
2154 
2155 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2156 
2157 SND_SOC_DAPM_MUX("Input Mode L", SND_SOC_NOPM, 0, 0, &input_mode_mux),
2158 SND_SOC_DAPM_MUX("Input Mode R", SND_SOC_NOPM, 0, 0, &input_mode_mux),
2159 
2160 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2161 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2162 
2163 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2164 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2165 
2166 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2167 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2168 
2169 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2170 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2171 
2172 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2173            hpmixl, ARRAY_SIZE(hpmixl)),
2174 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2175            hpmixr, ARRAY_SIZE(hpmixr)),
2176 
2177 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2178            out_pga_event, SND_SOC_DAPM_POST_PMU),
2179 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2180            out_pga_event, SND_SOC_DAPM_POST_PMU),
2181 
2182 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2183            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2184 
2185 SND_SOC_DAPM_OUTPUT("HPOUTL"),
2186 SND_SOC_DAPM_OUTPUT("HPOUTR"),
2187 };
2188 
2189 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2190 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2191            spkmixl, ARRAY_SIZE(spkmixl)),
2192 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2193            out_pga_event, SND_SOC_DAPM_POST_PMU),
2194 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2195 SND_SOC_DAPM_OUTPUT("SPKOUT"),
2196 };
2197 
2198 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2199 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2200            spkmixl, ARRAY_SIZE(spkmixl)),
2201 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2202            spkmixr, ARRAY_SIZE(spkmixr)),
2203 
2204 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2205            out_pga_event, SND_SOC_DAPM_POST_PMU),
2206 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2207            out_pga_event, SND_SOC_DAPM_POST_PMU),
2208 
2209 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2210 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2211 
2212 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2213 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2214 };
2215 
2216 static const struct snd_soc_dapm_route wm8962_intercon[] = {
2217     { "INPGAL", "IN1L Switch", "IN1L" },
2218     { "INPGAL", "IN2L Switch", "IN2L" },
2219     { "INPGAL", "IN3L Switch", "IN3L" },
2220     { "INPGAL", "IN4L Switch", "IN4L" },
2221 
2222     { "INPGAR", "IN1R Switch", "IN1R" },
2223     { "INPGAR", "IN2R Switch", "IN2R" },
2224     { "INPGAR", "IN3R Switch", "IN3R" },
2225     { "INPGAR", "IN4R Switch", "IN4R" },
2226 
2227     { "MIXINL", "IN2L Switch", "IN2L" },
2228     { "MIXINL", "IN3L Switch", "IN3L" },
2229     { "MIXINL", "PGA Switch", "INPGAL" },
2230 
2231     { "MIXINR", "IN2R Switch", "IN2R" },
2232     { "MIXINR", "IN3R Switch", "IN3R" },
2233     { "MIXINR", "PGA Switch", "INPGAR" },
2234 
2235     { "MICBIAS", NULL, "SYSCLK" },
2236 
2237     { "DMIC_ENA", NULL, "DMICDAT" },
2238 
2239     { "Input Mode L", "Analog", "MIXINL" },
2240     { "Input Mode L", "Digital", "DMIC_ENA" },
2241     { "Input Mode R", "Analog", "MIXINR" },
2242     { "Input Mode R", "Digital", "DMIC_ENA" },
2243 
2244     { "ADCL", NULL, "SYSCLK" },
2245     { "ADCL", NULL, "TOCLK" },
2246     { "ADCL", NULL, "Input Mode L" },
2247     { "ADCL", NULL, "DSP2" },
2248 
2249     { "ADCR", NULL, "SYSCLK" },
2250     { "ADCR", NULL, "TOCLK" },
2251     { "ADCR", NULL, "Input Mode R" },
2252     { "ADCR", NULL, "DSP2" },
2253 
2254     { "STL", "Left", "ADCL" },
2255     { "STL", "Right", "ADCR" },
2256     { "STL", NULL, "Class G" },
2257 
2258     { "STR", "Left", "ADCL" },
2259     { "STR", "Right", "ADCR" },
2260     { "STR", NULL, "Class G" },
2261 
2262     { "DACL", NULL, "SYSCLK" },
2263     { "DACL", NULL, "TOCLK" },
2264     { "DACL", NULL, "Beep" },
2265     { "DACL", NULL, "STL" },
2266     { "DACL", NULL, "DSP2" },
2267 
2268     { "DACR", NULL, "SYSCLK" },
2269     { "DACR", NULL, "TOCLK" },
2270     { "DACR", NULL, "Beep" },
2271     { "DACR", NULL, "STR" },
2272     { "DACR", NULL, "DSP2" },
2273 
2274     { "HPMIXL", "IN4L Switch", "IN4L" },
2275     { "HPMIXL", "IN4R Switch", "IN4R" },
2276     { "HPMIXL", "DACL Switch", "DACL" },
2277     { "HPMIXL", "DACR Switch", "DACR" },
2278     { "HPMIXL", "MIXINL Switch", "MIXINL" },
2279     { "HPMIXL", "MIXINR Switch", "MIXINR" },
2280 
2281     { "HPMIXR", "IN4L Switch", "IN4L" },
2282     { "HPMIXR", "IN4R Switch", "IN4R" },
2283     { "HPMIXR", "DACL Switch", "DACL" },
2284     { "HPMIXR", "DACR Switch", "DACR" },
2285     { "HPMIXR", "MIXINL Switch", "MIXINL" },
2286     { "HPMIXR", "MIXINR Switch", "MIXINR" },
2287 
2288     { "Left Bypass", NULL, "HPMIXL" },
2289     { "Left Bypass", NULL, "Class G" },
2290 
2291     { "Right Bypass", NULL, "HPMIXR" },
2292     { "Right Bypass", NULL, "Class G" },
2293 
2294     { "HPOUTL PGA", "Mixer", "Left Bypass" },
2295     { "HPOUTL PGA", "DAC", "DACL" },
2296 
2297     { "HPOUTR PGA", "Mixer", "Right Bypass" },
2298     { "HPOUTR PGA", "DAC", "DACR" },
2299 
2300     { "HPOUT", NULL, "HPOUTL PGA" },
2301     { "HPOUT", NULL, "HPOUTR PGA" },
2302     { "HPOUT", NULL, "Charge Pump" },
2303     { "HPOUT", NULL, "SYSCLK" },
2304     { "HPOUT", NULL, "TOCLK" },
2305 
2306     { "HPOUTL", NULL, "HPOUT" },
2307     { "HPOUTR", NULL, "HPOUT" },
2308 
2309     { "HPOUTL", NULL, "TEMP_HP" },
2310     { "HPOUTR", NULL, "TEMP_HP" },
2311 };
2312 
2313 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2314     { "Speaker Mixer", "IN4L Switch", "IN4L" },
2315     { "Speaker Mixer", "IN4R Switch", "IN4R" },
2316     { "Speaker Mixer", "DACL Switch", "DACL" },
2317     { "Speaker Mixer", "DACR Switch", "DACR" },
2318     { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2319     { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2320 
2321     { "Speaker PGA", "Mixer", "Speaker Mixer" },
2322     { "Speaker PGA", "DAC", "DACL" },
2323 
2324     { "Speaker Output", NULL, "Speaker PGA" },
2325     { "Speaker Output", NULL, "SYSCLK" },
2326     { "Speaker Output", NULL, "TOCLK" },
2327     { "Speaker Output", NULL, "TEMP_SPK" },
2328 
2329     { "SPKOUT", NULL, "Speaker Output" },
2330 };
2331 
2332 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2333     { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2334     { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2335     { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2336     { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2337     { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2338     { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2339 
2340     { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2341     { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2342     { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2343     { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2344     { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2345     { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2346 
2347     { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2348     { "SPKOUTL PGA", "DAC", "DACL" },
2349 
2350     { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2351     { "SPKOUTR PGA", "DAC", "DACR" },
2352 
2353     { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2354     { "SPKOUTL Output", NULL, "SYSCLK" },
2355     { "SPKOUTL Output", NULL, "TOCLK" },
2356     { "SPKOUTL Output", NULL, "TEMP_SPK" },
2357 
2358     { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2359     { "SPKOUTR Output", NULL, "SYSCLK" },
2360     { "SPKOUTR Output", NULL, "TOCLK" },
2361     { "SPKOUTR Output", NULL, "TEMP_SPK" },
2362 
2363     { "SPKOUTL", NULL, "SPKOUTL Output" },
2364     { "SPKOUTR", NULL, "SPKOUTR Output" },
2365 };
2366 
2367 static int wm8962_add_widgets(struct snd_soc_component *component)
2368 {
2369     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2370     struct wm8962_pdata *pdata = &wm8962->pdata;
2371     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2372 
2373     snd_soc_add_component_controls(component, wm8962_snd_controls,
2374                  ARRAY_SIZE(wm8962_snd_controls));
2375     if (pdata->spk_mono)
2376         snd_soc_add_component_controls(component, wm8962_spk_mono_controls,
2377                      ARRAY_SIZE(wm8962_spk_mono_controls));
2378     else
2379         snd_soc_add_component_controls(component, wm8962_spk_stereo_controls,
2380                      ARRAY_SIZE(wm8962_spk_stereo_controls));
2381 
2382 
2383     snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2384                   ARRAY_SIZE(wm8962_dapm_widgets));
2385     if (pdata->spk_mono)
2386         snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2387                       ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2388     else
2389         snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2390                       ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2391 
2392     snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2393                 ARRAY_SIZE(wm8962_intercon));
2394     if (pdata->spk_mono)
2395         snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2396                     ARRAY_SIZE(wm8962_spk_mono_intercon));
2397     else
2398         snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2399                     ARRAY_SIZE(wm8962_spk_stereo_intercon));
2400 
2401 
2402     snd_soc_dapm_disable_pin(dapm, "Beep");
2403 
2404     return 0;
2405 }
2406 
2407 /* -1 for reserved values */
2408 static const int bclk_divs[] = {
2409     1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2410 };
2411 
2412 static const int sysclk_rates[] = {
2413     64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2414 };
2415 
2416 static void wm8962_configure_bclk(struct snd_soc_component *component)
2417 {
2418     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2419     int best, min_diff, diff;
2420     int dspclk, i;
2421     int clocking2 = 0;
2422     int clocking4 = 0;
2423     int aif2 = 0;
2424 
2425     if (!wm8962->sysclk_rate) {
2426         dev_dbg(component->dev, "No SYSCLK configured\n");
2427         return;
2428     }
2429 
2430     if (!wm8962->bclk || !wm8962->lrclk) {
2431         dev_dbg(component->dev, "No audio clocks configured\n");
2432         return;
2433     }
2434 
2435     for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2436         if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2437             clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2438             break;
2439         }
2440     }
2441 
2442     if (i == ARRAY_SIZE(sysclk_rates)) {
2443         dev_err(component->dev, "Unsupported sysclk ratio %d\n",
2444             wm8962->sysclk_rate / wm8962->lrclk);
2445         return;
2446     }
2447 
2448     dev_dbg(component->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2449 
2450     snd_soc_component_update_bits(component, WM8962_CLOCKING_4,
2451                 WM8962_SYSCLK_RATE_MASK, clocking4);
2452 
2453     /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2454      * So we here provisionally enable it and then disable it afterward
2455      * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2456      */
2457     if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2458         snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2459                 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2460 
2461     dspclk = snd_soc_component_read(component, WM8962_CLOCKING1);
2462 
2463     if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON)
2464         snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2465                 WM8962_SYSCLK_ENA_MASK, 0);
2466 
2467     if (dspclk < 0) {
2468         dev_err(component->dev, "Failed to read DSPCLK: %d\n", dspclk);
2469         return;
2470     }
2471 
2472     dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2473     switch (dspclk) {
2474     case 0:
2475         dspclk = wm8962->sysclk_rate;
2476         break;
2477     case 1:
2478         dspclk = wm8962->sysclk_rate / 2;
2479         break;
2480     case 2:
2481         dspclk = wm8962->sysclk_rate / 4;
2482         break;
2483     default:
2484         dev_warn(component->dev, "Unknown DSPCLK divisor read back\n");
2485         dspclk = wm8962->sysclk_rate;
2486     }
2487 
2488     dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2489 
2490     /* Search a proper bclk, not exact match. */
2491     best = 0;
2492     min_diff = INT_MAX;
2493     for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2494         if (bclk_divs[i] < 0)
2495             continue;
2496 
2497         diff = (dspclk / bclk_divs[i]) - wm8962->bclk;
2498         if (diff < 0) /* Table is sorted */
2499             break;
2500         if (diff < min_diff) {
2501             best = i;
2502             min_diff = diff;
2503         }
2504     }
2505     wm8962->bclk = dspclk / bclk_divs[best];
2506     clocking2 |= best;
2507     dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",
2508         bclk_divs[best], wm8962->bclk);
2509 
2510     aif2 |= wm8962->bclk / wm8962->lrclk;
2511     dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
2512         wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2513 
2514     snd_soc_component_update_bits(component, WM8962_CLOCKING2,
2515                 WM8962_BCLK_DIV_MASK, clocking2);
2516     snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2,
2517                 WM8962_AIF_RATE_MASK, aif2);
2518 }
2519 
2520 static int wm8962_set_bias_level(struct snd_soc_component *component,
2521                  enum snd_soc_bias_level level)
2522 {
2523     switch (level) {
2524     case SND_SOC_BIAS_ON:
2525         break;
2526 
2527     case SND_SOC_BIAS_PREPARE:
2528         /* VMID 2*50k */
2529         snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2530                     WM8962_VMID_SEL_MASK, 0x80);
2531 
2532         wm8962_configure_bclk(component);
2533         break;
2534 
2535     case SND_SOC_BIAS_STANDBY:
2536         /* VMID 2*250k */
2537         snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1,
2538                     WM8962_VMID_SEL_MASK, 0x100);
2539 
2540         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
2541             msleep(100);
2542         break;
2543 
2544     case SND_SOC_BIAS_OFF:
2545         break;
2546     }
2547 
2548     return 0;
2549 }
2550 
2551 static const struct {
2552     int rate;
2553     int reg;
2554 } sr_vals[] = {
2555     { 48000, 0 },
2556     { 44100, 0 },
2557     { 32000, 1 },
2558     { 22050, 2 },
2559     { 24000, 2 },
2560     { 16000, 3 },
2561     { 11025, 4 },
2562     { 12000, 4 },
2563     { 8000,  5 },
2564     { 88200, 6 },
2565     { 96000, 6 },
2566 };
2567 
2568 static int wm8962_hw_params(struct snd_pcm_substream *substream,
2569                 struct snd_pcm_hw_params *params,
2570                 struct snd_soc_dai *dai)
2571 {
2572     struct snd_soc_component *component = dai->component;
2573     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2574     int i;
2575     int aif0 = 0;
2576     int adctl3 = 0;
2577 
2578     wm8962->bclk = snd_soc_params_to_bclk(params);
2579     if (params_channels(params) == 1)
2580         wm8962->bclk *= 2;
2581 
2582     wm8962->lrclk = params_rate(params);
2583 
2584     for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2585         if (sr_vals[i].rate == wm8962->lrclk) {
2586             adctl3 |= sr_vals[i].reg;
2587             break;
2588         }
2589     }
2590     if (i == ARRAY_SIZE(sr_vals)) {
2591         dev_err(component->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2592         return -EINVAL;
2593     }
2594 
2595     if (wm8962->lrclk % 8000 == 0)
2596         adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2597 
2598     switch (params_width(params)) {
2599     case 16:
2600         break;
2601     case 20:
2602         aif0 |= 0x4;
2603         break;
2604     case 24:
2605         aif0 |= 0x8;
2606         break;
2607     case 32:
2608         aif0 |= 0xc;
2609         break;
2610     default:
2611         return -EINVAL;
2612     }
2613 
2614     snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2615                 WM8962_WL_MASK, aif0);
2616     snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3,
2617                 WM8962_SAMPLE_RATE_INT_MODE |
2618                 WM8962_SAMPLE_RATE_MASK, adctl3);
2619 
2620     dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2621         wm8962->bclk, wm8962->lrclk);
2622 
2623     if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON)
2624         wm8962_configure_bclk(component);
2625 
2626     return 0;
2627 }
2628 
2629 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2630                  unsigned int freq, int dir)
2631 {
2632     struct snd_soc_component *component = dai->component;
2633     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2634     int src;
2635 
2636     switch (clk_id) {
2637     case WM8962_SYSCLK_MCLK:
2638         wm8962->sysclk = WM8962_SYSCLK_MCLK;
2639         src = 0;
2640         break;
2641     case WM8962_SYSCLK_FLL:
2642         wm8962->sysclk = WM8962_SYSCLK_FLL;
2643         src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2644         break;
2645     default:
2646         return -EINVAL;
2647     }
2648 
2649     snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2650                 src);
2651 
2652     wm8962->sysclk_rate = freq;
2653 
2654     return 0;
2655 }
2656 
2657 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2658 {
2659     struct snd_soc_component *component = dai->component;
2660     int aif0 = 0;
2661 
2662     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2663     case SND_SOC_DAIFMT_DSP_B:
2664         aif0 |= WM8962_LRCLK_INV | 3;
2665         fallthrough;
2666     case SND_SOC_DAIFMT_DSP_A:
2667         aif0 |= 3;
2668 
2669         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2670         case SND_SOC_DAIFMT_NB_NF:
2671         case SND_SOC_DAIFMT_IB_NF:
2672             break;
2673         default:
2674             return -EINVAL;
2675         }
2676         break;
2677 
2678     case SND_SOC_DAIFMT_RIGHT_J:
2679         break;
2680     case SND_SOC_DAIFMT_LEFT_J:
2681         aif0 |= 1;
2682         break;
2683     case SND_SOC_DAIFMT_I2S:
2684         aif0 |= 2;
2685         break;
2686     default:
2687         return -EINVAL;
2688     }
2689 
2690     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2691     case SND_SOC_DAIFMT_NB_NF:
2692         break;
2693     case SND_SOC_DAIFMT_IB_NF:
2694         aif0 |= WM8962_BCLK_INV;
2695         break;
2696     case SND_SOC_DAIFMT_NB_IF:
2697         aif0 |= WM8962_LRCLK_INV;
2698         break;
2699     case SND_SOC_DAIFMT_IB_IF:
2700         aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2701         break;
2702     default:
2703         return -EINVAL;
2704     }
2705 
2706     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2707     case SND_SOC_DAIFMT_CBM_CFM:
2708         aif0 |= WM8962_MSTR;
2709         break;
2710     case SND_SOC_DAIFMT_CBS_CFS:
2711         break;
2712     default:
2713         return -EINVAL;
2714     }
2715 
2716     snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0,
2717                 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2718                 WM8962_LRCLK_INV, aif0);
2719 
2720     return 0;
2721 }
2722 
2723 struct _fll_div {
2724     u16 fll_fratio;
2725     u16 fll_outdiv;
2726     u16 fll_refclk_div;
2727     u16 n;
2728     u16 theta;
2729     u16 lambda;
2730 };
2731 
2732 /* The size in bits of the FLL divide multiplied by 10
2733  * to allow rounding later */
2734 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2735 
2736 static struct {
2737     unsigned int min;
2738     unsigned int max;
2739     u16 fll_fratio;
2740     int ratio;
2741 } fll_fratios[] = {
2742     {       0,    64000, 4, 16 },
2743     {   64000,   128000, 3,  8 },
2744     {  128000,   256000, 2,  4 },
2745     {  256000,  1000000, 1,  2 },
2746     { 1000000, 13500000, 0,  1 },
2747 };
2748 
2749 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2750                unsigned int Fout)
2751 {
2752     unsigned int target;
2753     unsigned int div;
2754     unsigned int fratio, gcd_fll;
2755     int i;
2756 
2757     /* Fref must be <=13.5MHz */
2758     div = 1;
2759     fll_div->fll_refclk_div = 0;
2760     while ((Fref / div) > 13500000) {
2761         div *= 2;
2762         fll_div->fll_refclk_div++;
2763 
2764         if (div > 4) {
2765             pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2766                    Fref);
2767             return -EINVAL;
2768         }
2769     }
2770 
2771     pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2772 
2773     /* Apply the division for our remaining calculations */
2774     Fref /= div;
2775 
2776     /* Fvco should be 90-100MHz; don't check the upper bound */
2777     div = 2;
2778     while (Fout * div < 90000000) {
2779         div++;
2780         if (div > 64) {
2781             pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2782                    Fout);
2783             return -EINVAL;
2784         }
2785     }
2786     target = Fout * div;
2787     fll_div->fll_outdiv = div - 1;
2788 
2789     pr_debug("FLL Fvco=%dHz\n", target);
2790 
2791     /* Find an appropriate FLL_FRATIO and factor it out of the target */
2792     for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2793         if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2794             fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2795             fratio = fll_fratios[i].ratio;
2796             break;
2797         }
2798     }
2799     if (i == ARRAY_SIZE(fll_fratios)) {
2800         pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2801         return -EINVAL;
2802     }
2803 
2804     fll_div->n = target / (fratio * Fref);
2805 
2806     if (target % Fref == 0) {
2807         fll_div->theta = 0;
2808         fll_div->lambda = 1;
2809     } else {
2810         gcd_fll = gcd(target, fratio * Fref);
2811 
2812         fll_div->theta = (target - (fll_div->n * fratio * Fref))
2813             / gcd_fll;
2814         fll_div->lambda = (fratio * Fref) / gcd_fll;
2815     }
2816 
2817     pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2818          fll_div->n, fll_div->theta, fll_div->lambda);
2819     pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2820          fll_div->fll_fratio, fll_div->fll_outdiv,
2821          fll_div->fll_refclk_div);
2822 
2823     return 0;
2824 }
2825 
2826 static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source,
2827               unsigned int Fref, unsigned int Fout)
2828 {
2829     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
2830     struct _fll_div fll_div;
2831     unsigned long timeout;
2832     int ret;
2833     int fll1 = 0;
2834 
2835     /* Any change? */
2836     if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2837         Fout == wm8962->fll_fout)
2838         return 0;
2839 
2840     if (Fout == 0) {
2841         dev_dbg(component->dev, "FLL disabled\n");
2842 
2843         wm8962->fll_fref = 0;
2844         wm8962->fll_fout = 0;
2845 
2846         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2847                     WM8962_FLL_ENA, 0);
2848 
2849         pm_runtime_put(component->dev);
2850 
2851         return 0;
2852     }
2853 
2854     ret = fll_factors(&fll_div, Fref, Fout);
2855     if (ret != 0)
2856         return ret;
2857 
2858     /* Parameters good, disable so we can reprogram */
2859     snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2860 
2861     switch (fll_id) {
2862     case WM8962_FLL_MCLK:
2863     case WM8962_FLL_BCLK:
2864     case WM8962_FLL_OSC:
2865         fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2866         break;
2867     case WM8962_FLL_INT:
2868         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2869                     WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2870         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5,
2871                     WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2872         break;
2873     default:
2874         dev_err(component->dev, "Unknown FLL source %d\n", ret);
2875         return -EINVAL;
2876     }
2877 
2878     if (fll_div.theta)
2879         fll1 |= WM8962_FLL_FRAC;
2880 
2881     /* Stop the FLL while we reconfigure */
2882     snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2883 
2884     snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2,
2885                 WM8962_FLL_OUTDIV_MASK |
2886                 WM8962_FLL_REFCLK_DIV_MASK,
2887                 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2888                 (fll_div.fll_refclk_div));
2889 
2890     snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3,
2891                 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2892 
2893     snd_soc_component_write(component, WM8962_FLL_CONTROL_6, fll_div.theta);
2894     snd_soc_component_write(component, WM8962_FLL_CONTROL_7, fll_div.lambda);
2895     snd_soc_component_write(component, WM8962_FLL_CONTROL_8, fll_div.n);
2896 
2897     reinit_completion(&wm8962->fll_lock);
2898 
2899     ret = pm_runtime_resume_and_get(component->dev);
2900     if (ret < 0) {
2901         dev_err(component->dev, "Failed to resume device: %d\n", ret);
2902         return ret;
2903     }
2904 
2905     snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2906                 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2907                 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2908 
2909     dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2910 
2911     /* This should be a massive overestimate but go even
2912      * higher if we'll error out
2913      */
2914     if (wm8962->irq)
2915         timeout = msecs_to_jiffies(5);
2916     else
2917         timeout = msecs_to_jiffies(1);
2918 
2919     timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2920                           timeout);
2921 
2922     if (timeout == 0 && wm8962->irq) {
2923         dev_err(component->dev, "FLL lock timed out");
2924         snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1,
2925                     WM8962_FLL_ENA, 0);
2926         pm_runtime_put(component->dev);
2927         return -ETIMEDOUT;
2928     }
2929 
2930     wm8962->fll_fref = Fref;
2931     wm8962->fll_fout = Fout;
2932     wm8962->fll_src = source;
2933 
2934     return 0;
2935 }
2936 
2937 static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction)
2938 {
2939     struct snd_soc_component *component = dai->component;
2940     int val, ret;
2941 
2942     if (mute)
2943         val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
2944     else
2945         val = 0;
2946 
2947     /**
2948      * The DAC mute bit is mirrored in two registers, update both to keep
2949      * the register cache consistent.
2950      */
2951     ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1,
2952                   WM8962_DAC_MUTE_ALT, val);
2953     if (ret < 0)
2954         return ret;
2955 
2956     return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1,
2957                    WM8962_DAC_MUTE, val);
2958 }
2959 
2960 #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
2961         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
2962 
2963 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2964             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2965 
2966 static const struct snd_soc_dai_ops wm8962_dai_ops = {
2967     .hw_params = wm8962_hw_params,
2968     .set_sysclk = wm8962_set_dai_sysclk,
2969     .set_fmt = wm8962_set_dai_fmt,
2970     .mute_stream = wm8962_mute,
2971     .no_capture_mute = 1,
2972 };
2973 
2974 static struct snd_soc_dai_driver wm8962_dai = {
2975     .name = "wm8962",
2976     .playback = {
2977         .stream_name = "Playback",
2978         .channels_min = 1,
2979         .channels_max = 2,
2980         .rates = WM8962_RATES,
2981         .formats = WM8962_FORMATS,
2982     },
2983     .capture = {
2984         .stream_name = "Capture",
2985         .channels_min = 1,
2986         .channels_max = 2,
2987         .rates = WM8962_RATES,
2988         .formats = WM8962_FORMATS,
2989     },
2990     .ops = &wm8962_dai_ops,
2991     .symmetric_rate = 1,
2992 };
2993 
2994 static void wm8962_mic_work(struct work_struct *work)
2995 {
2996     struct wm8962_priv *wm8962 = container_of(work,
2997                           struct wm8962_priv,
2998                           mic_work.work);
2999     struct snd_soc_component *component = wm8962->component;
3000     int status = 0;
3001     int irq_pol = 0;
3002     int reg;
3003 
3004     reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4);
3005 
3006     if (reg & WM8962_MICDET_STS) {
3007         status |= SND_JACK_MICROPHONE;
3008         irq_pol |= WM8962_MICD_IRQ_POL;
3009     }
3010 
3011     if (reg & WM8962_MICSHORT_STS) {
3012         status |= SND_JACK_BTN_0;
3013         irq_pol |= WM8962_MICSCD_IRQ_POL;
3014     }
3015 
3016     snd_soc_jack_report(wm8962->jack, status,
3017                 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3018 
3019     snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL,
3020                 WM8962_MICSCD_IRQ_POL |
3021                 WM8962_MICD_IRQ_POL, irq_pol);
3022 }
3023 
3024 static irqreturn_t wm8962_irq(int irq, void *data)
3025 {
3026     struct device *dev = data;
3027     struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3028     unsigned int mask;
3029     unsigned int active;
3030     int reg, ret;
3031 
3032     ret = pm_runtime_resume_and_get(dev);
3033     if (ret < 0) {
3034         dev_err(dev, "Failed to resume: %d\n", ret);
3035         return IRQ_NONE;
3036     }
3037 
3038     ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3039               &mask);
3040     if (ret != 0) {
3041         pm_runtime_put(dev);
3042         dev_err(dev, "Failed to read interrupt mask: %d\n",
3043             ret);
3044         return IRQ_NONE;
3045     }
3046 
3047     ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3048     if (ret != 0) {
3049         pm_runtime_put(dev);
3050         dev_err(dev, "Failed to read interrupt: %d\n", ret);
3051         return IRQ_NONE;
3052     }
3053 
3054     active &= ~mask;
3055 
3056     if (!active) {
3057         pm_runtime_put(dev);
3058         return IRQ_NONE;
3059     }
3060 
3061     /* Acknowledge the interrupts */
3062     ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3063     if (ret != 0)
3064         dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3065 
3066     if (active & WM8962_FLL_LOCK_EINT) {
3067         dev_dbg(dev, "FLL locked\n");
3068         complete(&wm8962->fll_lock);
3069     }
3070 
3071     if (active & WM8962_FIFOS_ERR_EINT)
3072         dev_err(dev, "FIFO error\n");
3073 
3074     if (active & WM8962_TEMP_SHUT_EINT) {
3075         dev_crit(dev, "Thermal shutdown\n");
3076 
3077         ret = regmap_read(wm8962->regmap,
3078                   WM8962_THERMAL_SHUTDOWN_STATUS,  &reg);
3079         if (ret != 0) {
3080             dev_warn(dev, "Failed to read thermal status: %d\n",
3081                  ret);
3082             reg = 0;
3083         }
3084 
3085         if (reg & WM8962_TEMP_ERR_HP)
3086             dev_crit(dev, "Headphone thermal error\n");
3087         if (reg & WM8962_TEMP_WARN_HP)
3088             dev_crit(dev, "Headphone thermal warning\n");
3089         if (reg & WM8962_TEMP_ERR_SPK)
3090             dev_crit(dev, "Speaker thermal error\n");
3091         if (reg & WM8962_TEMP_WARN_SPK)
3092             dev_crit(dev, "Speaker thermal warning\n");
3093     }
3094 
3095     if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3096         dev_dbg(dev, "Microphone event detected\n");
3097 
3098 #ifndef CONFIG_SND_SOC_WM8962_MODULE
3099         trace_snd_soc_jack_irq(dev_name(dev));
3100 #endif
3101 
3102         pm_wakeup_event(dev, 300);
3103 
3104         queue_delayed_work(system_power_efficient_wq,
3105                    &wm8962->mic_work,
3106                    msecs_to_jiffies(250));
3107     }
3108 
3109     pm_runtime_put(dev);
3110 
3111     return IRQ_HANDLED;
3112 }
3113 
3114 /**
3115  * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3116  *
3117  * @component:  WM8962 component
3118  * @jack:   jack to report detection events on
3119  *
3120  * Enable microphone detection via IRQ on the WM8962.  If GPIOs are
3121  * being used to bring out signals to the processor then only platform
3122  * data configuration is needed for WM8962 and processor GPIOs should
3123  * be configured using snd_soc_jack_add_gpios() instead.
3124  *
3125  * If no jack is supplied detection will be disabled.
3126  */
3127 int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
3128 {
3129     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3130     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3131     int irq_mask, enable;
3132 
3133     wm8962->jack = jack;
3134     if (jack) {
3135         irq_mask = 0;
3136         enable = WM8962_MICDET_ENA;
3137     } else {
3138         irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3139         enable = 0;
3140     }
3141 
3142     snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK,
3143                 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3144     snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4,
3145                 WM8962_MICDET_ENA, enable);
3146 
3147     /* Send an initial empty report */
3148     snd_soc_jack_report(wm8962->jack, 0,
3149                 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3150 
3151     snd_soc_dapm_mutex_lock(dapm);
3152 
3153     if (jack) {
3154         snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3155         snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
3156     } else {
3157         snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3158         snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
3159     }
3160 
3161     snd_soc_dapm_mutex_unlock(dapm);
3162 
3163     return 0;
3164 }
3165 EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3166 
3167 static int beep_rates[] = {
3168     500, 1000, 2000, 4000,
3169 };
3170 
3171 static void wm8962_beep_work(struct work_struct *work)
3172 {
3173     struct wm8962_priv *wm8962 =
3174         container_of(work, struct wm8962_priv, beep_work);
3175     struct snd_soc_component *component = wm8962->component;
3176     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3177     int i;
3178     int reg = 0;
3179     int best = 0;
3180 
3181     if (wm8962->beep_rate) {
3182         for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3183             if (abs(wm8962->beep_rate - beep_rates[i]) <
3184                 abs(wm8962->beep_rate - beep_rates[best]))
3185                 best = i;
3186         }
3187 
3188         dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
3189             beep_rates[best], wm8962->beep_rate);
3190 
3191         reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3192 
3193         snd_soc_dapm_enable_pin(dapm, "Beep");
3194     } else {
3195         dev_dbg(component->dev, "Disabling beep\n");
3196         snd_soc_dapm_disable_pin(dapm, "Beep");
3197     }
3198 
3199     snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1,
3200                 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3201 
3202     snd_soc_dapm_sync(dapm);
3203 }
3204 
3205 /* For usability define a way of injecting beep events for the device -
3206  * many systems will not have a keyboard.
3207  */
3208 static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3209                  unsigned int code, int hz)
3210 {
3211     struct snd_soc_component *component = input_get_drvdata(dev);
3212     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3213 
3214     dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
3215 
3216     switch (code) {
3217     case SND_BELL:
3218         if (hz)
3219             hz = 1000;
3220         fallthrough;
3221     case SND_TONE:
3222         break;
3223     default:
3224         return -1;
3225     }
3226 
3227     /* Kick the beep from a workqueue */
3228     wm8962->beep_rate = hz;
3229     schedule_work(&wm8962->beep_work);
3230     return 0;
3231 }
3232 
3233 static ssize_t beep_store(struct device *dev, struct device_attribute *attr,
3234               const char *buf, size_t count)
3235 {
3236     struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3237     long int time;
3238     int ret;
3239 
3240     ret = kstrtol(buf, 10, &time);
3241     if (ret != 0)
3242         return ret;
3243 
3244     input_event(wm8962->beep, EV_SND, SND_TONE, time);
3245 
3246     return count;
3247 }
3248 
3249 static DEVICE_ATTR_WO(beep);
3250 
3251 static void wm8962_init_beep(struct snd_soc_component *component)
3252 {
3253     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3254     int ret;
3255 
3256     wm8962->beep = devm_input_allocate_device(component->dev);
3257     if (!wm8962->beep) {
3258         dev_err(component->dev, "Failed to allocate beep device\n");
3259         return;
3260     }
3261 
3262     INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3263     wm8962->beep_rate = 0;
3264 
3265     wm8962->beep->name = "WM8962 Beep Generator";
3266     wm8962->beep->phys = dev_name(component->dev);
3267     wm8962->beep->id.bustype = BUS_I2C;
3268 
3269     wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3270     wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3271     wm8962->beep->event = wm8962_beep_event;
3272     wm8962->beep->dev.parent = component->dev;
3273     input_set_drvdata(wm8962->beep, component);
3274 
3275     ret = input_register_device(wm8962->beep);
3276     if (ret != 0) {
3277         wm8962->beep = NULL;
3278         dev_err(component->dev, "Failed to register beep device\n");
3279     }
3280 
3281     ret = device_create_file(component->dev, &dev_attr_beep);
3282     if (ret != 0) {
3283         dev_err(component->dev, "Failed to create keyclick file: %d\n",
3284             ret);
3285     }
3286 }
3287 
3288 static void wm8962_free_beep(struct snd_soc_component *component)
3289 {
3290     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3291 
3292     device_remove_file(component->dev, &dev_attr_beep);
3293     cancel_work_sync(&wm8962->beep_work);
3294     wm8962->beep = NULL;
3295 
3296     snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3297 }
3298 
3299 static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3300 {
3301     int mask = 0;
3302     int val = 0;
3303 
3304     /* Some of the GPIOs are behind MFP configuration and need to
3305      * be put into GPIO mode. */
3306     switch (gpio) {
3307     case 2:
3308         mask = WM8962_CLKOUT2_SEL_MASK;
3309         val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3310         break;
3311     case 3:
3312         mask = WM8962_CLKOUT3_SEL_MASK;
3313         val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3314         break;
3315     default:
3316         break;
3317     }
3318 
3319     if (mask)
3320         regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3321                    mask, val);
3322 }
3323 
3324 #ifdef CONFIG_GPIOLIB
3325 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3326 {
3327     struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3328 
3329     /* The WM8962 GPIOs aren't linearly numbered.  For simplicity
3330      * we export linear numbers and error out if the unsupported
3331      * ones are requsted.
3332      */
3333     switch (offset + 1) {
3334     case 2:
3335     case 3:
3336     case 5:
3337     case 6:
3338         break;
3339     default:
3340         return -EINVAL;
3341     }
3342 
3343     wm8962_set_gpio_mode(wm8962, offset + 1);
3344 
3345     return 0;
3346 }
3347 
3348 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3349 {
3350     struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3351     struct snd_soc_component *component = wm8962->component;
3352 
3353     snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3354                 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3355 }
3356 
3357 static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3358                      unsigned offset, int value)
3359 {
3360     struct wm8962_priv *wm8962 = gpiochip_get_data(chip);
3361     struct snd_soc_component *component = wm8962->component;
3362     int ret, val;
3363 
3364     /* Force function 1 (logic output) */
3365     val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3366 
3367     ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset,
3368                   WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3369     if (ret < 0)
3370         return ret;
3371 
3372     return 0;
3373 }
3374 
3375 static const struct gpio_chip wm8962_template_chip = {
3376     .label          = "wm8962",
3377     .owner          = THIS_MODULE,
3378     .request        = wm8962_gpio_request,
3379     .direction_output   = wm8962_gpio_direction_out,
3380     .set            = wm8962_gpio_set,
3381     .can_sleep      = 1,
3382 };
3383 
3384 static void wm8962_init_gpio(struct snd_soc_component *component)
3385 {
3386     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3387     struct wm8962_pdata *pdata = &wm8962->pdata;
3388     int ret;
3389 
3390     wm8962->gpio_chip = wm8962_template_chip;
3391     wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3392     wm8962->gpio_chip.parent = component->dev;
3393 
3394     if (pdata->gpio_base)
3395         wm8962->gpio_chip.base = pdata->gpio_base;
3396     else
3397         wm8962->gpio_chip.base = -1;
3398 
3399     ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962);
3400     if (ret != 0)
3401         dev_err(component->dev, "Failed to add GPIOs: %d\n", ret);
3402 }
3403 
3404 static void wm8962_free_gpio(struct snd_soc_component *component)
3405 {
3406     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3407 
3408     gpiochip_remove(&wm8962->gpio_chip);
3409 }
3410 #else
3411 static void wm8962_init_gpio(struct snd_soc_component *component)
3412 {
3413 }
3414 
3415 static void wm8962_free_gpio(struct snd_soc_component *component)
3416 {
3417 }
3418 #endif
3419 
3420 static int wm8962_probe(struct snd_soc_component *component)
3421 {
3422     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3423     int ret;
3424     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3425     int i;
3426     bool dmicclk, dmicdat;
3427 
3428     wm8962->component = component;
3429 
3430     wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3431     wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3432     wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3433     wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3434     wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3435     wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3436     wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3437     wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3438 
3439     /* This should really be moved into the regulator core */
3440     for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3441         ret = devm_regulator_register_notifier(
3442                         wm8962->supplies[i].consumer,
3443                         &wm8962->disable_nb[i]);
3444         if (ret != 0) {
3445             dev_err(component->dev,
3446                 "Failed to register regulator notifier: %d\n",
3447                 ret);
3448         }
3449     }
3450 
3451     wm8962_add_widgets(component);
3452 
3453     /* Save boards having to disable DMIC when not in use */
3454     dmicclk = false;
3455     dmicdat = false;
3456     for (i = 1; i < WM8962_MAX_GPIO; i++) {
3457         /*
3458          * Register 515 (WM8962_GPIO_BASE + 3) does not exist,
3459          * so skip its access
3460          */
3461         if (i == 3)
3462             continue;
3463         switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i)
3464             & WM8962_GP2_FN_MASK) {
3465         case WM8962_GPIO_FN_DMICCLK:
3466             dmicclk = true;
3467             break;
3468         case WM8962_GPIO_FN_DMICDAT:
3469             dmicdat = true;
3470             break;
3471         default:
3472             break;
3473         }
3474     }
3475     if (!dmicclk || !dmicdat) {
3476         dev_dbg(component->dev, "DMIC not in use, disabling\n");
3477         snd_soc_dapm_nc_pin(dapm, "DMICDAT");
3478     }
3479     if (dmicclk != dmicdat)
3480         dev_warn(component->dev, "DMIC GPIOs partially configured\n");
3481 
3482     wm8962_init_beep(component);
3483     wm8962_init_gpio(component);
3484 
3485     return 0;
3486 }
3487 
3488 static void wm8962_remove(struct snd_soc_component *component)
3489 {
3490     struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);
3491 
3492     cancel_delayed_work_sync(&wm8962->mic_work);
3493 
3494     wm8962_free_gpio(component);
3495     wm8962_free_beep(component);
3496 }
3497 
3498 static const struct snd_soc_component_driver soc_component_dev_wm8962 = {
3499     .probe          = wm8962_probe,
3500     .remove         = wm8962_remove,
3501     .set_bias_level     = wm8962_set_bias_level,
3502     .set_pll        = wm8962_set_fll,
3503     .use_pmdown_time    = 1,
3504     .endianness     = 1,
3505 };
3506 
3507 /* Improve power consumption for IN4 DC measurement mode */
3508 static const struct reg_sequence wm8962_dc_measure[] = {
3509     { 0xfd, 0x1 },
3510     { 0xcc, 0x40 },
3511     { 0xfd, 0 },
3512 };
3513 
3514 static const struct regmap_config wm8962_regmap = {
3515     .reg_bits = 16,
3516     .val_bits = 16,
3517 
3518     .max_register = WM8962_MAX_REGISTER,
3519     .reg_defaults = wm8962_reg,
3520     .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3521     .volatile_reg = wm8962_volatile_register,
3522     .readable_reg = wm8962_readable_register,
3523     .cache_type = REGCACHE_RBTREE,
3524 };
3525 
3526 static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3527                     struct wm8962_pdata *pdata)
3528 {
3529     const struct device_node *np = i2c->dev.of_node;
3530     u32 val32;
3531     int i;
3532 
3533     if (of_property_read_bool(np, "spk-mono"))
3534         pdata->spk_mono = true;
3535 
3536     if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3537         pdata->mic_cfg = val32;
3538 
3539     if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3540                        ARRAY_SIZE(pdata->gpio_init)) >= 0)
3541         for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3542             /*
3543              * The range of GPIO register value is [0x0, 0xffff]
3544              * While the default value of each register is 0x0
3545              * Any other value will be regarded as default value
3546              */
3547             if (pdata->gpio_init[i] > 0xffff)
3548                 pdata->gpio_init[i] = 0x0;
3549         }
3550 
3551     pdata->mclk = devm_clk_get_optional(&i2c->dev, NULL);
3552     return PTR_ERR_OR_ZERO(pdata->mclk);
3553 }
3554 
3555 static int wm8962_i2c_probe(struct i2c_client *i2c)
3556 {
3557     struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3558     struct wm8962_priv *wm8962;
3559     unsigned int reg;
3560     int ret, i, irq_pol, trigger;
3561 
3562     wm8962 = devm_kzalloc(&i2c->dev, sizeof(*wm8962), GFP_KERNEL);
3563     if (wm8962 == NULL)
3564         return -ENOMEM;
3565 
3566     mutex_init(&wm8962->dsp2_ena_lock);
3567 
3568     i2c_set_clientdata(i2c, wm8962);
3569 
3570     INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3571     init_completion(&wm8962->fll_lock);
3572     wm8962->irq = i2c->irq;
3573 
3574     /* If platform data was supplied, update the default data in priv */
3575     if (pdata) {
3576         memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
3577     } else if (i2c->dev.of_node) {
3578         ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3579         if (ret != 0)
3580             return ret;
3581     }
3582 
3583     for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3584         wm8962->supplies[i].supply = wm8962_supply_names[i];
3585 
3586     ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3587                  wm8962->supplies);
3588     if (ret != 0) {
3589         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3590         goto err;
3591     }
3592 
3593     ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3594                     wm8962->supplies);
3595     if (ret != 0) {
3596         dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3597         return ret;
3598     }
3599 
3600     wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3601     if (IS_ERR(wm8962->regmap)) {
3602         ret = PTR_ERR(wm8962->regmap);
3603         dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3604         goto err_enable;
3605     }
3606 
3607     /*
3608      * We haven't marked the chip revision as volatile due to
3609      * sharing a register with the right input volume; explicitly
3610      * bypass the cache to read it.
3611      */
3612     regcache_cache_bypass(wm8962->regmap, true);
3613 
3614     ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3615     if (ret < 0) {
3616         dev_err(&i2c->dev, "Failed to read ID register\n");
3617         goto err_enable;
3618     }
3619     if (reg != 0x6243) {
3620         dev_err(&i2c->dev,
3621             "Device is not a WM8962, ID %x != 0x6243\n", reg);
3622         ret = -EINVAL;
3623         goto err_enable;
3624     }
3625 
3626     ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3627     if (ret < 0) {
3628         dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3629             ret);
3630         goto err_enable;
3631     }
3632 
3633     dev_info(&i2c->dev, "customer id %x revision %c\n",
3634          (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3635          ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3636          + 'A');
3637 
3638     regcache_cache_bypass(wm8962->regmap, false);
3639 
3640     ret = wm8962_reset(wm8962);
3641     if (ret < 0) {
3642         dev_err(&i2c->dev, "Failed to issue reset\n");
3643         goto err_enable;
3644     }
3645 
3646     /* SYSCLK defaults to on; make sure it is off so we can safely
3647      * write to registers if the device is declocked.
3648      */
3649     regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3650                WM8962_SYSCLK_ENA, 0);
3651 
3652     /* Ensure we have soft control over all registers */
3653     regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3654                WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3655 
3656     /* Ensure that the oscillator and PLLs are disabled */
3657     regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3658                WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3659                0);
3660 
3661     /* Apply static configuration for GPIOs */
3662     for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3663         if (wm8962->pdata.gpio_init[i]) {
3664             wm8962_set_gpio_mode(wm8962, i + 1);
3665             regmap_write(wm8962->regmap, 0x200 + i,
3666                      wm8962->pdata.gpio_init[i] & 0xffff);
3667         }
3668 
3669 
3670     /* Put the speakers into mono mode? */
3671     if (wm8962->pdata.spk_mono)
3672         regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3673                    WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3674 
3675     /* Micbias setup, detection enable and detection
3676      * threasholds. */
3677     if (wm8962->pdata.mic_cfg)
3678         regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3679                    WM8962_MICDET_ENA |
3680                    WM8962_MICDET_THR_MASK |
3681                    WM8962_MICSHORT_THR_MASK |
3682                    WM8962_MICBIAS_LVL,
3683                    wm8962->pdata.mic_cfg);
3684 
3685     /* Latch volume update bits */
3686     regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3687                WM8962_IN_VU, WM8962_IN_VU);
3688     regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3689                WM8962_IN_VU, WM8962_IN_VU);
3690     regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3691                WM8962_ADC_VU, WM8962_ADC_VU);
3692     regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3693                WM8962_ADC_VU, WM8962_ADC_VU);
3694     regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3695                WM8962_DAC_VU, WM8962_DAC_VU);
3696     regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3697                WM8962_DAC_VU, WM8962_DAC_VU);
3698     regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3699                WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3700     regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3701                WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3702     regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3703                WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3704     regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3705                WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3706 
3707     /* Stereo control for EQ */
3708     regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3709                WM8962_EQ_SHARED_COEFF, 0);
3710 
3711     /* Don't debouce interrupts so we don't need SYSCLK */
3712     regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3713                WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3714                WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3715                0);
3716 
3717     if (wm8962->pdata.in4_dc_measure) {
3718         ret = regmap_register_patch(wm8962->regmap,
3719                         wm8962_dc_measure,
3720                         ARRAY_SIZE(wm8962_dc_measure));
3721         if (ret != 0)
3722             dev_err(&i2c->dev,
3723                 "Failed to configure for DC measurement: %d\n",
3724                 ret);
3725     }
3726 
3727     if (wm8962->irq) {
3728         if (wm8962->pdata.irq_active_low) {
3729             trigger = IRQF_TRIGGER_LOW;
3730             irq_pol = WM8962_IRQ_POL;
3731         } else {
3732             trigger = IRQF_TRIGGER_HIGH;
3733             irq_pol = 0;
3734         }
3735 
3736         regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3737                    WM8962_IRQ_POL, irq_pol);
3738 
3739         ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3740                         wm8962_irq,
3741                         trigger | IRQF_ONESHOT,
3742                         "wm8962", &i2c->dev);
3743         if (ret != 0) {
3744             dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3745                 wm8962->irq, ret);
3746             wm8962->irq = 0;
3747             /* Non-fatal */
3748         } else {
3749             /* Enable some IRQs by default */
3750             regmap_update_bits(wm8962->regmap,
3751                        WM8962_INTERRUPT_STATUS_2_MASK,
3752                        WM8962_FLL_LOCK_EINT |
3753                        WM8962_TEMP_SHUT_EINT |
3754                        WM8962_FIFOS_ERR_EINT, 0);
3755         }
3756     }
3757 
3758     pm_runtime_enable(&i2c->dev);
3759     pm_request_idle(&i2c->dev);
3760 
3761     ret = devm_snd_soc_register_component(&i2c->dev,
3762                      &soc_component_dev_wm8962, &wm8962_dai, 1);
3763     if (ret < 0)
3764         goto err_pm_runtime;
3765 
3766     regcache_cache_only(wm8962->regmap, true);
3767 
3768     /* The drivers should power up as needed */
3769     regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3770 
3771     return 0;
3772 
3773 err_pm_runtime:
3774     pm_runtime_disable(&i2c->dev);
3775 err_enable:
3776     regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3777 err:
3778     return ret;
3779 }
3780 
3781 static int wm8962_i2c_remove(struct i2c_client *client)
3782 {
3783     pm_runtime_disable(&client->dev);
3784     return 0;
3785 }
3786 
3787 #ifdef CONFIG_PM
3788 static int wm8962_runtime_resume(struct device *dev)
3789 {
3790     struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3791     int ret;
3792 
3793     ret = clk_prepare_enable(wm8962->pdata.mclk);
3794     if (ret) {
3795         dev_err(dev, "Failed to enable MCLK: %d\n", ret);
3796         return ret;
3797     }
3798 
3799     ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3800                     wm8962->supplies);
3801     if (ret != 0) {
3802         dev_err(dev, "Failed to enable supplies: %d\n", ret);
3803         goto disable_clock;
3804     }
3805 
3806     regcache_cache_only(wm8962->regmap, false);
3807 
3808     wm8962_reset(wm8962);
3809 
3810     regcache_mark_dirty(wm8962->regmap);
3811 
3812     /* SYSCLK defaults to on; make sure it is off so we can safely
3813      * write to registers if the device is declocked.
3814      */
3815     regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2,
3816               WM8962_SYSCLK_ENA, 0);
3817 
3818     /* Ensure we have soft control over all registers */
3819     regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3820                WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3821 
3822     /* Ensure that the oscillator and PLLs are disabled */
3823     regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3824                WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3825                0);
3826 
3827     regcache_sync(wm8962->regmap);
3828 
3829     regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3830                WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3831                WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3832 
3833     /* Bias enable at 2*5k (fast start-up) */
3834     regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3835                WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3836                WM8962_BIAS_ENA | 0x180);
3837 
3838     msleep(5);
3839 
3840     return 0;
3841 
3842 disable_clock:
3843     clk_disable_unprepare(wm8962->pdata.mclk);
3844     return ret;
3845 }
3846 
3847 static int wm8962_runtime_suspend(struct device *dev)
3848 {
3849     struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3850 
3851     regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3852                WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3853 
3854     regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3855                WM8962_STARTUP_BIAS_ENA |
3856                WM8962_VMID_BUF_ENA, 0);
3857 
3858     regcache_cache_only(wm8962->regmap, true);
3859 
3860     regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3861                    wm8962->supplies);
3862 
3863     clk_disable_unprepare(wm8962->pdata.mclk);
3864 
3865     return 0;
3866 }
3867 #endif
3868 
3869 static const struct dev_pm_ops wm8962_pm = {
3870     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3871     SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3872 };
3873 
3874 static const struct i2c_device_id wm8962_i2c_id[] = {
3875     { "wm8962", 0 },
3876     { }
3877 };
3878 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3879 
3880 static const struct of_device_id wm8962_of_match[] = {
3881     { .compatible = "wlf,wm8962", },
3882     { }
3883 };
3884 MODULE_DEVICE_TABLE(of, wm8962_of_match);
3885 
3886 static struct i2c_driver wm8962_i2c_driver = {
3887     .driver = {
3888         .name = "wm8962",
3889         .of_match_table = wm8962_of_match,
3890         .pm = &wm8962_pm,
3891     },
3892     .probe_new = wm8962_i2c_probe,
3893     .remove =   wm8962_i2c_remove,
3894     .id_table = wm8962_i2c_id,
3895 };
3896 
3897 module_i2c_driver(wm8962_i2c_driver);
3898 
3899 MODULE_DESCRIPTION("ASoC WM8962 driver");
3900 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3901 MODULE_LICENSE("GPL");
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