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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8961.c  --  WM8961 ALSA SoC Audio driver
0004  *
0005  * Copyright 2009-10 Wolfson Microelectronics, plc
0006  *
0007  * Author: Mark Brown
0008  *
0009  * Currently unimplemented features:
0010  *  - ALC
0011  */
0012 
0013 #include <linux/module.h>
0014 #include <linux/moduleparam.h>
0015 #include <linux/init.h>
0016 #include <linux/delay.h>
0017 #include <linux/pm.h>
0018 #include <linux/i2c.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021 #include <sound/core.h>
0022 #include <sound/pcm.h>
0023 #include <sound/pcm_params.h>
0024 #include <sound/soc.h>
0025 #include <sound/initval.h>
0026 #include <sound/tlv.h>
0027 
0028 #include "wm8961.h"
0029 
0030 #define WM8961_MAX_REGISTER                     0xFC
0031 
0032 static const struct reg_default wm8961_reg_defaults[] = {
0033     {  0, 0x009F },     /* R0   - Left Input volume */
0034     {  1, 0x009F },     /* R1   - Right Input volume */
0035     {  2, 0x0000 },     /* R2   - LOUT1 volume */
0036     {  3, 0x0000 },     /* R3   - ROUT1 volume */
0037     {  4, 0x0020 },     /* R4   - Clocking1 */
0038     {  5, 0x0008 },     /* R5   - ADC & DAC Control 1 */
0039     {  6, 0x0000 },     /* R6   - ADC & DAC Control 2 */
0040     {  7, 0x000A },     /* R7   - Audio Interface 0 */
0041     {  8, 0x01F4 },     /* R8   - Clocking2 */
0042     {  9, 0x0000 },     /* R9   - Audio Interface 1 */
0043     { 10, 0x00FF },     /* R10  - Left DAC volume */
0044     { 11, 0x00FF },     /* R11  - Right DAC volume */
0045 
0046     { 14, 0x0040 },     /* R14  - Audio Interface 2 */
0047 
0048     { 17, 0x007B },     /* R17  - ALC1 */
0049     { 18, 0x0000 },     /* R18  - ALC2 */
0050     { 19, 0x0032 },     /* R19  - ALC3 */
0051     { 20, 0x0000 },     /* R20  - Noise Gate */
0052     { 21, 0x00C0 },     /* R21  - Left ADC volume */
0053     { 22, 0x00C0 },     /* R22  - Right ADC volume */
0054     { 23, 0x0120 },     /* R23  - Additional control(1) */
0055     { 24, 0x0000 },     /* R24  - Additional control(2) */
0056     { 25, 0x0000 },     /* R25  - Pwr Mgmt (1) */
0057     { 26, 0x0000 },     /* R26  - Pwr Mgmt (2) */
0058     { 27, 0x0000 },     /* R27  - Additional Control (3) */
0059     { 28, 0x0000 },     /* R28  - Anti-pop */
0060 
0061     { 30, 0x005F },     /* R30  - Clocking 3 */
0062 
0063     { 32, 0x0000 },     /* R32  - ADCL signal path */
0064     { 33, 0x0000 },     /* R33  - ADCR signal path */
0065 
0066     { 40, 0x0000 },     /* R40  - LOUT2 volume */
0067     { 41, 0x0000 },     /* R41  - ROUT2 volume */
0068 
0069     { 47, 0x0000 },     /* R47  - Pwr Mgmt (3) */
0070     { 48, 0x0023 },     /* R48  - Additional Control (4) */
0071     { 49, 0x0000 },     /* R49  - Class D Control 1 */
0072 
0073     { 51, 0x0003 },     /* R51  - Class D Control 2 */
0074 
0075     { 56, 0x0106 },     /* R56  - Clocking 4 */
0076     { 57, 0x0000 },     /* R57  - DSP Sidetone 0 */
0077     { 58, 0x0000 },     /* R58  - DSP Sidetone 1 */
0078 
0079     { 60, 0x0000 },     /* R60  - DC Servo 0 */
0080     { 61, 0x0000 },     /* R61  - DC Servo 1 */
0081 
0082     { 63, 0x015E },     /* R63  - DC Servo 3 */
0083 
0084     { 65, 0x0010 },     /* R65  - DC Servo 5 */
0085 
0086     { 68, 0x0003 },     /* R68  - Analogue PGA Bias */
0087     { 69, 0x0000 },     /* R69  - Analogue HP 0 */
0088 
0089     { 71, 0x01FB },     /* R71  - Analogue HP 2 */
0090     { 72, 0x0000 },     /* R72  - Charge Pump 1 */
0091 
0092     { 82, 0x0000 },     /* R82  - Charge Pump B */
0093 
0094     { 87, 0x0000 },     /* R87  - Write Sequencer 1 */
0095     { 88, 0x0000 },     /* R88  - Write Sequencer 2 */
0096     { 89, 0x0000 },     /* R89  - Write Sequencer 3 */
0097     { 90, 0x0000 },     /* R90  - Write Sequencer 4 */
0098     { 91, 0x0000 },     /* R91  - Write Sequencer 5 */
0099     { 92, 0x0000 },     /* R92  - Write Sequencer 6 */
0100     { 93, 0x0000 },     /* R93  - Write Sequencer 7 */
0101 
0102     { 252, 0x0001 },     /* R252 - General test 1 */
0103 };
0104 
0105 struct wm8961_priv {
0106     struct regmap *regmap;
0107     int sysclk;
0108 };
0109 
0110 static bool wm8961_volatile(struct device *dev, unsigned int reg)
0111 {
0112     switch (reg) {
0113     case WM8961_SOFTWARE_RESET:
0114     case WM8961_WRITE_SEQUENCER_7:
0115     case WM8961_DC_SERVO_1:
0116         return true;
0117 
0118     default:
0119         return false;
0120     }
0121 }
0122 
0123 static bool wm8961_readable(struct device *dev, unsigned int reg)
0124 {
0125     switch (reg) {
0126     case WM8961_LEFT_INPUT_VOLUME:
0127     case WM8961_RIGHT_INPUT_VOLUME:
0128     case WM8961_LOUT1_VOLUME:
0129     case WM8961_ROUT1_VOLUME:
0130     case WM8961_CLOCKING1:
0131     case WM8961_ADC_DAC_CONTROL_1:
0132     case WM8961_ADC_DAC_CONTROL_2:
0133     case WM8961_AUDIO_INTERFACE_0:
0134     case WM8961_CLOCKING2:
0135     case WM8961_AUDIO_INTERFACE_1:
0136     case WM8961_LEFT_DAC_VOLUME:
0137     case WM8961_RIGHT_DAC_VOLUME:
0138     case WM8961_AUDIO_INTERFACE_2:
0139     case WM8961_SOFTWARE_RESET:
0140     case WM8961_ALC1:
0141     case WM8961_ALC2:
0142     case WM8961_ALC3:
0143     case WM8961_NOISE_GATE:
0144     case WM8961_LEFT_ADC_VOLUME:
0145     case WM8961_RIGHT_ADC_VOLUME:
0146     case WM8961_ADDITIONAL_CONTROL_1:
0147     case WM8961_ADDITIONAL_CONTROL_2:
0148     case WM8961_PWR_MGMT_1:
0149     case WM8961_PWR_MGMT_2:
0150     case WM8961_ADDITIONAL_CONTROL_3:
0151     case WM8961_ANTI_POP:
0152     case WM8961_CLOCKING_3:
0153     case WM8961_ADCL_SIGNAL_PATH:
0154     case WM8961_ADCR_SIGNAL_PATH:
0155     case WM8961_LOUT2_VOLUME:
0156     case WM8961_ROUT2_VOLUME:
0157     case WM8961_PWR_MGMT_3:
0158     case WM8961_ADDITIONAL_CONTROL_4:
0159     case WM8961_CLASS_D_CONTROL_1:
0160     case WM8961_CLASS_D_CONTROL_2:
0161     case WM8961_CLOCKING_4:
0162     case WM8961_DSP_SIDETONE_0:
0163     case WM8961_DSP_SIDETONE_1:
0164     case WM8961_DC_SERVO_0:
0165     case WM8961_DC_SERVO_1:
0166     case WM8961_DC_SERVO_3:
0167     case WM8961_DC_SERVO_5:
0168     case WM8961_ANALOGUE_PGA_BIAS:
0169     case WM8961_ANALOGUE_HP_0:
0170     case WM8961_ANALOGUE_HP_2:
0171     case WM8961_CHARGE_PUMP_1:
0172     case WM8961_CHARGE_PUMP_B:
0173     case WM8961_WRITE_SEQUENCER_1:
0174     case WM8961_WRITE_SEQUENCER_2:
0175     case WM8961_WRITE_SEQUENCER_3:
0176     case WM8961_WRITE_SEQUENCER_4:
0177     case WM8961_WRITE_SEQUENCER_5:
0178     case WM8961_WRITE_SEQUENCER_6:
0179     case WM8961_WRITE_SEQUENCER_7:
0180     case WM8961_GENERAL_TEST_1:
0181         return true;
0182     default:
0183         return false;
0184     }
0185 }
0186 
0187 /*
0188  * The headphone output supports special anti-pop sequences giving
0189  * silent power up and power down.
0190  */
0191 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
0192                struct snd_kcontrol *kcontrol, int event)
0193 {
0194     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0195     u16 hp_reg = snd_soc_component_read(component, WM8961_ANALOGUE_HP_0);
0196     u16 cp_reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_1);
0197     u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
0198     u16 dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
0199     int timeout = 500;
0200 
0201     if (event & SND_SOC_DAPM_POST_PMU) {
0202         /* Make sure the output is shorted */
0203         hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
0204         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0205 
0206         /* Enable the charge pump */
0207         cp_reg |= WM8961_CP_ENA;
0208         snd_soc_component_write(component, WM8961_CHARGE_PUMP_1, cp_reg);
0209         mdelay(5);
0210 
0211         /* Enable the PGA */
0212         pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
0213         snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
0214 
0215         /* Enable the amplifier */
0216         hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
0217         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0218 
0219         /* Second stage enable */
0220         hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
0221         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0222 
0223         /* Enable the DC servo & trigger startup */
0224         dcs_reg |=
0225             WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
0226             WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
0227         dev_dbg(component->dev, "Enabling DC servo\n");
0228 
0229         snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
0230         do {
0231             msleep(1);
0232             dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);
0233         } while (--timeout &&
0234              dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
0235                 WM8961_DCS_TRIG_STARTUP_HPL));
0236         if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
0237                    WM8961_DCS_TRIG_STARTUP_HPL))
0238             dev_err(component->dev, "DC servo timed out\n");
0239         else
0240             dev_dbg(component->dev, "DC servo startup complete\n");
0241 
0242         /* Enable the output stage */
0243         hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
0244         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0245 
0246         /* Remove the short on the output stage */
0247         hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
0248         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0249     }
0250 
0251     if (event & SND_SOC_DAPM_PRE_PMD) {
0252         /* Short the output */
0253         hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
0254         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0255 
0256         /* Disable the output stage */
0257         hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
0258         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0259 
0260         /* Disable DC offset cancellation */
0261         dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
0262                  WM8961_DCS_ENA_CHAN_HPL);
0263         snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);
0264 
0265         /* Finish up */
0266         hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
0267                 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
0268         snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);
0269 
0270         /* Disable the PGA */
0271         pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
0272         snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
0273 
0274         /* Disable the charge pump */
0275         dev_dbg(component->dev, "Disabling charge pump\n");
0276         snd_soc_component_write(component, WM8961_CHARGE_PUMP_1,
0277                  cp_reg & ~WM8961_CP_ENA);
0278     }
0279 
0280     return 0;
0281 }
0282 
0283 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
0284                 struct snd_kcontrol *kcontrol, int event)
0285 {
0286     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0287     u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);
0288     u16 spk_reg = snd_soc_component_read(component, WM8961_CLASS_D_CONTROL_1);
0289 
0290     if (event & SND_SOC_DAPM_POST_PMU) {
0291         /* Enable the PGA */
0292         pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
0293         snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
0294 
0295         /* Enable the amplifier */
0296         spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
0297         snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);
0298     }
0299 
0300     if (event & SND_SOC_DAPM_PRE_PMD) {
0301         /* Disable the amplifier */
0302         spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
0303         snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);
0304 
0305         /* Disable the PGA */
0306         pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
0307         snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);
0308     }
0309 
0310     return 0;
0311 }
0312 
0313 static const char *adc_hpf_text[] = {
0314     "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
0315 };
0316 
0317 static SOC_ENUM_SINGLE_DECL(adc_hpf,
0318                 WM8961_ADC_DAC_CONTROL_2, 7, adc_hpf_text);
0319 
0320 static const char *dac_deemph_text[] = {
0321     "None", "32kHz", "44.1kHz", "48kHz",
0322 };
0323 
0324 static SOC_ENUM_SINGLE_DECL(dac_deemph,
0325                 WM8961_ADC_DAC_CONTROL_1, 1, dac_deemph_text);
0326 
0327 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
0328 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
0329 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
0330 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
0331 static const DECLARE_TLV_DB_RANGE(boost_tlv,
0332     0, 0, TLV_DB_SCALE_ITEM(0,  0, 0),
0333     1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
0334     2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
0335     3, 3, TLV_DB_SCALE_ITEM(29, 0, 0)
0336 );
0337 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
0338 
0339 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
0340 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
0341          0, 127, 0, out_tlv),
0342 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
0343            6, 3, 7, 0, hp_sec_tlv),
0344 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
0345          7, 1, 0),
0346 
0347 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
0348          0, 127, 0, out_tlv),
0349 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
0350        7, 1, 0),
0351 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
0352 
0353 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
0354 SOC_ENUM("DAC Deemphasis", dac_deemph),
0355 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
0356 
0357 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
0358          WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
0359 
0360 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
0361 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
0362 
0363 SOC_DOUBLE_R_TLV("Capture Volume",
0364          WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
0365          1, 119, 0, adc_tlv),
0366 SOC_DOUBLE_R_TLV("Capture Boost Volume",
0367          WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
0368          4, 3, 0, boost_tlv),
0369 SOC_DOUBLE_R_TLV("Capture PGA Volume",
0370          WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
0371          0, 62, 0, pga_tlv),
0372 SOC_DOUBLE_R("Capture PGA ZC Switch",
0373          WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
0374          6, 1, 1),
0375 SOC_DOUBLE_R("Capture PGA Switch",
0376          WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
0377          7, 1, 1),
0378 };
0379 
0380 static const char *sidetone_text[] = {
0381     "None", "Left", "Right"
0382 };
0383 
0384 static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
0385                 WM8961_DSP_SIDETONE_0, 2, sidetone_text);
0386 
0387 static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
0388                 WM8961_DSP_SIDETONE_1, 2, sidetone_text);
0389 
0390 static const struct snd_kcontrol_new dacl_mux =
0391     SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
0392 
0393 static const struct snd_kcontrol_new dacr_mux =
0394     SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
0395 
0396 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
0397 SND_SOC_DAPM_INPUT("LINPUT"),
0398 SND_SOC_DAPM_INPUT("RINPUT"),
0399 
0400 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
0401 
0402 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
0403 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
0404 
0405 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
0406 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
0407 
0408 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
0409 
0410 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
0411 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
0412 
0413 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
0414 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
0415 
0416 /* Handle as a mono path for DCS */
0417 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
0418            4, 0, NULL, 0, wm8961_hp_event,
0419            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0420 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
0421            4, 0, NULL, 0, wm8961_spk_event,
0422            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0423 
0424 SND_SOC_DAPM_OUTPUT("HP_L"),
0425 SND_SOC_DAPM_OUTPUT("HP_R"),
0426 SND_SOC_DAPM_OUTPUT("SPK_LN"),
0427 SND_SOC_DAPM_OUTPUT("SPK_LP"),
0428 SND_SOC_DAPM_OUTPUT("SPK_RN"),
0429 SND_SOC_DAPM_OUTPUT("SPK_RP"),
0430 };
0431 
0432 
0433 static const struct snd_soc_dapm_route audio_paths[] = {
0434     { "DACL", NULL, "CLK_DSP" },
0435     { "DACL", NULL, "DACL Sidetone" },
0436     { "DACR", NULL, "CLK_DSP" },
0437     { "DACR", NULL, "DACR Sidetone" },
0438 
0439     { "DACL Sidetone", "Left", "ADCL" },
0440     { "DACL Sidetone", "Right", "ADCR" },
0441 
0442     { "DACR Sidetone", "Left", "ADCL" },
0443     { "DACR Sidetone", "Right", "ADCR" },
0444 
0445     { "HP_L", NULL, "Headphone Output" },
0446     { "HP_R", NULL, "Headphone Output" },
0447     { "Headphone Output", NULL, "DACL" },
0448     { "Headphone Output", NULL, "DACR" },
0449 
0450     { "SPK_LN", NULL, "Speaker Output" },
0451     { "SPK_LP", NULL, "Speaker Output" },
0452     { "SPK_RN", NULL, "Speaker Output" },
0453     { "SPK_RP", NULL, "Speaker Output" },
0454 
0455     { "Speaker Output", NULL, "DACL" },
0456     { "Speaker Output", NULL, "DACR" },
0457 
0458     { "ADCL", NULL, "Left Input" },
0459     { "ADCL", NULL, "CLK_DSP" },
0460     { "ADCR", NULL, "Right Input" },
0461     { "ADCR", NULL, "CLK_DSP" },
0462 
0463     { "Left Input", NULL, "LINPUT" },
0464     { "Right Input", NULL, "RINPUT" },
0465 
0466 };
0467 
0468 /* Values for CLK_SYS_RATE */
0469 static struct {
0470     int ratio;
0471     u16 val;
0472 } wm8961_clk_sys_ratio[] = {
0473     {  64,  0 },
0474     {  128, 1 },
0475     {  192, 2 },
0476     {  256, 3 },
0477     {  384, 4 },
0478     {  512, 5 },
0479     {  768, 6 },
0480     { 1024, 7 },
0481     { 1408, 8 },
0482     { 1536, 9 },
0483 };
0484 
0485 /* Values for SAMPLE_RATE */
0486 static struct {
0487     int rate;
0488     u16 val;
0489 } wm8961_srate[] = {
0490     { 48000, 0 },
0491     { 44100, 0 },
0492     { 32000, 1 },
0493     { 22050, 2 },
0494     { 24000, 2 },
0495     { 16000, 3 },
0496     { 11250, 4 },
0497     { 12000, 4 },
0498     {  8000, 5 },
0499 };
0500 
0501 static int wm8961_hw_params(struct snd_pcm_substream *substream,
0502                 struct snd_pcm_hw_params *params,
0503                 struct snd_soc_dai *dai)
0504 {
0505     struct snd_soc_component *component = dai->component;
0506     struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
0507     int i, best, target, fs;
0508     u16 reg;
0509 
0510     fs = params_rate(params);
0511 
0512     if (!wm8961->sysclk) {
0513         dev_err(component->dev, "MCLK has not been specified\n");
0514         return -EINVAL;
0515     }
0516 
0517     /* Find the closest sample rate for the filters */
0518     best = 0;
0519     for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
0520         if (abs(wm8961_srate[i].rate - fs) <
0521             abs(wm8961_srate[best].rate - fs))
0522             best = i;
0523     }
0524     reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_3);
0525     reg &= ~WM8961_SAMPLE_RATE_MASK;
0526     reg |= wm8961_srate[best].val;
0527     snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg);
0528     dev_dbg(component->dev, "Selected SRATE %dHz for %dHz\n",
0529         wm8961_srate[best].rate, fs);
0530 
0531     /* Select a CLK_SYS/fs ratio equal to or higher than required */
0532     target = wm8961->sysclk / fs;
0533 
0534     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
0535         dev_err(component->dev,
0536             "SYSCLK must be at least 64*fs for DAC\n");
0537         return -EINVAL;
0538     }
0539     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
0540         dev_err(component->dev,
0541             "SYSCLK must be at least 256*fs for ADC\n");
0542         return -EINVAL;
0543     }
0544 
0545     for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
0546         if (wm8961_clk_sys_ratio[i].ratio >= target)
0547             break;
0548     }
0549     if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
0550         dev_err(component->dev, "Unable to generate CLK_SYS_RATE\n");
0551         return -EINVAL;
0552     }
0553     dev_dbg(component->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
0554         wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
0555         wm8961->sysclk / fs);
0556 
0557     reg = snd_soc_component_read(component, WM8961_CLOCKING_4);
0558     reg &= ~WM8961_CLK_SYS_RATE_MASK;
0559     reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
0560     snd_soc_component_write(component, WM8961_CLOCKING_4, reg);
0561 
0562     reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
0563     reg &= ~WM8961_WL_MASK;
0564     switch (params_width(params)) {
0565     case 16:
0566         break;
0567     case 20:
0568         reg |= 1 << WM8961_WL_SHIFT;
0569         break;
0570     case 24:
0571         reg |= 2 << WM8961_WL_SHIFT;
0572         break;
0573     case 32:
0574         reg |= 3 << WM8961_WL_SHIFT;
0575         break;
0576     default:
0577         return -EINVAL;
0578     }
0579     snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg);
0580 
0581     /* Sloping stop-band filter is recommended for <= 24kHz */
0582     reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
0583     if (fs <= 24000)
0584         reg |= WM8961_DACSLOPE;
0585     else
0586         reg &= ~WM8961_DACSLOPE;
0587     snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
0588 
0589     return 0;
0590 }
0591 
0592 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0593                  unsigned int freq,
0594                  int dir)
0595 {
0596     struct snd_soc_component *component = dai->component;
0597     struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);
0598     u16 reg = snd_soc_component_read(component, WM8961_CLOCKING1);
0599 
0600     if (freq > 33000000) {
0601         dev_err(component->dev, "MCLK must be <33MHz\n");
0602         return -EINVAL;
0603     }
0604 
0605     if (freq > 16500000) {
0606         dev_dbg(component->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
0607         reg |= WM8961_MCLKDIV;
0608         freq /= 2;
0609     } else {
0610         dev_dbg(component->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
0611         reg &= ~WM8961_MCLKDIV;
0612     }
0613 
0614     snd_soc_component_write(component, WM8961_CLOCKING1, reg);
0615 
0616     wm8961->sysclk = freq;
0617 
0618     return 0;
0619 }
0620 
0621 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0622 {
0623     struct snd_soc_component *component = dai->component;
0624     u16 aif = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);
0625 
0626     aif &= ~(WM8961_BCLKINV | WM8961_LRP |
0627          WM8961_MS | WM8961_FORMAT_MASK);
0628 
0629     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0630     case SND_SOC_DAIFMT_CBM_CFM:
0631         aif |= WM8961_MS;
0632         break;
0633     case SND_SOC_DAIFMT_CBS_CFS:
0634         break;
0635     default:
0636         return -EINVAL;
0637     }
0638 
0639     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0640     case SND_SOC_DAIFMT_RIGHT_J:
0641         break;
0642 
0643     case SND_SOC_DAIFMT_LEFT_J:
0644         aif |= 1;
0645         break;
0646 
0647     case SND_SOC_DAIFMT_I2S:
0648         aif |= 2;
0649         break;
0650 
0651     case SND_SOC_DAIFMT_DSP_B:
0652         aif |= WM8961_LRP;
0653         fallthrough;
0654     case SND_SOC_DAIFMT_DSP_A:
0655         aif |= 3;
0656         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0657         case SND_SOC_DAIFMT_NB_NF:
0658         case SND_SOC_DAIFMT_IB_NF:
0659             break;
0660         default:
0661             return -EINVAL;
0662         }
0663         break;
0664 
0665     default:
0666         return -EINVAL;
0667     }
0668 
0669     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0670     case SND_SOC_DAIFMT_NB_NF:
0671         break;
0672     case SND_SOC_DAIFMT_NB_IF:
0673         aif |= WM8961_LRP;
0674         break;
0675     case SND_SOC_DAIFMT_IB_NF:
0676         aif |= WM8961_BCLKINV;
0677         break;
0678     case SND_SOC_DAIFMT_IB_IF:
0679         aif |= WM8961_BCLKINV | WM8961_LRP;
0680         break;
0681     default:
0682         return -EINVAL;
0683     }
0684 
0685     return snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, aif);
0686 }
0687 
0688 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
0689 {
0690     struct snd_soc_component *component = dai->component;
0691     u16 reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_2);
0692 
0693     if (tristate)
0694         reg |= WM8961_TRIS;
0695     else
0696         reg &= ~WM8961_TRIS;
0697 
0698     return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg);
0699 }
0700 
0701 static int wm8961_mute(struct snd_soc_dai *dai, int mute, int direction)
0702 {
0703     struct snd_soc_component *component = dai->component;
0704     u16 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_1);
0705 
0706     if (mute)
0707         reg |= WM8961_DACMU;
0708     else
0709         reg &= ~WM8961_DACMU;
0710 
0711     msleep(17);
0712 
0713     return snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_1, reg);
0714 }
0715 
0716 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
0717 {
0718     struct snd_soc_component *component = dai->component;
0719     u16 reg;
0720 
0721     switch (div_id) {
0722     case WM8961_BCLK:
0723         reg = snd_soc_component_read(component, WM8961_CLOCKING2);
0724         reg &= ~WM8961_BCLKDIV_MASK;
0725         reg |= div;
0726         snd_soc_component_write(component, WM8961_CLOCKING2, reg);
0727         break;
0728 
0729     case WM8961_LRCLK:
0730         reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_2);
0731         reg &= ~WM8961_LRCLK_RATE_MASK;
0732         reg |= div;
0733         snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg);
0734         break;
0735 
0736     default:
0737         return -EINVAL;
0738     }
0739 
0740     return 0;
0741 }
0742 
0743 static int wm8961_set_bias_level(struct snd_soc_component *component,
0744                  enum snd_soc_bias_level level)
0745 {
0746     u16 reg;
0747 
0748     /* This is all slightly unusual since we have no bypass paths
0749      * and the output amplifier structure means we can just slam
0750      * the biases straight up rather than having to ramp them
0751      * slowly.
0752      */
0753     switch (level) {
0754     case SND_SOC_BIAS_ON:
0755         break;
0756 
0757     case SND_SOC_BIAS_PREPARE:
0758         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {
0759             /* Enable bias generation */
0760             reg = snd_soc_component_read(component, WM8961_ANTI_POP);
0761             reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
0762             snd_soc_component_write(component, WM8961_ANTI_POP, reg);
0763 
0764             /* VMID=2*50k, VREF */
0765             reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
0766             reg &= ~WM8961_VMIDSEL_MASK;
0767             reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
0768             snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
0769         }
0770         break;
0771 
0772     case SND_SOC_BIAS_STANDBY:
0773         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
0774             /* VREF off */
0775             reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
0776             reg &= ~WM8961_VREF;
0777             snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
0778 
0779             /* Bias generation off */
0780             reg = snd_soc_component_read(component, WM8961_ANTI_POP);
0781             reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
0782             snd_soc_component_write(component, WM8961_ANTI_POP, reg);
0783 
0784             /* VMID off */
0785             reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);
0786             reg &= ~WM8961_VMIDSEL_MASK;
0787             snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);
0788         }
0789         break;
0790 
0791     case SND_SOC_BIAS_OFF:
0792         break;
0793     }
0794 
0795     return 0;
0796 }
0797 
0798 
0799 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
0800 
0801 #define WM8961_FORMATS \
0802     (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0803     SNDRV_PCM_FMTBIT_S24_LE)
0804 
0805 static const struct snd_soc_dai_ops wm8961_dai_ops = {
0806     .hw_params = wm8961_hw_params,
0807     .set_sysclk = wm8961_set_sysclk,
0808     .set_fmt = wm8961_set_fmt,
0809     .mute_stream = wm8961_mute,
0810     .set_tristate = wm8961_set_tristate,
0811     .set_clkdiv = wm8961_set_clkdiv,
0812     .no_capture_mute = 1,
0813 };
0814 
0815 static struct snd_soc_dai_driver wm8961_dai = {
0816     .name = "wm8961-hifi",
0817     .playback = {
0818         .stream_name = "HiFi Playback",
0819         .channels_min = 1,
0820         .channels_max = 2,
0821         .rates = WM8961_RATES,
0822         .formats = WM8961_FORMATS,},
0823     .capture = {
0824         .stream_name = "HiFi Capture",
0825         .channels_min = 1,
0826         .channels_max = 2,
0827         .rates = WM8961_RATES,
0828         .formats = WM8961_FORMATS,},
0829     .ops = &wm8961_dai_ops,
0830 };
0831 
0832 static int wm8961_probe(struct snd_soc_component *component)
0833 {
0834     u16 reg;
0835 
0836     /* Enable class W */
0837     reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_B);
0838     reg |= WM8961_CP_DYN_PWR_MASK;
0839     snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg);
0840 
0841     /* Latch volume update bits (right channel only, we always
0842      * write both out) and default ZC on. */
0843     reg = snd_soc_component_read(component, WM8961_ROUT1_VOLUME);
0844     snd_soc_component_write(component, WM8961_ROUT1_VOLUME,
0845              reg | WM8961_LO1ZC | WM8961_OUT1VU);
0846     snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
0847     reg = snd_soc_component_read(component, WM8961_ROUT2_VOLUME);
0848     snd_soc_component_write(component, WM8961_ROUT2_VOLUME,
0849              reg | WM8961_SPKRZC | WM8961_SPKVU);
0850     snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
0851 
0852     reg = snd_soc_component_read(component, WM8961_RIGHT_ADC_VOLUME);
0853     snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
0854     reg = snd_soc_component_read(component, WM8961_RIGHT_INPUT_VOLUME);
0855     snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
0856 
0857     /* Use soft mute by default */
0858     reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);
0859     reg |= WM8961_DACSMM;
0860     snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);
0861 
0862     /* Use automatic clocking mode by default; for now this is all
0863      * we support.
0864      */
0865     reg = snd_soc_component_read(component, WM8961_CLOCKING_3);
0866     reg &= ~WM8961_MANUAL_MODE;
0867     snd_soc_component_write(component, WM8961_CLOCKING_3, reg);
0868 
0869     return 0;
0870 }
0871 
0872 #ifdef CONFIG_PM
0873 
0874 static int wm8961_resume(struct snd_soc_component *component)
0875 {
0876     snd_soc_component_cache_sync(component);
0877 
0878     return 0;
0879 }
0880 #else
0881 #define wm8961_resume NULL
0882 #endif
0883 
0884 static const struct snd_soc_component_driver soc_component_dev_wm8961 = {
0885     .probe          = wm8961_probe,
0886     .resume         = wm8961_resume,
0887     .set_bias_level     = wm8961_set_bias_level,
0888     .controls       = wm8961_snd_controls,
0889     .num_controls       = ARRAY_SIZE(wm8961_snd_controls),
0890     .dapm_widgets       = wm8961_dapm_widgets,
0891     .num_dapm_widgets   = ARRAY_SIZE(wm8961_dapm_widgets),
0892     .dapm_routes        = audio_paths,
0893     .num_dapm_routes    = ARRAY_SIZE(audio_paths),
0894     .suspend_bias_off   = 1,
0895     .idle_bias_on       = 1,
0896     .use_pmdown_time    = 1,
0897     .endianness     = 1,
0898 };
0899 
0900 static const struct regmap_config wm8961_regmap = {
0901     .reg_bits = 8,
0902     .val_bits = 16,
0903     .max_register = WM8961_MAX_REGISTER,
0904 
0905     .reg_defaults = wm8961_reg_defaults,
0906     .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),
0907     .cache_type = REGCACHE_RBTREE,
0908 
0909     .volatile_reg = wm8961_volatile,
0910     .readable_reg = wm8961_readable,
0911 };
0912 
0913 static int wm8961_i2c_probe(struct i2c_client *i2c)
0914 {
0915     struct wm8961_priv *wm8961;
0916     unsigned int val;
0917     int ret;
0918 
0919     wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
0920                   GFP_KERNEL);
0921     if (wm8961 == NULL)
0922         return -ENOMEM;
0923 
0924     wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);
0925     if (IS_ERR(wm8961->regmap))
0926         return PTR_ERR(wm8961->regmap);
0927 
0928     ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);
0929     if (ret != 0) {
0930         dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
0931         return ret;
0932     }
0933 
0934     if (val != 0x1801) {
0935         dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);
0936         return -EINVAL;
0937     }
0938 
0939     /* This isn't volatile - readback doesn't correspond to write */
0940     regcache_cache_bypass(wm8961->regmap, true);
0941     ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);
0942     regcache_cache_bypass(wm8961->regmap, false);
0943 
0944     if (ret != 0) {
0945         dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
0946         return ret;
0947     }
0948 
0949     dev_info(&i2c->dev, "WM8961 family %d revision %c\n",
0950          (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
0951          ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
0952          + 'A');
0953 
0954     ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);
0955     if (ret != 0) {
0956         dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
0957         return ret;
0958     }
0959 
0960     i2c_set_clientdata(i2c, wm8961);
0961 
0962     ret = devm_snd_soc_register_component(&i2c->dev,
0963             &soc_component_dev_wm8961, &wm8961_dai, 1);
0964 
0965     return ret;
0966 }
0967 
0968 static const struct i2c_device_id wm8961_i2c_id[] = {
0969     { "wm8961", 0 },
0970     { }
0971 };
0972 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
0973 
0974 static struct i2c_driver wm8961_i2c_driver = {
0975     .driver = {
0976         .name = "wm8961",
0977     },
0978     .probe_new = wm8961_i2c_probe,
0979     .id_table = wm8961_i2c_id,
0980 };
0981 
0982 module_i2c_driver(wm8961_i2c_driver);
0983 
0984 MODULE_DESCRIPTION("ASoC WM8961 driver");
0985 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
0986 MODULE_LICENSE("GPL");
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