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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8955.c  --  WM8955 ALSA SoC Audio driver
0004  *
0005  * Copyright 2009 Wolfson Microelectronics plc
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/i2c.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/slab.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/initval.h>
0024 #include <sound/tlv.h>
0025 #include <sound/wm8955.h>
0026 
0027 #include "wm8955.h"
0028 
0029 #define WM8955_NUM_SUPPLIES 4
0030 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
0031     "DCVDD",
0032     "DBVDD",
0033     "HPVDD",
0034     "AVDD",
0035 };
0036 
0037 /* codec private data */
0038 struct wm8955_priv {
0039     struct regmap *regmap;
0040 
0041     unsigned int mclk_rate;
0042 
0043     int deemph;
0044     int fs;
0045 
0046     struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
0047 };
0048 
0049 static const struct reg_default wm8955_reg_defaults[] = {
0050     { 2,  0x0079 },     /* R2  - LOUT1 volume */
0051     { 3,  0x0079 },     /* R3  - ROUT1 volume */
0052     { 5,  0x0008 },     /* R5  - DAC Control */
0053     { 7,  0x000A },     /* R7  - Audio Interface */
0054     { 8,  0x0000 },     /* R8  - Sample Rate */
0055     { 10, 0x00FF },     /* R10 - Left DAC volume */
0056     { 11, 0x00FF },     /* R11 - Right DAC volume */
0057     { 12, 0x000F },     /* R12 - Bass control */
0058     { 13, 0x000F },     /* R13 - Treble control */
0059     { 23, 0x00C1 },     /* R23 - Additional control (1) */
0060     { 24, 0x0000 },     /* R24 - Additional control (2) */
0061     { 25, 0x0000 },     /* R25 - Power Management (1) */
0062     { 26, 0x0000 },     /* R26 - Power Management (2) */
0063     { 27, 0x0000 },     /* R27 - Additional Control (3) */
0064     { 34, 0x0050 },     /* R34 - Left out Mix (1) */
0065     { 35, 0x0050 },     /* R35 - Left out Mix (2) */
0066     { 36, 0x0050 },     /* R36 - Right out Mix (1) */
0067     { 37, 0x0050 },     /* R37 - Right Out Mix (2) */
0068     { 38, 0x0050 },     /* R38 - Mono out Mix (1) */
0069     { 39, 0x0050 },     /* R39 - Mono out Mix (2) */
0070     { 40, 0x0079 },     /* R40 - LOUT2 volume */
0071     { 41, 0x0079 },     /* R41 - ROUT2 volume */
0072     { 42, 0x0079 },     /* R42 - MONOOUT volume */
0073     { 43, 0x0000 },     /* R43 - Clocking / PLL */
0074     { 44, 0x0103 },     /* R44 - PLL Control 1 */
0075     { 45, 0x0024 },     /* R45 - PLL Control 2 */
0076     { 46, 0x01BA },     /* R46 - PLL Control 3 */
0077     { 59, 0x0000 },     /* R59 - PLL Control 4 */
0078 };
0079 
0080 static bool wm8955_writeable(struct device *dev, unsigned int reg)
0081 {
0082     switch (reg) {
0083     case WM8955_LOUT1_VOLUME:
0084     case WM8955_ROUT1_VOLUME:
0085     case WM8955_DAC_CONTROL:
0086     case WM8955_AUDIO_INTERFACE:
0087     case WM8955_SAMPLE_RATE:
0088     case WM8955_LEFT_DAC_VOLUME:
0089     case WM8955_RIGHT_DAC_VOLUME:
0090     case WM8955_BASS_CONTROL:
0091     case WM8955_TREBLE_CONTROL:
0092     case WM8955_RESET:
0093     case WM8955_ADDITIONAL_CONTROL_1:
0094     case WM8955_ADDITIONAL_CONTROL_2:
0095     case WM8955_POWER_MANAGEMENT_1:
0096     case WM8955_POWER_MANAGEMENT_2:
0097     case WM8955_ADDITIONAL_CONTROL_3:
0098     case WM8955_LEFT_OUT_MIX_1:
0099     case WM8955_LEFT_OUT_MIX_2:
0100     case WM8955_RIGHT_OUT_MIX_1:
0101     case WM8955_RIGHT_OUT_MIX_2:
0102     case WM8955_MONO_OUT_MIX_1:
0103     case WM8955_MONO_OUT_MIX_2:
0104     case WM8955_LOUT2_VOLUME:
0105     case WM8955_ROUT2_VOLUME:
0106     case WM8955_MONOOUT_VOLUME:
0107     case WM8955_CLOCKING_PLL:
0108     case WM8955_PLL_CONTROL_1:
0109     case WM8955_PLL_CONTROL_2:
0110     case WM8955_PLL_CONTROL_3:
0111     case WM8955_PLL_CONTROL_4:
0112         return true;
0113     default:
0114         return false;
0115     }
0116 }
0117 
0118 static bool wm8955_volatile(struct device *dev, unsigned int reg)
0119 {
0120     switch (reg) {
0121     case WM8955_RESET:
0122         return true;
0123     default:
0124         return false;
0125     }
0126 }
0127 
0128 static int wm8955_reset(struct snd_soc_component *component)
0129 {
0130     return snd_soc_component_write(component, WM8955_RESET, 0);
0131 }
0132 
0133 struct pll_factors {
0134     int n;
0135     int k;
0136     int outdiv;
0137 };
0138 
0139 /* The size in bits of the FLL divide multiplied by 10
0140  * to allow rounding later */
0141 #define FIXED_FLL_SIZE ((1 << 22) * 10)
0142 
0143 static int wm8955_pll_factors(struct device *dev,
0144                   int Fref, int Fout, struct pll_factors *pll)
0145 {
0146     u64 Kpart;
0147     unsigned int K, Ndiv, Nmod, target;
0148 
0149     dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
0150 
0151     /* The oscilator should run at should be 90-100MHz, and
0152      * there's a divide by 4 plus an optional divide by 2 in the
0153      * output path to generate the system clock.  The clock table
0154      * is sortd so we should always generate a suitable target. */
0155     target = Fout * 4;
0156     if (target < 90000000) {
0157         pll->outdiv = 1;
0158         target *= 2;
0159     } else {
0160         pll->outdiv = 0;
0161     }
0162 
0163     WARN_ON(target < 90000000 || target > 100000000);
0164 
0165     dev_dbg(dev, "Fvco=%dHz\n", target);
0166 
0167     /* Now, calculate N.K */
0168     Ndiv = target / Fref;
0169 
0170     pll->n = Ndiv;
0171     Nmod = target % Fref;
0172     dev_dbg(dev, "Nmod=%d\n", Nmod);
0173 
0174     /* Calculate fractional part - scale up so we can round. */
0175     Kpart = FIXED_FLL_SIZE * (long long)Nmod;
0176 
0177     do_div(Kpart, Fref);
0178 
0179     K = Kpart & 0xFFFFFFFF;
0180 
0181     if ((K % 10) >= 5)
0182         K += 5;
0183 
0184     /* Move down to proper range now rounding is done */
0185     pll->k = K / 10;
0186 
0187     dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
0188 
0189     return 0;
0190 }
0191 
0192 /* Lookup table specifying SRATE (table 25 in datasheet); some of the
0193  * output frequencies have been rounded to the standard frequencies
0194  * they are intended to match where the error is slight. */
0195 static struct {
0196     int mclk;
0197     int fs;
0198     int usb;
0199     int sr;
0200 } clock_cfgs[] = {
0201     { 18432000,  8000, 0,  3, },
0202     { 18432000, 12000, 0,  9, },
0203     { 18432000, 16000, 0, 11, },
0204     { 18432000, 24000, 0, 29, },
0205     { 18432000, 32000, 0, 13, },
0206     { 18432000, 48000, 0,  1, },
0207     { 18432000, 96000, 0, 15, },
0208 
0209     { 16934400,  8018, 0, 19, },
0210     { 16934400, 11025, 0, 25, },
0211     { 16934400, 22050, 0, 27, },
0212     { 16934400, 44100, 0, 17, },
0213     { 16934400, 88200, 0, 31, },
0214 
0215     { 12000000,  8000, 1,  2, },
0216     { 12000000, 11025, 1, 25, },
0217     { 12000000, 12000, 1,  8, },
0218     { 12000000, 16000, 1, 10, },
0219     { 12000000, 22050, 1, 27, },
0220     { 12000000, 24000, 1, 28, },
0221     { 12000000, 32000, 1, 12, },
0222     { 12000000, 44100, 1, 17, },
0223     { 12000000, 48000, 1,  0, },
0224     { 12000000, 88200, 1, 31, },
0225     { 12000000, 96000, 1, 14, },
0226 
0227     { 12288000,  8000, 0,  2, },
0228     { 12288000, 12000, 0,  8, },
0229     { 12288000, 16000, 0, 10, },
0230     { 12288000, 24000, 0, 28, },
0231     { 12288000, 32000, 0, 12, },
0232     { 12288000, 48000, 0,  0, },
0233     { 12288000, 96000, 0, 14, },
0234 
0235     { 12289600,  8018, 0, 18, },
0236     { 12289600, 11025, 0, 24, },
0237     { 12289600, 22050, 0, 26, },
0238     { 11289600, 44100, 0, 16, },
0239     { 11289600, 88200, 0, 31, },
0240 };
0241 
0242 static int wm8955_configure_clocking(struct snd_soc_component *component)
0243 {
0244     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0245     int i, ret, val;
0246     int clocking = 0;
0247     int srate = 0;
0248     int sr = -1;
0249     struct pll_factors pll;
0250 
0251     /* If we're not running a sample rate currently just pick one */
0252     if (wm8955->fs == 0)
0253         wm8955->fs = 8000;
0254 
0255     /* Can we generate an exact output? */
0256     for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
0257         if (wm8955->fs != clock_cfgs[i].fs)
0258             continue;
0259         sr = i;
0260 
0261         if (wm8955->mclk_rate == clock_cfgs[i].mclk)
0262             break;
0263     }
0264 
0265     /* We should never get here with an unsupported sample rate */
0266     if (sr == -1) {
0267         dev_err(component->dev, "Sample rate %dHz unsupported\n",
0268             wm8955->fs);
0269         WARN_ON(sr == -1);
0270         return -EINVAL;
0271     }
0272 
0273     if (i == ARRAY_SIZE(clock_cfgs)) {
0274         /* If we can't generate the right clock from MCLK then
0275          * we should configure the PLL to supply us with an
0276          * appropriate clock.
0277          */
0278         clocking |= WM8955_MCLKSEL;
0279 
0280         /* Use the last divider configuration we saw for the
0281          * sample rate. */
0282         ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate,
0283                      clock_cfgs[sr].mclk, &pll);
0284         if (ret != 0) {
0285             dev_err(component->dev,
0286                 "Unable to generate %dHz from %dHz MCLK\n",
0287                 wm8955->fs, wm8955->mclk_rate);
0288             return -EINVAL;
0289         }
0290 
0291         snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_1,
0292                     WM8955_N_MASK | WM8955_K_21_18_MASK,
0293                     (pll.n << WM8955_N_SHIFT) |
0294                     pll.k >> 18);
0295         snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_2,
0296                     WM8955_K_17_9_MASK,
0297                     (pll.k >> 9) & WM8955_K_17_9_MASK);
0298         snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_3,
0299                     WM8955_K_8_0_MASK,
0300                     pll.k & WM8955_K_8_0_MASK);
0301         if (pll.k)
0302             snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
0303                         WM8955_KEN, WM8955_KEN);
0304         else
0305             snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4,
0306                         WM8955_KEN, 0);
0307 
0308         if (pll.outdiv)
0309             val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
0310         else
0311             val = WM8955_PLL_RB;
0312 
0313         /* Now start the PLL running */
0314         snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
0315                     WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
0316         snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
0317                     WM8955_PLLEN, WM8955_PLLEN);
0318     }
0319 
0320     srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
0321 
0322     snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
0323                 WM8955_USB | WM8955_SR_MASK, srate);
0324     snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
0325                 WM8955_MCLKSEL, clocking);
0326 
0327     return 0;
0328 }
0329 
0330 static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
0331              struct snd_kcontrol *kcontrol, int event)
0332 {
0333     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0334     int ret = 0;
0335 
0336     /* Always disable the clocks - if we're doing reconfiguration this
0337      * avoids misclocking.
0338      */
0339     snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
0340                 WM8955_DIGENB, 0);
0341     snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
0342                 WM8955_PLL_RB | WM8955_PLLEN, 0);
0343 
0344     switch (event) {
0345     case SND_SOC_DAPM_POST_PMD:
0346         break;
0347     case SND_SOC_DAPM_PRE_PMU:
0348         ret = wm8955_configure_clocking(component);
0349         break;
0350     default:
0351         ret = -EINVAL;
0352         break;
0353     }
0354 
0355     return ret;
0356 }
0357 
0358 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
0359 
0360 static int wm8955_set_deemph(struct snd_soc_component *component)
0361 {
0362     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0363     int val, i, best;
0364 
0365     /* If we're using deemphasis select the nearest available sample
0366      * rate.
0367      */
0368     if (wm8955->deemph) {
0369         best = 1;
0370         for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
0371             if (abs(deemph_settings[i] - wm8955->fs) <
0372                 abs(deemph_settings[best] - wm8955->fs))
0373                 best = i;
0374         }
0375 
0376         val = best << WM8955_DEEMPH_SHIFT;
0377     } else {
0378         val = 0;
0379     }
0380 
0381     dev_dbg(component->dev, "Set deemphasis %d\n", val);
0382 
0383     return snd_soc_component_update_bits(component, WM8955_DAC_CONTROL,
0384                    WM8955_DEEMPH_MASK, val);
0385 }
0386 
0387 static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
0388                  struct snd_ctl_elem_value *ucontrol)
0389 {
0390     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0391     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0392 
0393     ucontrol->value.integer.value[0] = wm8955->deemph;
0394     return 0;
0395 }
0396 
0397 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
0398                  struct snd_ctl_elem_value *ucontrol)
0399 {
0400     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0401     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0402     unsigned int deemph = ucontrol->value.integer.value[0];
0403 
0404     if (deemph > 1)
0405         return -EINVAL;
0406 
0407     wm8955->deemph = deemph;
0408 
0409     return wm8955_set_deemph(component);
0410 }
0411 
0412 static const char *bass_mode_text[] = {
0413     "Linear", "Adaptive",
0414 };
0415 
0416 static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text);
0417 
0418 static const char *bass_cutoff_text[] = {
0419     "Low", "High"
0420 };
0421 
0422 static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6,
0423                 bass_cutoff_text);
0424 
0425 static const char *treble_cutoff_text[] = {
0426     "High", "Low"
0427 };
0428 
0429 static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2,
0430                 treble_cutoff_text);
0431 
0432 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
0433 static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
0434 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
0435 static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
0436 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
0437 static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
0438 
0439 static const struct snd_kcontrol_new wm8955_snd_controls[] = {
0440 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
0441          WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
0442 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
0443            atten_tlv),
0444 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
0445             wm8955_get_deemph, wm8955_put_deemph),
0446 
0447 SOC_ENUM("Bass Mode", bass_mode),
0448 SOC_ENUM("Bass Cutoff", bass_cutoff),
0449 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
0450 
0451 SOC_ENUM("Treble Cutoff", treble_cutoff),
0452 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
0453 
0454 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
0455            bypass_tlv),
0456 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
0457            bypass_tlv),
0458 
0459 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
0460            bypass_tlv),
0461 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
0462            bypass_tlv),
0463 
0464 /* Not a stereo pair so they line up with the DAPM switches */
0465 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
0466            mono_tlv),
0467 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
0468            mono_tlv),
0469 
0470 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
0471          WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
0472 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
0473          WM8955_ROUT1_VOLUME, 7, 1, 0),
0474 
0475 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
0476          WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
0477 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
0478          WM8955_ROUT2_VOLUME, 7, 1, 0),
0479 
0480 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
0481 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
0482 };
0483 
0484 static const struct snd_kcontrol_new lmixer[] = {
0485 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
0486 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
0487 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
0488 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
0489 };
0490 
0491 static const struct snd_kcontrol_new rmixer[] = {
0492 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
0493 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
0494 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
0495 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
0496 };
0497 
0498 static const struct snd_kcontrol_new mmixer[] = {
0499 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
0500 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
0501 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
0502 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
0503 };
0504 
0505 static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
0506 SND_SOC_DAPM_INPUT("MONOIN-"),
0507 SND_SOC_DAPM_INPUT("MONOIN+"),
0508 SND_SOC_DAPM_INPUT("LINEINR"),
0509 SND_SOC_DAPM_INPUT("LINEINL"),
0510 
0511 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
0512 
0513 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
0514             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0515 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
0516 
0517 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
0518 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
0519 
0520 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
0521 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
0522 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
0523 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
0524 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
0525 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
0526 
0527 /* The names are chosen to make the control names nice */
0528 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
0529            lmixer, ARRAY_SIZE(lmixer)),
0530 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
0531            rmixer, ARRAY_SIZE(rmixer)),
0532 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
0533            mmixer, ARRAY_SIZE(mmixer)),
0534 
0535 SND_SOC_DAPM_OUTPUT("LOUT1"),
0536 SND_SOC_DAPM_OUTPUT("ROUT1"),
0537 SND_SOC_DAPM_OUTPUT("LOUT2"),
0538 SND_SOC_DAPM_OUTPUT("ROUT2"),
0539 SND_SOC_DAPM_OUTPUT("MONOOUT"),
0540 SND_SOC_DAPM_OUTPUT("OUT3"),
0541 };
0542 
0543 static const struct snd_soc_dapm_route wm8955_dapm_routes[] = {
0544     { "DACL", NULL, "SYSCLK" },
0545     { "DACR", NULL, "SYSCLK" },
0546 
0547     { "Mono Input", NULL, "MONOIN-" },
0548     { "Mono Input", NULL, "MONOIN+" },
0549 
0550     { "Left", "Playback Switch", "DACL" },
0551     { "Left", "Right Playback Switch", "DACR" },
0552     { "Left", "Bypass Switch", "LINEINL" },
0553     { "Left", "Mono Switch", "Mono Input" },
0554 
0555     { "Right", "Playback Switch", "DACR" },
0556     { "Right", "Left Playback Switch", "DACL" },
0557     { "Right", "Bypass Switch", "LINEINR" },
0558     { "Right", "Mono Switch", "Mono Input" },
0559 
0560     { "Mono", "Left Playback Switch", "DACL" },
0561     { "Mono", "Right Playback Switch", "DACR" },
0562     { "Mono", "Left Bypass Switch", "LINEINL" },
0563     { "Mono", "Right Bypass Switch", "LINEINR" },
0564 
0565     { "LOUT1 PGA", NULL, "Left" },
0566     { "LOUT1", NULL, "TSDEN" },
0567     { "LOUT1", NULL, "LOUT1 PGA" },
0568 
0569     { "ROUT1 PGA", NULL, "Right" },
0570     { "ROUT1", NULL, "TSDEN" },
0571     { "ROUT1", NULL, "ROUT1 PGA" },
0572 
0573     { "LOUT2 PGA", NULL, "Left" },
0574     { "LOUT2", NULL, "TSDEN" },
0575     { "LOUT2", NULL, "LOUT2 PGA" },
0576 
0577     { "ROUT2 PGA", NULL, "Right" },
0578     { "ROUT2", NULL, "TSDEN" },
0579     { "ROUT2", NULL, "ROUT2 PGA" },
0580 
0581     { "MOUT PGA", NULL, "Mono" },
0582     { "MONOOUT", NULL, "MOUT PGA" },
0583 
0584     /* OUT3 not currently implemented */
0585     { "OUT3", NULL, "OUT3 PGA" },
0586 };
0587 
0588 static int wm8955_hw_params(struct snd_pcm_substream *substream,
0589                 struct snd_pcm_hw_params *params,
0590                 struct snd_soc_dai *dai)
0591 {
0592     struct snd_soc_component *component = dai->component;
0593     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0594     int ret;
0595     int wl;
0596 
0597     switch (params_width(params)) {
0598     case 16:
0599         wl = 0;
0600         break;
0601     case 20:
0602         wl = 0x4;
0603         break;
0604     case 24:
0605         wl = 0x8;
0606         break;
0607     case 32:
0608         wl = 0xc;
0609         break;
0610     default:
0611         return -EINVAL;
0612     }
0613     snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
0614                 WM8955_WL_MASK, wl);
0615 
0616     wm8955->fs = params_rate(params);
0617     wm8955_set_deemph(component);
0618 
0619     /* If the chip is clocked then disable the clocks and force a
0620      * reconfiguration, otherwise DAPM will power up the
0621      * clocks for us later. */
0622     ret = snd_soc_component_read(component, WM8955_POWER_MANAGEMENT_1);
0623     if (ret < 0)
0624         return ret;
0625     if (ret & WM8955_DIGENB) {
0626         snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
0627                     WM8955_DIGENB, 0);
0628         snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL,
0629                     WM8955_PLL_RB | WM8955_PLLEN, 0);
0630 
0631         wm8955_configure_clocking(component);
0632     }
0633 
0634     return 0;
0635 }
0636 
0637 
0638 static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0639                  unsigned int freq, int dir)
0640 {
0641     struct snd_soc_component *component = dai->component;
0642     struct wm8955_priv *priv = snd_soc_component_get_drvdata(component);
0643     int div;
0644 
0645     switch (clk_id) {
0646     case WM8955_CLK_MCLK:
0647         if (freq > 15000000) {
0648             priv->mclk_rate = freq /= 2;
0649             div = WM8955_MCLKDIV2;
0650         } else {
0651             priv->mclk_rate = freq;
0652             div = 0;
0653         }
0654 
0655         snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE,
0656                     WM8955_MCLKDIV2, div);
0657         break;
0658 
0659     default:
0660         return -EINVAL;
0661     }
0662 
0663     dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
0664 
0665     return 0;
0666 }
0667 
0668 static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0669 {
0670     struct snd_soc_component *component = dai->component;
0671     u16 aif = 0;
0672 
0673     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0674     case SND_SOC_DAIFMT_CBS_CFS:
0675         break;
0676     case SND_SOC_DAIFMT_CBM_CFM:
0677         aif |= WM8955_MS;
0678         break;
0679     default:
0680         return -EINVAL;
0681     }
0682 
0683     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0684     case SND_SOC_DAIFMT_DSP_B:
0685         aif |= WM8955_LRP;
0686         fallthrough;
0687     case SND_SOC_DAIFMT_DSP_A:
0688         aif |= 0x3;
0689         break;
0690     case SND_SOC_DAIFMT_I2S:
0691         aif |= 0x2;
0692         break;
0693     case SND_SOC_DAIFMT_RIGHT_J:
0694         break;
0695     case SND_SOC_DAIFMT_LEFT_J:
0696         aif |= 0x1;
0697         break;
0698     default:
0699         return -EINVAL;
0700     }
0701 
0702     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0703     case SND_SOC_DAIFMT_DSP_A:
0704     case SND_SOC_DAIFMT_DSP_B:
0705         /* frame inversion not valid for DSP modes */
0706         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0707         case SND_SOC_DAIFMT_NB_NF:
0708             break;
0709         case SND_SOC_DAIFMT_IB_NF:
0710             aif |= WM8955_BCLKINV;
0711             break;
0712         default:
0713             return -EINVAL;
0714         }
0715         break;
0716 
0717     case SND_SOC_DAIFMT_I2S:
0718     case SND_SOC_DAIFMT_RIGHT_J:
0719     case SND_SOC_DAIFMT_LEFT_J:
0720         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0721         case SND_SOC_DAIFMT_NB_NF:
0722             break;
0723         case SND_SOC_DAIFMT_IB_IF:
0724             aif |= WM8955_BCLKINV | WM8955_LRP;
0725             break;
0726         case SND_SOC_DAIFMT_IB_NF:
0727             aif |= WM8955_BCLKINV;
0728             break;
0729         case SND_SOC_DAIFMT_NB_IF:
0730             aif |= WM8955_LRP;
0731             break;
0732         default:
0733             return -EINVAL;
0734         }
0735         break;
0736     default:
0737         return -EINVAL;
0738     }
0739 
0740     snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE,
0741                 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
0742                 WM8955_LRP, aif);
0743 
0744     return 0;
0745 }
0746 
0747 
0748 static int wm8955_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
0749 {
0750     struct snd_soc_component *component = codec_dai->component;
0751     int val;
0752 
0753     if (mute)
0754         val = WM8955_DACMU;
0755     else
0756         val = 0;
0757 
0758     snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val);
0759 
0760     return 0;
0761 }
0762 
0763 static int wm8955_set_bias_level(struct snd_soc_component *component,
0764                  enum snd_soc_bias_level level)
0765 {
0766     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0767     int ret;
0768 
0769     switch (level) {
0770     case SND_SOC_BIAS_ON:
0771         break;
0772 
0773     case SND_SOC_BIAS_PREPARE:
0774         /* VMID resistance 2*50k */
0775         snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
0776                     WM8955_VMIDSEL_MASK,
0777                     0x1 << WM8955_VMIDSEL_SHIFT);
0778 
0779         /* Default bias current */
0780         snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
0781                     WM8955_VSEL_MASK,
0782                     0x2 << WM8955_VSEL_SHIFT);
0783         break;
0784 
0785     case SND_SOC_BIAS_STANDBY:
0786         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0787             ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
0788                             wm8955->supplies);
0789             if (ret != 0) {
0790                 dev_err(component->dev,
0791                     "Failed to enable supplies: %d\n",
0792                     ret);
0793                 return ret;
0794             }
0795 
0796             regcache_sync(wm8955->regmap);
0797 
0798             /* Enable VREF and VMID */
0799             snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
0800                         WM8955_VREF |
0801                         WM8955_VMIDSEL_MASK,
0802                         WM8955_VREF |
0803                         0x3 << WM8955_VREF_SHIFT);
0804 
0805             /* Let VMID ramp */
0806             msleep(500);
0807 
0808             /* High resistance VROI to maintain outputs */
0809             snd_soc_component_update_bits(component,
0810                         WM8955_ADDITIONAL_CONTROL_3,
0811                         WM8955_VROI, WM8955_VROI);
0812         }
0813 
0814         /* Maintain VMID with 2*250k */
0815         snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
0816                     WM8955_VMIDSEL_MASK,
0817                     0x2 << WM8955_VMIDSEL_SHIFT);
0818 
0819         /* Minimum bias current */
0820         snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1,
0821                     WM8955_VSEL_MASK, 0);
0822         break;
0823 
0824     case SND_SOC_BIAS_OFF:
0825         /* Low resistance VROI to help discharge */
0826         snd_soc_component_update_bits(component,
0827                     WM8955_ADDITIONAL_CONTROL_3,
0828                     WM8955_VROI, 0);
0829 
0830         /* Turn off VMID and VREF */
0831         snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1,
0832                     WM8955_VREF |
0833                     WM8955_VMIDSEL_MASK, 0);
0834 
0835         regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
0836                        wm8955->supplies);
0837         break;
0838     }
0839     return 0;
0840 }
0841 
0842 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
0843 
0844 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
0845             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0846 
0847 static const struct snd_soc_dai_ops wm8955_dai_ops = {
0848     .set_sysclk = wm8955_set_sysclk,
0849     .set_fmt = wm8955_set_fmt,
0850     .hw_params = wm8955_hw_params,
0851     .mute_stream = wm8955_mute,
0852     .no_capture_mute = 1,
0853 };
0854 
0855 static struct snd_soc_dai_driver wm8955_dai = {
0856     .name = "wm8955-hifi",
0857     .playback = {
0858         .stream_name = "Playback",
0859         .channels_min = 2,
0860         .channels_max = 2,
0861         .rates = WM8955_RATES,
0862         .formats = WM8955_FORMATS,
0863     },
0864     .ops = &wm8955_dai_ops,
0865 };
0866 
0867 static int wm8955_probe(struct snd_soc_component *component)
0868 {
0869     struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component);
0870     struct wm8955_pdata *pdata = dev_get_platdata(component->dev);
0871     int ret, i;
0872 
0873     for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
0874         wm8955->supplies[i].supply = wm8955_supply_names[i];
0875 
0876     ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8955->supplies),
0877                  wm8955->supplies);
0878     if (ret != 0) {
0879         dev_err(component->dev, "Failed to request supplies: %d\n", ret);
0880         return ret;
0881     }
0882 
0883     ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
0884                     wm8955->supplies);
0885     if (ret != 0) {
0886         dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
0887         return ret;
0888     }
0889 
0890     ret = wm8955_reset(component);
0891     if (ret < 0) {
0892         dev_err(component->dev, "Failed to issue reset: %d\n", ret);
0893         goto err_enable;
0894     }
0895 
0896     /* Change some default settings - latch VU and enable ZC */
0897     snd_soc_component_update_bits(component, WM8955_LEFT_DAC_VOLUME,
0898                 WM8955_LDVU, WM8955_LDVU);
0899     snd_soc_component_update_bits(component, WM8955_RIGHT_DAC_VOLUME,
0900                 WM8955_RDVU, WM8955_RDVU);
0901     snd_soc_component_update_bits(component, WM8955_LOUT1_VOLUME,
0902                 WM8955_LO1VU | WM8955_LO1ZC,
0903                 WM8955_LO1VU | WM8955_LO1ZC);
0904     snd_soc_component_update_bits(component, WM8955_ROUT1_VOLUME,
0905                 WM8955_RO1VU | WM8955_RO1ZC,
0906                 WM8955_RO1VU | WM8955_RO1ZC);
0907     snd_soc_component_update_bits(component, WM8955_LOUT2_VOLUME,
0908                 WM8955_LO2VU | WM8955_LO2ZC,
0909                 WM8955_LO2VU | WM8955_LO2ZC);
0910     snd_soc_component_update_bits(component, WM8955_ROUT2_VOLUME,
0911                 WM8955_RO2VU | WM8955_RO2ZC,
0912                 WM8955_RO2VU | WM8955_RO2ZC);
0913     snd_soc_component_update_bits(component, WM8955_MONOOUT_VOLUME,
0914                 WM8955_MOZC, WM8955_MOZC);
0915 
0916     /* Also enable adaptive bass boost by default */
0917     snd_soc_component_update_bits(component, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB);
0918 
0919     /* Set platform data values */
0920     if (pdata) {
0921         if (pdata->out2_speaker)
0922             snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_2,
0923                         WM8955_ROUT2INV, WM8955_ROUT2INV);
0924 
0925         if (pdata->monoin_diff)
0926             snd_soc_component_update_bits(component, WM8955_MONO_OUT_MIX_1,
0927                         WM8955_DMEN, WM8955_DMEN);
0928     }
0929 
0930     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
0931 
0932     /* Bias level configuration will have done an extra enable */
0933     regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
0934 
0935     return 0;
0936 
0937 err_enable:
0938     regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
0939     return ret;
0940 }
0941 
0942 static const struct snd_soc_component_driver soc_component_dev_wm8955 = {
0943     .probe          = wm8955_probe,
0944     .set_bias_level     = wm8955_set_bias_level,
0945     .controls       = wm8955_snd_controls,
0946     .num_controls       = ARRAY_SIZE(wm8955_snd_controls),
0947     .dapm_widgets       = wm8955_dapm_widgets,
0948     .num_dapm_widgets   = ARRAY_SIZE(wm8955_dapm_widgets),
0949     .dapm_routes        = wm8955_dapm_routes,
0950     .num_dapm_routes    = ARRAY_SIZE(wm8955_dapm_routes),
0951     .suspend_bias_off   = 1,
0952     .idle_bias_on       = 1,
0953     .use_pmdown_time    = 1,
0954     .endianness     = 1,
0955 };
0956 
0957 static const struct regmap_config wm8955_regmap = {
0958     .reg_bits = 7,
0959     .val_bits = 9,
0960 
0961     .max_register = WM8955_MAX_REGISTER,
0962     .volatile_reg = wm8955_volatile,
0963     .writeable_reg = wm8955_writeable,
0964 
0965     .cache_type = REGCACHE_RBTREE,
0966     .reg_defaults = wm8955_reg_defaults,
0967     .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults),
0968 };
0969 
0970 static int wm8955_i2c_probe(struct i2c_client *i2c)
0971 {
0972     struct wm8955_priv *wm8955;
0973     int ret;
0974 
0975     wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv),
0976                   GFP_KERNEL);
0977     if (wm8955 == NULL)
0978         return -ENOMEM;
0979 
0980     wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap);
0981     if (IS_ERR(wm8955->regmap)) {
0982         ret = PTR_ERR(wm8955->regmap);
0983         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
0984             ret);
0985         return ret;
0986     }
0987 
0988     i2c_set_clientdata(i2c, wm8955);
0989 
0990     ret = devm_snd_soc_register_component(&i2c->dev,
0991             &soc_component_dev_wm8955, &wm8955_dai, 1);
0992 
0993     return ret;
0994 }
0995 
0996 static const struct i2c_device_id wm8955_i2c_id[] = {
0997     { "wm8955", 0 },
0998     { }
0999 };
1000 MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1001 
1002 static struct i2c_driver wm8955_i2c_driver = {
1003     .driver = {
1004         .name = "wm8955",
1005     },
1006     .probe_new = wm8955_i2c_probe,
1007     .id_table = wm8955_i2c_id,
1008 };
1009 
1010 module_i2c_driver(wm8955_i2c_driver);
1011 
1012 MODULE_DESCRIPTION("ASoC WM8955 driver");
1013 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1014 MODULE_LICENSE("GPL");
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