soc/codecs/wm8940.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * wm8940.h -- WM8940 Soc Audio driver
0004  */
0005
0006 #ifndef _WM8940_H
0007 #define _WM8940_H
0008
0009 struct wm8940_setup_data {
0010     /* Vref to analogue output resistance */
0011 #define WM8940_VROI_1K 0
0012 #define WM8940_VROI_30K 1
0013     unsigned int vroi:1;
0014 };
0015
0016 /* WM8940 register space */
0017 #define WM8940_SOFTRESET    0x00
0018 #define WM8940_POWER1       0x01
0019 #define WM8940_POWER2       0x02
0020 #define WM8940_POWER3       0x03
0021 #define WM8940_IFACE        0x04
0022 #define WM8940_COMPANDINGCTL    0x05
0023 #define WM8940_CLOCK        0x06
0024 #define WM8940_ADDCNTRL     0x07
0025 #define WM8940_GPIO     0x08
0026 #define WM8940_CTLINT       0x09
0027 #define WM8940_DAC      0x0A
0028 #define WM8940_DACVOL       0x0B
0029
0030 #define WM8940_ADC      0x0E
0031 #define WM8940_ADCVOL       0x0F
0032 #define WM8940_NOTCH1       0x10
0033 #define WM8940_NOTCH2       0x11
0034 #define WM8940_NOTCH3       0x12
0035 #define WM8940_NOTCH4       0x13
0036 #define WM8940_NOTCH5       0x14
0037 #define WM8940_NOTCH6       0x15
0038 #define WM8940_NOTCH7       0x16
0039 #define WM8940_NOTCH8       0x17
0040 #define WM8940_DACLIM1      0x18
0041 #define WM8940_DACLIM2      0x19
0042
0043 #define WM8940_ALC1     0x20
0044 #define WM8940_ALC2     0x21
0045 #define WM8940_ALC3     0x22
0046 #define WM8940_NOISEGATE    0x23
0047 #define WM8940_PLLN     0x24
0048 #define WM8940_PLLK1        0x25
0049 #define WM8940_PLLK2        0x26
0050 #define WM8940_PLLK3        0x27
0051
0052 #define WM8940_ALC4     0x2A
0053
0054 #define WM8940_INPUTCTL     0x2C
0055 #define WM8940_PGAGAIN      0x2D
0056
0057 #define WM8940_ADCBOOST     0x2F
0058
0059 #define WM8940_OUTPUTCTL    0x31
0060 #define WM8940_SPKMIX       0x32
0061
0062 #define WM8940_SPKVOL       0x36
0063
0064 #define WM8940_MONOMIX      0x38
0065
0066 #define WM8940_CACHEREGNUM  0x57
0067
0068
0069 /* Clock divider Id's */
0070 #define WM8940_BCLKDIV 0
0071 #define WM8940_MCLKDIV 1
0072 #define WM8940_OPCLKDIV 2
0073
0074 /* MCLK clock dividers */
0075 #define WM8940_MCLKDIV_1    0
0076 #define WM8940_MCLKDIV_1_5  1
0077 #define WM8940_MCLKDIV_2    2
0078 #define WM8940_MCLKDIV_3    3
0079 #define WM8940_MCLKDIV_4    4
0080 #define WM8940_MCLKDIV_6    5
0081 #define WM8940_MCLKDIV_8    6
0082 #define WM8940_MCLKDIV_12   7
0083
0084 /* BCLK clock dividers */
0085 #define WM8940_BCLKDIV_1 0
0086 #define WM8940_BCLKDIV_2 1
0087 #define WM8940_BCLKDIV_4 2
0088 #define WM8940_BCLKDIV_8 3
0089 #define WM8940_BCLKDIV_16 4
0090 #define WM8940_BCLKDIV_32 5
0091
0092 /* PLL Out Dividers */
0093 #define WM8940_OPCLKDIV_1 0
0094 #define WM8940_OPCLKDIV_2 1
0095 #define WM8940_OPCLKDIV_3 2
0096 #define WM8940_OPCLKDIV_4 3
0097
0098 #endif /* _WM8940_H */
0099