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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8904.c  --  WM8904 ALSA SoC Audio driver
0004  *
0005  * Copyright 2009-12 Wolfson Microelectronics plc
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/module.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/i2c.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/consumer.h>
0018 #include <linux/slab.h>
0019 #include <sound/core.h>
0020 #include <sound/pcm.h>
0021 #include <sound/pcm_params.h>
0022 #include <sound/soc.h>
0023 #include <sound/initval.h>
0024 #include <sound/tlv.h>
0025 #include <sound/wm8904.h>
0026 
0027 #include "wm8904.h"
0028 
0029 enum wm8904_type {
0030     WM8904,
0031     WM8912,
0032 };
0033 
0034 #define WM8904_NUM_DCS_CHANNELS 4
0035 
0036 #define WM8904_NUM_SUPPLIES 5
0037 static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
0038     "DCVDD",
0039     "DBVDD",
0040     "AVDD",
0041     "CPVDD",
0042     "MICVDD",
0043 };
0044 
0045 /* codec private data */
0046 struct wm8904_priv {
0047     struct regmap *regmap;
0048     struct clk *mclk;
0049 
0050     enum wm8904_type devtype;
0051 
0052     struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
0053 
0054     struct wm8904_pdata *pdata;
0055 
0056     int deemph;
0057 
0058     /* Platform provided DRC configuration */
0059     const char **drc_texts;
0060     int drc_cfg;
0061     struct soc_enum drc_enum;
0062 
0063     /* Platform provided ReTune mobile configuration */
0064     int num_retune_mobile_texts;
0065     const char **retune_mobile_texts;
0066     int retune_mobile_cfg;
0067     struct soc_enum retune_mobile_enum;
0068 
0069     /* FLL setup */
0070     int fll_src;
0071     int fll_fref;
0072     int fll_fout;
0073 
0074     /* Clocking configuration */
0075     unsigned int mclk_rate;
0076     int sysclk_src;
0077     unsigned int sysclk_rate;
0078 
0079     int tdm_width;
0080     int tdm_slots;
0081     int bclk;
0082     int fs;
0083 
0084     /* DC servo configuration - cached offset values */
0085     int dcs_state[WM8904_NUM_DCS_CHANNELS];
0086 };
0087 
0088 static const struct reg_default wm8904_reg_defaults[] = {
0089     { 4,   0x0018 },     /* R4   - Bias Control 0 */
0090     { 5,   0x0000 },     /* R5   - VMID Control 0 */
0091     { 6,   0x0000 },     /* R6   - Mic Bias Control 0 */
0092     { 7,   0x0000 },     /* R7   - Mic Bias Control 1 */
0093     { 8,   0x0001 },     /* R8   - Analogue DAC 0 */
0094     { 9,   0x9696 },     /* R9   - mic Filter Control */
0095     { 10,  0x0001 },     /* R10  - Analogue ADC 0 */
0096     { 12,  0x0000 },     /* R12  - Power Management 0 */
0097     { 14,  0x0000 },     /* R14  - Power Management 2 */
0098     { 15,  0x0000 },     /* R15  - Power Management 3 */
0099     { 18,  0x0000 },     /* R18  - Power Management 6 */
0100     { 20,  0x945E },     /* R20  - Clock Rates 0 */
0101     { 21,  0x0C05 },     /* R21  - Clock Rates 1 */
0102     { 22,  0x0006 },     /* R22  - Clock Rates 2 */
0103     { 24,  0x0050 },     /* R24  - Audio Interface 0 */
0104     { 25,  0x000A },     /* R25  - Audio Interface 1 */
0105     { 26,  0x00E4 },     /* R26  - Audio Interface 2 */
0106     { 27,  0x0040 },     /* R27  - Audio Interface 3 */
0107     { 30,  0x00C0 },     /* R30  - DAC Digital Volume Left */
0108     { 31,  0x00C0 },     /* R31  - DAC Digital Volume Right */
0109     { 32,  0x0000 },     /* R32  - DAC Digital 0 */
0110     { 33,  0x0008 },     /* R33  - DAC Digital 1 */
0111     { 36,  0x00C0 },     /* R36  - ADC Digital Volume Left */
0112     { 37,  0x00C0 },     /* R37  - ADC Digital Volume Right */
0113     { 38,  0x0010 },     /* R38  - ADC Digital 0 */
0114     { 39,  0x0000 },     /* R39  - Digital Microphone 0 */
0115     { 40,  0x01AF },     /* R40  - DRC 0 */
0116     { 41,  0x3248 },     /* R41  - DRC 1 */
0117     { 42,  0x0000 },     /* R42  - DRC 2 */
0118     { 43,  0x0000 },     /* R43  - DRC 3 */
0119     { 44,  0x0085 },     /* R44  - Analogue Left Input 0 */
0120     { 45,  0x0085 },     /* R45  - Analogue Right Input 0 */
0121     { 46,  0x0044 },     /* R46  - Analogue Left Input 1 */
0122     { 47,  0x0044 },     /* R47  - Analogue Right Input 1 */
0123     { 57,  0x002D },     /* R57  - Analogue OUT1 Left */
0124     { 58,  0x002D },     /* R58  - Analogue OUT1 Right */
0125     { 59,  0x0039 },     /* R59  - Analogue OUT2 Left */
0126     { 60,  0x0039 },     /* R60  - Analogue OUT2 Right */
0127     { 61,  0x0000 },     /* R61  - Analogue OUT12 ZC */
0128     { 67,  0x0000 },     /* R67  - DC Servo 0 */
0129     { 69,  0xAAAA },     /* R69  - DC Servo 2 */
0130     { 71,  0xAAAA },     /* R71  - DC Servo 4 */
0131     { 72,  0xAAAA },     /* R72  - DC Servo 5 */
0132     { 90,  0x0000 },     /* R90  - Analogue HP 0 */
0133     { 94,  0x0000 },     /* R94  - Analogue Lineout 0 */
0134     { 98,  0x0000 },     /* R98  - Charge Pump 0 */
0135     { 104, 0x0004 },     /* R104 - Class W 0 */
0136     { 108, 0x0000 },     /* R108 - Write Sequencer 0 */
0137     { 109, 0x0000 },     /* R109 - Write Sequencer 1 */
0138     { 110, 0x0000 },     /* R110 - Write Sequencer 2 */
0139     { 111, 0x0000 },     /* R111 - Write Sequencer 3 */
0140     { 112, 0x0000 },     /* R112 - Write Sequencer 4 */
0141     { 116, 0x0000 },     /* R116 - FLL Control 1 */
0142     { 117, 0x0007 },     /* R117 - FLL Control 2 */
0143     { 118, 0x0000 },     /* R118 - FLL Control 3 */
0144     { 119, 0x2EE0 },     /* R119 - FLL Control 4 */
0145     { 120, 0x0004 },     /* R120 - FLL Control 5 */
0146     { 121, 0x0014 },     /* R121 - GPIO Control 1 */
0147     { 122, 0x0010 },     /* R122 - GPIO Control 2 */
0148     { 123, 0x0010 },     /* R123 - GPIO Control 3 */
0149     { 124, 0x0000 },     /* R124 - GPIO Control 4 */
0150     { 126, 0x0000 },     /* R126 - Digital Pulls */
0151     { 128, 0xFFFF },     /* R128 - Interrupt Status Mask */
0152     { 129, 0x0000 },     /* R129 - Interrupt Polarity */
0153     { 130, 0x0000 },     /* R130 - Interrupt Debounce */
0154     { 134, 0x0000 },     /* R134 - EQ1 */
0155     { 135, 0x000C },     /* R135 - EQ2 */
0156     { 136, 0x000C },     /* R136 - EQ3 */
0157     { 137, 0x000C },     /* R137 - EQ4 */
0158     { 138, 0x000C },     /* R138 - EQ5 */
0159     { 139, 0x000C },     /* R139 - EQ6 */
0160     { 140, 0x0FCA },     /* R140 - EQ7 */
0161     { 141, 0x0400 },     /* R141 - EQ8 */
0162     { 142, 0x00D8 },     /* R142 - EQ9 */
0163     { 143, 0x1EB5 },     /* R143 - EQ10 */
0164     { 144, 0xF145 },     /* R144 - EQ11 */
0165     { 145, 0x0B75 },     /* R145 - EQ12 */
0166     { 146, 0x01C5 },     /* R146 - EQ13 */
0167     { 147, 0x1C58 },     /* R147 - EQ14 */
0168     { 148, 0xF373 },     /* R148 - EQ15 */
0169     { 149, 0x0A54 },     /* R149 - EQ16 */
0170     { 150, 0x0558 },     /* R150 - EQ17 */
0171     { 151, 0x168E },     /* R151 - EQ18 */
0172     { 152, 0xF829 },     /* R152 - EQ19 */
0173     { 153, 0x07AD },     /* R153 - EQ20 */
0174     { 154, 0x1103 },     /* R154 - EQ21 */
0175     { 155, 0x0564 },     /* R155 - EQ22 */
0176     { 156, 0x0559 },     /* R156 - EQ23 */
0177     { 157, 0x4000 },     /* R157 - EQ24 */
0178     { 161, 0x0000 },     /* R161 - Control Interface Test 1 */
0179     { 204, 0x0000 },     /* R204 - Analogue Output Bias 0 */
0180     { 247, 0x0000 },     /* R247 - FLL NCO Test 0 */
0181     { 248, 0x0019 },     /* R248 - FLL NCO Test 1 */
0182 };
0183 
0184 static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
0185 {
0186     switch (reg) {
0187     case WM8904_SW_RESET_AND_ID:
0188     case WM8904_REVISION:
0189     case WM8904_DC_SERVO_1:
0190     case WM8904_DC_SERVO_6:
0191     case WM8904_DC_SERVO_7:
0192     case WM8904_DC_SERVO_8:
0193     case WM8904_DC_SERVO_9:
0194     case WM8904_DC_SERVO_READBACK_0:
0195     case WM8904_INTERRUPT_STATUS:
0196         return true;
0197     default:
0198         return false;
0199     }
0200 }
0201 
0202 static bool wm8904_readable_register(struct device *dev, unsigned int reg)
0203 {
0204     switch (reg) {
0205     case WM8904_SW_RESET_AND_ID:
0206     case WM8904_REVISION:
0207     case WM8904_BIAS_CONTROL_0:
0208     case WM8904_VMID_CONTROL_0:
0209     case WM8904_MIC_BIAS_CONTROL_0:
0210     case WM8904_MIC_BIAS_CONTROL_1:
0211     case WM8904_ANALOGUE_DAC_0:
0212     case WM8904_MIC_FILTER_CONTROL:
0213     case WM8904_ANALOGUE_ADC_0:
0214     case WM8904_POWER_MANAGEMENT_0:
0215     case WM8904_POWER_MANAGEMENT_2:
0216     case WM8904_POWER_MANAGEMENT_3:
0217     case WM8904_POWER_MANAGEMENT_6:
0218     case WM8904_CLOCK_RATES_0:
0219     case WM8904_CLOCK_RATES_1:
0220     case WM8904_CLOCK_RATES_2:
0221     case WM8904_AUDIO_INTERFACE_0:
0222     case WM8904_AUDIO_INTERFACE_1:
0223     case WM8904_AUDIO_INTERFACE_2:
0224     case WM8904_AUDIO_INTERFACE_3:
0225     case WM8904_DAC_DIGITAL_VOLUME_LEFT:
0226     case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
0227     case WM8904_DAC_DIGITAL_0:
0228     case WM8904_DAC_DIGITAL_1:
0229     case WM8904_ADC_DIGITAL_VOLUME_LEFT:
0230     case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
0231     case WM8904_ADC_DIGITAL_0:
0232     case WM8904_DIGITAL_MICROPHONE_0:
0233     case WM8904_DRC_0:
0234     case WM8904_DRC_1:
0235     case WM8904_DRC_2:
0236     case WM8904_DRC_3:
0237     case WM8904_ANALOGUE_LEFT_INPUT_0:
0238     case WM8904_ANALOGUE_RIGHT_INPUT_0:
0239     case WM8904_ANALOGUE_LEFT_INPUT_1:
0240     case WM8904_ANALOGUE_RIGHT_INPUT_1:
0241     case WM8904_ANALOGUE_OUT1_LEFT:
0242     case WM8904_ANALOGUE_OUT1_RIGHT:
0243     case WM8904_ANALOGUE_OUT2_LEFT:
0244     case WM8904_ANALOGUE_OUT2_RIGHT:
0245     case WM8904_ANALOGUE_OUT12_ZC:
0246     case WM8904_DC_SERVO_0:
0247     case WM8904_DC_SERVO_1:
0248     case WM8904_DC_SERVO_2:
0249     case WM8904_DC_SERVO_4:
0250     case WM8904_DC_SERVO_5:
0251     case WM8904_DC_SERVO_6:
0252     case WM8904_DC_SERVO_7:
0253     case WM8904_DC_SERVO_8:
0254     case WM8904_DC_SERVO_9:
0255     case WM8904_DC_SERVO_READBACK_0:
0256     case WM8904_ANALOGUE_HP_0:
0257     case WM8904_ANALOGUE_LINEOUT_0:
0258     case WM8904_CHARGE_PUMP_0:
0259     case WM8904_CLASS_W_0:
0260     case WM8904_WRITE_SEQUENCER_0:
0261     case WM8904_WRITE_SEQUENCER_1:
0262     case WM8904_WRITE_SEQUENCER_2:
0263     case WM8904_WRITE_SEQUENCER_3:
0264     case WM8904_WRITE_SEQUENCER_4:
0265     case WM8904_FLL_CONTROL_1:
0266     case WM8904_FLL_CONTROL_2:
0267     case WM8904_FLL_CONTROL_3:
0268     case WM8904_FLL_CONTROL_4:
0269     case WM8904_FLL_CONTROL_5:
0270     case WM8904_GPIO_CONTROL_1:
0271     case WM8904_GPIO_CONTROL_2:
0272     case WM8904_GPIO_CONTROL_3:
0273     case WM8904_GPIO_CONTROL_4:
0274     case WM8904_DIGITAL_PULLS:
0275     case WM8904_INTERRUPT_STATUS:
0276     case WM8904_INTERRUPT_STATUS_MASK:
0277     case WM8904_INTERRUPT_POLARITY:
0278     case WM8904_INTERRUPT_DEBOUNCE:
0279     case WM8904_EQ1:
0280     case WM8904_EQ2:
0281     case WM8904_EQ3:
0282     case WM8904_EQ4:
0283     case WM8904_EQ5:
0284     case WM8904_EQ6:
0285     case WM8904_EQ7:
0286     case WM8904_EQ8:
0287     case WM8904_EQ9:
0288     case WM8904_EQ10:
0289     case WM8904_EQ11:
0290     case WM8904_EQ12:
0291     case WM8904_EQ13:
0292     case WM8904_EQ14:
0293     case WM8904_EQ15:
0294     case WM8904_EQ16:
0295     case WM8904_EQ17:
0296     case WM8904_EQ18:
0297     case WM8904_EQ19:
0298     case WM8904_EQ20:
0299     case WM8904_EQ21:
0300     case WM8904_EQ22:
0301     case WM8904_EQ23:
0302     case WM8904_EQ24:
0303     case WM8904_CONTROL_INTERFACE_TEST_1:
0304     case WM8904_ADC_TEST_0:
0305     case WM8904_ANALOGUE_OUTPUT_BIAS_0:
0306     case WM8904_FLL_NCO_TEST_0:
0307     case WM8904_FLL_NCO_TEST_1:
0308         return true;
0309     default:
0310         return false;
0311     }
0312 }
0313 
0314 static int wm8904_configure_clocking(struct snd_soc_component *component)
0315 {
0316     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0317     unsigned int clock0, clock2, rate;
0318 
0319     /* Gate the clock while we're updating to avoid misclocking */
0320     clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
0321     snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
0322                 WM8904_SYSCLK_SRC, 0);
0323 
0324     /* This should be done on init() for bypass paths */
0325     switch (wm8904->sysclk_src) {
0326     case WM8904_CLK_MCLK:
0327         dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
0328 
0329         clock2 &= ~WM8904_SYSCLK_SRC;
0330         rate = wm8904->mclk_rate;
0331 
0332         /* Ensure the FLL is stopped */
0333         snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
0334                     WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
0335         break;
0336 
0337     case WM8904_CLK_FLL:
0338         dev_dbg(component->dev, "Using %dHz FLL clock\n",
0339             wm8904->fll_fout);
0340 
0341         clock2 |= WM8904_SYSCLK_SRC;
0342         rate = wm8904->fll_fout;
0343         break;
0344 
0345     default:
0346         dev_err(component->dev, "System clock not configured\n");
0347         return -EINVAL;
0348     }
0349 
0350     /* SYSCLK shouldn't be over 13.5MHz */
0351     if (rate > 13500000) {
0352         clock0 = WM8904_MCLK_DIV;
0353         wm8904->sysclk_rate = rate / 2;
0354     } else {
0355         clock0 = 0;
0356         wm8904->sysclk_rate = rate;
0357     }
0358 
0359     snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
0360                 clock0);
0361 
0362     snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
0363                 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
0364 
0365     dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
0366 
0367     return 0;
0368 }
0369 
0370 static void wm8904_set_drc(struct snd_soc_component *component)
0371 {
0372     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0373     struct wm8904_pdata *pdata = wm8904->pdata;
0374     int save, i;
0375 
0376     /* Save any enables; the configuration should clear them. */
0377     save = snd_soc_component_read(component, WM8904_DRC_0);
0378 
0379     for (i = 0; i < WM8904_DRC_REGS; i++)
0380         snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff,
0381                     pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
0382 
0383     /* Reenable the DRC */
0384     snd_soc_component_update_bits(component, WM8904_DRC_0,
0385                 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
0386 }
0387 
0388 static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
0389                    struct snd_ctl_elem_value *ucontrol)
0390 {
0391     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0392     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0393     struct wm8904_pdata *pdata = wm8904->pdata;
0394     int value = ucontrol->value.enumerated.item[0];
0395 
0396     if (value >= pdata->num_drc_cfgs)
0397         return -EINVAL;
0398 
0399     wm8904->drc_cfg = value;
0400 
0401     wm8904_set_drc(component);
0402 
0403     return 0;
0404 }
0405 
0406 static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
0407                    struct snd_ctl_elem_value *ucontrol)
0408 {
0409     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0410     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0411 
0412     ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
0413 
0414     return 0;
0415 }
0416 
0417 static void wm8904_set_retune_mobile(struct snd_soc_component *component)
0418 {
0419     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0420     struct wm8904_pdata *pdata = wm8904->pdata;
0421     int best, best_val, save, i, cfg;
0422 
0423     if (!pdata || !wm8904->num_retune_mobile_texts)
0424         return;
0425 
0426     /* Find the version of the currently selected configuration
0427      * with the nearest sample rate. */
0428     cfg = wm8904->retune_mobile_cfg;
0429     best = 0;
0430     best_val = INT_MAX;
0431     for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
0432         if (strcmp(pdata->retune_mobile_cfgs[i].name,
0433                wm8904->retune_mobile_texts[cfg]) == 0 &&
0434             abs(pdata->retune_mobile_cfgs[i].rate
0435             - wm8904->fs) < best_val) {
0436             best = i;
0437             best_val = abs(pdata->retune_mobile_cfgs[i].rate
0438                        - wm8904->fs);
0439         }
0440     }
0441 
0442     dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
0443         pdata->retune_mobile_cfgs[best].name,
0444         pdata->retune_mobile_cfgs[best].rate,
0445         wm8904->fs);
0446 
0447     /* The EQ will be disabled while reconfiguring it, remember the
0448      * current configuration. 
0449      */
0450     save = snd_soc_component_read(component, WM8904_EQ1);
0451 
0452     for (i = 0; i < WM8904_EQ_REGS; i++)
0453         snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff,
0454                 pdata->retune_mobile_cfgs[best].regs[i]);
0455 
0456     snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save);
0457 }
0458 
0459 static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
0460                      struct snd_ctl_elem_value *ucontrol)
0461 {
0462     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0463     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0464     struct wm8904_pdata *pdata = wm8904->pdata;
0465     int value = ucontrol->value.enumerated.item[0];
0466 
0467     if (value >= pdata->num_retune_mobile_cfgs)
0468         return -EINVAL;
0469 
0470     wm8904->retune_mobile_cfg = value;
0471 
0472     wm8904_set_retune_mobile(component);
0473 
0474     return 0;
0475 }
0476 
0477 static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
0478                      struct snd_ctl_elem_value *ucontrol)
0479 {
0480     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0481     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0482 
0483     ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
0484 
0485     return 0;
0486 }
0487 
0488 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
0489 
0490 static int wm8904_set_deemph(struct snd_soc_component *component)
0491 {
0492     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0493     int val, i, best;
0494 
0495     /* If we're using deemphasis select the nearest available sample 
0496      * rate.
0497      */
0498     if (wm8904->deemph) {
0499         best = 1;
0500         for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
0501             if (abs(deemph_settings[i] - wm8904->fs) <
0502                 abs(deemph_settings[best] - wm8904->fs))
0503                 best = i;
0504         }
0505 
0506         val = best << WM8904_DEEMPH_SHIFT;
0507     } else {
0508         val = 0;
0509     }
0510 
0511     dev_dbg(component->dev, "Set deemphasis %d\n", val);
0512 
0513     return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
0514                    WM8904_DEEMPH_MASK, val);
0515 }
0516 
0517 static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
0518                  struct snd_ctl_elem_value *ucontrol)
0519 {
0520     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0521     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0522 
0523     ucontrol->value.integer.value[0] = wm8904->deemph;
0524     return 0;
0525 }
0526 
0527 static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
0528                   struct snd_ctl_elem_value *ucontrol)
0529 {
0530     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0531     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0532     unsigned int deemph = ucontrol->value.integer.value[0];
0533 
0534     if (deemph > 1)
0535         return -EINVAL;
0536 
0537     wm8904->deemph = deemph;
0538 
0539     return wm8904_set_deemph(component);
0540 }
0541 
0542 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
0543 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
0544 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
0545 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
0546 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0547 
0548 static const char *hpf_mode_text[] = {
0549     "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
0550 };
0551 
0552 static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
0553                 hpf_mode_text);
0554 
0555 static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
0556                   struct snd_ctl_elem_value *ucontrol)
0557 {
0558     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0559     unsigned int val;
0560     int ret;
0561 
0562     ret = snd_soc_put_volsw(kcontrol, ucontrol);
0563     if (ret < 0)
0564         return ret;
0565 
0566     if (ucontrol->value.integer.value[0])
0567         val = 0;
0568     else
0569         val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
0570 
0571     snd_soc_component_update_bits(component, WM8904_ADC_TEST_0,
0572                 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
0573                 val);
0574 
0575     return ret;
0576 }
0577 
0578 static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
0579 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
0580          WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
0581 
0582 /* No TLV since it depends on mode */
0583 SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
0584          WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
0585 SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
0586          WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
0587 
0588 SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
0589 SOC_ENUM("High Pass Filter Mode", hpf_mode),
0590 SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
0591     snd_soc_get_volsw, wm8904_adc_osr_put),
0592 };
0593 
0594 static const char *drc_path_text[] = {
0595     "ADC", "DAC"
0596 };
0597 
0598 static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
0599 
0600 static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
0601 SOC_SINGLE_TLV("Digital Playback Boost Volume", 
0602            WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
0603 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
0604          WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
0605 
0606 SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
0607          WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
0608 SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
0609          WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
0610 SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
0611          WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
0612 
0613 SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
0614          WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
0615 SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
0616          WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
0617 SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
0618          WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
0619 
0620 SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
0621 SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
0622 SOC_ENUM("DRC Path", drc_path),
0623 SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
0624 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
0625             wm8904_get_deemph, wm8904_put_deemph),
0626 };
0627 
0628 static const struct snd_kcontrol_new wm8904_snd_controls[] = {
0629 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
0630            sidetone_tlv),
0631 };
0632 
0633 static const struct snd_kcontrol_new wm8904_eq_controls[] = {
0634 SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
0635 SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
0636 SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
0637 SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
0638 SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
0639 };
0640 
0641 static int cp_event(struct snd_soc_dapm_widget *w,
0642             struct snd_kcontrol *kcontrol, int event)
0643 {
0644     if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
0645         return -EINVAL;
0646 
0647     /* Maximum startup time */
0648     udelay(500);
0649 
0650     return 0;
0651 }
0652 
0653 static int sysclk_event(struct snd_soc_dapm_widget *w,
0654              struct snd_kcontrol *kcontrol, int event)
0655 {
0656     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0657     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0658 
0659     switch (event) {
0660     case SND_SOC_DAPM_PRE_PMU:
0661         /* If we're using the FLL then we only start it when
0662          * required; we assume that the configuration has been
0663          * done previously and all we need to do is kick it
0664          * off.
0665          */
0666         switch (wm8904->sysclk_src) {
0667         case WM8904_CLK_FLL:
0668             snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
0669                         WM8904_FLL_OSC_ENA,
0670                         WM8904_FLL_OSC_ENA);
0671 
0672             snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
0673                         WM8904_FLL_ENA,
0674                         WM8904_FLL_ENA);
0675             break;
0676 
0677         default:
0678             break;
0679         }
0680         break;
0681 
0682     case SND_SOC_DAPM_POST_PMD:
0683         snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
0684                     WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
0685         break;
0686     }
0687 
0688     return 0;
0689 }
0690 
0691 static int out_pga_event(struct snd_soc_dapm_widget *w,
0692              struct snd_kcontrol *kcontrol, int event)
0693 {
0694     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0695     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
0696     int reg, val;
0697     int dcs_mask;
0698     int dcs_l, dcs_r;
0699     int dcs_l_reg, dcs_r_reg;
0700     int timeout;
0701     int pwr_reg;
0702 
0703     /* This code is shared between HP and LINEOUT; we do all our
0704      * power management in stereo pairs to avoid latency issues so
0705      * we reuse shift to identify which rather than strcmp() the
0706      * name. */
0707     reg = w->shift;
0708 
0709     switch (reg) {
0710     case WM8904_ANALOGUE_HP_0:
0711         pwr_reg = WM8904_POWER_MANAGEMENT_2;
0712         dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
0713         dcs_r_reg = WM8904_DC_SERVO_8;
0714         dcs_l_reg = WM8904_DC_SERVO_9;
0715         dcs_l = 0;
0716         dcs_r = 1;
0717         break;
0718     case WM8904_ANALOGUE_LINEOUT_0:
0719         pwr_reg = WM8904_POWER_MANAGEMENT_3;
0720         dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
0721         dcs_r_reg = WM8904_DC_SERVO_6;
0722         dcs_l_reg = WM8904_DC_SERVO_7;
0723         dcs_l = 2;
0724         dcs_r = 3;
0725         break;
0726     default:
0727         WARN(1, "Invalid reg %d\n", reg);
0728         return -EINVAL;
0729     }
0730 
0731     switch (event) {
0732     case SND_SOC_DAPM_PRE_PMU:
0733         /* Power on the PGAs */
0734         snd_soc_component_update_bits(component, pwr_reg,
0735                     WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
0736                     WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
0737 
0738         /* Power on the amplifier */
0739         snd_soc_component_update_bits(component, reg,
0740                     WM8904_HPL_ENA | WM8904_HPR_ENA,
0741                     WM8904_HPL_ENA | WM8904_HPR_ENA);
0742 
0743 
0744         /* Enable the first stage */
0745         snd_soc_component_update_bits(component, reg,
0746                     WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
0747                     WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
0748 
0749         /* Power up the DC servo */
0750         snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
0751                     dcs_mask, dcs_mask);
0752 
0753         /* Either calibrate the DC servo or restore cached state
0754          * if we have that.
0755          */
0756         if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
0757             dev_dbg(component->dev, "Restoring DC servo state\n");
0758 
0759             snd_soc_component_write(component, dcs_l_reg,
0760                       wm8904->dcs_state[dcs_l]);
0761             snd_soc_component_write(component, dcs_r_reg,
0762                       wm8904->dcs_state[dcs_r]);
0763 
0764             snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask);
0765 
0766             timeout = 20;
0767         } else {
0768             dev_dbg(component->dev, "Calibrating DC servo\n");
0769 
0770             snd_soc_component_write(component, WM8904_DC_SERVO_1,
0771                 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
0772 
0773             timeout = 500;
0774         }
0775 
0776         /* Wait for DC servo to complete */
0777         dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
0778         do {
0779             val = snd_soc_component_read(component, WM8904_DC_SERVO_READBACK_0);
0780             if ((val & dcs_mask) == dcs_mask)
0781                 break;
0782 
0783             msleep(1);
0784         } while (--timeout);
0785 
0786         if ((val & dcs_mask) != dcs_mask)
0787             dev_warn(component->dev, "DC servo timed out\n");
0788         else
0789             dev_dbg(component->dev, "DC servo ready\n");
0790 
0791         /* Enable the output stage */
0792         snd_soc_component_update_bits(component, reg,
0793                     WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
0794                     WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
0795         break;
0796 
0797     case SND_SOC_DAPM_POST_PMU:
0798         /* Unshort the output itself */
0799         snd_soc_component_update_bits(component, reg,
0800                     WM8904_HPL_RMV_SHORT |
0801                     WM8904_HPR_RMV_SHORT,
0802                     WM8904_HPL_RMV_SHORT |
0803                     WM8904_HPR_RMV_SHORT);
0804 
0805         break;
0806 
0807     case SND_SOC_DAPM_PRE_PMD:
0808         /* Short the output */
0809         snd_soc_component_update_bits(component, reg,
0810                     WM8904_HPL_RMV_SHORT |
0811                     WM8904_HPR_RMV_SHORT, 0);
0812         break;
0813 
0814     case SND_SOC_DAPM_POST_PMD:
0815         /* Cache the DC servo configuration; this will be
0816          * invalidated if we change the configuration. */
0817         wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg);
0818         wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg);
0819 
0820         snd_soc_component_update_bits(component, WM8904_DC_SERVO_0,
0821                     dcs_mask, 0);
0822 
0823         /* Disable the amplifier input and output stages */
0824         snd_soc_component_update_bits(component, reg,
0825                     WM8904_HPL_ENA | WM8904_HPR_ENA |
0826                     WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
0827                     WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
0828                     0);
0829 
0830         /* PGAs too */
0831         snd_soc_component_update_bits(component, pwr_reg,
0832                     WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
0833                     0);
0834         break;
0835     }
0836 
0837     return 0;
0838 }
0839 
0840 static const char *input_mode_text[] = {
0841     "Single-Ended", "Differential Line", "Differential Mic"
0842 };
0843 
0844 static const char *lin_text[] = {
0845     "IN1L", "IN2L", "IN3L"
0846 };
0847 
0848 static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
0849                 lin_text);
0850 
0851 static const struct snd_kcontrol_new lin_mux =
0852     SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
0853 
0854 static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
0855                 lin_text);
0856 
0857 static const struct snd_kcontrol_new lin_inv_mux =
0858     SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum);
0859 
0860 static SOC_ENUM_SINGLE_DECL(lin_mode_enum,
0861                 WM8904_ANALOGUE_LEFT_INPUT_1, 0,
0862                 input_mode_text);
0863 
0864 static const struct snd_kcontrol_new lin_mode =
0865     SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum);
0866 
0867 static const char *rin_text[] = {
0868     "IN1R", "IN2R", "IN3R"
0869 };
0870 
0871 static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
0872                 rin_text);
0873 
0874 static const struct snd_kcontrol_new rin_mux =
0875     SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
0876 
0877 static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
0878                 rin_text);
0879 
0880 static const struct snd_kcontrol_new rin_inv_mux =
0881     SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum);
0882 
0883 static SOC_ENUM_SINGLE_DECL(rin_mode_enum,
0884                 WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
0885                 input_mode_text);
0886 
0887 static const struct snd_kcontrol_new rin_mode =
0888     SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum);
0889 
0890 static const char *aif_text[] = {
0891     "Left", "Right"
0892 };
0893 
0894 static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
0895                 aif_text);
0896 
0897 static const struct snd_kcontrol_new aifoutl_mux =
0898     SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
0899 
0900 static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
0901                 aif_text);
0902 
0903 static const struct snd_kcontrol_new aifoutr_mux =
0904     SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
0905 
0906 static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
0907                 aif_text);
0908 
0909 static const struct snd_kcontrol_new aifinl_mux =
0910     SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
0911 
0912 static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
0913                 aif_text);
0914 
0915 static const struct snd_kcontrol_new aifinr_mux =
0916     SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
0917 
0918 static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
0919 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
0920             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0921 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
0922 SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
0923 };
0924 
0925 static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
0926 SND_SOC_DAPM_INPUT("IN1L"),
0927 SND_SOC_DAPM_INPUT("IN1R"),
0928 SND_SOC_DAPM_INPUT("IN2L"),
0929 SND_SOC_DAPM_INPUT("IN2R"),
0930 SND_SOC_DAPM_INPUT("IN3L"),
0931 SND_SOC_DAPM_INPUT("IN3R"),
0932 
0933 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
0934 
0935 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
0936 SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
0937          &lin_inv_mux),
0938 SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode),
0939 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
0940 SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
0941          &rin_inv_mux),
0942 SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode),
0943 
0944 SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
0945          NULL, 0),
0946 SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
0947          NULL, 0),
0948 
0949 SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
0950 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
0951 
0952 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
0953 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
0954 
0955 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
0956 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
0957 };
0958 
0959 static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
0960 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
0961 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
0962 
0963 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
0964 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
0965 
0966 SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
0967 SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
0968 
0969 SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
0970             SND_SOC_DAPM_POST_PMU),
0971 
0972 SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
0973 SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
0974 
0975 SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
0976 SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
0977 
0978 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
0979            0, NULL, 0, out_pga_event,
0980            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0981            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0982 SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
0983            0, NULL, 0, out_pga_event,
0984            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0985            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0986 
0987 SND_SOC_DAPM_OUTPUT("HPOUTL"),
0988 SND_SOC_DAPM_OUTPUT("HPOUTR"),
0989 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
0990 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
0991 };
0992 
0993 static const char *out_mux_text[] = {
0994     "DAC", "Bypass"
0995 };
0996 
0997 static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
0998                 out_mux_text);
0999 
1000 static const struct snd_kcontrol_new hpl_mux =
1001     SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1002 
1003 static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
1004                 out_mux_text);
1005 
1006 static const struct snd_kcontrol_new hpr_mux =
1007     SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1008 
1009 static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
1010                 out_mux_text);
1011 
1012 static const struct snd_kcontrol_new linel_mux =
1013     SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1014 
1015 static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
1016                 out_mux_text);
1017 
1018 static const struct snd_kcontrol_new liner_mux =
1019     SOC_DAPM_ENUM("LINER Mux", liner_enum);
1020 
1021 static const char *sidetone_text[] = {
1022     "None", "Left", "Right"
1023 };
1024 
1025 static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
1026                 sidetone_text);
1027 
1028 static const struct snd_kcontrol_new dacl_sidetone_mux =
1029     SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1030 
1031 static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
1032                 sidetone_text);
1033 
1034 static const struct snd_kcontrol_new dacr_sidetone_mux =
1035     SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1036 
1037 static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1038 SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1039 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1040 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1041 
1042 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1043 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1044 
1045 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1046 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1047 SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1048 SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1049 };
1050 
1051 static const struct snd_soc_dapm_route core_intercon[] = {
1052     { "CLK_DSP", NULL, "SYSCLK" },
1053     { "TOCLK", NULL, "SYSCLK" },
1054 };
1055 
1056 static const struct snd_soc_dapm_route adc_intercon[] = {
1057     { "Left Capture Mux", "IN1L", "IN1L" },
1058     { "Left Capture Mux", "IN2L", "IN2L" },
1059     { "Left Capture Mux", "IN3L", "IN3L" },
1060 
1061     { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1062     { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1063     { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1064 
1065     { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" },
1066     { "Left Capture Mode", "Differential Line", "Left Capture Mux" },
1067     { "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" },
1068     { "Left Capture Mode", "Differential Mic", "Left Capture Mux" },
1069     { "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" },
1070 
1071     { "Right Capture Mux", "IN1R", "IN1R" },
1072     { "Right Capture Mux", "IN2R", "IN2R" },
1073     { "Right Capture Mux", "IN3R", "IN3R" },
1074 
1075     { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1076     { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1077     { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1078 
1079     { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" },
1080     { "Right Capture Mode", "Differential Line", "Right Capture Mux" },
1081     { "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" },
1082     { "Right Capture Mode", "Differential Mic", "Right Capture Mux" },
1083     { "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" },
1084 
1085     { "Left Capture PGA", NULL, "Left Capture Mode" },
1086     { "Right Capture PGA", NULL, "Right Capture Mode" },
1087 
1088     { "AIFOUTL Mux", "Left", "ADCL" },
1089     { "AIFOUTL Mux", "Right", "ADCR" },
1090     { "AIFOUTR Mux", "Left", "ADCL" },
1091     { "AIFOUTR Mux", "Right", "ADCR" },
1092 
1093     { "AIFOUTL", NULL, "AIFOUTL Mux" },
1094     { "AIFOUTR", NULL, "AIFOUTR Mux" },
1095 
1096     { "ADCL", NULL, "CLK_DSP" },
1097     { "ADCL", NULL, "Left Capture PGA" },
1098 
1099     { "ADCR", NULL, "CLK_DSP" },
1100     { "ADCR", NULL, "Right Capture PGA" },
1101 };
1102 
1103 static const struct snd_soc_dapm_route dac_intercon[] = {
1104     { "DACL Mux", "Left", "AIFINL" },
1105     { "DACL Mux", "Right", "AIFINR" },
1106 
1107     { "DACR Mux", "Left", "AIFINL" },
1108     { "DACR Mux", "Right", "AIFINR" },
1109 
1110     { "DACL", NULL, "DACL Mux" },
1111     { "DACL", NULL, "CLK_DSP" },
1112 
1113     { "DACR", NULL, "DACR Mux" },
1114     { "DACR", NULL, "CLK_DSP" },
1115 
1116     { "Charge pump", NULL, "SYSCLK" },
1117 
1118     { "Headphone Output", NULL, "HPL PGA" },
1119     { "Headphone Output", NULL, "HPR PGA" },
1120     { "Headphone Output", NULL, "Charge pump" },
1121     { "Headphone Output", NULL, "TOCLK" },
1122 
1123     { "Line Output", NULL, "LINEL PGA" },
1124     { "Line Output", NULL, "LINER PGA" },
1125     { "Line Output", NULL, "Charge pump" },
1126     { "Line Output", NULL, "TOCLK" },
1127 
1128     { "HPOUTL", NULL, "Headphone Output" },
1129     { "HPOUTR", NULL, "Headphone Output" },
1130 
1131     { "LINEOUTL", NULL, "Line Output" },
1132     { "LINEOUTR", NULL, "Line Output" },
1133 };
1134 
1135 static const struct snd_soc_dapm_route wm8904_intercon[] = {
1136     { "Left Sidetone", "Left", "ADCL" },
1137     { "Left Sidetone", "Right", "ADCR" },
1138     { "DACL", NULL, "Left Sidetone" },
1139     
1140     { "Right Sidetone", "Left", "ADCL" },
1141     { "Right Sidetone", "Right", "ADCR" },
1142     { "DACR", NULL, "Right Sidetone" },
1143 
1144     { "Left Bypass", NULL, "Class G" },
1145     { "Left Bypass", NULL, "Left Capture PGA" },
1146 
1147     { "Right Bypass", NULL, "Class G" },
1148     { "Right Bypass", NULL, "Right Capture PGA" },
1149 
1150     { "HPL Mux", "DAC", "DACL" },
1151     { "HPL Mux", "Bypass", "Left Bypass" },
1152 
1153     { "HPR Mux", "DAC", "DACR" },
1154     { "HPR Mux", "Bypass", "Right Bypass" },
1155 
1156     { "LINEL Mux", "DAC", "DACL" },
1157     { "LINEL Mux", "Bypass", "Left Bypass" },
1158 
1159     { "LINER Mux", "DAC", "DACR" },
1160     { "LINER Mux", "Bypass", "Right Bypass" },
1161 
1162     { "HPL PGA", NULL, "HPL Mux" },
1163     { "HPR PGA", NULL, "HPR Mux" },
1164 
1165     { "LINEL PGA", NULL, "LINEL Mux" },
1166     { "LINER PGA", NULL, "LINER Mux" },
1167 };
1168 
1169 static const struct snd_soc_dapm_route wm8912_intercon[] = {
1170     { "HPL PGA", NULL, "DACL" },
1171     { "HPR PGA", NULL, "DACR" },
1172 
1173     { "LINEL PGA", NULL, "DACL" },
1174     { "LINER PGA", NULL, "DACR" },
1175 };
1176 
1177 static int wm8904_add_widgets(struct snd_soc_component *component)
1178 {
1179     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1180     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1181 
1182     snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
1183                   ARRAY_SIZE(wm8904_core_dapm_widgets));
1184     snd_soc_dapm_add_routes(dapm, core_intercon,
1185                 ARRAY_SIZE(core_intercon));
1186 
1187     switch (wm8904->devtype) {
1188     case WM8904:
1189         snd_soc_add_component_controls(component, wm8904_adc_snd_controls,
1190                      ARRAY_SIZE(wm8904_adc_snd_controls));
1191         snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
1192                      ARRAY_SIZE(wm8904_dac_snd_controls));
1193         snd_soc_add_component_controls(component, wm8904_snd_controls,
1194                      ARRAY_SIZE(wm8904_snd_controls));
1195 
1196         snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1197                       ARRAY_SIZE(wm8904_adc_dapm_widgets));
1198         snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1199                       ARRAY_SIZE(wm8904_dac_dapm_widgets));
1200         snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1201                       ARRAY_SIZE(wm8904_dapm_widgets));
1202 
1203         snd_soc_dapm_add_routes(dapm, adc_intercon,
1204                     ARRAY_SIZE(adc_intercon));
1205         snd_soc_dapm_add_routes(dapm, dac_intercon,
1206                     ARRAY_SIZE(dac_intercon));
1207         snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1208                     ARRAY_SIZE(wm8904_intercon));
1209         break;
1210 
1211     case WM8912:
1212         snd_soc_add_component_controls(component, wm8904_dac_snd_controls,
1213                      ARRAY_SIZE(wm8904_dac_snd_controls));
1214 
1215         snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1216                       ARRAY_SIZE(wm8904_dac_dapm_widgets));
1217 
1218         snd_soc_dapm_add_routes(dapm, dac_intercon,
1219                     ARRAY_SIZE(dac_intercon));
1220         snd_soc_dapm_add_routes(dapm, wm8912_intercon,
1221                     ARRAY_SIZE(wm8912_intercon));
1222         break;
1223     }
1224 
1225     return 0;
1226 }
1227 
1228 static struct {
1229     int ratio;
1230     unsigned int clk_sys_rate;
1231 } clk_sys_rates[] = {
1232     {   64,  0 },
1233     {  128,  1 },
1234     {  192,  2 },
1235     {  256,  3 },
1236     {  384,  4 },
1237     {  512,  5 },
1238     {  786,  6 },
1239     { 1024,  7 },
1240     { 1408,  8 },
1241     { 1536,  9 },
1242 };
1243 
1244 static struct {
1245     int rate;
1246     int sample_rate;
1247 } sample_rates[] = {
1248     { 8000,  0  },
1249     { 11025, 1  },
1250     { 12000, 1  },
1251     { 16000, 2  },
1252     { 22050, 3  },
1253     { 24000, 3  },
1254     { 32000, 4  },
1255     { 44100, 5  },
1256     { 48000, 5  },
1257 };
1258 
1259 static struct {
1260     int div; /* *10 due to .5s */
1261     int bclk_div;
1262 } bclk_divs[] = {
1263     { 10,  0  },
1264     { 15,  1  },
1265     { 20,  2  },
1266     { 30,  3  },
1267     { 40,  4  },
1268     { 50,  5  },
1269     { 55,  6  },
1270     { 60,  7  },
1271     { 80,  8  },
1272     { 100, 9  },
1273     { 110, 10 },
1274     { 120, 11 },
1275     { 160, 12 },
1276     { 200, 13 },
1277     { 220, 14 },
1278     { 240, 16 },
1279     { 200, 17 },
1280     { 320, 18 },
1281     { 440, 19 },
1282     { 480, 20 },
1283 };
1284 
1285 
1286 static int wm8904_hw_params(struct snd_pcm_substream *substream,
1287                 struct snd_pcm_hw_params *params,
1288                 struct snd_soc_dai *dai)
1289 {
1290     struct snd_soc_component *component = dai->component;
1291     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1292     int ret, i, best, best_val, cur_val;
1293     unsigned int aif1 = 0;
1294     unsigned int aif2 = 0;
1295     unsigned int aif3 = 0;
1296     unsigned int clock1 = 0;
1297     unsigned int dac_digital1 = 0;
1298 
1299     /* What BCLK do we need? */
1300     wm8904->fs = params_rate(params);
1301     if (wm8904->tdm_slots) {
1302         dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1303             wm8904->tdm_slots, wm8904->tdm_width);
1304         wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1305                          wm8904->tdm_width, 2,
1306                          wm8904->tdm_slots);
1307     } else {
1308         wm8904->bclk = snd_soc_params_to_bclk(params);
1309     }
1310 
1311     switch (params_width(params)) {
1312     case 16:
1313         break;
1314     case 20:
1315         aif1 |= 0x40;
1316         break;
1317     case 24:
1318         aif1 |= 0x80;
1319         break;
1320     case 32:
1321         aif1 |= 0xc0;
1322         break;
1323     default:
1324         return -EINVAL;
1325     }
1326 
1327 
1328     dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1329 
1330     ret = wm8904_configure_clocking(component);
1331     if (ret != 0)
1332         return ret;
1333 
1334     /* Select nearest CLK_SYS_RATE */
1335     best = 0;
1336     best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1337                - wm8904->fs);
1338     for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1339         cur_val = abs((wm8904->sysclk_rate /
1340                    clk_sys_rates[i].ratio) - wm8904->fs);
1341         if (cur_val < best_val) {
1342             best = i;
1343             best_val = cur_val;
1344         }
1345     }
1346     dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1347         clk_sys_rates[best].ratio);
1348     clock1 |= (clk_sys_rates[best].clk_sys_rate
1349            << WM8904_CLK_SYS_RATE_SHIFT);
1350 
1351     /* SAMPLE_RATE */
1352     best = 0;
1353     best_val = abs(wm8904->fs - sample_rates[0].rate);
1354     for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1355         /* Closest match */
1356         cur_val = abs(wm8904->fs - sample_rates[i].rate);
1357         if (cur_val < best_val) {
1358             best = i;
1359             best_val = cur_val;
1360         }
1361     }
1362     dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1363         sample_rates[best].rate);
1364     clock1 |= (sample_rates[best].sample_rate
1365            << WM8904_SAMPLE_RATE_SHIFT);
1366 
1367     /* Enable sloping stopband filter for low sample rates */
1368     if (wm8904->fs <= 24000)
1369         dac_digital1 |= WM8904_DAC_SB_FILT;
1370 
1371     /* BCLK_DIV */
1372     best = 0;
1373     best_val = INT_MAX;
1374     for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1375         cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1376             - wm8904->bclk;
1377         if (cur_val < 0) /* Table is sorted */
1378             break;
1379         if (cur_val < best_val) {
1380             best = i;
1381             best_val = cur_val;
1382         }
1383     }
1384     wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1385     dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1386         bclk_divs[best].div, wm8904->bclk);
1387     aif2 |= bclk_divs[best].bclk_div;
1388 
1389     /* LRCLK is a simple fraction of BCLK */
1390     dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1391     aif3 |= wm8904->bclk / wm8904->fs;
1392 
1393     /* Apply the settings */
1394     snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1,
1395                 WM8904_DAC_SB_FILT, dac_digital1);
1396     snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1397                 WM8904_AIF_WL_MASK, aif1);
1398     snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2,
1399                 WM8904_BCLK_DIV_MASK, aif2);
1400     snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
1401                 WM8904_LRCLK_RATE_MASK, aif3);
1402     snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1,
1403                 WM8904_SAMPLE_RATE_MASK |
1404                 WM8904_CLK_SYS_RATE_MASK, clock1);
1405 
1406     /* Update filters for the new settings */
1407     wm8904_set_retune_mobile(component);
1408     wm8904_set_deemph(component);
1409 
1410     return 0;
1411 }
1412 
1413 static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1414 {
1415     struct snd_soc_component *component = dai->component;
1416     unsigned int aif1 = 0;
1417     unsigned int aif3 = 0;
1418 
1419     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1420     case SND_SOC_DAIFMT_CBS_CFS:
1421         break;
1422     case SND_SOC_DAIFMT_CBS_CFM:
1423         aif3 |= WM8904_LRCLK_DIR;
1424         break;
1425     case SND_SOC_DAIFMT_CBM_CFS:
1426         aif1 |= WM8904_BCLK_DIR;
1427         break;
1428     case SND_SOC_DAIFMT_CBM_CFM:
1429         aif1 |= WM8904_BCLK_DIR;
1430         aif3 |= WM8904_LRCLK_DIR;
1431         break;
1432     default:
1433         return -EINVAL;
1434     }
1435 
1436     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1437     case SND_SOC_DAIFMT_DSP_B:
1438         aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
1439         fallthrough;
1440     case SND_SOC_DAIFMT_DSP_A:
1441         aif1 |= 0x3;
1442         break;
1443     case SND_SOC_DAIFMT_I2S:
1444         aif1 |= 0x2;
1445         break;
1446     case SND_SOC_DAIFMT_RIGHT_J:
1447         break;
1448     case SND_SOC_DAIFMT_LEFT_J:
1449         aif1 |= 0x1;
1450         break;
1451     default:
1452         return -EINVAL;
1453     }
1454 
1455     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1456     case SND_SOC_DAIFMT_DSP_A:
1457     case SND_SOC_DAIFMT_DSP_B:
1458         /* frame inversion not valid for DSP modes */
1459         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1460         case SND_SOC_DAIFMT_NB_NF:
1461             break;
1462         case SND_SOC_DAIFMT_IB_NF:
1463             aif1 |= WM8904_AIF_BCLK_INV;
1464             break;
1465         default:
1466             return -EINVAL;
1467         }
1468         break;
1469 
1470     case SND_SOC_DAIFMT_I2S:
1471     case SND_SOC_DAIFMT_RIGHT_J:
1472     case SND_SOC_DAIFMT_LEFT_J:
1473         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1474         case SND_SOC_DAIFMT_NB_NF:
1475             break;
1476         case SND_SOC_DAIFMT_IB_IF:
1477             aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1478             break;
1479         case SND_SOC_DAIFMT_IB_NF:
1480             aif1 |= WM8904_AIF_BCLK_INV;
1481             break;
1482         case SND_SOC_DAIFMT_NB_IF:
1483             aif1 |= WM8904_AIF_LRCLK_INV;
1484             break;
1485         default:
1486             return -EINVAL;
1487         }
1488         break;
1489     default:
1490         return -EINVAL;
1491     }
1492 
1493     snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1494                 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1495                 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1496     snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3,
1497                 WM8904_LRCLK_DIR, aif3);
1498 
1499     return 0;
1500 }
1501 
1502 
1503 static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1504                    unsigned int rx_mask, int slots, int slot_width)
1505 {
1506     struct snd_soc_component *component = dai->component;
1507     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1508     int aif1 = 0;
1509 
1510     /* Don't need to validate anything if we're turning off TDM */
1511     if (slots == 0)
1512         goto out;
1513 
1514     /* Note that we allow configurations we can't handle ourselves - 
1515      * for example, we can generate clocks for slots 2 and up even if
1516      * we can't use those slots ourselves.
1517      */
1518     aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1519 
1520     switch (rx_mask) {
1521     case 3:
1522         break;
1523     case 0xc:
1524         aif1 |= WM8904_AIFADC_TDM_CHAN;
1525         break;
1526     default:
1527         return -EINVAL;
1528     }
1529 
1530 
1531     switch (tx_mask) {
1532     case 3:
1533         break;
1534     case 0xc:
1535         aif1 |= WM8904_AIFDAC_TDM_CHAN;
1536         break;
1537     default:
1538         return -EINVAL;
1539     }
1540 
1541 out:
1542     wm8904->tdm_width = slot_width;
1543     wm8904->tdm_slots = slots / 2;
1544 
1545     snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1,
1546                 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1547                 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1548 
1549     return 0;
1550 }
1551 
1552 struct _fll_div {
1553     u16 fll_fratio;
1554     u16 fll_outdiv;
1555     u16 fll_clk_ref_div;
1556     u16 n;
1557     u16 k;
1558 };
1559 
1560 /* The size in bits of the FLL divide multiplied by 10
1561  * to allow rounding later */
1562 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1563 
1564 static struct {
1565     unsigned int min;
1566     unsigned int max;
1567     u16 fll_fratio;
1568     int ratio;
1569 } fll_fratios[] = {
1570     {       0,    64000, 4, 16 },
1571     {   64000,   128000, 3,  8 },
1572     {  128000,   256000, 2,  4 },
1573     {  256000,  1000000, 1,  2 },
1574     { 1000000, 13500000, 0,  1 },
1575 };
1576 
1577 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1578                unsigned int Fout)
1579 {
1580     u64 Kpart;
1581     unsigned int K, Ndiv, Nmod, target;
1582     unsigned int div;
1583     int i;
1584 
1585     /* Fref must be <=13.5MHz */
1586     div = 1;
1587     fll_div->fll_clk_ref_div = 0;
1588     while ((Fref / div) > 13500000) {
1589         div *= 2;
1590         fll_div->fll_clk_ref_div++;
1591 
1592         if (div > 8) {
1593             pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1594                    Fref);
1595             return -EINVAL;
1596         }
1597     }
1598 
1599     pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1600 
1601     /* Apply the division for our remaining calculations */
1602     Fref /= div;
1603 
1604     /* Fvco should be 90-100MHz; don't check the upper bound */
1605     div = 4;
1606     while (Fout * div < 90000000) {
1607         div++;
1608         if (div > 64) {
1609             pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1610                    Fout);
1611             return -EINVAL;
1612         }
1613     }
1614     target = Fout * div;
1615     fll_div->fll_outdiv = div - 1;
1616 
1617     pr_debug("Fvco=%dHz\n", target);
1618 
1619     /* Find an appropriate FLL_FRATIO and factor it out of the target */
1620     for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1621         if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1622             fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1623             target /= fll_fratios[i].ratio;
1624             break;
1625         }
1626     }
1627     if (i == ARRAY_SIZE(fll_fratios)) {
1628         pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1629         return -EINVAL;
1630     }
1631 
1632     /* Now, calculate N.K */
1633     Ndiv = target / Fref;
1634 
1635     fll_div->n = Ndiv;
1636     Nmod = target % Fref;
1637     pr_debug("Nmod=%d\n", Nmod);
1638 
1639     /* Calculate fractional part - scale up so we can round. */
1640     Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1641 
1642     do_div(Kpart, Fref);
1643 
1644     K = Kpart & 0xFFFFFFFF;
1645 
1646     if ((K % 10) >= 5)
1647         K += 5;
1648 
1649     /* Move down to proper range now rounding is done */
1650     fll_div->k = K / 10;
1651 
1652     pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1653          fll_div->n, fll_div->k,
1654          fll_div->fll_fratio, fll_div->fll_outdiv,
1655          fll_div->fll_clk_ref_div);
1656 
1657     return 0;
1658 }
1659 
1660 static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1661               unsigned int Fref, unsigned int Fout)
1662 {
1663     struct snd_soc_component *component = dai->component;
1664     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1665     struct _fll_div fll_div;
1666     int ret, val;
1667     int clock2, fll1;
1668 
1669     /* Any change? */
1670     if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1671         Fout == wm8904->fll_fout)
1672         return 0;
1673 
1674     clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2);
1675 
1676     if (Fout == 0) {
1677         dev_dbg(component->dev, "FLL disabled\n");
1678 
1679         wm8904->fll_fref = 0;
1680         wm8904->fll_fout = 0;
1681 
1682         /* Gate SYSCLK to avoid glitches */
1683         snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1684                     WM8904_CLK_SYS_ENA, 0);
1685 
1686         snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1687                     WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1688 
1689         goto out;
1690     }
1691 
1692     /* Validate the FLL ID */
1693     switch (source) {
1694     case WM8904_FLL_MCLK:
1695     case WM8904_FLL_LRCLK:
1696     case WM8904_FLL_BCLK:
1697         ret = fll_factors(&fll_div, Fref, Fout);
1698         if (ret != 0)
1699             return ret;
1700         break;
1701 
1702     case WM8904_FLL_FREE_RUNNING:
1703         dev_dbg(component->dev, "Using free running FLL\n");
1704         /* Force 12MHz and output/4 for now */
1705         Fout = 12000000;
1706         Fref = 12000000;
1707 
1708         memset(&fll_div, 0, sizeof(fll_div));
1709         fll_div.fll_outdiv = 3;
1710         break;
1711 
1712     default:
1713         dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
1714         return -EINVAL;
1715     }
1716 
1717     /* Save current state then disable the FLL and SYSCLK to avoid
1718      * misclocking */
1719     fll1 = snd_soc_component_read(component, WM8904_FLL_CONTROL_1);
1720     snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1721                 WM8904_CLK_SYS_ENA, 0);
1722     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1723                 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1724 
1725     /* Unlock forced oscilator control to switch it on/off */
1726     snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
1727                 WM8904_USER_KEY, WM8904_USER_KEY);
1728 
1729     if (fll_id == WM8904_FLL_FREE_RUNNING) {
1730         val = WM8904_FLL_FRC_NCO;
1731     } else {
1732         val = 0;
1733     }
1734 
1735     snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1736                 val);
1737     snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1,
1738                 WM8904_USER_KEY, 0);
1739 
1740     switch (fll_id) {
1741     case WM8904_FLL_MCLK:
1742         snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1743                     WM8904_FLL_CLK_REF_SRC_MASK, 0);
1744         break;
1745 
1746     case WM8904_FLL_LRCLK:
1747         snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1748                     WM8904_FLL_CLK_REF_SRC_MASK, 1);
1749         break;
1750 
1751     case WM8904_FLL_BCLK:
1752         snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1753                     WM8904_FLL_CLK_REF_SRC_MASK, 2);
1754         break;
1755     }
1756 
1757     if (fll_div.k)
1758         val = WM8904_FLL_FRACN_ENA;
1759     else
1760         val = 0;
1761     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1762                 WM8904_FLL_FRACN_ENA, val);
1763 
1764     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2,
1765                 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1766                 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1767                 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1768 
1769     snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k);
1770 
1771     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1772                 fll_div.n << WM8904_FLL_N_SHIFT);
1773 
1774     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5,
1775                 WM8904_FLL_CLK_REF_DIV_MASK,
1776                 fll_div.fll_clk_ref_div 
1777                 << WM8904_FLL_CLK_REF_DIV_SHIFT);
1778 
1779     dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1780 
1781     wm8904->fll_fref = Fref;
1782     wm8904->fll_fout = Fout;
1783     wm8904->fll_src = source;
1784 
1785     /* Enable the FLL if it was previously active */
1786     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1787                 WM8904_FLL_OSC_ENA, fll1);
1788     snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1,
1789                 WM8904_FLL_ENA, fll1);
1790 
1791 out:
1792     /* Reenable SYSCLK if it was previously active */
1793     snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2,
1794                 WM8904_CLK_SYS_ENA, clock2);
1795 
1796     return 0;
1797 }
1798 
1799 static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1800                  unsigned int freq, int dir)
1801 {
1802     struct snd_soc_component *component = dai->component;
1803     struct wm8904_priv *priv = snd_soc_component_get_drvdata(component);
1804     unsigned long mclk_freq;
1805     int ret;
1806 
1807     switch (clk_id) {
1808     case WM8904_CLK_AUTO:
1809         /* We don't have any rate constraints, so just ignore the
1810          * request to disable constraining.
1811          */
1812         if (!freq)
1813             return 0;
1814 
1815         mclk_freq = clk_get_rate(priv->mclk);
1816         /* enable FLL if a different sysclk is desired */
1817         if (mclk_freq != freq) {
1818             priv->sysclk_src = WM8904_CLK_FLL;
1819             ret = wm8904_set_fll(dai, WM8904_FLL_MCLK,
1820                          WM8904_FLL_MCLK,
1821                          mclk_freq, freq);
1822             if (ret)
1823                 return ret;
1824             break;
1825         }
1826         clk_id = WM8904_CLK_MCLK;
1827         fallthrough;
1828 
1829     case WM8904_CLK_MCLK:
1830         priv->sysclk_src = clk_id;
1831         priv->mclk_rate = freq;
1832         break;
1833 
1834     case WM8904_CLK_FLL:
1835         priv->sysclk_src = clk_id;
1836         break;
1837 
1838     default:
1839         return -EINVAL;
1840     }
1841 
1842     dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1843 
1844     wm8904_configure_clocking(component);
1845 
1846     return 0;
1847 }
1848 
1849 static int wm8904_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1850 {
1851     struct snd_soc_component *component = codec_dai->component;
1852     int val;
1853 
1854     if (mute)
1855         val = WM8904_DAC_MUTE;
1856     else
1857         val = 0;
1858 
1859     snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1860 
1861     return 0;
1862 }
1863 
1864 static int wm8904_set_bias_level(struct snd_soc_component *component,
1865                  enum snd_soc_bias_level level)
1866 {
1867     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1868     int ret;
1869 
1870     switch (level) {
1871     case SND_SOC_BIAS_ON:
1872         break;
1873 
1874     case SND_SOC_BIAS_PREPARE:
1875         /* VMID resistance 2*50k */
1876         snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1877                     WM8904_VMID_RES_MASK,
1878                     0x1 << WM8904_VMID_RES_SHIFT);
1879 
1880         /* Normal bias current */
1881         snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1882                     WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1883         break;
1884 
1885     case SND_SOC_BIAS_STANDBY:
1886         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1887             ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1888                             wm8904->supplies);
1889             if (ret != 0) {
1890                 dev_err(component->dev,
1891                     "Failed to enable supplies: %d\n",
1892                     ret);
1893                 return ret;
1894             }
1895 
1896             ret = clk_prepare_enable(wm8904->mclk);
1897             if (ret) {
1898                 dev_err(component->dev,
1899                     "Failed to enable MCLK: %d\n", ret);
1900                 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1901                                wm8904->supplies);
1902                 return ret;
1903             }
1904 
1905             regcache_cache_only(wm8904->regmap, false);
1906             regcache_sync(wm8904->regmap);
1907 
1908             /* Enable bias */
1909             snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1910                         WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1911 
1912             /* Enable VMID, VMID buffering, 2*5k resistance */
1913             snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1914                         WM8904_VMID_ENA |
1915                         WM8904_VMID_RES_MASK,
1916                         WM8904_VMID_ENA |
1917                         0x3 << WM8904_VMID_RES_SHIFT);
1918 
1919             /* Let VMID ramp */
1920             msleep(1);
1921         }
1922 
1923         /* Maintain VMID with 2*250k */
1924         snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1925                     WM8904_VMID_RES_MASK,
1926                     0x2 << WM8904_VMID_RES_SHIFT);
1927 
1928         /* Bias current *0.5 */
1929         snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1930                     WM8904_ISEL_MASK, 0);
1931         break;
1932 
1933     case SND_SOC_BIAS_OFF:
1934         /* Turn off VMID */
1935         snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0,
1936                     WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1937 
1938         /* Stop bias generation */
1939         snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0,
1940                     WM8904_BIAS_ENA, 0);
1941 
1942         snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0);
1943         regcache_cache_only(wm8904->regmap, true);
1944         regcache_mark_dirty(wm8904->regmap);
1945 
1946         regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1947                        wm8904->supplies);
1948         clk_disable_unprepare(wm8904->mclk);
1949         break;
1950     }
1951     return 0;
1952 }
1953 
1954 #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1955 
1956 #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1957             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1958 
1959 static const struct snd_soc_dai_ops wm8904_dai_ops = {
1960     .set_sysclk = wm8904_set_sysclk,
1961     .set_fmt = wm8904_set_fmt,
1962     .set_tdm_slot = wm8904_set_tdm_slot,
1963     .set_pll = wm8904_set_fll,
1964     .hw_params = wm8904_hw_params,
1965     .mute_stream = wm8904_mute,
1966     .no_capture_mute = 1,
1967 };
1968 
1969 static struct snd_soc_dai_driver wm8904_dai = {
1970     .name = "wm8904-hifi",
1971     .playback = {
1972         .stream_name = "Playback",
1973         .channels_min = 2,
1974         .channels_max = 2,
1975         .rates = WM8904_RATES,
1976         .formats = WM8904_FORMATS,
1977     },
1978     .capture = {
1979         .stream_name = "Capture",
1980         .channels_min = 2,
1981         .channels_max = 2,
1982         .rates = WM8904_RATES,
1983         .formats = WM8904_FORMATS,
1984     },
1985     .ops = &wm8904_dai_ops,
1986     .symmetric_rate = 1,
1987 };
1988 
1989 static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component)
1990 {
1991     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
1992     struct wm8904_pdata *pdata = wm8904->pdata;
1993     struct snd_kcontrol_new control =
1994         SOC_ENUM_EXT("EQ Mode",
1995                  wm8904->retune_mobile_enum,
1996                  wm8904_get_retune_mobile_enum,
1997                  wm8904_put_retune_mobile_enum);
1998     int ret, i, j;
1999     const char **t;
2000 
2001     /* We need an array of texts for the enum API but the number
2002      * of texts is likely to be less than the number of
2003      * configurations due to the sample rate dependency of the
2004      * configurations. */
2005     wm8904->num_retune_mobile_texts = 0;
2006     wm8904->retune_mobile_texts = NULL;
2007     for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2008         for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2009             if (strcmp(pdata->retune_mobile_cfgs[i].name,
2010                    wm8904->retune_mobile_texts[j]) == 0)
2011                 break;
2012         }
2013 
2014         if (j != wm8904->num_retune_mobile_texts)
2015             continue;
2016 
2017         /* Expand the array... */
2018         t = krealloc(wm8904->retune_mobile_texts,
2019                  sizeof(char *) * 
2020                  (wm8904->num_retune_mobile_texts + 1),
2021                  GFP_KERNEL);
2022         if (t == NULL)
2023             continue;
2024 
2025         /* ...store the new entry... */
2026         t[wm8904->num_retune_mobile_texts] = 
2027             pdata->retune_mobile_cfgs[i].name;
2028 
2029         /* ...and remember the new version. */
2030         wm8904->num_retune_mobile_texts++;
2031         wm8904->retune_mobile_texts = t;
2032     }
2033 
2034     dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
2035         wm8904->num_retune_mobile_texts);
2036 
2037     wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
2038     wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2039 
2040     ret = snd_soc_add_component_controls(component, &control, 1);
2041     if (ret != 0)
2042         dev_err(component->dev,
2043             "Failed to add ReTune Mobile control: %d\n", ret);
2044 }
2045 
2046 static void wm8904_handle_pdata(struct snd_soc_component *component)
2047 {
2048     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2049     struct wm8904_pdata *pdata = wm8904->pdata;
2050     int ret, i;
2051 
2052     if (!pdata) {
2053         snd_soc_add_component_controls(component, wm8904_eq_controls,
2054                      ARRAY_SIZE(wm8904_eq_controls));
2055         return;
2056     }
2057 
2058     dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2059 
2060     if (pdata->num_drc_cfgs) {
2061         struct snd_kcontrol_new control =
2062             SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2063                      wm8904_get_drc_enum, wm8904_put_drc_enum);
2064 
2065         /* We need an array of texts for the enum API */
2066         wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs,
2067                           sizeof(char *),
2068                           GFP_KERNEL);
2069         if (!wm8904->drc_texts)
2070             return;
2071 
2072         for (i = 0; i < pdata->num_drc_cfgs; i++)
2073             wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2074 
2075         wm8904->drc_enum.items = pdata->num_drc_cfgs;
2076         wm8904->drc_enum.texts = wm8904->drc_texts;
2077 
2078         ret = snd_soc_add_component_controls(component, &control, 1);
2079         if (ret != 0)
2080             dev_err(component->dev,
2081                 "Failed to add DRC mode control: %d\n", ret);
2082 
2083         wm8904_set_drc(component);
2084     }
2085 
2086     dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
2087         pdata->num_retune_mobile_cfgs);
2088 
2089     if (pdata->num_retune_mobile_cfgs)
2090         wm8904_handle_retune_mobile_pdata(component);
2091     else
2092         snd_soc_add_component_controls(component, wm8904_eq_controls,
2093                      ARRAY_SIZE(wm8904_eq_controls));
2094 }
2095 
2096 
2097 static int wm8904_probe(struct snd_soc_component *component)
2098 {
2099     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2100 
2101     switch (wm8904->devtype) {
2102     case WM8904:
2103         break;
2104     case WM8912:
2105         memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2106         break;
2107     default:
2108         dev_err(component->dev, "Unknown device type %d\n",
2109             wm8904->devtype);
2110         return -EINVAL;
2111     }
2112 
2113     wm8904_handle_pdata(component);
2114 
2115     wm8904_add_widgets(component);
2116 
2117     return 0;
2118 }
2119 
2120 static void wm8904_remove(struct snd_soc_component *component)
2121 {
2122     struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component);
2123 
2124     kfree(wm8904->retune_mobile_texts);
2125     kfree(wm8904->drc_texts);
2126 }
2127 
2128 static const struct snd_soc_component_driver soc_component_dev_wm8904 = {
2129     .probe          = wm8904_probe,
2130     .remove         = wm8904_remove,
2131     .set_bias_level     = wm8904_set_bias_level,
2132     .use_pmdown_time    = 1,
2133     .endianness     = 1,
2134 };
2135 
2136 static const struct regmap_config wm8904_regmap = {
2137     .reg_bits = 8,
2138     .val_bits = 16,
2139 
2140     .max_register = WM8904_MAX_REGISTER,
2141     .volatile_reg = wm8904_volatile_register,
2142     .readable_reg = wm8904_readable_register,
2143 
2144     .cache_type = REGCACHE_RBTREE,
2145     .reg_defaults = wm8904_reg_defaults,
2146     .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
2147 };
2148 
2149 #ifdef CONFIG_OF
2150 static const struct of_device_id wm8904_of_match[] = {
2151     {
2152         .compatible = "wlf,wm8904",
2153         .data = (void *)WM8904,
2154     }, {
2155         .compatible = "wlf,wm8912",
2156         .data = (void *)WM8912,
2157     }, {
2158         /* sentinel */
2159     }
2160 };
2161 MODULE_DEVICE_TABLE(of, wm8904_of_match);
2162 #endif
2163 
2164 static const struct i2c_device_id wm8904_i2c_id[];
2165 
2166 static int wm8904_i2c_probe(struct i2c_client *i2c)
2167 {
2168     struct wm8904_priv *wm8904;
2169     unsigned int val;
2170     int ret, i;
2171 
2172     wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2173                   GFP_KERNEL);
2174     if (wm8904 == NULL)
2175         return -ENOMEM;
2176 
2177     wm8904->mclk = devm_clk_get(&i2c->dev, "mclk");
2178     if (IS_ERR(wm8904->mclk)) {
2179         ret = PTR_ERR(wm8904->mclk);
2180         dev_err(&i2c->dev, "Failed to get MCLK\n");
2181         return ret;
2182     }
2183 
2184     wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
2185     if (IS_ERR(wm8904->regmap)) {
2186         ret = PTR_ERR(wm8904->regmap);
2187         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2188             ret);
2189         return ret;
2190     }
2191 
2192     if (i2c->dev.of_node) {
2193         const struct of_device_id *match;
2194 
2195         match = of_match_node(wm8904_of_match, i2c->dev.of_node);
2196         if (match == NULL)
2197             return -EINVAL;
2198         wm8904->devtype = (enum wm8904_type)match->data;
2199     } else {
2200         const struct i2c_device_id *id =
2201             i2c_match_id(wm8904_i2c_id, i2c);
2202         wm8904->devtype = id->driver_data;
2203     }
2204 
2205     i2c_set_clientdata(i2c, wm8904);
2206     wm8904->pdata = i2c->dev.platform_data;
2207 
2208     for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2209         wm8904->supplies[i].supply = wm8904_supply_names[i];
2210 
2211     ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2212                       wm8904->supplies);
2213     if (ret != 0) {
2214         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2215         return ret;
2216     }
2217 
2218     ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2219                     wm8904->supplies);
2220     if (ret != 0) {
2221         dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2222         return ret;
2223     }
2224 
2225     ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2226     if (ret < 0) {
2227         dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2228         goto err_enable;
2229     }
2230     if (val != 0x8904) {
2231         dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2232         ret = -EINVAL;
2233         goto err_enable;
2234     }
2235 
2236     ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2237     if (ret < 0) {
2238         dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2239             ret);
2240         goto err_enable;
2241     }
2242     dev_info(&i2c->dev, "revision %c\n", val + 'A');
2243 
2244     ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2245     if (ret < 0) {
2246         dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2247         goto err_enable;
2248     }
2249 
2250     /* Change some default settings - latch VU and enable ZC */
2251     regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2252                WM8904_ADC_VU, WM8904_ADC_VU);
2253     regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2254                WM8904_ADC_VU, WM8904_ADC_VU);
2255     regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2256                WM8904_DAC_VU, WM8904_DAC_VU);
2257     regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2258                WM8904_DAC_VU, WM8904_DAC_VU);
2259     regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2260                WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2261                WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2262     regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2263                WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2264                WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2265     regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2266                WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2267                WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2268     regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2269                WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2270                WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2271     regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2272                WM8904_SR_MODE, 0);
2273 
2274     /* Apply configuration from the platform data. */
2275     if (wm8904->pdata) {
2276         for (i = 0; i < WM8904_GPIO_REGS; i++) {
2277             if (!wm8904->pdata->gpio_cfg[i])
2278                 continue;
2279 
2280             regmap_update_bits(wm8904->regmap,
2281                        WM8904_GPIO_CONTROL_1 + i,
2282                        0xffff,
2283                        wm8904->pdata->gpio_cfg[i]);
2284         }
2285 
2286         /* Zero is the default value for these anyway */
2287         for (i = 0; i < WM8904_MIC_REGS; i++)
2288             regmap_update_bits(wm8904->regmap,
2289                        WM8904_MIC_BIAS_CONTROL_0 + i,
2290                        0xffff,
2291                        wm8904->pdata->mic_cfg[i]);
2292     }
2293 
2294     /* Set Class W by default - this will be managed by the Class
2295      * G widget at runtime where bypass paths are available.
2296      */
2297     regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2298                 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2299 
2300     /* Use normal bias source */
2301     regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2302                 WM8904_POBCTRL, 0);
2303 
2304     /* Can leave the device powered off until we need it */
2305     regcache_cache_only(wm8904->regmap, true);
2306     regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2307 
2308     ret = devm_snd_soc_register_component(&i2c->dev,
2309             &soc_component_dev_wm8904, &wm8904_dai, 1);
2310     if (ret != 0)
2311         return ret;
2312 
2313     return 0;
2314 
2315 err_enable:
2316     regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2317     return ret;
2318 }
2319 
2320 static const struct i2c_device_id wm8904_i2c_id[] = {
2321     { "wm8904", WM8904 },
2322     { "wm8912", WM8912 },
2323     { "wm8918", WM8904 },   /* Actually a subset, updates to follow */
2324     { }
2325 };
2326 MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2327 
2328 static struct i2c_driver wm8904_i2c_driver = {
2329     .driver = {
2330         .name = "wm8904",
2331         .of_match_table = of_match_ptr(wm8904_of_match),
2332     },
2333     .probe_new = wm8904_i2c_probe,
2334     .id_table = wm8904_i2c_id,
2335 };
2336 
2337 module_i2c_driver(wm8904_i2c_driver);
2338 
2339 MODULE_DESCRIPTION("ASoC WM8904 driver");
2340 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2341 MODULE_LICENSE("GPL");
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