soc/codecs/wm8903.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8903.c  --  WM8903 ALSA SoC Audio driver
0004  *
0005  * Copyright 2008-12 Wolfson Microelectronics
0006  * Copyright 2011-2012 NVIDIA, Inc.
0007  *
0008  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0009  *
0010  * TODO:
0011  *  - TDM mode configuration.
0012  *  - Digital microphone support.
0013  */
0014
0015 #include <linux/module.h>
0016 #include <linux/moduleparam.h>
0017 #include <linux/init.h>
0018 #include <linux/completion.h>
0019 #include <linux/delay.h>
0020 #include <linux/gpio/driver.h>
0021 #include <linux/pm.h>
0022 #include <linux/i2c.h>
0023 #include <linux/regmap.h>
0024 #include <linux/regulator/consumer.h>
0025 #include <linux/slab.h>
0026 #include <linux/irq.h>
0027 #include <linux/mutex.h>
0028 #include <sound/core.h>
0029 #include <sound/jack.h>
0030 #include <sound/pcm.h>
0031 #include <sound/pcm_params.h>
0032 #include <sound/tlv.h>
0033 #include <sound/soc.h>
0034 #include <sound/initval.h>
0035 #include <sound/wm8903.h>
0036 #include <trace/events/asoc.h>
0037
0038 #include "wm8903.h"
0039
0040 /* Register defaults at reset */
0041 static const struct reg_default wm8903_reg_defaults[] = {
0042     { 4,  0x0018 },     /* R4   - Bias Control 0 */
0043     { 5,  0x0000 },     /* R5   - VMID Control 0 */
0044     { 6,  0x0000 },     /* R6   - Mic Bias Control 0 */
0045     { 8,  0x0001 },     /* R8   - Analogue DAC 0 */
0046     { 10, 0x0001 },     /* R10  - Analogue ADC 0 */
0047     { 12, 0x0000 },     /* R12  - Power Management 0 */
0048     { 13, 0x0000 },     /* R13  - Power Management 1 */
0049     { 14, 0x0000 },     /* R14  - Power Management 2 */
0050     { 15, 0x0000 },     /* R15  - Power Management 3 */
0051     { 16, 0x0000 },     /* R16  - Power Management 4 */
0052     { 17, 0x0000 },     /* R17  - Power Management 5 */
0053     { 18, 0x0000 },     /* R18  - Power Management 6 */
0054     { 20, 0x0400 },     /* R20  - Clock Rates 0 */
0055     { 21, 0x0D07 },     /* R21  - Clock Rates 1 */
0056     { 22, 0x0000 },     /* R22  - Clock Rates 2 */
0057     { 24, 0x0050 },     /* R24  - Audio Interface 0 */
0058     { 25, 0x0242 },     /* R25  - Audio Interface 1 */
0059     { 26, 0x0008 },     /* R26  - Audio Interface 2 */
0060     { 27, 0x0022 },     /* R27  - Audio Interface 3 */
0061     { 30, 0x00C0 },     /* R30  - DAC Digital Volume Left */
0062     { 31, 0x00C0 },     /* R31  - DAC Digital Volume Right */
0063     { 32, 0x0000 },     /* R32  - DAC Digital 0 */
0064     { 33, 0x0000 },     /* R33  - DAC Digital 1 */
0065     { 36, 0x00C0 },     /* R36  - ADC Digital Volume Left */
0066     { 37, 0x00C0 },     /* R37  - ADC Digital Volume Right */
0067     { 38, 0x0000 },     /* R38  - ADC Digital 0 */
0068     { 39, 0x0073 },     /* R39  - Digital Microphone 0 */
0069     { 40, 0x09BF },     /* R40  - DRC 0 */
0070     { 41, 0x3241 },     /* R41  - DRC 1 */
0071     { 42, 0x0020 },     /* R42  - DRC 2 */
0072     { 43, 0x0000 },     /* R43  - DRC 3 */
0073     { 44, 0x0085 },     /* R44  - Analogue Left Input 0 */
0074     { 45, 0x0085 },     /* R45  - Analogue Right Input 0 */
0075     { 46, 0x0044 },     /* R46  - Analogue Left Input 1 */
0076     { 47, 0x0044 },     /* R47  - Analogue Right Input 1 */
0077     { 50, 0x0008 },     /* R50  - Analogue Left Mix 0 */
0078     { 51, 0x0004 },     /* R51  - Analogue Right Mix 0 */
0079     { 52, 0x0000 },     /* R52  - Analogue Spk Mix Left 0 */
0080     { 53, 0x0000 },     /* R53  - Analogue Spk Mix Left 1 */
0081     { 54, 0x0000 },     /* R54  - Analogue Spk Mix Right 0 */
0082     { 55, 0x0000 },     /* R55  - Analogue Spk Mix Right 1 */
0083     { 57, 0x002D },     /* R57  - Analogue OUT1 Left */
0084     { 58, 0x002D },     /* R58  - Analogue OUT1 Right */
0085     { 59, 0x0039 },     /* R59  - Analogue OUT2 Left */
0086     { 60, 0x0039 },     /* R60  - Analogue OUT2 Right */
0087     { 62, 0x0139 },     /* R62  - Analogue OUT3 Left */
0088     { 63, 0x0139 },     /* R63  - Analogue OUT3 Right */
0089     { 64, 0x0000 },     /* R65  - Analogue SPK Output Control 0 */
0090     { 67, 0x0010 },     /* R67  - DC Servo 0 */
0091     { 69, 0x00A4 },     /* R69  - DC Servo 2 */
0092     { 90, 0x0000 },     /* R90  - Analogue HP 0 */
0093     { 94, 0x0000 },     /* R94  - Analogue Lineout 0 */
0094     { 98, 0x0000 },     /* R98  - Charge Pump 0 */
0095     { 104, 0x0000 },    /* R104 - Class W 0 */
0096     { 108, 0x0000 },    /* R108 - Write Sequencer 0 */
0097     { 109, 0x0000 },    /* R109 - Write Sequencer 1 */
0098     { 110, 0x0000 },    /* R110 - Write Sequencer 2 */
0099     { 111, 0x0000 },    /* R111 - Write Sequencer 3 */
0100     { 112, 0x0000 },    /* R112 - Write Sequencer 4 */
0101     { 114, 0x0000 },    /* R114 - Control Interface */
0102     { 116, 0x00A8 },    /* R116 - GPIO Control 1 */
0103     { 117, 0x00A8 },    /* R117 - GPIO Control 2 */
0104     { 118, 0x00A8 },    /* R118 - GPIO Control 3 */
0105     { 119, 0x0220 },    /* R119 - GPIO Control 4 */
0106     { 120, 0x01A0 },    /* R120 - GPIO Control 5 */
0107     { 122, 0xFFFF },    /* R122 - Interrupt Status 1 Mask */
0108     { 123, 0x0000 },    /* R123 - Interrupt Polarity 1 */
0109     { 126, 0x0000 },    /* R126 - Interrupt Control */
0110     { 129, 0x0000 },    /* R129 - Control Interface Test 1 */
0111     { 149, 0x6810 },    /* R149 - Charge Pump Test 1 */
0112     { 164, 0x0028 },    /* R164 - Clock Rate Test 4 */
0113     { 172, 0x0000 },    /* R172 - Analogue Output Bias 0 */
0114 };
0115
0116 #define WM8903_NUM_SUPPLIES 4
0117 static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = {
0118     "AVDD",
0119     "CPVDD",
0120     "DBVDD",
0121     "DCVDD",
0122 };
0123
0124 struct wm8903_priv {
0125     struct wm8903_platform_data *pdata;
0126     struct device *dev;
0127     struct regmap *regmap;
0128     struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES];
0129
0130     int sysclk;
0131     int irq;
0132
0133     struct mutex lock;
0134     int fs;
0135     int deemph;
0136
0137     int dcs_pending;
0138     int dcs_cache[4];
0139
0140     /* Reference count */
0141     int class_w_users;
0142
0143     struct snd_soc_jack *mic_jack;
0144     int mic_det;
0145     int mic_short;
0146     int mic_last_report;
0147     int mic_delay;
0148
0149 #ifdef CONFIG_GPIOLIB
0150     struct gpio_chip gpio_chip;
0151 #endif
0152 };
0153
0154 static bool wm8903_readable_register(struct device *dev, unsigned int reg)
0155 {
0156     switch (reg) {
0157     case WM8903_SW_RESET_AND_ID:
0158     case WM8903_REVISION_NUMBER:
0159     case WM8903_BIAS_CONTROL_0:
0160     case WM8903_VMID_CONTROL_0:
0161     case WM8903_MIC_BIAS_CONTROL_0:
0162     case WM8903_ANALOGUE_DAC_0:
0163     case WM8903_ANALOGUE_ADC_0:
0164     case WM8903_POWER_MANAGEMENT_0:
0165     case WM8903_POWER_MANAGEMENT_1:
0166     case WM8903_POWER_MANAGEMENT_2:
0167     case WM8903_POWER_MANAGEMENT_3:
0168     case WM8903_POWER_MANAGEMENT_4:
0169     case WM8903_POWER_MANAGEMENT_5:
0170     case WM8903_POWER_MANAGEMENT_6:
0171     case WM8903_CLOCK_RATES_0:
0172     case WM8903_CLOCK_RATES_1:
0173     case WM8903_CLOCK_RATES_2:
0174     case WM8903_AUDIO_INTERFACE_0:
0175     case WM8903_AUDIO_INTERFACE_1:
0176     case WM8903_AUDIO_INTERFACE_2:
0177     case WM8903_AUDIO_INTERFACE_3:
0178     case WM8903_DAC_DIGITAL_VOLUME_LEFT:
0179     case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
0180     case WM8903_DAC_DIGITAL_0:
0181     case WM8903_DAC_DIGITAL_1:
0182     case WM8903_ADC_DIGITAL_VOLUME_LEFT:
0183     case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
0184     case WM8903_ADC_DIGITAL_0:
0185     case WM8903_DIGITAL_MICROPHONE_0:
0186     case WM8903_DRC_0:
0187     case WM8903_DRC_1:
0188     case WM8903_DRC_2:
0189     case WM8903_DRC_3:
0190     case WM8903_ANALOGUE_LEFT_INPUT_0:
0191     case WM8903_ANALOGUE_RIGHT_INPUT_0:
0192     case WM8903_ANALOGUE_LEFT_INPUT_1:
0193     case WM8903_ANALOGUE_RIGHT_INPUT_1:
0194     case WM8903_ANALOGUE_LEFT_MIX_0:
0195     case WM8903_ANALOGUE_RIGHT_MIX_0:
0196     case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
0197     case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
0198     case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
0199     case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
0200     case WM8903_ANALOGUE_OUT1_LEFT:
0201     case WM8903_ANALOGUE_OUT1_RIGHT:
0202     case WM8903_ANALOGUE_OUT2_LEFT:
0203     case WM8903_ANALOGUE_OUT2_RIGHT:
0204     case WM8903_ANALOGUE_OUT3_LEFT:
0205     case WM8903_ANALOGUE_OUT3_RIGHT:
0206     case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
0207     case WM8903_DC_SERVO_0:
0208     case WM8903_DC_SERVO_2:
0209     case WM8903_DC_SERVO_READBACK_1:
0210     case WM8903_DC_SERVO_READBACK_2:
0211     case WM8903_DC_SERVO_READBACK_3:
0212     case WM8903_DC_SERVO_READBACK_4:
0213     case WM8903_ANALOGUE_HP_0:
0214     case WM8903_ANALOGUE_LINEOUT_0:
0215     case WM8903_CHARGE_PUMP_0:
0216     case WM8903_CLASS_W_0:
0217     case WM8903_WRITE_SEQUENCER_0:
0218     case WM8903_WRITE_SEQUENCER_1:
0219     case WM8903_WRITE_SEQUENCER_2:
0220     case WM8903_WRITE_SEQUENCER_3:
0221     case WM8903_WRITE_SEQUENCER_4:
0222     case WM8903_CONTROL_INTERFACE:
0223     case WM8903_GPIO_CONTROL_1:
0224     case WM8903_GPIO_CONTROL_2:
0225     case WM8903_GPIO_CONTROL_3:
0226     case WM8903_GPIO_CONTROL_4:
0227     case WM8903_GPIO_CONTROL_5:
0228     case WM8903_INTERRUPT_STATUS_1:
0229     case WM8903_INTERRUPT_STATUS_1_MASK:
0230     case WM8903_INTERRUPT_POLARITY_1:
0231     case WM8903_INTERRUPT_CONTROL:
0232     case WM8903_CLOCK_RATE_TEST_4:
0233     case WM8903_ANALOGUE_OUTPUT_BIAS_0:
0234         return true;
0235     default:
0236         return false;
0237     }
0238 }
0239
0240 static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
0241 {
0242     switch (reg) {
0243     case WM8903_SW_RESET_AND_ID:
0244     case WM8903_REVISION_NUMBER:
0245     case WM8903_INTERRUPT_STATUS_1:
0246     case WM8903_WRITE_SEQUENCER_4:
0247     case WM8903_DC_SERVO_READBACK_1:
0248     case WM8903_DC_SERVO_READBACK_2:
0249     case WM8903_DC_SERVO_READBACK_3:
0250     case WM8903_DC_SERVO_READBACK_4:
0251         return true;
0252
0253     default:
0254         return false;
0255     }
0256 }
0257
0258 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
0259                struct snd_kcontrol *kcontrol, int event)
0260 {
0261     WARN_ON(event != SND_SOC_DAPM_POST_PMU);
0262     mdelay(4);
0263
0264     return 0;
0265 }
0266
0267 static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
0268                 struct snd_kcontrol *kcontrol, int event)
0269 {
0270     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0271     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
0272
0273     switch (event) {
0274     case SND_SOC_DAPM_POST_PMU:
0275         wm8903->dcs_pending |= 1 << w->shift;
0276         break;
0277     case SND_SOC_DAPM_PRE_PMD:
0278         snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,
0279                     1 << w->shift, 0);
0280         break;
0281     }
0282
0283     return 0;
0284 }
0285
0286 #define WM8903_DCS_MODE_WRITE_STOP 0
0287 #define WM8903_DCS_MODE_START_STOP 2
0288
0289 static void wm8903_seq_notifier(struct snd_soc_component *component,
0290                 enum snd_soc_dapm_type event, int subseq)
0291 {
0292     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
0293     int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
0294     int i, val;
0295
0296     /* Complete any pending DC servo starts */
0297     if (wm8903->dcs_pending) {
0298         dev_dbg(component->dev, "Starting DC servo for %x\n",
0299             wm8903->dcs_pending);
0300
0301         /* If we've no cached values then we need to do startup */
0302         for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
0303             if (!(wm8903->dcs_pending & (1 << i)))
0304                 continue;
0305
0306             if (wm8903->dcs_cache[i]) {
0307                 dev_dbg(component->dev,
0308                     "Restore DC servo %d value %x\n",
0309                     3 - i, wm8903->dcs_cache[i]);
0310
0311                 snd_soc_component_write(component, WM8903_DC_SERVO_4 + i,
0312                           wm8903->dcs_cache[i] & 0xff);
0313             } else {
0314                 dev_dbg(component->dev,
0315                     "Calibrate DC servo %d\n", 3 - i);
0316                 dcs_mode = WM8903_DCS_MODE_START_STOP;
0317             }
0318         }
0319
0320         /* Don't trust the cache for analogue */
0321         if (wm8903->class_w_users)
0322             dcs_mode = WM8903_DCS_MODE_START_STOP;
0323
0324         snd_soc_component_update_bits(component, WM8903_DC_SERVO_2,
0325                     WM8903_DCS_MODE_MASK, dcs_mode);
0326
0327         snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,
0328                     WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
0329
0330         switch (dcs_mode) {
0331         case WM8903_DCS_MODE_WRITE_STOP:
0332             break;
0333
0334         case WM8903_DCS_MODE_START_STOP:
0335             msleep(270);
0336
0337             /* Cache the measured offsets for digital */
0338             if (wm8903->class_w_users)
0339                 break;
0340
0341             for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
0342                 if (!(wm8903->dcs_pending & (1 << i)))
0343                     continue;
0344
0345                 val = snd_soc_component_read(component,
0346                            WM8903_DC_SERVO_READBACK_1 + i);
0347                 dev_dbg(component->dev, "DC servo %d: %x\n",
0348                     3 - i, val);
0349                 wm8903->dcs_cache[i] = val;
0350             }
0351             break;
0352
0353         default:
0354             pr_warn("DCS mode %d delay not set\n", dcs_mode);
0355             break;
0356         }
0357
0358         wm8903->dcs_pending = 0;
0359     }
0360 }
0361
0362 /*
0363  * When used with DAC outputs only the WM8903 charge pump supports
0364  * operation in class W mode, providing very low power consumption
0365  * when used with digital sources.  Enable and disable this mode
0366  * automatically depending on the mixer configuration.
0367  *
0368  * All the relevant controls are simple switches.
0369  */
0370 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
0371                   struct snd_ctl_elem_value *ucontrol)
0372 {
0373     struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
0374     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
0375     u16 reg;
0376     int ret;
0377
0378     reg = snd_soc_component_read(component, WM8903_CLASS_W_0);
0379
0380     /* Turn it off if we're about to enable bypass */
0381     if (ucontrol->value.integer.value[0]) {
0382         if (wm8903->class_w_users == 0) {
0383             dev_dbg(component->dev, "Disabling Class W\n");
0384             snd_soc_component_write(component, WM8903_CLASS_W_0, reg &
0385                      ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
0386         }
0387         wm8903->class_w_users++;
0388     }
0389
0390     /* Implement the change */
0391     ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
0392
0393     /* If we've just disabled the last bypass path turn Class W on */
0394     if (!ucontrol->value.integer.value[0]) {
0395         if (wm8903->class_w_users == 1) {
0396             dev_dbg(component->dev, "Enabling Class W\n");
0397             snd_soc_component_write(component, WM8903_CLASS_W_0, reg |
0398                      WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
0399         }
0400         wm8903->class_w_users--;
0401     }
0402
0403     dev_dbg(component->dev, "Bypass use count now %d\n",
0404         wm8903->class_w_users);
0405
0406     return ret;
0407 }
0408
0409 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
0410     SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
0411         snd_soc_dapm_get_volsw, wm8903_class_w_put)
0412
0413
0414 static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
0415
0416 static int wm8903_set_deemph(struct snd_soc_component *component)
0417 {
0418     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
0419     int val, i, best;
0420
0421     /* If we're using deemphasis select the nearest available sample
0422      * rate.
0423      */
0424     if (wm8903->deemph) {
0425         best = 1;
0426         for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
0427             if (abs(wm8903_deemph[i] - wm8903->fs) <
0428                 abs(wm8903_deemph[best] - wm8903->fs))
0429                 best = i;
0430         }
0431
0432         val = best << WM8903_DEEMPH_SHIFT;
0433     } else {
0434         best = 0;
0435         val = 0;
0436     }
0437
0438     dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n",
0439         best, wm8903_deemph[best]);
0440
0441     return snd_soc_component_update_bits(component, WM8903_DAC_DIGITAL_1,
0442                    WM8903_DEEMPH_MASK, val);
0443 }
0444
0445 static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
0446                  struct snd_ctl_elem_value *ucontrol)
0447 {
0448     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0449     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
0450
0451     ucontrol->value.integer.value[0] = wm8903->deemph;
0452
0453     return 0;
0454 }
0455
0456 static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
0457                  struct snd_ctl_elem_value *ucontrol)
0458 {
0459     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0460     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
0461     unsigned int deemph = ucontrol->value.integer.value[0];
0462     int ret = 0;
0463
0464     if (deemph > 1)
0465         return -EINVAL;
0466
0467     mutex_lock(&wm8903->lock);
0468     if (wm8903->deemph != deemph) {
0469         wm8903->deemph = deemph;
0470
0471         wm8903_set_deemph(component);
0472
0473         ret = 1;
0474     }
0475     mutex_unlock(&wm8903->lock);
0476
0477     return ret;
0478 }
0479
0480 /* ALSA can only do steps of .01dB */
0481 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
0482
0483 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
0484
0485 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
0486 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
0487
0488 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
0489 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
0490 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
0491 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
0492 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
0493
0494 static const char *hpf_mode_text[] = {
0495     "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
0496 };
0497
0498 static SOC_ENUM_SINGLE_DECL(hpf_mode,
0499                 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
0500
0501 static const char *osr_text[] = {
0502     "Low power", "High performance"
0503 };
0504
0505 static SOC_ENUM_SINGLE_DECL(adc_osr,
0506                 WM8903_ANALOGUE_ADC_0, 0, osr_text);
0507
0508 static SOC_ENUM_SINGLE_DECL(dac_osr,
0509                 WM8903_DAC_DIGITAL_1, 0, osr_text);
0510
0511 static const char *drc_slope_text[] = {
0512     "1", "1/2", "1/4", "1/8", "1/16", "0"
0513 };
0514
0515 static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
0516                 WM8903_DRC_2, 3, drc_slope_text);
0517
0518 static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
0519                 WM8903_DRC_2, 0, drc_slope_text);
0520
0521 static const char *drc_attack_text[] = {
0522     "instantaneous",
0523     "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
0524     "46.4ms", "92.8ms", "185.6ms"
0525 };
0526
0527 static SOC_ENUM_SINGLE_DECL(drc_attack,
0528                 WM8903_DRC_1, 12, drc_attack_text);
0529
0530 static const char *drc_decay_text[] = {
0531     "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
0532     "23.87s", "47.56s"
0533 };
0534
0535 static SOC_ENUM_SINGLE_DECL(drc_decay,
0536                 WM8903_DRC_1, 8, drc_decay_text);
0537
0538 static const char *drc_ff_delay_text[] = {
0539     "5 samples", "9 samples"
0540 };
0541
0542 static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
0543                 WM8903_DRC_0, 5, drc_ff_delay_text);
0544
0545 static const char *drc_qr_decay_text[] = {
0546     "0.725ms", "1.45ms", "5.8ms"
0547 };
0548
0549 static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
0550                 WM8903_DRC_1, 4, drc_qr_decay_text);
0551
0552 static const char *drc_smoothing_text[] = {
0553     "Low", "Medium", "High"
0554 };
0555
0556 static SOC_ENUM_SINGLE_DECL(drc_smoothing,
0557                 WM8903_DRC_0, 11, drc_smoothing_text);
0558
0559 static const char *soft_mute_text[] = {
0560     "Fast (fs/2)", "Slow (fs/32)"
0561 };
0562
0563 static SOC_ENUM_SINGLE_DECL(soft_mute,
0564                 WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
0565
0566 static const char *mute_mode_text[] = {
0567     "Hard", "Soft"
0568 };
0569
0570 static SOC_ENUM_SINGLE_DECL(mute_mode,
0571                 WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
0572
0573 static const char *companding_text[] = {
0574     "ulaw", "alaw"
0575 };
0576
0577 static SOC_ENUM_SINGLE_DECL(dac_companding,
0578                 WM8903_AUDIO_INTERFACE_0, 0, companding_text);
0579
0580 static SOC_ENUM_SINGLE_DECL(adc_companding,
0581                 WM8903_AUDIO_INTERFACE_0, 2, companding_text);
0582
0583 static const char *input_mode_text[] = {
0584     "Single-Ended", "Differential Line", "Differential Mic"
0585 };
0586
0587 static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
0588                 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
0589
0590 static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
0591                 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
0592
0593 static const char *linput_mux_text[] = {
0594     "IN1L", "IN2L", "IN3L"
0595 };
0596
0597 static SOC_ENUM_SINGLE_DECL(linput_enum,
0598                 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
0599
0600 static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
0601                 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
0602
0603 static const char *rinput_mux_text[] = {
0604     "IN1R", "IN2R", "IN3R"
0605 };
0606
0607 static SOC_ENUM_SINGLE_DECL(rinput_enum,
0608                 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
0609
0610 static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
0611                 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
0612
0613
0614 static const char *sidetone_text[] = {
0615     "None", "Left", "Right"
0616 };
0617
0618 static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
0619                 WM8903_DAC_DIGITAL_0, 2, sidetone_text);
0620
0621 static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
0622                 WM8903_DAC_DIGITAL_0, 0, sidetone_text);
0623
0624 static const char *adcinput_text[] = {
0625     "ADC", "DMIC"
0626 };
0627
0628 static SOC_ENUM_SINGLE_DECL(adcinput_enum,
0629                 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
0630
0631 static const char *aif_text[] = {
0632     "Left", "Right"
0633 };
0634
0635 static SOC_ENUM_SINGLE_DECL(lcapture_enum,
0636                 WM8903_AUDIO_INTERFACE_0, 7, aif_text);
0637
0638 static SOC_ENUM_SINGLE_DECL(rcapture_enum,
0639                 WM8903_AUDIO_INTERFACE_0, 6, aif_text);
0640
0641 static SOC_ENUM_SINGLE_DECL(lplay_enum,
0642                 WM8903_AUDIO_INTERFACE_0, 5, aif_text);
0643
0644 static SOC_ENUM_SINGLE_DECL(rplay_enum,
0645                 WM8903_AUDIO_INTERFACE_0, 4, aif_text);
0646
0647 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
0648
0649 /* Input PGAs - No TLV since the scale depends on PGA mode */
0650 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
0651        7, 1, 1),
0652 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
0653        0, 31, 0),
0654 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
0655        6, 1, 0),
0656
0657 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
0658        7, 1, 1),
0659 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
0660        0, 31, 0),
0661 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
0662        6, 1, 0),
0663
0664 /* ADCs */
0665 SOC_ENUM("ADC OSR", adc_osr),
0666 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
0667 SOC_ENUM("HPF Mode", hpf_mode),
0668 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
0669 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
0670 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
0671 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
0672            drc_tlv_thresh),
0673 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
0674 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
0675 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
0676 SOC_ENUM("DRC Attack Rate", drc_attack),
0677 SOC_ENUM("DRC Decay Rate", drc_decay),
0678 SOC_ENUM("DRC FF Delay", drc_ff_delay),
0679 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
0680 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
0681 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
0682 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
0683 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
0684 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
0685 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
0686 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
0687
0688 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
0689          WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
0690 SOC_ENUM("ADC Companding Mode", adc_companding),
0691 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
0692
0693 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
0694            12, 0, digital_sidetone_tlv),
0695
0696 /* DAC */
0697 SOC_ENUM("DAC OSR", dac_osr),
0698 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
0699          WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
0700 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
0701 SOC_ENUM("DAC Mute Mode", mute_mode),
0702 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
0703 SOC_ENUM("DAC Companding Mode", dac_companding),
0704 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
0705 SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
0706            dac_boost_tlv),
0707 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
0708             wm8903_get_deemph, wm8903_put_deemph),
0709
0710 /* Headphones */
0711 SOC_DOUBLE_R("Headphone Switch",
0712          WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
0713          8, 1, 1),
0714 SOC_DOUBLE_R("Headphone ZC Switch",
0715          WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
0716          6, 1, 0),
0717 SOC_DOUBLE_R_TLV("Headphone Volume",
0718          WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
0719          0, 63, 0, out_tlv),
0720
0721 /* Line out */
0722 SOC_DOUBLE_R("Line Out Switch",
0723          WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
0724          8, 1, 1),
0725 SOC_DOUBLE_R("Line Out ZC Switch",
0726          WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
0727          6, 1, 0),
0728 SOC_DOUBLE_R_TLV("Line Out Volume",
0729          WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
0730          0, 63, 0, out_tlv),
0731
0732 /* Speaker */
0733 SOC_DOUBLE_R("Speaker Switch",
0734          WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
0735 SOC_DOUBLE_R("Speaker ZC Switch",
0736          WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
0737 SOC_DOUBLE_R_TLV("Speaker Volume",
0738          WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
0739          0, 63, 0, out_tlv),
0740 };
0741
0742 static const struct snd_kcontrol_new linput_mode_mux =
0743     SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
0744
0745 static const struct snd_kcontrol_new rinput_mode_mux =
0746     SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
0747
0748 static const struct snd_kcontrol_new linput_mux =
0749     SOC_DAPM_ENUM("Left Input Mux", linput_enum);
0750
0751 static const struct snd_kcontrol_new linput_inv_mux =
0752     SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
0753
0754 static const struct snd_kcontrol_new rinput_mux =
0755     SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
0756
0757 static const struct snd_kcontrol_new rinput_inv_mux =
0758     SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
0759
0760 static const struct snd_kcontrol_new lsidetone_mux =
0761     SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
0762
0763 static const struct snd_kcontrol_new rsidetone_mux =
0764     SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
0765
0766 static const struct snd_kcontrol_new adcinput_mux =
0767     SOC_DAPM_ENUM("ADC Input", adcinput_enum);
0768
0769 static const struct snd_kcontrol_new lcapture_mux =
0770     SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
0771
0772 static const struct snd_kcontrol_new rcapture_mux =
0773     SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
0774
0775 static const struct snd_kcontrol_new lplay_mux =
0776     SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
0777
0778 static const struct snd_kcontrol_new rplay_mux =
0779     SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
0780
0781 static const struct snd_kcontrol_new left_output_mixer[] = {
0782 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
0783 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
0784 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
0785 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
0786 };
0787
0788 static const struct snd_kcontrol_new right_output_mixer[] = {
0789 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
0790 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
0791 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
0792 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
0793 };
0794
0795 static const struct snd_kcontrol_new left_speaker_mixer[] = {
0796 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
0797 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
0798 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
0799 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
0800         0, 1, 0),
0801 };
0802
0803 static const struct snd_kcontrol_new right_speaker_mixer[] = {
0804 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
0805 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
0806 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
0807         1, 1, 0),
0808 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
0809         0, 1, 0),
0810 };
0811
0812 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
0813 SND_SOC_DAPM_INPUT("IN1L"),
0814 SND_SOC_DAPM_INPUT("IN1R"),
0815 SND_SOC_DAPM_INPUT("IN2L"),
0816 SND_SOC_DAPM_INPUT("IN2R"),
0817 SND_SOC_DAPM_INPUT("IN3L"),
0818 SND_SOC_DAPM_INPUT("IN3R"),
0819 SND_SOC_DAPM_INPUT("DMICDAT"),
0820
0821 SND_SOC_DAPM_OUTPUT("HPOUTL"),
0822 SND_SOC_DAPM_OUTPUT("HPOUTR"),
0823 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
0824 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
0825 SND_SOC_DAPM_OUTPUT("LOP"),
0826 SND_SOC_DAPM_OUTPUT("LON"),
0827 SND_SOC_DAPM_OUTPUT("ROP"),
0828 SND_SOC_DAPM_OUTPUT("RON"),
0829
0830 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
0831
0832 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
0833 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
0834          &linput_inv_mux),
0835 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
0836
0837 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
0838 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
0839          &rinput_inv_mux),
0840 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
0841
0842 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
0843 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
0844
0845 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
0846 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
0847
0848 SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
0849 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
0850
0851 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
0852 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
0853
0854 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
0855 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
0856
0857 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
0858 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
0859
0860 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
0861 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
0862
0863 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
0864 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
0865
0866 SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
0867 SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
0868
0869 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
0870            left_output_mixer, ARRAY_SIZE(left_output_mixer)),
0871 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
0872            right_output_mixer, ARRAY_SIZE(right_output_mixer)),
0873
0874 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
0875            left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
0876 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
0877            right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
0878
0879 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
0880            1, 0, NULL, 0),
0881 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
0882            0, 0, NULL, 0),
0883
0884 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
0885            NULL, 0),
0886 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
0887            NULL, 0),
0888
0889 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
0890 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
0891 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
0892 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
0893 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
0894 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
0895 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
0896 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
0897
0898 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
0899            NULL, 0),
0900 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
0901            NULL, 0),
0902 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
0903            NULL, 0),
0904 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
0905            NULL, 0),
0906 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
0907            NULL, 0),
0908 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
0909            NULL, 0),
0910 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
0911            NULL, 0),
0912 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
0913            NULL, 0),
0914
0915 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
0916 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
0917            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0918 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
0919            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0920 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
0921            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0922 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
0923            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0924
0925 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
0926          NULL, 0),
0927 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
0928          NULL, 0),
0929
0930 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
0931             wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
0932 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
0933 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
0934 };
0935
0936 static const struct snd_soc_dapm_route wm8903_intercon[] = {
0937
0938     { "CLK_DSP", NULL, "CLK_SYS" },
0939     { "MICBIAS", NULL, "CLK_SYS" },
0940     { "HPL_DCS", NULL, "CLK_SYS" },
0941     { "HPR_DCS", NULL, "CLK_SYS" },
0942     { "LINEOUTL_DCS", NULL, "CLK_SYS" },
0943     { "LINEOUTR_DCS", NULL, "CLK_SYS" },
0944
0945     { "Left Input Mux", "IN1L", "IN1L" },
0946     { "Left Input Mux", "IN2L", "IN2L" },
0947     { "Left Input Mux", "IN3L", "IN3L" },
0948
0949     { "Left Input Inverting Mux", "IN1L", "IN1L" },
0950     { "Left Input Inverting Mux", "IN2L", "IN2L" },
0951     { "Left Input Inverting Mux", "IN3L", "IN3L" },
0952
0953     { "Right Input Mux", "IN1R", "IN1R" },
0954     { "Right Input Mux", "IN2R", "IN2R" },
0955     { "Right Input Mux", "IN3R", "IN3R" },
0956
0957     { "Right Input Inverting Mux", "IN1R", "IN1R" },
0958     { "Right Input Inverting Mux", "IN2R", "IN2R" },
0959     { "Right Input Inverting Mux", "IN3R", "IN3R" },
0960
0961     { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
0962     { "Left Input Mode Mux", "Differential Line",
0963       "Left Input Mux" },
0964     { "Left Input Mode Mux", "Differential Line",
0965       "Left Input Inverting Mux" },
0966     { "Left Input Mode Mux", "Differential Mic",
0967       "Left Input Mux" },
0968     { "Left Input Mode Mux", "Differential Mic",
0969       "Left Input Inverting Mux" },
0970
0971     { "Right Input Mode Mux", "Single-Ended",
0972       "Right Input Inverting Mux" },
0973     { "Right Input Mode Mux", "Differential Line",
0974       "Right Input Mux" },
0975     { "Right Input Mode Mux", "Differential Line",
0976       "Right Input Inverting Mux" },
0977     { "Right Input Mode Mux", "Differential Mic",
0978       "Right Input Mux" },
0979     { "Right Input Mode Mux", "Differential Mic",
0980       "Right Input Inverting Mux" },
0981
0982     { "Left Input PGA", NULL, "Left Input Mode Mux" },
0983     { "Right Input PGA", NULL, "Right Input Mode Mux" },
0984
0985     { "Left ADC Input", "ADC", "Left Input PGA" },
0986     { "Left ADC Input", "DMIC", "DMICDAT" },
0987     { "Right ADC Input", "ADC", "Right Input PGA" },
0988     { "Right ADC Input", "DMIC", "DMICDAT" },
0989
0990     { "Left Capture Mux", "Left", "ADCL" },
0991     { "Left Capture Mux", "Right", "ADCR" },
0992
0993     { "Right Capture Mux", "Left", "ADCL" },
0994     { "Right Capture Mux", "Right", "ADCR" },
0995
0996     { "AIFTXL", NULL, "Left Capture Mux" },
0997     { "AIFTXR", NULL, "Right Capture Mux" },
0998
0999     { "ADCL", NULL, "Left ADC Input" },
1000     { "ADCL", NULL, "CLK_DSP" },
1001     { "ADCR", NULL, "Right ADC Input" },
1002     { "ADCR", NULL, "CLK_DSP" },
1003
1004     { "Left Playback Mux", "Left", "AIFRXL" },
1005     { "Left Playback Mux", "Right", "AIFRXR" },
1006
1007     { "Right Playback Mux", "Left", "AIFRXL" },
1008     { "Right Playback Mux", "Right", "AIFRXR" },
1009
1010     { "DACL Sidetone", "Left", "ADCL" },
1011     { "DACL Sidetone", "Right", "ADCR" },
1012     { "DACR Sidetone", "Left", "ADCL" },
1013     { "DACR Sidetone", "Right", "ADCR" },
1014
1015     { "DACL", NULL, "Left Playback Mux" },
1016     { "DACL", NULL, "DACL Sidetone" },
1017     { "DACL", NULL, "CLK_DSP" },
1018
1019     { "DACR", NULL, "Right Playback Mux" },
1020     { "DACR", NULL, "DACR Sidetone" },
1021     { "DACR", NULL, "CLK_DSP" },
1022
1023     { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1024     { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1025     { "Left Output Mixer", "DACL Switch", "DACL" },
1026     { "Left Output Mixer", "DACR Switch", "DACR" },
1027
1028     { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1029     { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1030     { "Right Output Mixer", "DACL Switch", "DACL" },
1031     { "Right Output Mixer", "DACR Switch", "DACR" },
1032
1033     { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1034     { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1035     { "Left Speaker Mixer", "DACL Switch", "DACL" },
1036     { "Left Speaker Mixer", "DACR Switch", "DACR" },
1037
1038     { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1039     { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1040     { "Right Speaker Mixer", "DACL Switch", "DACL" },
1041     { "Right Speaker Mixer", "DACR Switch", "DACR" },
1042
1043     { "Left Line Output PGA", NULL, "Left Output Mixer" },
1044     { "Right Line Output PGA", NULL, "Right Output Mixer" },
1045
1046     { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1047     { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1048
1049     { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1050     { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1051
1052     { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1053     { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1054     { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1055     { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1056     { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1057     { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1058     { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1059     { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
1060
1061     { "HPL_DCS", NULL, "DCS Master" },
1062     { "HPR_DCS", NULL, "DCS Master" },
1063     { "LINEOUTL_DCS", NULL, "DCS Master" },
1064     { "LINEOUTR_DCS", NULL, "DCS Master" },
1065
1066     { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1067     { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1068     { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1069     { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1070
1071     { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1072     { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1073     { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1074     { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1075
1076     { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1077     { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1078     { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1079     { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1080
1081     { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1082     { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1083     { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1084     { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
1085
1086     { "LOP", NULL, "Left Speaker PGA" },
1087     { "LON", NULL, "Left Speaker PGA" },
1088
1089     { "ROP", NULL, "Right Speaker PGA" },
1090     { "RON", NULL, "Right Speaker PGA" },
1091
1092     { "Charge Pump", NULL, "CLK_DSP" },
1093
1094     { "Left Headphone Output PGA", NULL, "Charge Pump" },
1095     { "Right Headphone Output PGA", NULL, "Charge Pump" },
1096     { "Left Line Output PGA", NULL, "Charge Pump" },
1097     { "Right Line Output PGA", NULL, "Charge Pump" },
1098 };
1099
1100 static int wm8903_set_bias_level(struct snd_soc_component *component,
1101                  enum snd_soc_bias_level level)
1102 {
1103     switch (level) {
1104     case SND_SOC_BIAS_ON:
1105         break;
1106
1107     case SND_SOC_BIAS_PREPARE:
1108         snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1109                     WM8903_VMID_RES_MASK,
1110                     WM8903_VMID_RES_50K);
1111         break;
1112
1113     case SND_SOC_BIAS_STANDBY:
1114         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1115             snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
1116                         WM8903_POBCTRL | WM8903_ISEL_MASK |
1117                         WM8903_STARTUP_BIAS_ENA |
1118                         WM8903_BIAS_ENA,
1119                         WM8903_POBCTRL |
1120                         (2 << WM8903_ISEL_SHIFT) |
1121                         WM8903_STARTUP_BIAS_ENA);
1122
1123             snd_soc_component_update_bits(component,
1124                         WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1125                         WM8903_SPK_DISCHARGE,
1126                         WM8903_SPK_DISCHARGE);
1127
1128             msleep(33);
1129
1130             snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,
1131                         WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1132                         WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1133
1134             snd_soc_component_update_bits(component,
1135                         WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1136                         WM8903_SPK_DISCHARGE, 0);
1137
1138             snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1139                         WM8903_VMID_TIE_ENA |
1140                         WM8903_BUFIO_ENA |
1141                         WM8903_VMID_IO_ENA |
1142                         WM8903_VMID_SOFT_MASK |
1143                         WM8903_VMID_RES_MASK |
1144                         WM8903_VMID_BUF_ENA,
1145                         WM8903_VMID_TIE_ENA |
1146                         WM8903_BUFIO_ENA |
1147                         WM8903_VMID_IO_ENA |
1148                         (2 << WM8903_VMID_SOFT_SHIFT) |
1149                         WM8903_VMID_RES_250K |
1150                         WM8903_VMID_BUF_ENA);
1151
1152             msleep(129);
1153
1154             snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,
1155                         WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1156                         0);
1157
1158             snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1159                         WM8903_VMID_SOFT_MASK, 0);
1160
1161             snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1162                         WM8903_VMID_RES_MASK,
1163                         WM8903_VMID_RES_50K);
1164
1165             snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
1166                         WM8903_BIAS_ENA | WM8903_POBCTRL,
1167                         WM8903_BIAS_ENA);
1168
1169             /* By default no bypass paths are enabled so
1170              * enable Class W support.
1171              */
1172             dev_dbg(component->dev, "Enabling Class W\n");
1173             snd_soc_component_update_bits(component, WM8903_CLASS_W_0,
1174                         WM8903_CP_DYN_FREQ |
1175                         WM8903_CP_DYN_V,
1176                         WM8903_CP_DYN_FREQ |
1177                         WM8903_CP_DYN_V);
1178         }
1179
1180         snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1181                     WM8903_VMID_RES_MASK,
1182                     WM8903_VMID_RES_250K);
1183         break;
1184
1185     case SND_SOC_BIAS_OFF:
1186         snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
1187                     WM8903_BIAS_ENA, 0);
1188
1189         snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1190                     WM8903_VMID_SOFT_MASK,
1191                     2 << WM8903_VMID_SOFT_SHIFT);
1192
1193         snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1194                     WM8903_VMID_BUF_ENA, 0);
1195
1196         msleep(290);
1197
1198         snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,
1199                     WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1200                     WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1201                     WM8903_VMID_SOFT_MASK |
1202                     WM8903_VMID_BUF_ENA, 0);
1203
1204         snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,
1205                     WM8903_STARTUP_BIAS_ENA, 0);
1206         break;
1207     }
1208
1209     return 0;
1210 }
1211
1212 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1213                  int clk_id, unsigned int freq, int dir)
1214 {
1215     struct snd_soc_component *component = codec_dai->component;
1216     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
1217
1218     wm8903->sysclk = freq;
1219
1220     return 0;
1221 }
1222
1223 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1224                   unsigned int fmt)
1225 {
1226     struct snd_soc_component *component = codec_dai->component;
1227     u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);
1228
1229     aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1230           WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1231
1232     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1233     case SND_SOC_DAIFMT_CBS_CFS:
1234         break;
1235     case SND_SOC_DAIFMT_CBS_CFM:
1236         aif1 |= WM8903_LRCLK_DIR;
1237         break;
1238     case SND_SOC_DAIFMT_CBM_CFM:
1239         aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1240         break;
1241     case SND_SOC_DAIFMT_CBM_CFS:
1242         aif1 |= WM8903_BCLK_DIR;
1243         break;
1244     default:
1245         return -EINVAL;
1246     }
1247
1248     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1249     case SND_SOC_DAIFMT_DSP_A:
1250         aif1 |= 0x3;
1251         break;
1252     case SND_SOC_DAIFMT_DSP_B:
1253         aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1254         break;
1255     case SND_SOC_DAIFMT_I2S:
1256         aif1 |= 0x2;
1257         break;
1258     case SND_SOC_DAIFMT_RIGHT_J:
1259         aif1 |= 0x1;
1260         break;
1261     case SND_SOC_DAIFMT_LEFT_J:
1262         break;
1263     default:
1264         return -EINVAL;
1265     }
1266
1267     /* Clock inversion */
1268     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1269     case SND_SOC_DAIFMT_DSP_A:
1270     case SND_SOC_DAIFMT_DSP_B:
1271         /* frame inversion not valid for DSP modes */
1272         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1273         case SND_SOC_DAIFMT_NB_NF:
1274             break;
1275         case SND_SOC_DAIFMT_IB_NF:
1276             aif1 |= WM8903_AIF_BCLK_INV;
1277             break;
1278         default:
1279             return -EINVAL;
1280         }
1281         break;
1282     case SND_SOC_DAIFMT_I2S:
1283     case SND_SOC_DAIFMT_RIGHT_J:
1284     case SND_SOC_DAIFMT_LEFT_J:
1285         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1286         case SND_SOC_DAIFMT_NB_NF:
1287             break;
1288         case SND_SOC_DAIFMT_IB_IF:
1289             aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1290             break;
1291         case SND_SOC_DAIFMT_IB_NF:
1292             aif1 |= WM8903_AIF_BCLK_INV;
1293             break;
1294         case SND_SOC_DAIFMT_NB_IF:
1295             aif1 |= WM8903_AIF_LRCLK_INV;
1296             break;
1297         default:
1298             return -EINVAL;
1299         }
1300         break;
1301     default:
1302         return -EINVAL;
1303     }
1304
1305     snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);
1306
1307     return 0;
1308 }
1309
1310 static int wm8903_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1311 {
1312     struct snd_soc_component *component = codec_dai->component;
1313     u16 reg;
1314
1315     reg = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);
1316
1317     if (mute)
1318         reg |= WM8903_DAC_MUTE;
1319     else
1320         reg &= ~WM8903_DAC_MUTE;
1321
1322     snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg);
1323
1324     return 0;
1325 }
1326
1327 /* Lookup table for CLK_SYS/fs ratio.  256fs or more is recommended
1328  * for optimal performance so we list the lower rates first and match
1329  * on the last match we find. */
1330 static struct {
1331     int div;
1332     int rate;
1333     int mode;
1334     int mclk_div;
1335 } clk_sys_ratios[] = {
1336     {   64, 0x0, 0x0, 1 },
1337     {   68, 0x0, 0x1, 1 },
1338     {  125, 0x0, 0x2, 1 },
1339     {  128, 0x1, 0x0, 1 },
1340     {  136, 0x1, 0x1, 1 },
1341     {  192, 0x2, 0x0, 1 },
1342     {  204, 0x2, 0x1, 1 },
1343
1344     {   64, 0x0, 0x0, 2 },
1345     {   68, 0x0, 0x1, 2 },
1346     {  125, 0x0, 0x2, 2 },
1347     {  128, 0x1, 0x0, 2 },
1348     {  136, 0x1, 0x1, 2 },
1349     {  192, 0x2, 0x0, 2 },
1350     {  204, 0x2, 0x1, 2 },
1351
1352     {  250, 0x2, 0x2, 1 },
1353     {  256, 0x3, 0x0, 1 },
1354     {  272, 0x3, 0x1, 1 },
1355     {  384, 0x4, 0x0, 1 },
1356     {  408, 0x4, 0x1, 1 },
1357     {  375, 0x4, 0x2, 1 },
1358     {  512, 0x5, 0x0, 1 },
1359     {  544, 0x5, 0x1, 1 },
1360     {  500, 0x5, 0x2, 1 },
1361     {  768, 0x6, 0x0, 1 },
1362     {  816, 0x6, 0x1, 1 },
1363     {  750, 0x6, 0x2, 1 },
1364     { 1024, 0x7, 0x0, 1 },
1365     { 1088, 0x7, 0x1, 1 },
1366     { 1000, 0x7, 0x2, 1 },
1367     { 1408, 0x8, 0x0, 1 },
1368     { 1496, 0x8, 0x1, 1 },
1369     { 1536, 0x9, 0x0, 1 },
1370     { 1632, 0x9, 0x1, 1 },
1371     { 1500, 0x9, 0x2, 1 },
1372
1373     {  250, 0x2, 0x2, 2 },
1374     {  256, 0x3, 0x0, 2 },
1375     {  272, 0x3, 0x1, 2 },
1376     {  384, 0x4, 0x0, 2 },
1377     {  408, 0x4, 0x1, 2 },
1378     {  375, 0x4, 0x2, 2 },
1379     {  512, 0x5, 0x0, 2 },
1380     {  544, 0x5, 0x1, 2 },
1381     {  500, 0x5, 0x2, 2 },
1382     {  768, 0x6, 0x0, 2 },
1383     {  816, 0x6, 0x1, 2 },
1384     {  750, 0x6, 0x2, 2 },
1385     { 1024, 0x7, 0x0, 2 },
1386     { 1088, 0x7, 0x1, 2 },
1387     { 1000, 0x7, 0x2, 2 },
1388     { 1408, 0x8, 0x0, 2 },
1389     { 1496, 0x8, 0x1, 2 },
1390     { 1536, 0x9, 0x0, 2 },
1391     { 1632, 0x9, 0x1, 2 },
1392     { 1500, 0x9, 0x2, 2 },
1393 };
1394
1395 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1396 static struct {
1397     int ratio;
1398     int div;
1399 } bclk_divs[] = {
1400     {  10,  0 },
1401     {  20,  2 },
1402     {  30,  3 },
1403     {  40,  4 },
1404     {  50,  5 },
1405     {  60,  7 },
1406     {  80,  8 },
1407     { 100,  9 },
1408     { 120, 11 },
1409     { 160, 12 },
1410     { 200, 13 },
1411     { 220, 14 },
1412     { 240, 15 },
1413     { 300, 17 },
1414     { 320, 18 },
1415     { 440, 19 },
1416     { 480, 20 },
1417 };
1418
1419 /* Sample rates for DSP */
1420 static struct {
1421     int rate;
1422     int value;
1423 } sample_rates[] = {
1424     {  8000,  0 },
1425     { 11025,  1 },
1426     { 12000,  2 },
1427     { 16000,  3 },
1428     { 22050,  4 },
1429     { 24000,  5 },
1430     { 32000,  6 },
1431     { 44100,  7 },
1432     { 48000,  8 },
1433     { 88200,  9 },
1434     { 96000, 10 },
1435     { 0,      0 },
1436 };
1437
1438 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1439                 struct snd_pcm_hw_params *params,
1440                 struct snd_soc_dai *dai)
1441 {
1442     struct snd_soc_component *component = dai->component;
1443     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
1444     int fs = params_rate(params);
1445     int bclk;
1446     int bclk_div;
1447     int i;
1448     int dsp_config;
1449     int clk_config;
1450     int best_val;
1451     int cur_val;
1452     int clk_sys;
1453
1454     u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);
1455     u16 aif2 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_2);
1456     u16 aif3 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_3);
1457     u16 clock0 = snd_soc_component_read(component, WM8903_CLOCK_RATES_0);
1458     u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1);
1459     u16 dac_digital1 = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);
1460
1461     /* Enable sloping stopband filter for low sample rates */
1462     if (fs <= 24000)
1463         dac_digital1 |= WM8903_DAC_SB_FILT;
1464     else
1465         dac_digital1 &= ~WM8903_DAC_SB_FILT;
1466
1467     /* Configure sample rate logic for DSP - choose nearest rate */
1468     dsp_config = 0;
1469     best_val = abs(sample_rates[dsp_config].rate - fs);
1470     for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1471         cur_val = abs(sample_rates[i].rate - fs);
1472         if (cur_val <= best_val) {
1473             dsp_config = i;
1474             best_val = cur_val;
1475         }
1476     }
1477
1478     dev_dbg(component->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1479     clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1480     clock1 |= sample_rates[dsp_config].value;
1481
1482     aif1 &= ~WM8903_AIF_WL_MASK;
1483     bclk = 2 * fs;
1484     switch (params_width(params)) {
1485     case 16:
1486         bclk *= 16;
1487         break;
1488     case 20:
1489         bclk *= 20;
1490         aif1 |= 0x4;
1491         break;
1492     case 24:
1493         bclk *= 24;
1494         aif1 |= 0x8;
1495         break;
1496     case 32:
1497         bclk *= 32;
1498         aif1 |= 0xc;
1499         break;
1500     default:
1501         return -EINVAL;
1502     }
1503
1504     dev_dbg(component->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1505         wm8903->sysclk, fs);
1506
1507     /* We may not have an MCLK which allows us to generate exactly
1508      * the clock we want, particularly with USB derived inputs, so
1509      * approximate.
1510      */
1511     clk_config = 0;
1512     best_val = abs((wm8903->sysclk /
1513             (clk_sys_ratios[0].mclk_div *
1514              clk_sys_ratios[0].div)) - fs);
1515     for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1516         cur_val = abs((wm8903->sysclk /
1517                    (clk_sys_ratios[i].mclk_div *
1518                 clk_sys_ratios[i].div)) - fs);
1519
1520         if (cur_val <= best_val) {
1521             clk_config = i;
1522             best_val = cur_val;
1523         }
1524     }
1525
1526     if (clk_sys_ratios[clk_config].mclk_div == 2) {
1527         clock0 |= WM8903_MCLKDIV2;
1528         clk_sys = wm8903->sysclk / 2;
1529     } else {
1530         clock0 &= ~WM8903_MCLKDIV2;
1531         clk_sys = wm8903->sysclk;
1532     }
1533
1534     clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1535             WM8903_CLK_SYS_MODE_MASK);
1536     clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1537     clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1538
1539     dev_dbg(component->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1540         clk_sys_ratios[clk_config].rate,
1541         clk_sys_ratios[clk_config].mode,
1542         clk_sys_ratios[clk_config].div);
1543
1544     dev_dbg(component->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1545
1546     /* We may not get quite the right frequency if using
1547      * approximate clocks so look for the closest match that is
1548      * higher than the target (we need to ensure that there enough
1549      * BCLKs to clock out the samples).
1550      */
1551     bclk_div = 0;
1552     i = 1;
1553     while (i < ARRAY_SIZE(bclk_divs)) {
1554         cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1555         if (cur_val < 0) /* BCLK table is sorted */
1556             break;
1557         bclk_div = i;
1558         i++;
1559     }
1560
1561     aif2 &= ~WM8903_BCLK_DIV_MASK;
1562     aif3 &= ~WM8903_LRCLK_RATE_MASK;
1563
1564     dev_dbg(component->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1565         bclk_divs[bclk_div].ratio / 10, bclk,
1566         (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1567
1568     aif2 |= bclk_divs[bclk_div].div;
1569     aif3 |= bclk / fs;
1570
1571     wm8903->fs = params_rate(params);
1572     wm8903_set_deemph(component);
1573
1574     snd_soc_component_write(component, WM8903_CLOCK_RATES_0, clock0);
1575     snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1);
1576     snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);
1577     snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_2, aif2);
1578     snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_3, aif3);
1579     snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, dac_digital1);
1580
1581     return 0;
1582 }
1583
1584 /**
1585  * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1586  *
1587  * @component:  WM8903 component
1588  * @jack:   jack to report detection events on
1589  * @det:    value to report for presence detection
1590  * @shrt:   value to report for short detection
1591  *
1592  * Enable microphone detection via IRQ on the WM8903.  If GPIOs are
1593  * being used to bring out signals to the processor then only platform
1594  * data configuration is needed for WM8903 and processor GPIOs should
1595  * be configured using snd_soc_jack_add_gpios() instead.
1596  *
1597  * The current threasholds for detection should be configured using
1598  * micdet_cfg in the platform data.  Using this function will force on
1599  * the microphone bias for the device.
1600  */
1601 int wm8903_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
1602               int det, int shrt)
1603 {
1604     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
1605     int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1606
1607     dev_dbg(component->dev, "Enabling microphone detection: %x %x\n",
1608         det, shrt);
1609
1610     /* Store the configuration */
1611     wm8903->mic_jack = jack;
1612     wm8903->mic_det = det;
1613     wm8903->mic_short = shrt;
1614
1615     /* Enable interrupts we've got a report configured for */
1616     if (det)
1617         irq_mask &= ~WM8903_MICDET_EINT;
1618     if (shrt)
1619         irq_mask &= ~WM8903_MICSHRT_EINT;
1620
1621     snd_soc_component_update_bits(component, WM8903_INTERRUPT_STATUS_1_MASK,
1622                 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1623                 irq_mask);
1624
1625     if (det || shrt) {
1626         /* Enable mic detection, this may not have been set through
1627          * platform data (eg, if the defaults are OK). */
1628         snd_soc_component_update_bits(component, WM8903_WRITE_SEQUENCER_0,
1629                     WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1630         snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,
1631                     WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1632     } else {
1633         snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,
1634                     WM8903_MICDET_ENA, 0);
1635     }
1636
1637     return 0;
1638 }
1639 EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1640
1641 static irqreturn_t wm8903_irq(int irq, void *data)
1642 {
1643     struct wm8903_priv *wm8903 = data;
1644     int mic_report, ret;
1645     unsigned int int_val, mask, int_pol;
1646
1647     ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
1648               &mask);
1649     if (ret != 0) {
1650         dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
1651         return IRQ_NONE;
1652     }
1653
1654     ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
1655     if (ret != 0) {
1656         dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
1657         return IRQ_NONE;
1658     }
1659
1660     int_val &= ~mask;
1661
1662     if (int_val & WM8903_WSEQ_BUSY_EINT) {
1663         dev_warn(wm8903->dev, "Write sequencer done\n");
1664     }
1665
1666     /*
1667      * The rest is microphone jack detection.  We need to manually
1668      * invert the polarity of the interrupt after each event - to
1669      * simplify the code keep track of the last state we reported
1670      * and just invert the relevant bits in both the report and
1671      * the polarity register.
1672      */
1673     mic_report = wm8903->mic_last_report;
1674     ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1675               &int_pol);
1676     if (ret != 0) {
1677         dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
1678             ret);
1679         return IRQ_HANDLED;
1680     }
1681
1682 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1683     if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1684         trace_snd_soc_jack_irq(dev_name(wm8903->dev));
1685 #endif
1686
1687     if (int_val & WM8903_MICSHRT_EINT) {
1688         dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
1689
1690         mic_report ^= wm8903->mic_short;
1691         int_pol ^= WM8903_MICSHRT_INV;
1692     }
1693
1694     if (int_val & WM8903_MICDET_EINT) {
1695         dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
1696
1697         mic_report ^= wm8903->mic_det;
1698         int_pol ^= WM8903_MICDET_INV;
1699
1700         msleep(wm8903->mic_delay);
1701     }
1702
1703     regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1704                WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1705
1706     snd_soc_jack_report(wm8903->mic_jack, mic_report,
1707                 wm8903->mic_short | wm8903->mic_det);
1708
1709     wm8903->mic_last_report = mic_report;
1710
1711     return IRQ_HANDLED;
1712 }
1713
1714 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1715                    SNDRV_PCM_RATE_11025 |   \
1716                    SNDRV_PCM_RATE_16000 |   \
1717                    SNDRV_PCM_RATE_22050 |   \
1718                    SNDRV_PCM_RATE_32000 |   \
1719                    SNDRV_PCM_RATE_44100 |   \
1720                    SNDRV_PCM_RATE_48000 |   \
1721                    SNDRV_PCM_RATE_88200 |   \
1722                    SNDRV_PCM_RATE_96000)
1723
1724 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1725                   SNDRV_PCM_RATE_11025 |    \
1726                   SNDRV_PCM_RATE_16000 |    \
1727                   SNDRV_PCM_RATE_22050 |    \
1728                   SNDRV_PCM_RATE_32000 |    \
1729                   SNDRV_PCM_RATE_44100 |    \
1730                   SNDRV_PCM_RATE_48000)
1731
1732 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1733             SNDRV_PCM_FMTBIT_S20_3LE |\
1734             SNDRV_PCM_FMTBIT_S24_LE)
1735
1736 static const struct snd_soc_dai_ops wm8903_dai_ops = {
1737     .hw_params  = wm8903_hw_params,
1738     .mute_stream    = wm8903_mute,
1739     .set_fmt    = wm8903_set_dai_fmt,
1740     .set_sysclk = wm8903_set_dai_sysclk,
1741     .no_capture_mute = 1,
1742 };
1743
1744 static struct snd_soc_dai_driver wm8903_dai = {
1745     .name = "wm8903-hifi",
1746     .playback = {
1747         .stream_name = "Playback",
1748         .channels_min = 2,
1749         .channels_max = 2,
1750         .rates = WM8903_PLAYBACK_RATES,
1751         .formats = WM8903_FORMATS,
1752     },
1753     .capture = {
1754          .stream_name = "Capture",
1755          .channels_min = 2,
1756          .channels_max = 2,
1757          .rates = WM8903_CAPTURE_RATES,
1758          .formats = WM8903_FORMATS,
1759      },
1760     .ops = &wm8903_dai_ops,
1761     .symmetric_rate = 1,
1762 };
1763
1764 static int wm8903_resume(struct snd_soc_component *component)
1765 {
1766     struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);
1767
1768     regcache_sync(wm8903->regmap);
1769
1770     return 0;
1771 }
1772
1773 #ifdef CONFIG_GPIOLIB
1774 static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1775 {
1776     if (offset >= WM8903_NUM_GPIO)
1777         return -EINVAL;
1778
1779     return 0;
1780 }
1781
1782 static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1783 {
1784     struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1785     unsigned int mask, val;
1786     int ret;
1787
1788     mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1789     val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1790         WM8903_GP1_DIR;
1791
1792     ret = regmap_update_bits(wm8903->regmap,
1793                  WM8903_GPIO_CONTROL_1 + offset, mask, val);
1794     if (ret < 0)
1795         return ret;
1796
1797     return 0;
1798 }
1799
1800 static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1801 {
1802     struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1803     unsigned int reg;
1804
1805     regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, &reg);
1806
1807     return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT);
1808 }
1809
1810 static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1811                      unsigned offset, int value)
1812 {
1813     struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1814     unsigned int mask, val;
1815     int ret;
1816
1817     mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1818     val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1819         (value << WM8903_GP2_LVL_SHIFT);
1820
1821     ret = regmap_update_bits(wm8903->regmap,
1822                  WM8903_GPIO_CONTROL_1 + offset, mask, val);
1823     if (ret < 0)
1824         return ret;
1825
1826     return 0;
1827 }
1828
1829 static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1830 {
1831     struct wm8903_priv *wm8903 = gpiochip_get_data(chip);
1832
1833     regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
1834                WM8903_GP1_LVL_MASK,
1835                !!value << WM8903_GP1_LVL_SHIFT);
1836 }
1837
1838 static const struct gpio_chip wm8903_template_chip = {
1839     .label          = "wm8903",
1840     .owner          = THIS_MODULE,
1841     .request        = wm8903_gpio_request,
1842     .direction_input    = wm8903_gpio_direction_in,
1843     .get            = wm8903_gpio_get,
1844     .direction_output   = wm8903_gpio_direction_out,
1845     .set            = wm8903_gpio_set,
1846     .can_sleep      = 1,
1847 };
1848
1849 static void wm8903_init_gpio(struct wm8903_priv *wm8903)
1850 {
1851     struct wm8903_platform_data *pdata = wm8903->pdata;
1852     int ret;
1853
1854     wm8903->gpio_chip = wm8903_template_chip;
1855     wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1856     wm8903->gpio_chip.parent = wm8903->dev;
1857
1858     if (pdata->gpio_base)
1859         wm8903->gpio_chip.base = pdata->gpio_base;
1860     else
1861         wm8903->gpio_chip.base = -1;
1862
1863     ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903);
1864     if (ret != 0)
1865         dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
1866 }
1867
1868 static void wm8903_free_gpio(struct wm8903_priv *wm8903)
1869 {
1870     gpiochip_remove(&wm8903->gpio_chip);
1871 }
1872 #else
1873 static void wm8903_init_gpio(struct wm8903_priv *wm8903)
1874 {
1875 }
1876
1877 static void wm8903_free_gpio(struct wm8903_priv *wm8903)
1878 {
1879 }
1880 #endif
1881
1882 static const struct snd_soc_component_driver soc_component_dev_wm8903 = {
1883     .resume         = wm8903_resume,
1884     .set_bias_level     = wm8903_set_bias_level,
1885     .seq_notifier       = wm8903_seq_notifier,
1886     .controls       = wm8903_snd_controls,
1887     .num_controls       = ARRAY_SIZE(wm8903_snd_controls),
1888     .dapm_widgets       = wm8903_dapm_widgets,
1889     .num_dapm_widgets   = ARRAY_SIZE(wm8903_dapm_widgets),
1890     .dapm_routes        = wm8903_intercon,
1891     .num_dapm_routes    = ARRAY_SIZE(wm8903_intercon),
1892     .suspend_bias_off   = 1,
1893     .idle_bias_on       = 1,
1894     .use_pmdown_time    = 1,
1895     .endianness     = 1,
1896 };
1897
1898 static const struct regmap_config wm8903_regmap = {
1899     .reg_bits = 8,
1900     .val_bits = 16,
1901
1902     .max_register = WM8903_MAX_REGISTER,
1903     .volatile_reg = wm8903_volatile_register,
1904     .readable_reg = wm8903_readable_register,
1905
1906     .cache_type = REGCACHE_RBTREE,
1907     .reg_defaults = wm8903_reg_defaults,
1908     .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
1909 };
1910
1911 static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
1912                     struct wm8903_platform_data *pdata)
1913 {
1914     struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
1915     if (!irq_data) {
1916         dev_err(&i2c->dev, "Invalid IRQ: %d\n",
1917             i2c->irq);
1918         return -EINVAL;
1919     }
1920
1921     switch (irqd_get_trigger_type(irq_data)) {
1922     case IRQ_TYPE_NONE:
1923     default:
1924         /*
1925         * We assume the controller imposes no restrictions,
1926         * so we are able to select active-high
1927         */
1928         fallthrough;
1929     case IRQ_TYPE_LEVEL_HIGH:
1930         pdata->irq_active_low = false;
1931         break;
1932     case IRQ_TYPE_LEVEL_LOW:
1933         pdata->irq_active_low = true;
1934         break;
1935     }
1936
1937     return 0;
1938 }
1939
1940 static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
1941                     struct wm8903_platform_data *pdata)
1942 {
1943     const struct device_node *np = i2c->dev.of_node;
1944     u32 val32;
1945     int i;
1946
1947     if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
1948         pdata->micdet_cfg = val32;
1949
1950     if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
1951         pdata->micdet_delay = val32;
1952
1953     if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
1954                        ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
1955         /*
1956          * In device tree: 0 means "write 0",
1957          * 0xffffffff means "don't touch".
1958          *
1959          * In platform data: 0 means "don't touch",
1960          * 0x8000 means "write 0".
1961          *
1962          * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
1963          *
1964          *  Convert from DT to pdata representation here,
1965          * so no other code needs to change.
1966          */
1967         for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1968             if (pdata->gpio_cfg[i] == 0) {
1969                 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
1970             } else if (pdata->gpio_cfg[i] == 0xffffffff) {
1971                 pdata->gpio_cfg[i] = 0;
1972             } else if (pdata->gpio_cfg[i] > 0x7fff) {
1973                 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
1974                     i, pdata->gpio_cfg[i]);
1975                 return -EINVAL;
1976             }
1977         }
1978     }
1979
1980     return 0;
1981 }
1982
1983 static int wm8903_i2c_probe(struct i2c_client *i2c)
1984 {
1985     struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
1986     struct wm8903_priv *wm8903;
1987     int trigger;
1988     bool mic_gpio = false;
1989     unsigned int val, irq_pol;
1990     int ret, i;
1991
1992     wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL);
1993     if (wm8903 == NULL)
1994         return -ENOMEM;
1995
1996     mutex_init(&wm8903->lock);
1997     wm8903->dev = &i2c->dev;
1998
1999     wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
2000     if (IS_ERR(wm8903->regmap)) {
2001         ret = PTR_ERR(wm8903->regmap);
2002         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2003             ret);
2004         return ret;
2005     }
2006
2007     i2c_set_clientdata(i2c, wm8903);
2008
2009     /* If no platform data was supplied, create storage for defaults */
2010     if (pdata) {
2011         wm8903->pdata = pdata;
2012     } else {
2013         wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata),
2014                          GFP_KERNEL);
2015         if (!wm8903->pdata)
2016             return -ENOMEM;
2017
2018         if (i2c->irq) {
2019             ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
2020             if (ret != 0)
2021                 return ret;
2022         }
2023
2024         if (i2c->dev.of_node) {
2025             ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
2026             if (ret != 0)
2027                 return ret;
2028         }
2029     }
2030
2031     pdata = wm8903->pdata;
2032
2033     for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++)
2034         wm8903->supplies[i].supply = wm8903_supply_names[i];
2035
2036     ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies),
2037                       wm8903->supplies);
2038     if (ret != 0) {
2039         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2040         return ret;
2041     }
2042
2043     ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies),
2044                     wm8903->supplies);
2045     if (ret != 0) {
2046         dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2047         return ret;
2048     }
2049
2050     ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2051     if (ret != 0) {
2052         dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2053         goto err;
2054     }
2055     if (val != 0x8903) {
2056         dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2057         ret = -ENODEV;
2058         goto err;
2059     }
2060
2061     ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2062     if (ret != 0) {
2063         dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2064         goto err;
2065     }
2066     dev_info(&i2c->dev, "WM8903 revision %c\n",
2067          (val & WM8903_CHIP_REV_MASK) + 'A');
2068
2069     /* Reset the device */
2070     regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2071
2072     wm8903_init_gpio(wm8903);
2073
2074     /* Set up GPIO pin state, detect if any are MIC detect outputs */
2075     for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
2076         if ((!pdata->gpio_cfg[i]) ||
2077             (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
2078             continue;
2079
2080         regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
2081                 pdata->gpio_cfg[i] & 0x7fff);
2082
2083         val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
2084             >> WM8903_GP1_FN_SHIFT;
2085
2086         switch (val) {
2087         case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
2088         case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
2089             mic_gpio = true;
2090             break;
2091         default:
2092             break;
2093         }
2094     }
2095
2096     /* Set up microphone detection */
2097     regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
2098              pdata->micdet_cfg);
2099
2100     /* Microphone detection needs the WSEQ clock */
2101     if (pdata->micdet_cfg)
2102         regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
2103                    WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
2104
2105     /* If microphone detection is enabled by pdata but
2106      * detected via IRQ then interrupts can be lost before
2107      * the machine driver has set up microphone detection
2108      * IRQs as the IRQs are clear on read.  The detection
2109      * will be enabled when the machine driver configures.
2110      */
2111     WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
2112
2113     wm8903->mic_delay = pdata->micdet_delay;
2114
2115     if (i2c->irq) {
2116         if (pdata->irq_active_low) {
2117             trigger = IRQF_TRIGGER_LOW;
2118             irq_pol = WM8903_IRQ_POL;
2119         } else {
2120             trigger = IRQF_TRIGGER_HIGH;
2121             irq_pol = 0;
2122         }
2123
2124         regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
2125                    WM8903_IRQ_POL, irq_pol);
2126
2127         ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
2128                        trigger | IRQF_ONESHOT,
2129                        "wm8903", wm8903);
2130         if (ret != 0) {
2131             dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
2132                 ret);
2133             goto err;
2134         }
2135
2136         /* Enable write sequencer interrupts */
2137         regmap_update_bits(wm8903->regmap,
2138                    WM8903_INTERRUPT_STATUS_1_MASK,
2139                    WM8903_IM_WSEQ_BUSY_EINT, 0);
2140     }
2141
2142     /* Latch volume update bits */
2143     regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
2144                WM8903_ADCVU, WM8903_ADCVU);
2145     regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
2146                WM8903_ADCVU, WM8903_ADCVU);
2147
2148     regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
2149                WM8903_DACVU, WM8903_DACVU);
2150     regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
2151                WM8903_DACVU, WM8903_DACVU);
2152
2153     regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
2154                WM8903_HPOUTVU, WM8903_HPOUTVU);
2155     regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
2156                WM8903_HPOUTVU, WM8903_HPOUTVU);
2157
2158     regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
2159                WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2160     regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
2161                WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2162
2163     regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
2164                WM8903_SPKVU, WM8903_SPKVU);
2165     regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
2166                WM8903_SPKVU, WM8903_SPKVU);
2167
2168     /* Enable DAC soft mute by default */
2169     regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
2170                WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2171                WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
2172
2173     ret = devm_snd_soc_register_component(&i2c->dev,
2174             &soc_component_dev_wm8903, &wm8903_dai, 1);
2175     if (ret != 0)
2176         goto err;
2177
2178     return 0;
2179 err:
2180     regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
2181                    wm8903->supplies);
2182     return ret;
2183 }
2184
2185 static int wm8903_i2c_remove(struct i2c_client *client)
2186 {
2187     struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2188
2189     regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),
2190                    wm8903->supplies);
2191     if (client->irq)
2192         free_irq(client->irq, wm8903);
2193     wm8903_free_gpio(wm8903);
2194
2195     return 0;
2196 }
2197
2198 static const struct of_device_id wm8903_of_match[] = {
2199     { .compatible = "wlf,wm8903", },
2200     {},
2201 };
2202 MODULE_DEVICE_TABLE(of, wm8903_of_match);
2203
2204 static const struct i2c_device_id wm8903_i2c_id[] = {
2205     { "wm8903", 0 },
2206     { }
2207 };
2208 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2209
2210 static struct i2c_driver wm8903_i2c_driver = {
2211     .driver = {
2212         .name = "wm8903",
2213         .of_match_table = wm8903_of_match,
2214     },
2215     .probe_new = wm8903_i2c_probe,
2216     .remove =   wm8903_i2c_remove,
2217     .id_table = wm8903_i2c_id,
2218 };
2219
2220 module_i2c_driver(wm8903_i2c_driver);
2221
2222 MODULE_DESCRIPTION("ASoC WM8903 driver");
2223 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2224 MODULE_LICENSE("GPL");