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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8900.c  --  WM8900 ALSA Soc Audio driver
0004  *
0005  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  *
0009  * TODO:
0010  *  - Tristating.
0011  *  - TDM.
0012  *  - Jack detect.
0013  *  - FLL source configuration, currently only MCLK is supported.
0014  */
0015 
0016 #include <linux/module.h>
0017 #include <linux/moduleparam.h>
0018 #include <linux/kernel.h>
0019 #include <linux/init.h>
0020 #include <linux/delay.h>
0021 #include <linux/pm.h>
0022 #include <linux/i2c.h>
0023 #include <linux/regmap.h>
0024 #include <linux/spi/spi.h>
0025 #include <linux/slab.h>
0026 #include <sound/core.h>
0027 #include <sound/pcm.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/soc.h>
0030 #include <sound/initval.h>
0031 #include <sound/tlv.h>
0032 
0033 #include "wm8900.h"
0034 
0035 /* WM8900 register space */
0036 #define WM8900_REG_RESET    0x0
0037 #define WM8900_REG_ID       0x0
0038 #define WM8900_REG_POWER1   0x1
0039 #define WM8900_REG_POWER2   0x2
0040 #define WM8900_REG_POWER3   0x3
0041 #define WM8900_REG_AUDIO1   0x4
0042 #define WM8900_REG_AUDIO2   0x5
0043 #define WM8900_REG_CLOCKING1    0x6
0044 #define WM8900_REG_CLOCKING2    0x7
0045 #define WM8900_REG_AUDIO3       0x8
0046 #define WM8900_REG_AUDIO4       0x9
0047 #define WM8900_REG_DACCTRL      0xa
0048 #define WM8900_REG_LDAC_DV      0xb
0049 #define WM8900_REG_RDAC_DV      0xc
0050 #define WM8900_REG_SIDETONE     0xd
0051 #define WM8900_REG_ADCCTRL      0xe
0052 #define WM8900_REG_LADC_DV  0xf
0053 #define WM8900_REG_RADC_DV      0x10
0054 #define WM8900_REG_GPIO         0x12
0055 #define WM8900_REG_INCTL    0x15
0056 #define WM8900_REG_LINVOL   0x16
0057 #define WM8900_REG_RINVOL   0x17
0058 #define WM8900_REG_INBOOSTMIX1  0x18
0059 #define WM8900_REG_INBOOSTMIX2  0x19
0060 #define WM8900_REG_ADCPATH  0x1a
0061 #define WM8900_REG_AUXBOOST 0x1b
0062 #define WM8900_REG_ADDCTL       0x1e
0063 #define WM8900_REG_FLLCTL1      0x24
0064 #define WM8900_REG_FLLCTL2      0x25
0065 #define WM8900_REG_FLLCTL3      0x26
0066 #define WM8900_REG_FLLCTL4      0x27
0067 #define WM8900_REG_FLLCTL5      0x28
0068 #define WM8900_REG_FLLCTL6      0x29
0069 #define WM8900_REG_LOUTMIXCTL1  0x2c
0070 #define WM8900_REG_ROUTMIXCTL1  0x2d
0071 #define WM8900_REG_BYPASS1  0x2e
0072 #define WM8900_REG_BYPASS2  0x2f
0073 #define WM8900_REG_AUXOUT_CTL   0x30
0074 #define WM8900_REG_LOUT1CTL     0x33
0075 #define WM8900_REG_ROUT1CTL     0x34
0076 #define WM8900_REG_LOUT2CTL 0x35
0077 #define WM8900_REG_ROUT2CTL 0x36
0078 #define WM8900_REG_HPCTL1   0x3a
0079 #define WM8900_REG_OUTBIASCTL   0x73
0080 
0081 #define WM8900_MAXREG       0x80
0082 
0083 #define WM8900_REG_ADDCTL_OUT1_DIS    0x80
0084 #define WM8900_REG_ADDCTL_OUT2_DIS    0x40
0085 #define WM8900_REG_ADDCTL_VMID_DIS    0x20
0086 #define WM8900_REG_ADDCTL_BIAS_SRC    0x10
0087 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
0088 #define WM8900_REG_ADDCTL_TEMP_SD     0x02
0089 
0090 #define WM8900_REG_GPIO_TEMP_ENA   0x2
0091 
0092 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
0093 #define WM8900_REG_POWER1_BIAS_ENA         0x0008
0094 #define WM8900_REG_POWER1_VMID_BUF_ENA     0x0004
0095 #define WM8900_REG_POWER1_FLL_ENA          0x0040
0096 
0097 #define WM8900_REG_POWER2_SYSCLK_ENA  0x8000
0098 #define WM8900_REG_POWER2_ADCL_ENA    0x0002
0099 #define WM8900_REG_POWER2_ADCR_ENA    0x0001
0100 
0101 #define WM8900_REG_POWER3_DACL_ENA    0x0002
0102 #define WM8900_REG_POWER3_DACR_ENA    0x0001
0103 
0104 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
0105 #define WM8900_REG_AUDIO1_LRCLK_INV    0x0080
0106 #define WM8900_REG_AUDIO1_BCLK_INV     0x0100
0107 
0108 #define WM8900_REG_CLOCKING1_BCLK_DIR   0x1
0109 #define WM8900_REG_CLOCKING1_MCLK_SRC   0x100
0110 #define WM8900_REG_CLOCKING1_BCLK_MASK  0x01e
0111 #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
0112 
0113 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
0114 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
0115 
0116 #define WM8900_REG_DACCTRL_MUTE          0x004
0117 #define WM8900_REG_DACCTRL_DAC_SB_FILT   0x100
0118 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
0119 
0120 #define WM8900_REG_AUDIO3_ADCLRC_DIR    0x0800
0121 
0122 #define WM8900_REG_AUDIO4_DACLRC_DIR    0x0800
0123 
0124 #define WM8900_REG_FLLCTL1_OSC_ENA    0x100
0125 
0126 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
0127 
0128 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
0129 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
0130 #define WM8900_REG_HPCTL1_HP_CLAMP_IP    0x20
0131 #define WM8900_REG_HPCTL1_HP_CLAMP_OP    0x10
0132 #define WM8900_REG_HPCTL1_HP_SHORT       0x08
0133 #define WM8900_REG_HPCTL1_HP_SHORT2      0x04
0134 
0135 #define WM8900_LRC_MASK 0x03ff
0136 
0137 struct wm8900_priv {
0138     struct regmap *regmap;
0139 
0140     u32 fll_in; /* FLL input frequency */
0141     u32 fll_out; /* FLL output frequency */
0142 };
0143 
0144 /*
0145  * wm8900 register cache.  We can't read the entire register space and we
0146  * have slow control buses so we cache the registers.
0147  */
0148 static const struct reg_default wm8900_reg_defaults[] = {
0149     {  1, 0x0000 },
0150     {  2, 0xc000 },
0151     {  3, 0x0000 },
0152     {  4, 0x4050 },
0153     {  5, 0x4000 },
0154     {  6, 0x0008 },
0155     {  7, 0x0000 },
0156     {  8, 0x0040 },
0157     {  9, 0x0040 },
0158     { 10, 0x1004 },
0159     { 11, 0x00c0 },
0160     { 12, 0x00c0 },
0161     { 13, 0x0000 },
0162     { 14, 0x0100 },
0163     { 15, 0x00c0 },
0164     { 16, 0x00c0 },
0165     { 17, 0x0000 },
0166     { 18, 0xb001 },
0167     { 19, 0x0000 },
0168     { 20, 0x0000 },
0169     { 21, 0x0044 },
0170     { 22, 0x004c },
0171     { 23, 0x004c },
0172     { 24, 0x0044 },
0173     { 25, 0x0044 },
0174     { 26, 0x0000 },
0175     { 27, 0x0044 },
0176     { 28, 0x0000 },
0177     { 29, 0x0000 },
0178     { 30, 0x0002 },
0179     { 31, 0x0000 },
0180     { 32, 0x0000 },
0181     { 33, 0x0000 },
0182     { 34, 0x0000 },
0183     { 35, 0x0000 },
0184     { 36, 0x0008 },
0185     { 37, 0x0000 },
0186     { 38, 0x0000 },
0187     { 39, 0x0008 },
0188     { 40, 0x0097 },
0189     { 41, 0x0100 },
0190     { 42, 0x0000 },
0191     { 43, 0x0000 },
0192     { 44, 0x0050 },
0193     { 45, 0x0050 },
0194     { 46, 0x0055 },
0195     { 47, 0x0055 },
0196     { 48, 0x0055 },
0197     { 49, 0x0000 },
0198     { 50, 0x0000 },
0199     { 51, 0x0079 },
0200     { 52, 0x0079 },
0201     { 53, 0x0079 },
0202     { 54, 0x0079 },
0203     { 55, 0x0000 },
0204 };
0205 
0206 static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
0207 {
0208     switch (reg) {
0209     case WM8900_REG_ID:
0210         return true;
0211     default:
0212         return false;
0213     }
0214 }
0215 
0216 static void wm8900_reset(struct snd_soc_component *component)
0217 {
0218     snd_soc_component_write(component, WM8900_REG_RESET, 0);
0219 }
0220 
0221 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
0222                struct snd_kcontrol *kcontrol, int event)
0223 {
0224     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0225     u16 hpctl1 = snd_soc_component_read(component, WM8900_REG_HPCTL1);
0226 
0227     switch (event) {
0228     case SND_SOC_DAPM_PRE_PMU:
0229         /* Clamp headphone outputs */
0230         hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
0231             WM8900_REG_HPCTL1_HP_CLAMP_OP;
0232         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0233         break;
0234 
0235     case SND_SOC_DAPM_POST_PMU:
0236         /* Enable the input stage */
0237         hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
0238         hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
0239             WM8900_REG_HPCTL1_HP_SHORT2 |
0240             WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
0241         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0242 
0243         msleep(400);
0244 
0245         /* Enable the output stage */
0246         hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
0247         hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
0248         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0249 
0250         /* Remove the shorts */
0251         hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
0252         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0253         hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
0254         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0255         break;
0256 
0257     case SND_SOC_DAPM_PRE_PMD:
0258         /* Short the output */
0259         hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
0260         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0261 
0262         /* Disable the output stage */
0263         hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
0264         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0265 
0266         /* Clamp the outputs and power down input */
0267         hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
0268             WM8900_REG_HPCTL1_HP_CLAMP_OP;
0269         hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
0270         snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
0271         break;
0272 
0273     case SND_SOC_DAPM_POST_PMD:
0274         /* Disable everything */
0275         snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
0276         break;
0277 
0278     default:
0279         WARN(1, "Invalid event %d\n", event);
0280         break;
0281     }
0282 
0283     return 0;
0284 }
0285 
0286 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
0287 
0288 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
0289 
0290 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
0291 
0292 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
0293 
0294 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
0295 
0296 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
0297 
0298 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
0299 
0300 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
0301 
0302 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
0303 
0304 static SOC_ENUM_SINGLE_DECL(mic_bias_level,
0305                 WM8900_REG_INCTL, 8, mic_bias_level_txt);
0306 
0307 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
0308 
0309 static SOC_ENUM_SINGLE_DECL(dac_mute_rate,
0310                 WM8900_REG_DACCTRL, 7, dac_mute_rate_txt);
0311 
0312 static const char *dac_deemphasis_txt[] = {
0313     "Disabled", "32kHz", "44.1kHz", "48kHz"
0314 };
0315 
0316 static SOC_ENUM_SINGLE_DECL(dac_deemphasis,
0317                 WM8900_REG_DACCTRL, 4, dac_deemphasis_txt);
0318 
0319 static const char *adc_hpf_cut_txt[] = {
0320     "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
0321 };
0322 
0323 static SOC_ENUM_SINGLE_DECL(adc_hpf_cut,
0324                 WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt);
0325 
0326 static const char *lr_txt[] = {
0327     "Left", "Right"
0328 };
0329 
0330 static SOC_ENUM_SINGLE_DECL(aifl_src,
0331                 WM8900_REG_AUDIO1, 15, lr_txt);
0332 
0333 static SOC_ENUM_SINGLE_DECL(aifr_src,
0334                 WM8900_REG_AUDIO1, 14, lr_txt);
0335 
0336 static SOC_ENUM_SINGLE_DECL(dacl_src,
0337                 WM8900_REG_AUDIO2, 15, lr_txt);
0338 
0339 static SOC_ENUM_SINGLE_DECL(dacr_src,
0340                 WM8900_REG_AUDIO2, 14, lr_txt);
0341 
0342 static const char *sidetone_txt[] = {
0343     "Disabled", "Left ADC", "Right ADC"
0344 };
0345 
0346 static SOC_ENUM_SINGLE_DECL(dacl_sidetone,
0347                 WM8900_REG_SIDETONE, 2, sidetone_txt);
0348 
0349 static SOC_ENUM_SINGLE_DECL(dacr_sidetone,
0350                 WM8900_REG_SIDETONE, 0, sidetone_txt);
0351 
0352 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
0353 SOC_ENUM("Mic Bias Level", mic_bias_level),
0354 
0355 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
0356            in_pga_tlv),
0357 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
0358 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
0359 
0360 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
0361            in_pga_tlv),
0362 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
0363 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
0364 
0365 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
0366 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
0367 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
0368 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0369 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
0370        12, 1, 0),
0371 
0372 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
0373 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
0374 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
0375 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
0376            adc_svol_tlv),
0377 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
0378            adc_svol_tlv),
0379 SOC_ENUM("Left Digital Audio Source", aifl_src),
0380 SOC_ENUM("Right Digital Audio Source", aifr_src),
0381 
0382 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
0383            dac_boost_tlv),
0384 SOC_ENUM("Left DAC Source", dacl_src),
0385 SOC_ENUM("Right DAC Source", dacr_src),
0386 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
0387 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
0388 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
0389 
0390 SOC_DOUBLE_R_TLV("Digital Playback Volume",
0391          WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
0392          1, 96, 0, dac_tlv),
0393 SOC_DOUBLE_R_TLV("Digital Capture Volume",
0394          WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
0395 
0396 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
0397            out_mix_tlv),
0398 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
0399            out_mix_tlv),
0400 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
0401            out_mix_tlv),
0402 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
0403            out_mix_tlv),
0404 
0405 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
0406            out_mix_tlv),
0407 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
0408            out_mix_tlv),
0409 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
0410            out_mix_tlv),
0411 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
0412            out_mix_tlv),
0413 
0414 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
0415            in_boost_tlv),
0416 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
0417            in_boost_tlv),
0418 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
0419            in_boost_tlv),
0420 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
0421            in_boost_tlv),
0422 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
0423            in_boost_tlv),
0424 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
0425            in_boost_tlv),
0426 
0427 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
0428            0, 63, 0, out_pga_tlv),
0429 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
0430          6, 1, 1),
0431 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
0432          7, 1, 0),
0433 
0434 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
0435          WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
0436          0, 63, 0, out_pga_tlv),
0437 SOC_DOUBLE_R("LINEOUT2 Switch",
0438          WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
0439 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
0440          WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
0441 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
0442        0, 1, 1),
0443 
0444 };
0445 
0446 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
0447 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
0448 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
0449 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
0450 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
0451 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
0452 };
0453 
0454 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
0455 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
0456 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
0457 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
0458 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
0459 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
0460 };
0461 
0462 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
0463 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
0464 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
0465 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
0466 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
0467 };
0468 
0469 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
0470 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
0471 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
0472 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
0473 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
0474 };
0475 
0476 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
0477 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
0478 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
0479 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
0480 };
0481 
0482 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
0483 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
0484 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
0485 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
0486 };
0487 
0488 static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
0489 
0490 static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux,
0491                 WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux);
0492 
0493 static const struct snd_kcontrol_new wm8900_lineout2_lp =
0494 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
0495 
0496 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
0497 
0498 /* Externally visible pins */
0499 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
0500 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
0501 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
0502 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
0503 SND_SOC_DAPM_OUTPUT("HP_L"),
0504 SND_SOC_DAPM_OUTPUT("HP_R"),
0505 
0506 SND_SOC_DAPM_INPUT("RINPUT1"),
0507 SND_SOC_DAPM_INPUT("LINPUT1"),
0508 SND_SOC_DAPM_INPUT("RINPUT2"),
0509 SND_SOC_DAPM_INPUT("LINPUT2"),
0510 SND_SOC_DAPM_INPUT("RINPUT3"),
0511 SND_SOC_DAPM_INPUT("LINPUT3"),
0512 SND_SOC_DAPM_INPUT("AUX"),
0513 
0514 SND_SOC_DAPM_VMID("VMID"),
0515 
0516 /* Input */
0517 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
0518            wm8900_linpga_controls,
0519            ARRAY_SIZE(wm8900_linpga_controls)),
0520 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
0521            wm8900_rinpga_controls,
0522            ARRAY_SIZE(wm8900_rinpga_controls)),
0523 
0524 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
0525            wm8900_linmix_controls,
0526            ARRAY_SIZE(wm8900_linmix_controls)),
0527 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
0528            wm8900_rinmix_controls,
0529            ARRAY_SIZE(wm8900_rinmix_controls)),
0530 
0531 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
0532 
0533 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
0534 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
0535 
0536 /* Output */
0537 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
0538 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
0539 
0540 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
0541            wm8900_hp_event,
0542            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
0543            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
0544 
0545 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
0546 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
0547 
0548 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
0549 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
0550 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
0551 
0552 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
0553            wm8900_loutmix_controls,
0554            ARRAY_SIZE(wm8900_loutmix_controls)),
0555 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
0556            wm8900_routmix_controls,
0557            ARRAY_SIZE(wm8900_routmix_controls)),
0558 };
0559 
0560 /* Target, Path, Source */
0561 static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
0562 /* Inputs */
0563 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
0564 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
0565 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
0566 
0567 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
0568 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
0569 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
0570 
0571 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
0572 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
0573 {"Left Input Mixer", "AUX Switch", "AUX"},
0574 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
0575 
0576 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
0577 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
0578 {"Right Input Mixer", "AUX Switch", "AUX"},
0579 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
0580 
0581 {"ADCL", NULL, "Left Input Mixer"},
0582 {"ADCR", NULL, "Right Input Mixer"},
0583 
0584 /* Outputs */
0585 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
0586 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
0587 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
0588 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
0589 
0590 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
0591 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
0592 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
0593 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
0594 
0595 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
0596 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
0597 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
0598 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
0599 
0600 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
0601 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
0602 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
0603 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
0604 {"Left Output Mixer", "DACL Switch", "DACL"},
0605 
0606 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
0607 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
0608 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
0609 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
0610 {"Right Output Mixer", "DACR Switch", "DACR"},
0611 
0612 /* Note that the headphone output stage needs to be connected
0613  * externally to LINEOUT2 via DC blocking capacitors.  Other
0614  * configurations are not supported.
0615  *
0616  * Note also that left and right headphone paths are treated as a
0617  * mono path.
0618  */
0619 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
0620 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
0621 {"HP_L", NULL, "Headphone Amplifier"},
0622 {"HP_R", NULL, "Headphone Amplifier"},
0623 };
0624 
0625 static int wm8900_hw_params(struct snd_pcm_substream *substream,
0626     struct snd_pcm_hw_params *params,
0627     struct snd_soc_dai *dai)
0628 {
0629     struct snd_soc_component *component = dai->component;
0630     u16 reg;
0631 
0632     reg = snd_soc_component_read(component, WM8900_REG_AUDIO1) & ~0x60;
0633 
0634     switch (params_width(params)) {
0635     case 16:
0636         break;
0637     case 20:
0638         reg |= 0x20;
0639         break;
0640     case 24:
0641         reg |= 0x40;
0642         break;
0643     case 32:
0644         reg |= 0x60;
0645         break;
0646     default:
0647         return -EINVAL;
0648     }
0649 
0650     snd_soc_component_write(component, WM8900_REG_AUDIO1, reg);
0651 
0652     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0653         reg = snd_soc_component_read(component, WM8900_REG_DACCTRL);
0654 
0655         if (params_rate(params) <= 24000)
0656             reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
0657         else
0658             reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
0659 
0660         snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
0661     }
0662 
0663     return 0;
0664 }
0665 
0666 /* FLL divisors */
0667 struct _fll_div {
0668     u16 fll_ratio;
0669     u16 fllclk_div;
0670     u16 fll_slow_lock_ref;
0671     u16 n;
0672     u16 k;
0673 };
0674 
0675 /* The size in bits of the FLL divide multiplied by 10
0676  * to allow rounding later */
0677 #define FIXED_FLL_SIZE ((1 << 16) * 10)
0678 
0679 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
0680                unsigned int Fout)
0681 {
0682     u64 Kpart;
0683     unsigned int K, Ndiv, Nmod, target;
0684     unsigned int div;
0685 
0686     if (WARN_ON(!Fout))
0687         return -EINVAL;
0688 
0689     /* The FLL must run at 90-100MHz which is then scaled down to
0690      * the output value by FLLCLK_DIV. */
0691     target = Fout;
0692     div = 1;
0693     while (target < 90000000) {
0694         div *= 2;
0695         target *= 2;
0696     }
0697 
0698     if (target > 100000000)
0699         printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
0700                " Fout=%u\n", target, Fref, Fout);
0701     if (div > 32) {
0702         printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
0703                "Fref=%u, Fout=%u, target=%u\n",
0704                div, Fref, Fout, target);
0705         return -EINVAL;
0706     }
0707 
0708     fll_div->fllclk_div = div >> 2;
0709 
0710     if (Fref < 48000)
0711         fll_div->fll_slow_lock_ref = 1;
0712     else
0713         fll_div->fll_slow_lock_ref = 0;
0714 
0715     Ndiv = target / Fref;
0716 
0717     if (Fref < 1000000)
0718         fll_div->fll_ratio = 8;
0719     else
0720         fll_div->fll_ratio = 1;
0721 
0722     fll_div->n = Ndiv / fll_div->fll_ratio;
0723     Nmod = (target / fll_div->fll_ratio) % Fref;
0724 
0725     /* Calculate fractional part - scale up so we can round. */
0726     Kpart = FIXED_FLL_SIZE * (long long)Nmod;
0727 
0728     do_div(Kpart, Fref);
0729 
0730     K = Kpart & 0xFFFFFFFF;
0731 
0732     if ((K % 10) >= 5)
0733         K += 5;
0734 
0735     /* Move down to proper range now rounding is done */
0736     fll_div->k = K / 10;
0737 
0738     if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
0739         WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
0740         return -EINVAL;
0741 
0742     return 0;
0743 }
0744 
0745 static int wm8900_set_fll(struct snd_soc_component *component,
0746     int fll_id, unsigned int freq_in, unsigned int freq_out)
0747 {
0748     struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
0749     struct _fll_div fll_div;
0750 
0751     if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
0752         return 0;
0753 
0754     /* The digital side should be disabled during any change. */
0755     snd_soc_component_update_bits(component, WM8900_REG_POWER1,
0756                 WM8900_REG_POWER1_FLL_ENA, 0);
0757 
0758     /* Disable the FLL? */
0759     if (!freq_in || !freq_out) {
0760         snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
0761                     WM8900_REG_CLOCKING1_MCLK_SRC, 0);
0762         snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1,
0763                     WM8900_REG_FLLCTL1_OSC_ENA, 0);
0764         wm8900->fll_in = freq_in;
0765         wm8900->fll_out = freq_out;
0766 
0767         return 0;
0768     }
0769 
0770     if (fll_factors(&fll_div, freq_in, freq_out) != 0)
0771         goto reenable;
0772 
0773     wm8900->fll_in = freq_in;
0774     wm8900->fll_out = freq_out;
0775 
0776     /* The osclilator *MUST* be enabled before we enable the
0777      * digital circuit. */
0778     snd_soc_component_write(component, WM8900_REG_FLLCTL1,
0779              fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
0780 
0781     snd_soc_component_write(component, WM8900_REG_FLLCTL4, fll_div.n >> 5);
0782     snd_soc_component_write(component, WM8900_REG_FLLCTL5,
0783              (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
0784 
0785     if (fll_div.k) {
0786         snd_soc_component_write(component, WM8900_REG_FLLCTL2,
0787                  (fll_div.k >> 8) | 0x100);
0788         snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0789     } else
0790         snd_soc_component_write(component, WM8900_REG_FLLCTL2, 0);
0791 
0792     if (fll_div.fll_slow_lock_ref)
0793         snd_soc_component_write(component, WM8900_REG_FLLCTL6,
0794                  WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
0795     else
0796         snd_soc_component_write(component, WM8900_REG_FLLCTL6, 0);
0797 
0798     snd_soc_component_update_bits(component, WM8900_REG_POWER1,
0799                 WM8900_REG_POWER1_FLL_ENA,
0800                 WM8900_REG_POWER1_FLL_ENA);
0801 
0802 reenable:
0803     snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
0804                 WM8900_REG_CLOCKING1_MCLK_SRC,
0805                 WM8900_REG_CLOCKING1_MCLK_SRC);
0806     return 0;
0807 }
0808 
0809 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
0810         int source, unsigned int freq_in, unsigned int freq_out)
0811 {
0812     return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out);
0813 }
0814 
0815 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
0816                  int div_id, int div)
0817 {
0818     struct snd_soc_component *component = codec_dai->component;
0819 
0820     switch (div_id) {
0821     case WM8900_BCLK_DIV:
0822         snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
0823                     WM8900_REG_CLOCKING1_BCLK_MASK, div);
0824         break;
0825     case WM8900_OPCLK_DIV:
0826         snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
0827                     WM8900_REG_CLOCKING1_OPCLK_MASK, div);
0828         break;
0829     case WM8900_DAC_LRCLK:
0830         snd_soc_component_update_bits(component, WM8900_REG_AUDIO4,
0831                     WM8900_LRC_MASK, div);
0832         break;
0833     case WM8900_ADC_LRCLK:
0834         snd_soc_component_update_bits(component, WM8900_REG_AUDIO3,
0835                     WM8900_LRC_MASK, div);
0836         break;
0837     case WM8900_DAC_CLKDIV:
0838         snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
0839                     WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
0840         break;
0841     case WM8900_ADC_CLKDIV:
0842         snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
0843                     WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
0844         break;
0845     case WM8900_LRCLK_MODE:
0846         snd_soc_component_update_bits(component, WM8900_REG_DACCTRL,
0847                     WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
0848         break;
0849     default:
0850         return -EINVAL;
0851     }
0852 
0853     return 0;
0854 }
0855 
0856 
0857 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
0858                   unsigned int fmt)
0859 {
0860     struct snd_soc_component *component = codec_dai->component;
0861     unsigned int clocking1, aif1, aif3, aif4;
0862 
0863     clocking1 = snd_soc_component_read(component, WM8900_REG_CLOCKING1);
0864     aif1 = snd_soc_component_read(component, WM8900_REG_AUDIO1);
0865     aif3 = snd_soc_component_read(component, WM8900_REG_AUDIO3);
0866     aif4 = snd_soc_component_read(component, WM8900_REG_AUDIO4);
0867 
0868     /* set master/slave audio interface */
0869     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0870     case SND_SOC_DAIFMT_CBS_CFS:
0871         clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
0872         aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
0873         aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
0874         break;
0875     case SND_SOC_DAIFMT_CBS_CFM:
0876         clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
0877         aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
0878         aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
0879         break;
0880     case SND_SOC_DAIFMT_CBM_CFM:
0881         clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
0882         aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
0883         aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
0884         break;
0885     case SND_SOC_DAIFMT_CBM_CFS:
0886         clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
0887         aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
0888         aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
0889         break;
0890     default:
0891         return -EINVAL;
0892     }
0893 
0894     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0895     case SND_SOC_DAIFMT_DSP_A:
0896         aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
0897         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
0898         break;
0899     case SND_SOC_DAIFMT_DSP_B:
0900         aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
0901         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
0902         break;
0903     case SND_SOC_DAIFMT_I2S:
0904         aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
0905         aif1 |= 0x10;
0906         break;
0907     case SND_SOC_DAIFMT_RIGHT_J:
0908         aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
0909         break;
0910     case SND_SOC_DAIFMT_LEFT_J:
0911         aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
0912         aif1 |= 0x8;
0913         break;
0914     default:
0915         return -EINVAL;
0916     }
0917 
0918     /* Clock inversion */
0919     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0920     case SND_SOC_DAIFMT_DSP_A:
0921     case SND_SOC_DAIFMT_DSP_B:
0922         /* frame inversion not valid for DSP modes */
0923         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0924         case SND_SOC_DAIFMT_NB_NF:
0925             aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
0926             break;
0927         case SND_SOC_DAIFMT_IB_NF:
0928             aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
0929             break;
0930         default:
0931             return -EINVAL;
0932         }
0933         break;
0934     case SND_SOC_DAIFMT_I2S:
0935     case SND_SOC_DAIFMT_RIGHT_J:
0936     case SND_SOC_DAIFMT_LEFT_J:
0937         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0938         case SND_SOC_DAIFMT_NB_NF:
0939             aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
0940             aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
0941             break;
0942         case SND_SOC_DAIFMT_IB_IF:
0943             aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
0944             aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
0945             break;
0946         case SND_SOC_DAIFMT_IB_NF:
0947             aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
0948             aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
0949             break;
0950         case SND_SOC_DAIFMT_NB_IF:
0951             aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
0952             aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
0953             break;
0954         default:
0955             return -EINVAL;
0956         }
0957         break;
0958     default:
0959         return -EINVAL;
0960     }
0961 
0962     snd_soc_component_write(component, WM8900_REG_CLOCKING1, clocking1);
0963     snd_soc_component_write(component, WM8900_REG_AUDIO1, aif1);
0964     snd_soc_component_write(component, WM8900_REG_AUDIO3, aif3);
0965     snd_soc_component_write(component, WM8900_REG_AUDIO4, aif4);
0966 
0967     return 0;
0968 }
0969 
0970 static int wm8900_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
0971 {
0972     struct snd_soc_component *component = codec_dai->component;
0973     u16 reg;
0974 
0975     reg = snd_soc_component_read(component, WM8900_REG_DACCTRL);
0976 
0977     if (mute)
0978         reg |= WM8900_REG_DACCTRL_MUTE;
0979     else
0980         reg &= ~WM8900_REG_DACCTRL_MUTE;
0981 
0982     snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
0983 
0984     return 0;
0985 }
0986 
0987 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
0988               SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
0989               SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
0990 
0991 #define WM8900_PCM_FORMATS \
0992     (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0993      SNDRV_PCM_FMTBIT_S24_LE)
0994 
0995 static const struct snd_soc_dai_ops wm8900_dai_ops = {
0996     .hw_params  = wm8900_hw_params,
0997     .set_clkdiv = wm8900_set_dai_clkdiv,
0998     .set_pll    = wm8900_set_dai_pll,
0999     .set_fmt    = wm8900_set_dai_fmt,
1000     .mute_stream    = wm8900_mute,
1001     .no_capture_mute = 1,
1002 };
1003 
1004 static struct snd_soc_dai_driver wm8900_dai = {
1005     .name = "wm8900-hifi",
1006     .playback = {
1007         .stream_name = "HiFi Playback",
1008         .channels_min = 1,
1009         .channels_max = 2,
1010         .rates = WM8900_RATES,
1011         .formats = WM8900_PCM_FORMATS,
1012     },
1013     .capture = {
1014         .stream_name = "HiFi Capture",
1015         .channels_min = 1,
1016         .channels_max = 2,
1017         .rates = WM8900_RATES,
1018         .formats = WM8900_PCM_FORMATS,
1019      },
1020     .ops = &wm8900_dai_ops,
1021 };
1022 
1023 static int wm8900_set_bias_level(struct snd_soc_component *component,
1024                  enum snd_soc_bias_level level)
1025 {
1026     u16 reg;
1027 
1028     switch (level) {
1029     case SND_SOC_BIAS_ON:
1030         /* Enable thermal shutdown */
1031         snd_soc_component_update_bits(component, WM8900_REG_GPIO,
1032                     WM8900_REG_GPIO_TEMP_ENA,
1033                     WM8900_REG_GPIO_TEMP_ENA);
1034         snd_soc_component_update_bits(component, WM8900_REG_ADDCTL,
1035                     WM8900_REG_ADDCTL_TEMP_SD,
1036                     WM8900_REG_ADDCTL_TEMP_SD);
1037         break;
1038 
1039     case SND_SOC_BIAS_PREPARE:
1040         break;
1041 
1042     case SND_SOC_BIAS_STANDBY:
1043         /* Charge capacitors if initial power up */
1044         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1045             /* STARTUP_BIAS_ENA on */
1046             snd_soc_component_write(component, WM8900_REG_POWER1,
1047                      WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1048 
1049             /* Startup bias mode */
1050             snd_soc_component_write(component, WM8900_REG_ADDCTL,
1051                      WM8900_REG_ADDCTL_BIAS_SRC |
1052                      WM8900_REG_ADDCTL_VMID_SOFTST);
1053 
1054             /* VMID 2x50k */
1055             snd_soc_component_write(component, WM8900_REG_POWER1,
1056                      WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1057 
1058             /* Allow capacitors to charge */
1059             schedule_timeout_interruptible(msecs_to_jiffies(400));
1060 
1061             /* Enable bias */
1062             snd_soc_component_write(component, WM8900_REG_POWER1,
1063                      WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1064                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1065 
1066             snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
1067 
1068             snd_soc_component_write(component, WM8900_REG_POWER1,
1069                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1070         }
1071 
1072         reg = snd_soc_component_read(component, WM8900_REG_POWER1);
1073         snd_soc_component_write(component, WM8900_REG_POWER1,
1074                  (reg & WM8900_REG_POWER1_FLL_ENA) |
1075                  WM8900_REG_POWER1_BIAS_ENA | 0x1);
1076         snd_soc_component_write(component, WM8900_REG_POWER2,
1077                  WM8900_REG_POWER2_SYSCLK_ENA);
1078         snd_soc_component_write(component, WM8900_REG_POWER3, 0);
1079         break;
1080 
1081     case SND_SOC_BIAS_OFF:
1082         /* Startup bias enable */
1083         reg = snd_soc_component_read(component, WM8900_REG_POWER1);
1084         snd_soc_component_write(component, WM8900_REG_POWER1,
1085                  reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1086         snd_soc_component_write(component, WM8900_REG_ADDCTL,
1087                  WM8900_REG_ADDCTL_BIAS_SRC |
1088                  WM8900_REG_ADDCTL_VMID_SOFTST);
1089 
1090         /* Discharge caps */
1091         snd_soc_component_write(component, WM8900_REG_POWER1,
1092                  WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1093         schedule_timeout_interruptible(msecs_to_jiffies(500));
1094 
1095         /* Remove clamp */
1096         snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
1097 
1098         /* Power down */
1099         snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
1100         snd_soc_component_write(component, WM8900_REG_POWER1, 0);
1101         snd_soc_component_write(component, WM8900_REG_POWER2, 0);
1102         snd_soc_component_write(component, WM8900_REG_POWER3, 0);
1103 
1104         /* Need to let things settle before stopping the clock
1105          * to ensure that restart works, see "Stopping the
1106          * master clock" in the datasheet. */
1107         schedule_timeout_interruptible(msecs_to_jiffies(1));
1108         snd_soc_component_write(component, WM8900_REG_POWER2,
1109                  WM8900_REG_POWER2_SYSCLK_ENA);
1110         break;
1111     }
1112     return 0;
1113 }
1114 
1115 static int wm8900_suspend(struct snd_soc_component *component)
1116 {
1117     struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
1118     int fll_out = wm8900->fll_out;
1119     int fll_in  = wm8900->fll_in;
1120     int ret;
1121 
1122     /* Stop the FLL in an orderly fashion */
1123     ret = wm8900_set_fll(component, 0, 0, 0);
1124     if (ret != 0) {
1125         dev_err(component->dev, "Failed to stop FLL\n");
1126         return ret;
1127     }
1128 
1129     wm8900->fll_out = fll_out;
1130     wm8900->fll_in = fll_in;
1131 
1132     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1133 
1134     return 0;
1135 }
1136 
1137 static int wm8900_resume(struct snd_soc_component *component)
1138 {
1139     struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
1140     int ret;
1141 
1142     wm8900_reset(component);
1143 
1144     ret = regcache_sync(wm8900->regmap);
1145     if (ret != 0) {
1146         dev_err(component->dev, "Failed to restore cache: %d\n", ret);
1147         return ret;
1148     }
1149 
1150     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1151 
1152     /* Restart the FLL? */
1153     if (wm8900->fll_out) {
1154         int fll_out = wm8900->fll_out;
1155         int fll_in  = wm8900->fll_in;
1156 
1157         wm8900->fll_in = 0;
1158         wm8900->fll_out = 0;
1159 
1160         ret = wm8900_set_fll(component, 0, fll_in, fll_out);
1161         if (ret != 0) {
1162             dev_err(component->dev, "Failed to restart FLL\n");
1163             return ret;
1164         }
1165     }
1166 
1167     return 0;
1168 }
1169 
1170 static int wm8900_probe(struct snd_soc_component *component)
1171 {
1172     int reg;
1173 
1174     reg = snd_soc_component_read(component, WM8900_REG_ID);
1175     if (reg != 0x8900) {
1176         dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg);
1177         return -ENODEV;
1178     }
1179 
1180     wm8900_reset(component);
1181 
1182     /* Turn the chip on */
1183     snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1184 
1185     /* Latch the volume update bits */
1186     snd_soc_component_update_bits(component, WM8900_REG_LINVOL, 0x100, 0x100);
1187     snd_soc_component_update_bits(component, WM8900_REG_RINVOL, 0x100, 0x100);
1188     snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1189     snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1190     snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1191     snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1192     snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, 0x100, 0x100);
1193     snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, 0x100, 0x100);
1194     snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, 0x100, 0x100);
1195     snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, 0x100, 0x100);
1196 
1197     /* Set the DAC and mixer output bias */
1198     snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, 0x81);
1199 
1200     return 0;
1201 }
1202 
1203 static const struct snd_soc_component_driver soc_component_dev_wm8900 = {
1204     .probe          = wm8900_probe,
1205     .suspend        = wm8900_suspend,
1206     .resume         = wm8900_resume,
1207     .set_bias_level     = wm8900_set_bias_level,
1208     .controls       = wm8900_snd_controls,
1209     .num_controls       = ARRAY_SIZE(wm8900_snd_controls),
1210     .dapm_widgets       = wm8900_dapm_widgets,
1211     .num_dapm_widgets   = ARRAY_SIZE(wm8900_dapm_widgets),
1212     .dapm_routes        = wm8900_dapm_routes,
1213     .num_dapm_routes    = ARRAY_SIZE(wm8900_dapm_routes),
1214     .idle_bias_on       = 1,
1215     .use_pmdown_time    = 1,
1216     .endianness     = 1,
1217 };
1218 
1219 static const struct regmap_config wm8900_regmap = {
1220     .reg_bits = 8,
1221     .val_bits = 16,
1222     .max_register = WM8900_MAXREG,
1223 
1224     .reg_defaults = wm8900_reg_defaults,
1225     .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
1226     .cache_type = REGCACHE_RBTREE,
1227 
1228     .volatile_reg = wm8900_volatile_register,
1229 };
1230 
1231 #if defined(CONFIG_SPI_MASTER)
1232 static int wm8900_spi_probe(struct spi_device *spi)
1233 {
1234     struct wm8900_priv *wm8900;
1235     int ret;
1236 
1237     wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
1238                   GFP_KERNEL);
1239     if (wm8900 == NULL)
1240         return -ENOMEM;
1241 
1242     wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
1243     if (IS_ERR(wm8900->regmap))
1244         return PTR_ERR(wm8900->regmap);
1245 
1246     spi_set_drvdata(spi, wm8900);
1247 
1248     ret = devm_snd_soc_register_component(&spi->dev,
1249             &soc_component_dev_wm8900, &wm8900_dai, 1);
1250 
1251     return ret;
1252 }
1253 
1254 static struct spi_driver wm8900_spi_driver = {
1255     .driver = {
1256         .name   = "wm8900",
1257     },
1258     .probe      = wm8900_spi_probe,
1259 };
1260 #endif /* CONFIG_SPI_MASTER */
1261 
1262 #if IS_ENABLED(CONFIG_I2C)
1263 static int wm8900_i2c_probe(struct i2c_client *i2c)
1264 {
1265     struct wm8900_priv *wm8900;
1266     int ret;
1267 
1268     wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
1269                   GFP_KERNEL);
1270     if (wm8900 == NULL)
1271         return -ENOMEM;
1272 
1273     wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
1274     if (IS_ERR(wm8900->regmap))
1275         return PTR_ERR(wm8900->regmap);
1276 
1277     i2c_set_clientdata(i2c, wm8900);
1278 
1279     ret = devm_snd_soc_register_component(&i2c->dev,
1280             &soc_component_dev_wm8900, &wm8900_dai, 1);
1281 
1282     return ret;
1283 }
1284 
1285 static int wm8900_i2c_remove(struct i2c_client *client)
1286 {
1287     return 0;
1288 }
1289 
1290 static const struct i2c_device_id wm8900_i2c_id[] = {
1291     { "wm8900", 0 },
1292     { }
1293 };
1294 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1295 
1296 static struct i2c_driver wm8900_i2c_driver = {
1297     .driver = {
1298         .name = "wm8900",
1299     },
1300     .probe_new = wm8900_i2c_probe,
1301     .remove =   wm8900_i2c_remove,
1302     .id_table = wm8900_i2c_id,
1303 };
1304 #endif
1305 
1306 static int __init wm8900_modinit(void)
1307 {
1308     int ret = 0;
1309 #if IS_ENABLED(CONFIG_I2C)
1310     ret = i2c_add_driver(&wm8900_i2c_driver);
1311     if (ret != 0) {
1312         printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1313                ret);
1314     }
1315 #endif
1316 #if defined(CONFIG_SPI_MASTER)
1317     ret = spi_register_driver(&wm8900_spi_driver);
1318     if (ret != 0) {
1319         printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1320                ret);
1321     }
1322 #endif
1323     return ret;
1324 }
1325 module_init(wm8900_modinit);
1326 
1327 static void __exit wm8900_exit(void)
1328 {
1329 #if IS_ENABLED(CONFIG_I2C)
1330     i2c_del_driver(&wm8900_i2c_driver);
1331 #endif
1332 #if defined(CONFIG_SPI_MASTER)
1333     spi_unregister_driver(&wm8900_spi_driver);
1334 #endif
1335 }
1336 module_exit(wm8900_exit);
1337 
1338 MODULE_DESCRIPTION("ASoC WM8900 driver");
1339 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1340 MODULE_LICENSE("GPL");
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