soc/codecs/wm8804.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8804.c  --  WM8804 S/PDIF transceiver driver
0004  *
0005  * Copyright 2010-11 Wolfson Microelectronics plc
0006  *
0007  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
0008  */
0009
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/delay.h>
0015 #include <linux/pm.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/of_device.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/slab.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/initval.h>
0025 #include <sound/tlv.h>
0026 #include <sound/soc-dapm.h>
0027
0028 #include "wm8804.h"
0029
0030 #define WM8804_NUM_SUPPLIES 2
0031 static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
0032     "PVDD",
0033     "DVDD"
0034 };
0035
0036 static const struct reg_default wm8804_reg_defaults[] = {
0037     { 3,  0x21 },     /* R3  - PLL1 */
0038     { 4,  0xFD },     /* R4  - PLL2 */
0039     { 5,  0x36 },     /* R5  - PLL3 */
0040     { 6,  0x07 },     /* R6  - PLL4 */
0041     { 7,  0x16 },     /* R7  - PLL5 */
0042     { 8,  0x18 },     /* R8  - PLL6 */
0043     { 9,  0xFF },     /* R9  - SPDMODE */
0044     { 10, 0x00 },     /* R10 - INTMASK */
0045     { 18, 0x00 },     /* R18 - SPDTX1 */
0046     { 19, 0x00 },     /* R19 - SPDTX2 */
0047     { 20, 0x00 },     /* R20 - SPDTX3 */
0048     { 21, 0x71 },     /* R21 - SPDTX4 */
0049     { 22, 0x0B },     /* R22 - SPDTX5 */
0050     { 23, 0x70 },     /* R23 - GPO0 */
0051     { 24, 0x57 },     /* R24 - GPO1 */
0052     { 26, 0x42 },     /* R26 - GPO2 */
0053     { 27, 0x06 },     /* R27 - AIFTX */
0054     { 28, 0x06 },     /* R28 - AIFRX */
0055     { 29, 0x80 },     /* R29 - SPDRX1 */
0056     { 30, 0x07 },     /* R30 - PWRDN */
0057 };
0058
0059 struct wm8804_priv {
0060     struct device *dev;
0061     struct regmap *regmap;
0062     struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
0063     struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
0064     int mclk_div;
0065
0066     struct gpio_desc *reset;
0067
0068     int aif_pwr;
0069 };
0070
0071 static int txsrc_put(struct snd_kcontrol *kcontrol,
0072              struct snd_ctl_elem_value *ucontrol);
0073
0074 static int wm8804_aif_event(struct snd_soc_dapm_widget *w,
0075                 struct snd_kcontrol *kcontrol, int event);
0076
0077 /*
0078  * We can't use the same notifier block for more than one supply and
0079  * there's no way I can see to get from a callback to the caller
0080  * except container_of().
0081  */
0082 #define WM8804_REGULATOR_EVENT(n) \
0083 static int wm8804_regulator_event_##n(struct notifier_block *nb, \
0084                       unsigned long event, void *data)    \
0085 { \
0086     struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
0087                           disable_nb[n]); \
0088     if (event & REGULATOR_EVENT_DISABLE) { \
0089         regcache_mark_dirty(wm8804->regmap);    \
0090     } \
0091     return 0; \
0092 }
0093
0094 WM8804_REGULATOR_EVENT(0)
0095 WM8804_REGULATOR_EVENT(1)
0096
0097 static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
0098 static SOC_ENUM_SINGLE_DECL(txsrc, WM8804_SPDTX4, 6, txsrc_text);
0099
0100 static const struct snd_kcontrol_new wm8804_tx_source_mux[] = {
0101     SOC_DAPM_ENUM_EXT("Input Source", txsrc,
0102               snd_soc_dapm_get_enum_double, txsrc_put),
0103 };
0104
0105 static const struct snd_soc_dapm_widget wm8804_dapm_widgets[] = {
0106 SND_SOC_DAPM_OUTPUT("SPDIF Out"),
0107 SND_SOC_DAPM_INPUT("SPDIF In"),
0108
0109 SND_SOC_DAPM_PGA("SPDIFTX", WM8804_PWRDN, 2, 1, NULL, 0),
0110 SND_SOC_DAPM_PGA("SPDIFRX", WM8804_PWRDN, 1, 1, NULL, 0),
0111
0112 SND_SOC_DAPM_MUX("Tx Source", SND_SOC_NOPM, 6, 0, wm8804_tx_source_mux),
0113
0114 SND_SOC_DAPM_AIF_OUT_E("AIFTX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
0115                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0116 SND_SOC_DAPM_AIF_IN_E("AIFRX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
0117               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
0118 };
0119
0120 static const struct snd_soc_dapm_route wm8804_dapm_routes[] = {
0121     { "AIFRX", NULL, "Playback" },
0122     { "Tx Source", "AIF", "AIFRX" },
0123
0124     { "SPDIFRX", NULL, "SPDIF In" },
0125     { "Tx Source", "S/PDIF RX", "SPDIFRX" },
0126
0127     { "SPDIFTX", NULL, "Tx Source" },
0128     { "SPDIF Out", NULL, "SPDIFTX" },
0129
0130     { "AIFTX", NULL, "SPDIFRX" },
0131     { "Capture", NULL, "AIFTX" },
0132 };
0133
0134 static int wm8804_aif_event(struct snd_soc_dapm_widget *w,
0135                 struct snd_kcontrol *kcontrol, int event)
0136 {
0137     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0138     struct wm8804_priv *wm8804 = snd_soc_component_get_drvdata(component);
0139
0140     switch (event) {
0141     case SND_SOC_DAPM_POST_PMU:
0142         /* power up the aif */
0143         if (!wm8804->aif_pwr)
0144             snd_soc_component_update_bits(component, WM8804_PWRDN, 0x10, 0x0);
0145         wm8804->aif_pwr++;
0146         break;
0147     case SND_SOC_DAPM_POST_PMD:
0148         /* power down only both paths are disabled */
0149         wm8804->aif_pwr--;
0150         if (!wm8804->aif_pwr)
0151             snd_soc_component_update_bits(component, WM8804_PWRDN, 0x10, 0x10);
0152         break;
0153     }
0154
0155     return 0;
0156 }
0157
0158 static int txsrc_put(struct snd_kcontrol *kcontrol,
0159              struct snd_ctl_elem_value *ucontrol)
0160 {
0161     struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
0162     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0163     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
0164     unsigned int val = ucontrol->value.enumerated.item[0] << e->shift_l;
0165     unsigned int mask = 1 << e->shift_l;
0166     unsigned int txpwr;
0167
0168     if (val != 0 && val != mask)
0169         return -EINVAL;
0170
0171     snd_soc_dapm_mutex_lock(dapm);
0172
0173     if (snd_soc_component_test_bits(component, e->reg, mask, val)) {
0174         /* save the current power state of the transmitter */
0175         txpwr = snd_soc_component_read(component, WM8804_PWRDN) & 0x4;
0176
0177         /* power down the transmitter */
0178         snd_soc_component_update_bits(component, WM8804_PWRDN, 0x4, 0x4);
0179
0180         /* set the tx source */
0181         snd_soc_component_update_bits(component, e->reg, mask, val);
0182
0183         /* restore the transmitter's configuration */
0184         snd_soc_component_update_bits(component, WM8804_PWRDN, 0x4, txpwr);
0185     }
0186
0187     snd_soc_dapm_mutex_unlock(dapm);
0188
0189     return 0;
0190 }
0191
0192 static bool wm8804_volatile(struct device *dev, unsigned int reg)
0193 {
0194     switch (reg) {
0195     case WM8804_RST_DEVID1:
0196     case WM8804_DEVID2:
0197     case WM8804_DEVREV:
0198     case WM8804_INTSTAT:
0199     case WM8804_SPDSTAT:
0200     case WM8804_RXCHAN1:
0201     case WM8804_RXCHAN2:
0202     case WM8804_RXCHAN3:
0203     case WM8804_RXCHAN4:
0204     case WM8804_RXCHAN5:
0205         return true;
0206     default:
0207         return false;
0208     }
0209 }
0210
0211 static int wm8804_soft_reset(struct wm8804_priv *wm8804)
0212 {
0213     return regmap_write(wm8804->regmap, WM8804_RST_DEVID1, 0x0);
0214 }
0215
0216 static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
0217 {
0218     struct snd_soc_component *component;
0219     u16 format, master, bcp, lrp;
0220
0221     component = dai->component;
0222
0223     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0224     case SND_SOC_DAIFMT_I2S:
0225         format = 0x2;
0226         break;
0227     case SND_SOC_DAIFMT_RIGHT_J:
0228         format = 0x0;
0229         break;
0230     case SND_SOC_DAIFMT_LEFT_J:
0231         format = 0x1;
0232         break;
0233     case SND_SOC_DAIFMT_DSP_A:
0234     case SND_SOC_DAIFMT_DSP_B:
0235         format = 0x3;
0236         break;
0237     default:
0238         dev_err(dai->dev, "Unknown dai format\n");
0239         return -EINVAL;
0240     }
0241
0242     /* set data format */
0243     snd_soc_component_update_bits(component, WM8804_AIFTX, 0x3, format);
0244     snd_soc_component_update_bits(component, WM8804_AIFRX, 0x3, format);
0245
0246     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0247     case SND_SOC_DAIFMT_CBM_CFM:
0248         master = 1;
0249         break;
0250     case SND_SOC_DAIFMT_CBS_CFS:
0251         master = 0;
0252         break;
0253     default:
0254         dev_err(dai->dev, "Unknown master/slave configuration\n");
0255         return -EINVAL;
0256     }
0257
0258     /* set master/slave mode */
0259     snd_soc_component_update_bits(component, WM8804_AIFRX, 0x40, master << 6);
0260
0261     bcp = lrp = 0;
0262     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0263     case SND_SOC_DAIFMT_NB_NF:
0264         break;
0265     case SND_SOC_DAIFMT_IB_IF:
0266         bcp = lrp = 1;
0267         break;
0268     case SND_SOC_DAIFMT_IB_NF:
0269         bcp = 1;
0270         break;
0271     case SND_SOC_DAIFMT_NB_IF:
0272         lrp = 1;
0273         break;
0274     default:
0275         dev_err(dai->dev, "Unknown polarity configuration\n");
0276         return -EINVAL;
0277     }
0278
0279     /* set frame inversion */
0280     snd_soc_component_update_bits(component, WM8804_AIFTX, 0x10 | 0x20,
0281                 (bcp << 4) | (lrp << 5));
0282     snd_soc_component_update_bits(component, WM8804_AIFRX, 0x10 | 0x20,
0283                 (bcp << 4) | (lrp << 5));
0284     return 0;
0285 }
0286
0287 static int wm8804_hw_params(struct snd_pcm_substream *substream,
0288                 struct snd_pcm_hw_params *params,
0289                 struct snd_soc_dai *dai)
0290 {
0291     struct snd_soc_component *component;
0292     u16 blen;
0293
0294     component = dai->component;
0295
0296     switch (params_width(params)) {
0297     case 16:
0298         blen = 0x0;
0299         break;
0300     case 20:
0301         blen = 0x1;
0302         break;
0303     case 24:
0304         blen = 0x2;
0305         break;
0306     default:
0307         dev_err(dai->dev, "Unsupported word length: %u\n",
0308             params_width(params));
0309         return -EINVAL;
0310     }
0311
0312     /* set word length */
0313     snd_soc_component_update_bits(component, WM8804_AIFTX, 0xc, blen << 2);
0314     snd_soc_component_update_bits(component, WM8804_AIFRX, 0xc, blen << 2);
0315
0316     return 0;
0317 }
0318
0319 struct pll_div {
0320     u32 prescale:1;
0321     u32 mclkdiv:1;
0322     u32 freqmode:2;
0323     u32 n:4;
0324     u32 k:22;
0325 };
0326
0327 /* PLL rate to output rate divisions */
0328 static struct {
0329     unsigned int div;
0330     unsigned int freqmode;
0331     unsigned int mclkdiv;
0332 } post_table[] = {
0333     {  2,  0, 0 },
0334     {  4,  0, 1 },
0335     {  4,  1, 0 },
0336     {  8,  1, 1 },
0337     {  8,  2, 0 },
0338     { 16,  2, 1 },
0339     { 12,  3, 0 },
0340     { 24,  3, 1 }
0341 };
0342
0343 #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
0344 static int pll_factors(struct pll_div *pll_div, unsigned int target,
0345                unsigned int source, unsigned int mclk_div)
0346 {
0347     u64 Kpart;
0348     unsigned long int K, Ndiv, Nmod, tmp;
0349     int i;
0350
0351     /*
0352      * Scale the output frequency up; the PLL should run in the
0353      * region of 90-100MHz.
0354      */
0355     for (i = 0; i < ARRAY_SIZE(post_table); i++) {
0356         tmp = target * post_table[i].div;
0357         if ((tmp >= 90000000 && tmp <= 100000000) &&
0358             (mclk_div == post_table[i].mclkdiv)) {
0359             pll_div->freqmode = post_table[i].freqmode;
0360             pll_div->mclkdiv = post_table[i].mclkdiv;
0361             target *= post_table[i].div;
0362             break;
0363         }
0364     }
0365
0366     if (i == ARRAY_SIZE(post_table)) {
0367         pr_err("%s: Unable to scale output frequency: %uHz\n",
0368                __func__, target);
0369         return -EINVAL;
0370     }
0371
0372     pll_div->prescale = 0;
0373     Ndiv = target / source;
0374     if (Ndiv < 5) {
0375         source >>= 1;
0376         pll_div->prescale = 1;
0377         Ndiv = target / source;
0378     }
0379
0380     if (Ndiv < 5 || Ndiv > 13) {
0381         pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
0382                __func__, Ndiv);
0383         return -EINVAL;
0384     }
0385     pll_div->n = Ndiv;
0386
0387     Nmod = target % source;
0388     Kpart = FIXED_PLL_SIZE * (u64)Nmod;
0389
0390     do_div(Kpart, source);
0391
0392     K = Kpart & 0xffffffff;
0393     if ((K % 10) >= 5)
0394         K += 5;
0395     K /= 10;
0396     pll_div->k = K;
0397
0398     return 0;
0399 }
0400
0401 static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
0402               int source, unsigned int freq_in,
0403               unsigned int freq_out)
0404 {
0405     struct snd_soc_component *component = dai->component;
0406     struct wm8804_priv *wm8804 = snd_soc_component_get_drvdata(component);
0407     bool change;
0408
0409     if (!freq_in || !freq_out) {
0410         /* disable the PLL */
0411         regmap_update_bits_check(wm8804->regmap, WM8804_PWRDN,
0412                      0x1, 0x1, &change);
0413         if (change)
0414             pm_runtime_put(wm8804->dev);
0415     } else {
0416         int ret;
0417         struct pll_div pll_div;
0418
0419         ret = pll_factors(&pll_div, freq_out, freq_in,
0420                   wm8804->mclk_div);
0421         if (ret)
0422             return ret;
0423
0424         /* power down the PLL before reprogramming it */
0425         regmap_update_bits_check(wm8804->regmap, WM8804_PWRDN,
0426                      0x1, 0x1, &change);
0427         if (!change)
0428             pm_runtime_get_sync(wm8804->dev);
0429
0430         /* set PLLN and PRESCALE */
0431         snd_soc_component_update_bits(component, WM8804_PLL4, 0xf | 0x10,
0432                     pll_div.n | (pll_div.prescale << 4));
0433         /* set mclkdiv and freqmode */
0434         snd_soc_component_update_bits(component, WM8804_PLL5, 0x3 | 0x8,
0435                     pll_div.freqmode | (pll_div.mclkdiv << 3));
0436         /* set PLLK */
0437         snd_soc_component_write(component, WM8804_PLL1, pll_div.k & 0xff);
0438         snd_soc_component_write(component, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
0439         snd_soc_component_write(component, WM8804_PLL3, pll_div.k >> 16);
0440
0441         /* power up the PLL */
0442         snd_soc_component_update_bits(component, WM8804_PWRDN, 0x1, 0);
0443     }
0444
0445     return 0;
0446 }
0447
0448 static int wm8804_set_sysclk(struct snd_soc_dai *dai,
0449                  int clk_id, unsigned int freq, int dir)
0450 {
0451     struct snd_soc_component *component;
0452
0453     component = dai->component;
0454
0455     switch (clk_id) {
0456     case WM8804_TX_CLKSRC_MCLK:
0457         if ((freq >= 10000000 && freq <= 14400000)
0458                 || (freq >= 16280000 && freq <= 27000000))
0459             snd_soc_component_update_bits(component, WM8804_PLL6, 0x80, 0x80);
0460         else {
0461             dev_err(dai->dev, "OSCCLOCK is not within the "
0462                 "recommended range: %uHz\n", freq);
0463             return -EINVAL;
0464         }
0465         break;
0466     case WM8804_TX_CLKSRC_PLL:
0467         snd_soc_component_update_bits(component, WM8804_PLL6, 0x80, 0);
0468         break;
0469     case WM8804_CLKOUT_SRC_CLK1:
0470         snd_soc_component_update_bits(component, WM8804_PLL6, 0x8, 0);
0471         break;
0472     case WM8804_CLKOUT_SRC_OSCCLK:
0473         snd_soc_component_update_bits(component, WM8804_PLL6, 0x8, 0x8);
0474         break;
0475     default:
0476         dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
0477         return -EINVAL;
0478     }
0479
0480     return 0;
0481 }
0482
0483 static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
0484                  int div_id, int div)
0485 {
0486     struct snd_soc_component *component;
0487     struct wm8804_priv *wm8804;
0488
0489     component = dai->component;
0490     switch (div_id) {
0491     case WM8804_CLKOUT_DIV:
0492         snd_soc_component_update_bits(component, WM8804_PLL5, 0x30,
0493                     (div & 0x3) << 4);
0494         break;
0495     case WM8804_MCLK_DIV:
0496         wm8804 = snd_soc_component_get_drvdata(component);
0497         wm8804->mclk_div = div;
0498         break;
0499     default:
0500         dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
0501         return -EINVAL;
0502     }
0503     return 0;
0504 }
0505
0506 static const struct snd_soc_dai_ops wm8804_dai_ops = {
0507     .hw_params = wm8804_hw_params,
0508     .set_fmt = wm8804_set_fmt,
0509     .set_sysclk = wm8804_set_sysclk,
0510     .set_clkdiv = wm8804_set_clkdiv,
0511     .set_pll = wm8804_set_pll
0512 };
0513
0514 #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
0515             SNDRV_PCM_FMTBIT_S24_LE)
0516
0517 #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
0518               SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
0519               SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
0520               SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
0521
0522 static struct snd_soc_dai_driver wm8804_dai = {
0523     .name = "wm8804-spdif",
0524     .playback = {
0525         .stream_name = "Playback",
0526         .channels_min = 2,
0527         .channels_max = 2,
0528         .rates = WM8804_RATES,
0529         .formats = WM8804_FORMATS,
0530     },
0531     .capture = {
0532         .stream_name = "Capture",
0533         .channels_min = 2,
0534         .channels_max = 2,
0535         .rates = WM8804_RATES,
0536         .formats = WM8804_FORMATS,
0537     },
0538     .ops = &wm8804_dai_ops,
0539     .symmetric_rate = 1
0540 };
0541
0542 static const struct snd_soc_component_driver soc_component_dev_wm8804 = {
0543     .dapm_widgets       = wm8804_dapm_widgets,
0544     .num_dapm_widgets   = ARRAY_SIZE(wm8804_dapm_widgets),
0545     .dapm_routes        = wm8804_dapm_routes,
0546     .num_dapm_routes    = ARRAY_SIZE(wm8804_dapm_routes),
0547     .use_pmdown_time    = 1,
0548     .endianness     = 1,
0549 };
0550
0551 const struct regmap_config wm8804_regmap_config = {
0552     .reg_bits = 8,
0553     .val_bits = 8,
0554
0555     .max_register = WM8804_MAX_REGISTER,
0556     .volatile_reg = wm8804_volatile,
0557
0558     .cache_type = REGCACHE_RBTREE,
0559     .reg_defaults = wm8804_reg_defaults,
0560     .num_reg_defaults = ARRAY_SIZE(wm8804_reg_defaults),
0561 };
0562 EXPORT_SYMBOL_GPL(wm8804_regmap_config);
0563
0564 int wm8804_probe(struct device *dev, struct regmap *regmap)
0565 {
0566     struct wm8804_priv *wm8804;
0567     unsigned int id1, id2;
0568     int i, ret;
0569
0570     wm8804 = devm_kzalloc(dev, sizeof(*wm8804), GFP_KERNEL);
0571     if (!wm8804)
0572         return -ENOMEM;
0573
0574     dev_set_drvdata(dev, wm8804);
0575
0576     wm8804->dev = dev;
0577     wm8804->regmap = regmap;
0578
0579     wm8804->reset = devm_gpiod_get_optional(dev, "wlf,reset",
0580                         GPIOD_OUT_LOW);
0581     if (IS_ERR(wm8804->reset)) {
0582         ret = PTR_ERR(wm8804->reset);
0583         dev_err(dev, "Failed to get reset line: %d\n", ret);
0584         return ret;
0585     }
0586
0587     for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
0588         wm8804->supplies[i].supply = wm8804_supply_names[i];
0589
0590     ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(wm8804->supplies),
0591                       wm8804->supplies);
0592     if (ret) {
0593         dev_err(dev, "Failed to request supplies: %d\n", ret);
0594         return ret;
0595     }
0596
0597     wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
0598     wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
0599
0600     /* This should really be moved into the regulator core */
0601     for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
0602         struct regulator *regulator = wm8804->supplies[i].consumer;
0603
0604         ret = devm_regulator_register_notifier(regulator,
0605                                &wm8804->disable_nb[i]);
0606         if (ret != 0) {
0607             dev_err(dev,
0608                 "Failed to register regulator notifier: %d\n",
0609                 ret);
0610             return ret;
0611         }
0612     }
0613
0614     ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
0615                     wm8804->supplies);
0616     if (ret) {
0617         dev_err(dev, "Failed to enable supplies: %d\n", ret);
0618         return ret;
0619     }
0620
0621     gpiod_set_value_cansleep(wm8804->reset, 1);
0622
0623     ret = regmap_read(regmap, WM8804_RST_DEVID1, &id1);
0624     if (ret < 0) {
0625         dev_err(dev, "Failed to read device ID: %d\n", ret);
0626         goto err_reg_enable;
0627     }
0628
0629     ret = regmap_read(regmap, WM8804_DEVID2, &id2);
0630     if (ret < 0) {
0631         dev_err(dev, "Failed to read device ID: %d\n", ret);
0632         goto err_reg_enable;
0633     }
0634
0635     id2 = (id2 << 8) | id1;
0636
0637     if (id2 != 0x8805) {
0638         dev_err(dev, "Invalid device ID: %#x\n", id2);
0639         ret = -EINVAL;
0640         goto err_reg_enable;
0641     }
0642
0643     ret = regmap_read(regmap, WM8804_DEVREV, &id1);
0644     if (ret < 0) {
0645         dev_err(dev, "Failed to read device revision: %d\n",
0646             ret);
0647         goto err_reg_enable;
0648     }
0649     dev_info(dev, "revision %c\n", id1 + 'A');
0650
0651     if (!wm8804->reset) {
0652         ret = wm8804_soft_reset(wm8804);
0653         if (ret < 0) {
0654             dev_err(dev, "Failed to issue reset: %d\n", ret);
0655             goto err_reg_enable;
0656         }
0657     }
0658
0659     ret = devm_snd_soc_register_component(dev, &soc_component_dev_wm8804,
0660                      &wm8804_dai, 1);
0661     if (ret < 0) {
0662         dev_err(dev, "Failed to register CODEC: %d\n", ret);
0663         goto err_reg_enable;
0664     }
0665
0666     pm_runtime_set_active(dev);
0667     pm_runtime_enable(dev);
0668     pm_runtime_idle(dev);
0669
0670     return 0;
0671
0672 err_reg_enable:
0673     regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
0674     return ret;
0675 }
0676 EXPORT_SYMBOL_GPL(wm8804_probe);
0677
0678 void wm8804_remove(struct device *dev)
0679 {
0680     pm_runtime_disable(dev);
0681 }
0682 EXPORT_SYMBOL_GPL(wm8804_remove);
0683
0684 #if IS_ENABLED(CONFIG_PM)
0685 static int wm8804_runtime_resume(struct device *dev)
0686 {
0687     struct wm8804_priv *wm8804 = dev_get_drvdata(dev);
0688     int ret;
0689
0690     ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
0691                     wm8804->supplies);
0692     if (ret) {
0693         dev_err(wm8804->dev, "Failed to enable supplies: %d\n", ret);
0694         return ret;
0695     }
0696
0697     regcache_sync(wm8804->regmap);
0698
0699     /* Power up OSCCLK */
0700     regmap_update_bits(wm8804->regmap, WM8804_PWRDN, 0x8, 0x0);
0701
0702     return 0;
0703 }
0704
0705 static int wm8804_runtime_suspend(struct device *dev)
0706 {
0707     struct wm8804_priv *wm8804 = dev_get_drvdata(dev);
0708
0709     /* Power down OSCCLK */
0710     regmap_update_bits(wm8804->regmap, WM8804_PWRDN, 0x8, 0x8);
0711
0712     regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
0713                    wm8804->supplies);
0714
0715     return 0;
0716 }
0717 #endif
0718
0719 const struct dev_pm_ops wm8804_pm = {
0720     SET_RUNTIME_PM_OPS(wm8804_runtime_suspend, wm8804_runtime_resume, NULL)
0721 };
0722 EXPORT_SYMBOL_GPL(wm8804_pm);
0723
0724 MODULE_DESCRIPTION("ASoC WM8804 driver");
0725 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
0726 MODULE_LICENSE("GPL");