soc/codecs/wm8753.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * wm8753.h  --  audio driver for WM8753
0004  *
0005  * Copyright 2003 Wolfson Microelectronics PLC.
0006  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
0007  */
0008
0009 #ifndef _WM8753_H
0010 #define _WM8753_H
0011
0012 /* WM8753 register space */
0013
0014 #define WM8753_DAC      0x01
0015 #define WM8753_ADC      0x02
0016 #define WM8753_PCM      0x03
0017 #define WM8753_HIFI     0x04
0018 #define WM8753_IOCTL        0x05
0019 #define WM8753_SRATE1       0x06
0020 #define WM8753_SRATE2       0x07
0021 #define WM8753_LDAC     0x08
0022 #define WM8753_RDAC     0x09
0023 #define WM8753_BASS     0x0a
0024 #define WM8753_TREBLE       0x0b
0025 #define WM8753_ALC1     0x0c
0026 #define WM8753_ALC2     0x0d
0027 #define WM8753_ALC3     0x0e
0028 #define WM8753_NGATE        0x0f
0029 #define WM8753_LADC     0x10
0030 #define WM8753_RADC     0x11
0031 #define WM8753_ADCTL1       0x12
0032 #define WM8753_3D       0x13
0033 #define WM8753_PWR1     0x14
0034 #define WM8753_PWR2     0x15
0035 #define WM8753_PWR3     0x16
0036 #define WM8753_PWR4     0x17
0037 #define WM8753_ID       0x18
0038 #define WM8753_INTPOL       0x19
0039 #define WM8753_INTEN        0x1a
0040 #define WM8753_GPIO1        0x1b
0041 #define WM8753_GPIO2        0x1c
0042 #define WM8753_RESET        0x1f
0043 #define WM8753_RECMIX1      0x20
0044 #define WM8753_RECMIX2      0x21
0045 #define WM8753_LOUTM1       0x22
0046 #define WM8753_LOUTM2       0x23
0047 #define WM8753_ROUTM1       0x24
0048 #define WM8753_ROUTM2       0x25
0049 #define WM8753_MOUTM1       0x26
0050 #define WM8753_MOUTM2       0x27
0051 #define WM8753_LOUT1V       0x28
0052 #define WM8753_ROUT1V       0x29
0053 #define WM8753_LOUT2V       0x2a
0054 #define WM8753_ROUT2V       0x2b
0055 #define WM8753_MOUTV        0x2c
0056 #define WM8753_OUTCTL       0x2d
0057 #define WM8753_ADCIN        0x2e
0058 #define WM8753_INCTL1       0x2f
0059 #define WM8753_INCTL2       0x30
0060 #define WM8753_LINVOL       0x31
0061 #define WM8753_RINVOL       0x32
0062 #define WM8753_MICBIAS      0x33
0063 #define WM8753_CLOCK        0x34
0064 #define WM8753_PLL1CTL1     0x35
0065 #define WM8753_PLL1CTL2     0x36
0066 #define WM8753_PLL1CTL3     0x37
0067 #define WM8753_PLL1CTL4     0x38
0068 #define WM8753_PLL2CTL1     0x39
0069 #define WM8753_PLL2CTL2     0x3a
0070 #define WM8753_PLL2CTL3     0x3b
0071 #define WM8753_PLL2CTL4     0x3c
0072 #define WM8753_BIASCTL      0x3d
0073 #define WM8753_ADCTL2       0x3f
0074
0075 #define WM8753_PLL1         0
0076 #define WM8753_PLL2         1
0077
0078 /* clock inputs */
0079 #define WM8753_MCLK     0
0080 #define WM8753_PCMCLK       1
0081
0082 /* clock divider id's */
0083 #define WM8753_PCMDIV       0
0084 #define WM8753_BCLKDIV      1
0085 #define WM8753_VXCLKDIV     2
0086
0087 /* PCM clock dividers */
0088 #define WM8753_PCM_DIV_1    (0 << 6)
0089 #define WM8753_PCM_DIV_3    (2 << 6)
0090 #define WM8753_PCM_DIV_5_5  (3 << 6)
0091 #define WM8753_PCM_DIV_2    (4 << 6)
0092 #define WM8753_PCM_DIV_4    (5 << 6)
0093 #define WM8753_PCM_DIV_6    (6 << 6)
0094 #define WM8753_PCM_DIV_8    (7 << 6)
0095
0096 /* BCLK clock dividers */
0097 #define WM8753_BCLK_DIV_1   (0 << 3)
0098 #define WM8753_BCLK_DIV_2   (1 << 3)
0099 #define WM8753_BCLK_DIV_4   (2 << 3)
0100 #define WM8753_BCLK_DIV_8   (3 << 3)
0101 #define WM8753_BCLK_DIV_16  (4 << 3)
0102
0103 /* VXCLK clock dividers */
0104 #define WM8753_VXCLK_DIV_1  (0 << 6)
0105 #define WM8753_VXCLK_DIV_2  (1 << 6)
0106 #define WM8753_VXCLK_DIV_4  (2 << 6)
0107 #define WM8753_VXCLK_DIV_8  (3 << 6)
0108 #define WM8753_VXCLK_DIV_16 (4 << 6)
0109
0110 #endif