Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8750.c -- WM8750 ALSA SoC audio driver
0004  *
0005  * Copyright 2005 Openedhand Ltd.
0006  *
0007  * Author: Richard Purdie <richard@openedhand.com>
0008  *
0009  * Based on WM8753.c
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/init.h>
0015 #include <linux/delay.h>
0016 #include <linux/pm.h>
0017 #include <linux/i2c.h>
0018 #include <linux/regmap.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/slab.h>
0021 #include <linux/of_device.h>
0022 #include <sound/core.h>
0023 #include <sound/pcm.h>
0024 #include <sound/pcm_params.h>
0025 #include <sound/soc.h>
0026 #include <sound/initval.h>
0027 
0028 #include "wm8750.h"
0029 
0030 /*
0031  * wm8750 register cache
0032  * We can't read the WM8750 register space when we
0033  * are using 2 wire for device control, so we cache them instead.
0034  */
0035 static const struct reg_default wm8750_reg_defaults[] = {
0036     {  0, 0x0097 },
0037     {  1, 0x0097 },
0038     {  2, 0x0079 },
0039     {  3, 0x0079 },
0040     {  4, 0x0000 },
0041     {  5, 0x0008 },
0042     {  6, 0x0000 },
0043     {  7, 0x000a },
0044     {  8, 0x0000 },
0045     {  9, 0x0000 },
0046     { 10, 0x00ff },
0047     { 11, 0x00ff },
0048     { 12, 0x000f },
0049     { 13, 0x000f },
0050     { 14, 0x0000 },
0051     { 15, 0x0000 },
0052     { 16, 0x0000 },
0053     { 17, 0x007b },
0054     { 18, 0x0000 },
0055     { 19, 0x0032 },
0056     { 20, 0x0000 },
0057     { 21, 0x00c3 },
0058     { 22, 0x00c3 },
0059     { 23, 0x00c0 },
0060     { 24, 0x0000 },
0061     { 25, 0x0000 },
0062     { 26, 0x0000 },
0063     { 27, 0x0000 },
0064     { 28, 0x0000 },
0065     { 29, 0x0000 },
0066     { 30, 0x0000 },
0067     { 31, 0x0000 },
0068     { 32, 0x0000 },
0069     { 33, 0x0000 },
0070     { 34, 0x0050 },
0071     { 35, 0x0050 },
0072     { 36, 0x0050 },
0073     { 37, 0x0050 },
0074     { 38, 0x0050 },
0075     { 39, 0x0050 },
0076     { 40, 0x0079 },
0077     { 41, 0x0079 },
0078     { 42, 0x0079 },
0079 };
0080 
0081 /* codec private data */
0082 struct wm8750_priv {
0083     unsigned int sysclk;
0084 };
0085 
0086 #define wm8750_reset(c) snd_soc_component_write(c, WM8750_RESET, 0)
0087 
0088 /*
0089  * WM8750 Controls
0090  */
0091 static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
0092 static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
0093 static const char *wm8750_treble[] = {"8kHz", "4kHz"};
0094 static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
0095 static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
0096 static const char *wm8750_3d_func[] = {"Capture", "Playback"};
0097 static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
0098 static const char *wm8750_ng_type[] = {"Constant PGA Gain",
0099     "Mute ADC Output"};
0100 static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
0101     "Differential"};
0102 static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
0103     "Differential"};
0104 static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
0105     "ROUT1"};
0106 static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
0107 static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
0108     "L + R Invert"};
0109 static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
0110 static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
0111     "Mono (Right)", "Digital Mono"};
0112 
0113 static const struct soc_enum wm8750_enum[] = {
0114 SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
0115 SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
0116 SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
0117 SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
0118 SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
0119 SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
0120 SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
0121 SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
0122 SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
0123 SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
0124 SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
0125 SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
0126 SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
0127 SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
0128 SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
0129 SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
0130 SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
0131 
0132 };
0133 
0134 static const struct snd_kcontrol_new wm8750_snd_controls[] = {
0135 
0136 SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
0137 SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
0138 SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
0139 
0140 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
0141     WM8750_ROUT1V, 7, 1, 0),
0142 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
0143     WM8750_ROUT2V, 7, 1, 0),
0144 
0145 SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
0146 
0147 SOC_ENUM("Capture Polarity", wm8750_enum[14]),
0148 SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
0149 SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
0150 
0151 SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
0152 
0153 SOC_ENUM("Bass Boost", wm8750_enum[0]),
0154 SOC_ENUM("Bass Filter", wm8750_enum[1]),
0155 SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
0156 
0157 SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
0158 SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
0159 
0160 SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
0161 SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
0162 SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
0163 SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
0164 SOC_ENUM("3D Mode", wm8750_enum[5]),
0165 
0166 SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
0167 SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
0168 SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
0169 SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
0170 SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
0171 SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
0172 SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
0173 SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
0174 SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
0175 SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
0176 
0177 SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
0178 SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
0179 
0180 SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
0181 SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
0182 
0183 SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
0184 
0185 /* Unimplemented */
0186 /* ADCDAC Bit 0 - ADCHPD */
0187 /* ADCDAC Bit 4 - HPOR */
0188 /* ADCTL1 Bit 2,3 - DATSEL */
0189 /* ADCTL1 Bit 4,5 - DMONOMIX */
0190 /* ADCTL1 Bit 6,7 - VSEL */
0191 /* ADCTL2 Bit 2 - LRCM */
0192 /* ADCTL2 Bit 3 - TRI */
0193 /* ADCTL3 Bit 5 - HPFLREN */
0194 /* ADCTL3 Bit 6 - VROI */
0195 /* ADCTL3 Bit 7,8 - ADCLRM */
0196 /* ADCIN Bit 4 - LDCM */
0197 /* ADCIN Bit 5 - RDCM */
0198 
0199 SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
0200 
0201 SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
0202     WM8750_LOUTM2, 4, 7, 1),
0203 SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
0204     WM8750_ROUTM2, 4, 7, 1),
0205 SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
0206     WM8750_MOUTM2, 4, 7, 1),
0207 
0208 SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
0209 
0210 SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
0211     0, 127, 0),
0212 SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
0213     0, 127, 0),
0214 
0215 SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
0216 
0217 };
0218 
0219 /*
0220  * DAPM Controls
0221  */
0222 
0223 /* Left Mixer */
0224 static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
0225 SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
0226 SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
0227 SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
0228 SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
0229 };
0230 
0231 /* Right Mixer */
0232 static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
0233 SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
0234 SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
0235 SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
0236 SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
0237 };
0238 
0239 /* Mono Mixer */
0240 static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
0241 SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
0242 SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
0243 SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
0244 SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
0245 };
0246 
0247 /* Left Line Mux */
0248 static const struct snd_kcontrol_new wm8750_left_line_controls =
0249 SOC_DAPM_ENUM("Route", wm8750_enum[8]);
0250 
0251 /* Right Line Mux */
0252 static const struct snd_kcontrol_new wm8750_right_line_controls =
0253 SOC_DAPM_ENUM("Route", wm8750_enum[9]);
0254 
0255 /* Left PGA Mux */
0256 static const struct snd_kcontrol_new wm8750_left_pga_controls =
0257 SOC_DAPM_ENUM("Route", wm8750_enum[10]);
0258 
0259 /* Right PGA Mux */
0260 static const struct snd_kcontrol_new wm8750_right_pga_controls =
0261 SOC_DAPM_ENUM("Route", wm8750_enum[11]);
0262 
0263 /* Out 3 Mux */
0264 static const struct snd_kcontrol_new wm8750_out3_controls =
0265 SOC_DAPM_ENUM("Route", wm8750_enum[12]);
0266 
0267 /* Differential Mux */
0268 static const struct snd_kcontrol_new wm8750_diffmux_controls =
0269 SOC_DAPM_ENUM("Route", wm8750_enum[13]);
0270 
0271 /* Mono ADC Mux */
0272 static const struct snd_kcontrol_new wm8750_monomux_controls =
0273 SOC_DAPM_ENUM("Route", wm8750_enum[16]);
0274 
0275 static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
0276     SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
0277         &wm8750_left_mixer_controls[0],
0278         ARRAY_SIZE(wm8750_left_mixer_controls)),
0279     SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
0280         &wm8750_right_mixer_controls[0],
0281         ARRAY_SIZE(wm8750_right_mixer_controls)),
0282     SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
0283         &wm8750_mono_mixer_controls[0],
0284         ARRAY_SIZE(wm8750_mono_mixer_controls)),
0285 
0286     SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
0287     SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
0288     SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
0289     SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
0290     SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
0291     SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
0292 
0293     SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
0294     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
0295     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
0296 
0297     SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
0298         &wm8750_left_pga_controls),
0299     SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
0300         &wm8750_right_pga_controls),
0301     SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
0302         &wm8750_left_line_controls),
0303     SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
0304         &wm8750_right_line_controls),
0305 
0306     SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
0307     SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
0308     SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
0309 
0310     SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
0311         &wm8750_diffmux_controls),
0312     SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
0313         &wm8750_monomux_controls),
0314     SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
0315         &wm8750_monomux_controls),
0316 
0317     SND_SOC_DAPM_OUTPUT("LOUT1"),
0318     SND_SOC_DAPM_OUTPUT("ROUT1"),
0319     SND_SOC_DAPM_OUTPUT("LOUT2"),
0320     SND_SOC_DAPM_OUTPUT("ROUT2"),
0321     SND_SOC_DAPM_OUTPUT("MONO1"),
0322     SND_SOC_DAPM_OUTPUT("OUT3"),
0323     SND_SOC_DAPM_VMID("VREF"),
0324 
0325     SND_SOC_DAPM_INPUT("LINPUT1"),
0326     SND_SOC_DAPM_INPUT("LINPUT2"),
0327     SND_SOC_DAPM_INPUT("LINPUT3"),
0328     SND_SOC_DAPM_INPUT("RINPUT1"),
0329     SND_SOC_DAPM_INPUT("RINPUT2"),
0330     SND_SOC_DAPM_INPUT("RINPUT3"),
0331 };
0332 
0333 static const struct snd_soc_dapm_route wm8750_dapm_routes[] = {
0334     /* left mixer */
0335     {"Left Mixer", "Playback Switch", "Left DAC"},
0336     {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
0337     {"Left Mixer", "Right Playback Switch", "Right DAC"},
0338     {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
0339 
0340     /* right mixer */
0341     {"Right Mixer", "Left Playback Switch", "Left DAC"},
0342     {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
0343     {"Right Mixer", "Playback Switch", "Right DAC"},
0344     {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
0345 
0346     /* left out 1 */
0347     {"Left Out 1", NULL, "Left Mixer"},
0348     {"LOUT1", NULL, "Left Out 1"},
0349 
0350     /* left out 2 */
0351     {"Left Out 2", NULL, "Left Mixer"},
0352     {"LOUT2", NULL, "Left Out 2"},
0353 
0354     /* right out 1 */
0355     {"Right Out 1", NULL, "Right Mixer"},
0356     {"ROUT1", NULL, "Right Out 1"},
0357 
0358     /* right out 2 */
0359     {"Right Out 2", NULL, "Right Mixer"},
0360     {"ROUT2", NULL, "Right Out 2"},
0361 
0362     /* mono mixer */
0363     {"Mono Mixer", "Left Playback Switch", "Left DAC"},
0364     {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
0365     {"Mono Mixer", "Right Playback Switch", "Right DAC"},
0366     {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
0367 
0368     /* mono out */
0369     {"Mono Out 1", NULL, "Mono Mixer"},
0370     {"MONO1", NULL, "Mono Out 1"},
0371 
0372     /* out 3 */
0373     {"Out3 Mux", "VREF", "VREF"},
0374     {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
0375     {"Out3 Mux", "ROUT1", "Right Mixer"},
0376     {"Out3 Mux", "MonoOut", "MONO1"},
0377     {"Out 3", NULL, "Out3 Mux"},
0378     {"OUT3", NULL, "Out 3"},
0379 
0380     /* Left Line Mux */
0381     {"Left Line Mux", "Line 1", "LINPUT1"},
0382     {"Left Line Mux", "Line 2", "LINPUT2"},
0383     {"Left Line Mux", "Line 3", "LINPUT3"},
0384     {"Left Line Mux", "PGA", "Left PGA Mux"},
0385     {"Left Line Mux", "Differential", "Differential Mux"},
0386 
0387     /* Right Line Mux */
0388     {"Right Line Mux", "Line 1", "RINPUT1"},
0389     {"Right Line Mux", "Line 2", "RINPUT2"},
0390     {"Right Line Mux", "Line 3", "RINPUT3"},
0391     {"Right Line Mux", "PGA", "Right PGA Mux"},
0392     {"Right Line Mux", "Differential", "Differential Mux"},
0393 
0394     /* Left PGA Mux */
0395     {"Left PGA Mux", "Line 1", "LINPUT1"},
0396     {"Left PGA Mux", "Line 2", "LINPUT2"},
0397     {"Left PGA Mux", "Line 3", "LINPUT3"},
0398     {"Left PGA Mux", "Differential", "Differential Mux"},
0399 
0400     /* Right PGA Mux */
0401     {"Right PGA Mux", "Line 1", "RINPUT1"},
0402     {"Right PGA Mux", "Line 2", "RINPUT2"},
0403     {"Right PGA Mux", "Line 3", "RINPUT3"},
0404     {"Right PGA Mux", "Differential", "Differential Mux"},
0405 
0406     /* Differential Mux */
0407     {"Differential Mux", "Line 1", "LINPUT1"},
0408     {"Differential Mux", "Line 1", "RINPUT1"},
0409     {"Differential Mux", "Line 2", "LINPUT2"},
0410     {"Differential Mux", "Line 2", "RINPUT2"},
0411 
0412     /* Left ADC Mux */
0413     {"Left ADC Mux", "Stereo", "Left PGA Mux"},
0414     {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
0415     {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
0416 
0417     /* Right ADC Mux */
0418     {"Right ADC Mux", "Stereo", "Right PGA Mux"},
0419     {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
0420     {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
0421 
0422     /* ADC */
0423     {"Left ADC", NULL, "Left ADC Mux"},
0424     {"Right ADC", NULL, "Right ADC Mux"},
0425 };
0426 
0427 struct _coeff_div {
0428     u32 mclk;
0429     u32 rate;
0430     u16 fs;
0431     u8 sr:5;
0432     u8 usb:1;
0433 };
0434 
0435 /* codec hifi mclk clock divider coefficients */
0436 static const struct _coeff_div coeff_div[] = {
0437     /* 8k */
0438     {12288000, 8000, 1536, 0x6, 0x0},
0439     {11289600, 8000, 1408, 0x16, 0x0},
0440     {18432000, 8000, 2304, 0x7, 0x0},
0441     {16934400, 8000, 2112, 0x17, 0x0},
0442     {12000000, 8000, 1500, 0x6, 0x1},
0443 
0444     /* 11.025k */
0445     {11289600, 11025, 1024, 0x18, 0x0},
0446     {16934400, 11025, 1536, 0x19, 0x0},
0447     {12000000, 11025, 1088, 0x19, 0x1},
0448 
0449     /* 16k */
0450     {12288000, 16000, 768, 0xa, 0x0},
0451     {18432000, 16000, 1152, 0xb, 0x0},
0452     {12000000, 16000, 750, 0xa, 0x1},
0453 
0454     /* 22.05k */
0455     {11289600, 22050, 512, 0x1a, 0x0},
0456     {16934400, 22050, 768, 0x1b, 0x0},
0457     {12000000, 22050, 544, 0x1b, 0x1},
0458 
0459     /* 32k */
0460     {12288000, 32000, 384, 0xc, 0x0},
0461     {18432000, 32000, 576, 0xd, 0x0},
0462     {12000000, 32000, 375, 0xa, 0x1},
0463 
0464     /* 44.1k */
0465     {11289600, 44100, 256, 0x10, 0x0},
0466     {16934400, 44100, 384, 0x11, 0x0},
0467     {12000000, 44100, 272, 0x11, 0x1},
0468 
0469     /* 48k */
0470     {12288000, 48000, 256, 0x0, 0x0},
0471     {18432000, 48000, 384, 0x1, 0x0},
0472     {12000000, 48000, 250, 0x0, 0x1},
0473 
0474     /* 88.2k */
0475     {11289600, 88200, 128, 0x1e, 0x0},
0476     {16934400, 88200, 192, 0x1f, 0x0},
0477     {12000000, 88200, 136, 0x1f, 0x1},
0478 
0479     /* 96k */
0480     {12288000, 96000, 128, 0xe, 0x0},
0481     {18432000, 96000, 192, 0xf, 0x0},
0482     {12000000, 96000, 125, 0xe, 0x1},
0483 };
0484 
0485 static inline int get_coeff(int mclk, int rate)
0486 {
0487     int i;
0488 
0489     for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
0490         if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
0491             return i;
0492     }
0493 
0494     printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
0495         mclk, rate);
0496     return -EINVAL;
0497 }
0498 
0499 static int wm8750_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0500         int clk_id, unsigned int freq, int dir)
0501 {
0502     struct snd_soc_component *component = codec_dai->component;
0503     struct wm8750_priv *wm8750 = snd_soc_component_get_drvdata(component);
0504 
0505     switch (freq) {
0506     case 11289600:
0507     case 12000000:
0508     case 12288000:
0509     case 16934400:
0510     case 18432000:
0511         wm8750->sysclk = freq;
0512         return 0;
0513     }
0514     return -EINVAL;
0515 }
0516 
0517 static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
0518         unsigned int fmt)
0519 {
0520     struct snd_soc_component *component = codec_dai->component;
0521     u16 iface = 0;
0522 
0523     /* set master/slave audio interface */
0524     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0525     case SND_SOC_DAIFMT_CBM_CFM:
0526         iface = 0x0040;
0527         break;
0528     case SND_SOC_DAIFMT_CBS_CFS:
0529         break;
0530     default:
0531         return -EINVAL;
0532     }
0533 
0534     /* interface format */
0535     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0536     case SND_SOC_DAIFMT_I2S:
0537         iface |= 0x0002;
0538         break;
0539     case SND_SOC_DAIFMT_RIGHT_J:
0540         break;
0541     case SND_SOC_DAIFMT_LEFT_J:
0542         iface |= 0x0001;
0543         break;
0544     case SND_SOC_DAIFMT_DSP_A:
0545         iface |= 0x0003;
0546         break;
0547     case SND_SOC_DAIFMT_DSP_B:
0548         iface |= 0x0013;
0549         break;
0550     default:
0551         return -EINVAL;
0552     }
0553 
0554     /* clock inversion */
0555     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0556     case SND_SOC_DAIFMT_NB_NF:
0557         break;
0558     case SND_SOC_DAIFMT_IB_IF:
0559         iface |= 0x0090;
0560         break;
0561     case SND_SOC_DAIFMT_IB_NF:
0562         iface |= 0x0080;
0563         break;
0564     case SND_SOC_DAIFMT_NB_IF:
0565         iface |= 0x0010;
0566         break;
0567     default:
0568         return -EINVAL;
0569     }
0570 
0571     snd_soc_component_write(component, WM8750_IFACE, iface);
0572     return 0;
0573 }
0574 
0575 static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
0576                 struct snd_pcm_hw_params *params,
0577                 struct snd_soc_dai *dai)
0578 {
0579     struct snd_soc_component *component = dai->component;
0580     struct wm8750_priv *wm8750 = snd_soc_component_get_drvdata(component);
0581     u16 iface = snd_soc_component_read(component, WM8750_IFACE) & 0x1f3;
0582     u16 srate = snd_soc_component_read(component, WM8750_SRATE) & 0x1c0;
0583     int coeff = get_coeff(wm8750->sysclk, params_rate(params));
0584 
0585     /* bit size */
0586     switch (params_width(params)) {
0587     case 16:
0588         break;
0589     case 20:
0590         iface |= 0x0004;
0591         break;
0592     case 24:
0593         iface |= 0x0008;
0594         break;
0595     case 32:
0596         iface |= 0x000c;
0597         break;
0598     }
0599 
0600     /* set iface & srate */
0601     snd_soc_component_write(component, WM8750_IFACE, iface);
0602     if (coeff >= 0)
0603         snd_soc_component_write(component, WM8750_SRATE, srate |
0604             (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
0605 
0606     return 0;
0607 }
0608 
0609 static int wm8750_mute(struct snd_soc_dai *dai, int mute, int direction)
0610 {
0611     struct snd_soc_component *component = dai->component;
0612     u16 mute_reg = snd_soc_component_read(component, WM8750_ADCDAC) & 0xfff7;
0613 
0614     if (mute)
0615         snd_soc_component_write(component, WM8750_ADCDAC, mute_reg | 0x8);
0616     else
0617         snd_soc_component_write(component, WM8750_ADCDAC, mute_reg);
0618     return 0;
0619 }
0620 
0621 static int wm8750_set_bias_level(struct snd_soc_component *component,
0622                  enum snd_soc_bias_level level)
0623 {
0624     u16 pwr_reg = snd_soc_component_read(component, WM8750_PWR1) & 0xfe3e;
0625 
0626     switch (level) {
0627     case SND_SOC_BIAS_ON:
0628         /* set vmid to 50k and unmute dac */
0629         snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x00c0);
0630         break;
0631     case SND_SOC_BIAS_PREPARE:
0632         break;
0633     case SND_SOC_BIAS_STANDBY:
0634         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0635             snd_soc_component_cache_sync(component);
0636 
0637             /* Set VMID to 5k */
0638             snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x01c1);
0639 
0640             /* ...and ramp */
0641             msleep(1000);
0642         }
0643 
0644         /* mute dac and set vmid to 500k, enable VREF */
0645         snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x0141);
0646         break;
0647     case SND_SOC_BIAS_OFF:
0648         snd_soc_component_write(component, WM8750_PWR1, 0x0001);
0649         break;
0650     }
0651     return 0;
0652 }
0653 
0654 #define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
0655     SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
0656     SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
0657 
0658 #define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
0659     SNDRV_PCM_FMTBIT_S24_LE)
0660 
0661 static const struct snd_soc_dai_ops wm8750_dai_ops = {
0662     .hw_params  = wm8750_pcm_hw_params,
0663     .mute_stream    = wm8750_mute,
0664     .set_fmt    = wm8750_set_dai_fmt,
0665     .set_sysclk = wm8750_set_dai_sysclk,
0666     .no_capture_mute = 1,
0667 };
0668 
0669 static struct snd_soc_dai_driver wm8750_dai = {
0670     .name = "wm8750-hifi",
0671     .playback = {
0672         .stream_name = "Playback",
0673         .channels_min = 1,
0674         .channels_max = 2,
0675         .rates = WM8750_RATES,
0676         .formats = WM8750_FORMATS,},
0677     .capture = {
0678         .stream_name = "Capture",
0679         .channels_min = 1,
0680         .channels_max = 2,
0681         .rates = WM8750_RATES,
0682         .formats = WM8750_FORMATS,},
0683     .ops = &wm8750_dai_ops,
0684 };
0685 
0686 static int wm8750_probe(struct snd_soc_component *component)
0687 {
0688     int ret;
0689 
0690     ret = wm8750_reset(component);
0691     if (ret < 0) {
0692         printk(KERN_ERR "wm8750: failed to reset: %d\n", ret);
0693         return ret;
0694     }
0695 
0696     /* set the update bits */
0697     snd_soc_component_update_bits(component, WM8750_LDAC, 0x0100, 0x0100);
0698     snd_soc_component_update_bits(component, WM8750_RDAC, 0x0100, 0x0100);
0699     snd_soc_component_update_bits(component, WM8750_LOUT1V, 0x0100, 0x0100);
0700     snd_soc_component_update_bits(component, WM8750_ROUT1V, 0x0100, 0x0100);
0701     snd_soc_component_update_bits(component, WM8750_LOUT2V, 0x0100, 0x0100);
0702     snd_soc_component_update_bits(component, WM8750_ROUT2V, 0x0100, 0x0100);
0703     snd_soc_component_update_bits(component, WM8750_LINVOL, 0x0100, 0x0100);
0704     snd_soc_component_update_bits(component, WM8750_RINVOL, 0x0100, 0x0100);
0705 
0706     return ret;
0707 }
0708 
0709 static const struct snd_soc_component_driver soc_component_dev_wm8750 = {
0710     .probe          = wm8750_probe,
0711     .set_bias_level     = wm8750_set_bias_level,
0712     .controls       = wm8750_snd_controls,
0713     .num_controls       = ARRAY_SIZE(wm8750_snd_controls),
0714     .dapm_widgets       = wm8750_dapm_widgets,
0715     .num_dapm_widgets   = ARRAY_SIZE(wm8750_dapm_widgets),
0716     .dapm_routes        = wm8750_dapm_routes,
0717     .num_dapm_routes    = ARRAY_SIZE(wm8750_dapm_routes),
0718     .suspend_bias_off   = 1,
0719     .idle_bias_on       = 1,
0720     .use_pmdown_time    = 1,
0721     .endianness     = 1,
0722 };
0723 
0724 static const struct of_device_id wm8750_of_match[] = {
0725     { .compatible = "wlf,wm8750", },
0726     { .compatible = "wlf,wm8987", },
0727     { }
0728 };
0729 MODULE_DEVICE_TABLE(of, wm8750_of_match);
0730 
0731 static const struct regmap_config wm8750_regmap = {
0732     .reg_bits = 7,
0733     .val_bits = 9,
0734     .max_register = WM8750_MOUTV,
0735 
0736     .reg_defaults = wm8750_reg_defaults,
0737     .num_reg_defaults = ARRAY_SIZE(wm8750_reg_defaults),
0738     .cache_type = REGCACHE_RBTREE,
0739 };
0740 
0741 #if defined(CONFIG_SPI_MASTER)
0742 static int wm8750_spi_probe(struct spi_device *spi)
0743 {
0744     struct wm8750_priv *wm8750;
0745     struct regmap *regmap;
0746     int ret;
0747 
0748     wm8750 = devm_kzalloc(&spi->dev, sizeof(struct wm8750_priv),
0749                   GFP_KERNEL);
0750     if (wm8750 == NULL)
0751         return -ENOMEM;
0752 
0753     regmap = devm_regmap_init_spi(spi, &wm8750_regmap);
0754     if (IS_ERR(regmap))
0755         return PTR_ERR(regmap);
0756 
0757     spi_set_drvdata(spi, wm8750);
0758 
0759     ret = devm_snd_soc_register_component(&spi->dev,
0760             &soc_component_dev_wm8750, &wm8750_dai, 1);
0761     return ret;
0762 }
0763 
0764 static const struct spi_device_id wm8750_spi_ids[] = {
0765     { "wm8750", 0 },
0766     { "wm8987", 0 },
0767     { },
0768 };
0769 MODULE_DEVICE_TABLE(spi, wm8750_spi_ids);
0770 
0771 static struct spi_driver wm8750_spi_driver = {
0772     .driver = {
0773         .name   = "wm8750",
0774         .of_match_table = wm8750_of_match,
0775     },
0776     .id_table   = wm8750_spi_ids,
0777     .probe      = wm8750_spi_probe,
0778 };
0779 #endif /* CONFIG_SPI_MASTER */
0780 
0781 #if IS_ENABLED(CONFIG_I2C)
0782 static int wm8750_i2c_probe(struct i2c_client *i2c)
0783 {
0784     struct wm8750_priv *wm8750;
0785     struct regmap *regmap;
0786     int ret;
0787 
0788     wm8750 = devm_kzalloc(&i2c->dev, sizeof(struct wm8750_priv),
0789                   GFP_KERNEL);
0790     if (wm8750 == NULL)
0791         return -ENOMEM;
0792 
0793     i2c_set_clientdata(i2c, wm8750);
0794 
0795     regmap = devm_regmap_init_i2c(i2c, &wm8750_regmap);
0796     if (IS_ERR(regmap))
0797         return PTR_ERR(regmap);
0798 
0799     ret = devm_snd_soc_register_component(&i2c->dev,
0800             &soc_component_dev_wm8750, &wm8750_dai, 1);
0801     return ret;
0802 }
0803 
0804 static const struct i2c_device_id wm8750_i2c_id[] = {
0805     { "wm8750", 0 },
0806     { "wm8987", 0 },
0807     { }
0808 };
0809 MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
0810 
0811 static struct i2c_driver wm8750_i2c_driver = {
0812     .driver = {
0813         .name = "wm8750",
0814         .of_match_table = wm8750_of_match,
0815     },
0816     .probe_new = wm8750_i2c_probe,
0817     .id_table = wm8750_i2c_id,
0818 };
0819 #endif
0820 
0821 static int __init wm8750_modinit(void)
0822 {
0823     int ret = 0;
0824 #if IS_ENABLED(CONFIG_I2C)
0825     ret = i2c_add_driver(&wm8750_i2c_driver);
0826     if (ret != 0) {
0827         printk(KERN_ERR "Failed to register wm8750 I2C driver: %d\n",
0828                ret);
0829     }
0830 #endif
0831 #if defined(CONFIG_SPI_MASTER)
0832     ret = spi_register_driver(&wm8750_spi_driver);
0833     if (ret != 0) {
0834         printk(KERN_ERR "Failed to register wm8750 SPI driver: %d\n",
0835                ret);
0836     }
0837 #endif
0838     return ret;
0839 }
0840 module_init(wm8750_modinit);
0841 
0842 static void __exit wm8750_exit(void)
0843 {
0844 #if IS_ENABLED(CONFIG_I2C)
0845     i2c_del_driver(&wm8750_i2c_driver);
0846 #endif
0847 #if defined(CONFIG_SPI_MASTER)
0848     spi_unregister_driver(&wm8750_spi_driver);
0849 #endif
0850 }
0851 module_exit(wm8750_exit);
0852 
0853 MODULE_DESCRIPTION("ASoC WM8750 driver");
0854 MODULE_AUTHOR("Liam Girdwood");
0855 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!