Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * wm8580.c  --  WM8580 and WM8581 ALSA Soc Audio driver
0004  *
0005  * Copyright 2008-12 Wolfson Microelectronics PLC.
0006  *
0007  * Notes:
0008  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
0009  *  DAC channels and two ADC channels.
0010  *
0011  *  The WM8581 is a multichannel codec with S/PDIF support, featuring eight
0012  *  DAC channels and two ADC channels.
0013  *
0014  *  Currently only the primary audio interface is supported - S/PDIF and
0015  *  the secondary audio interfaces are not.
0016  */
0017 
0018 #include <linux/module.h>
0019 #include <linux/moduleparam.h>
0020 #include <linux/kernel.h>
0021 #include <linux/init.h>
0022 #include <linux/delay.h>
0023 #include <linux/pm.h>
0024 #include <linux/i2c.h>
0025 #include <linux/regmap.h>
0026 #include <linux/regulator/consumer.h>
0027 #include <linux/slab.h>
0028 #include <linux/of_device.h>
0029 
0030 #include <sound/core.h>
0031 #include <sound/pcm.h>
0032 #include <sound/pcm_params.h>
0033 #include <sound/soc.h>
0034 #include <sound/tlv.h>
0035 #include <sound/initval.h>
0036 #include <asm/div64.h>
0037 
0038 #include "wm8580.h"
0039 
0040 /* WM8580 register space */
0041 #define WM8580_PLLA1                         0x00
0042 #define WM8580_PLLA2                         0x01
0043 #define WM8580_PLLA3                         0x02
0044 #define WM8580_PLLA4                         0x03
0045 #define WM8580_PLLB1                         0x04
0046 #define WM8580_PLLB2                         0x05
0047 #define WM8580_PLLB3                         0x06
0048 #define WM8580_PLLB4                         0x07
0049 #define WM8580_CLKSEL                        0x08
0050 #define WM8580_PAIF1                         0x09
0051 #define WM8580_PAIF2                         0x0A
0052 #define WM8580_SAIF1                         0x0B
0053 #define WM8580_PAIF3                         0x0C
0054 #define WM8580_PAIF4                         0x0D
0055 #define WM8580_SAIF2                         0x0E
0056 #define WM8580_DAC_CONTROL1                  0x0F
0057 #define WM8580_DAC_CONTROL2                  0x10
0058 #define WM8580_DAC_CONTROL3                  0x11
0059 #define WM8580_DAC_CONTROL4                  0x12
0060 #define WM8580_DAC_CONTROL5                  0x13
0061 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
0062 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
0063 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
0064 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
0065 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
0066 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
0067 #define WM8581_DIGITAL_ATTENUATION_DACL4     0x1A
0068 #define WM8581_DIGITAL_ATTENUATION_DACR4     0x1B
0069 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
0070 #define WM8580_ADC_CONTROL1                  0x1D
0071 #define WM8580_SPDTXCHAN0                    0x1E
0072 #define WM8580_SPDTXCHAN1                    0x1F
0073 #define WM8580_SPDTXCHAN2                    0x20
0074 #define WM8580_SPDTXCHAN3                    0x21
0075 #define WM8580_SPDTXCHAN4                    0x22
0076 #define WM8580_SPDTXCHAN5                    0x23
0077 #define WM8580_SPDMODE                       0x24
0078 #define WM8580_INTMASK                       0x25
0079 #define WM8580_GPO1                          0x26
0080 #define WM8580_GPO2                          0x27
0081 #define WM8580_GPO3                          0x28
0082 #define WM8580_GPO4                          0x29
0083 #define WM8580_GPO5                          0x2A
0084 #define WM8580_INTSTAT                       0x2B
0085 #define WM8580_SPDRXCHAN1                    0x2C
0086 #define WM8580_SPDRXCHAN2                    0x2D
0087 #define WM8580_SPDRXCHAN3                    0x2E
0088 #define WM8580_SPDRXCHAN4                    0x2F
0089 #define WM8580_SPDRXCHAN5                    0x30
0090 #define WM8580_SPDSTAT                       0x31
0091 #define WM8580_PWRDN1                        0x32
0092 #define WM8580_PWRDN2                        0x33
0093 #define WM8580_READBACK                      0x34
0094 #define WM8580_RESET                         0x35
0095 
0096 #define WM8580_MAX_REGISTER                  0x35
0097 
0098 #define WM8580_DACOSR 0x40
0099 
0100 /* PLLB4 (register 7h) */
0101 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
0102 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
0103 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
0104 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
0105 
0106 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
0107 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
0108 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
0109 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
0110 
0111 /* CLKSEL (register 8h) */
0112 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
0113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
0114 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
0115 
0116 /* AIF control 1 (registers 9h-bh) */
0117 #define WM8580_AIF_RATE_MASK       0x7
0118 #define WM8580_AIF_BCLKSEL_MASK   0x18
0119 
0120 #define WM8580_AIF_MS             0x20
0121 
0122 #define WM8580_AIF_CLKSRC_MASK    0xc0
0123 #define WM8580_AIF_CLKSRC_PLLA    0x40
0124 #define WM8580_AIF_CLKSRC_PLLB    0x40
0125 #define WM8580_AIF_CLKSRC_MCLK    0xc0
0126 
0127 /* AIF control 2 (registers ch-eh) */
0128 #define WM8580_AIF_FMT_MASK    0x03
0129 #define WM8580_AIF_FMT_RIGHTJ  0x00
0130 #define WM8580_AIF_FMT_LEFTJ   0x01
0131 #define WM8580_AIF_FMT_I2S     0x02
0132 #define WM8580_AIF_FMT_DSP     0x03
0133 
0134 #define WM8580_AIF_LENGTH_MASK   0x0c
0135 #define WM8580_AIF_LENGTH_16     0x00
0136 #define WM8580_AIF_LENGTH_20     0x04
0137 #define WM8580_AIF_LENGTH_24     0x08
0138 #define WM8580_AIF_LENGTH_32     0x0c
0139 
0140 #define WM8580_AIF_LRP         0x10
0141 #define WM8580_AIF_BCP         0x20
0142 
0143 /* Powerdown Register 1 (register 32h) */
0144 #define WM8580_PWRDN1_PWDN     0x001
0145 #define WM8580_PWRDN1_ALLDACPD 0x040
0146 
0147 /* Powerdown Register 2 (register 33h) */
0148 #define WM8580_PWRDN2_OSSCPD   0x001
0149 #define WM8580_PWRDN2_PLLAPD   0x002
0150 #define WM8580_PWRDN2_PLLBPD   0x004
0151 #define WM8580_PWRDN2_SPDIFPD  0x008
0152 #define WM8580_PWRDN2_SPDIFTXD 0x010
0153 #define WM8580_PWRDN2_SPDIFRXD 0x020
0154 
0155 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
0156 
0157 /*
0158  * wm8580 register cache
0159  * We can't read the WM8580 register space when we
0160  * are using 2 wire for device control, so we cache them instead.
0161  */
0162 static const struct reg_default wm8580_reg_defaults[] = {
0163     {  0, 0x0121 },
0164     {  1, 0x017e },
0165     {  2, 0x007d },
0166     {  3, 0x0014 },
0167     {  4, 0x0121 },
0168     {  5, 0x017e },
0169     {  6, 0x007d },
0170     {  7, 0x0194 },
0171     {  8, 0x0010 },
0172     {  9, 0x0002 },
0173     { 10, 0x0002 },
0174     { 11, 0x00c2 },
0175     { 12, 0x0182 },
0176     { 13, 0x0082 },
0177     { 14, 0x000a },
0178     { 15, 0x0024 },
0179     { 16, 0x0009 },
0180     { 17, 0x0000 },
0181     { 18, 0x00ff },
0182     { 19, 0x0000 },
0183     { 20, 0x00ff },
0184     { 21, 0x00ff },
0185     { 22, 0x00ff },
0186     { 23, 0x00ff },
0187     { 24, 0x00ff },
0188     { 25, 0x00ff },
0189     { 26, 0x00ff },
0190     { 27, 0x00ff },
0191     { 28, 0x01f0 },
0192     { 29, 0x0040 },
0193     { 30, 0x0000 },
0194     { 31, 0x0000 },
0195     { 32, 0x0000 },
0196     { 33, 0x0000 },
0197     { 34, 0x0031 },
0198     { 35, 0x000b },
0199     { 36, 0x0039 },
0200     { 37, 0x0000 },
0201     { 38, 0x0010 },
0202     { 39, 0x0032 },
0203     { 40, 0x0054 },
0204     { 41, 0x0076 },
0205     { 42, 0x0098 },
0206     { 43, 0x0000 },
0207     { 44, 0x0000 },
0208     { 45, 0x0000 },
0209     { 46, 0x0000 },
0210     { 47, 0x0000 },
0211     { 48, 0x0000 },
0212     { 49, 0x0000 },
0213     { 50, 0x005e },
0214     { 51, 0x003e },
0215     { 52, 0x0000 },
0216 };
0217 
0218 static bool wm8580_volatile(struct device *dev, unsigned int reg)
0219 {
0220     switch (reg) {
0221     case WM8580_RESET:
0222         return true;
0223     default:
0224         return false;
0225     }
0226 }
0227 
0228 struct pll_state {
0229     unsigned int in;
0230     unsigned int out;
0231 };
0232 
0233 #define WM8580_NUM_SUPPLIES 3
0234 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
0235     "AVDD",
0236     "DVDD",
0237     "PVDD",
0238 };
0239 
0240 struct wm8580_driver_data {
0241     int num_dacs;
0242 };
0243 
0244 /* codec private data */
0245 struct wm8580_priv {
0246     struct regmap *regmap;
0247     struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
0248     struct pll_state a;
0249     struct pll_state b;
0250     const struct wm8580_driver_data *drvdata;
0251     int sysclk[2];
0252 };
0253 
0254 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
0255 
0256 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
0257              struct snd_ctl_elem_value *ucontrol)
0258 {
0259     struct soc_mixer_control *mc =
0260         (struct soc_mixer_control *)kcontrol->private_value;
0261     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0262     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0263     unsigned int reg = mc->reg;
0264     unsigned int reg2 = mc->rreg;
0265     int ret;
0266 
0267     /* Clear the register cache VU so we write without VU set */
0268     regcache_cache_only(wm8580->regmap, true);
0269     regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000);
0270     regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000);
0271     regcache_cache_only(wm8580->regmap, false);
0272 
0273     ret = snd_soc_put_volsw(kcontrol, ucontrol);
0274     if (ret < 0)
0275         return ret;
0276 
0277     /* Now write again with the volume update bit set */
0278     snd_soc_component_update_bits(component, reg, 0x100, 0x100);
0279     snd_soc_component_update_bits(component, reg2, 0x100, 0x100);
0280 
0281     return 0;
0282 }
0283 
0284 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
0285 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
0286              WM8580_DIGITAL_ATTENUATION_DACL1,
0287              WM8580_DIGITAL_ATTENUATION_DACR1,
0288              0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
0289 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
0290              WM8580_DIGITAL_ATTENUATION_DACL2,
0291              WM8580_DIGITAL_ATTENUATION_DACR2,
0292              0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
0293 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
0294              WM8580_DIGITAL_ATTENUATION_DACL3,
0295              WM8580_DIGITAL_ATTENUATION_DACR3,
0296              0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
0297 
0298 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
0299 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
0300 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
0301 
0302 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
0303 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
0304 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
0305 
0306 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
0307 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
0308 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
0309 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
0310 
0311 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
0312 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
0313 };
0314 
0315 static const struct snd_kcontrol_new wm8581_snd_controls[] = {
0316 SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume",
0317              WM8581_DIGITAL_ATTENUATION_DACL4,
0318              WM8581_DIGITAL_ATTENUATION_DACR4,
0319              0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
0320 
0321 SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0),
0322 
0323 SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4,  8, 7, 1, 0),
0324 
0325 SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1),
0326 };
0327 
0328 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
0329 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
0330 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
0331 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
0332 
0333 SND_SOC_DAPM_OUTPUT("VOUT1L"),
0334 SND_SOC_DAPM_OUTPUT("VOUT1R"),
0335 SND_SOC_DAPM_OUTPUT("VOUT2L"),
0336 SND_SOC_DAPM_OUTPUT("VOUT2R"),
0337 SND_SOC_DAPM_OUTPUT("VOUT3L"),
0338 SND_SOC_DAPM_OUTPUT("VOUT3R"),
0339 
0340 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
0341 
0342 SND_SOC_DAPM_INPUT("AINL"),
0343 SND_SOC_DAPM_INPUT("AINR"),
0344 };
0345 
0346 static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = {
0347 SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1),
0348 
0349 SND_SOC_DAPM_OUTPUT("VOUT4L"),
0350 SND_SOC_DAPM_OUTPUT("VOUT4R"),
0351 };
0352 
0353 static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
0354     { "VOUT1L", NULL, "DAC1" },
0355     { "VOUT1R", NULL, "DAC1" },
0356 
0357     { "VOUT2L", NULL, "DAC2" },
0358     { "VOUT2R", NULL, "DAC2" },
0359 
0360     { "VOUT3L", NULL, "DAC3" },
0361     { "VOUT3R", NULL, "DAC3" },
0362 
0363     { "ADC", NULL, "AINL" },
0364     { "ADC", NULL, "AINR" },
0365 };
0366 
0367 static const struct snd_soc_dapm_route wm8581_dapm_routes[] = {
0368     { "VOUT4L", NULL, "DAC4" },
0369     { "VOUT4R", NULL, "DAC4" },
0370 };
0371 
0372 /* PLL divisors */
0373 struct _pll_div {
0374     u32 prescale:1;
0375     u32 postscale:1;
0376     u32 freqmode:2;
0377     u32 n:4;
0378     u32 k:24;
0379 };
0380 
0381 /* The size in bits of the pll divide */
0382 #define FIXED_PLL_SIZE (1 << 22)
0383 
0384 /* PLL rate to output rate divisions */
0385 static struct {
0386     unsigned int div;
0387     unsigned int freqmode;
0388     unsigned int postscale;
0389 } post_table[] = {
0390     {  2,  0, 0 },
0391     {  4,  0, 1 },
0392     {  4,  1, 0 },
0393     {  8,  1, 1 },
0394     {  8,  2, 0 },
0395     { 16,  2, 1 },
0396     { 12,  3, 0 },
0397     { 24,  3, 1 }
0398 };
0399 
0400 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
0401                unsigned int source)
0402 {
0403     u64 Kpart;
0404     unsigned int K, Ndiv, Nmod;
0405     int i;
0406 
0407     pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
0408 
0409     /* Scale the output frequency up; the PLL should run in the
0410      * region of 90-100MHz.
0411      */
0412     for (i = 0; i < ARRAY_SIZE(post_table); i++) {
0413         if (target * post_table[i].div >=  90000000 &&
0414             target * post_table[i].div <= 100000000) {
0415             pll_div->freqmode = post_table[i].freqmode;
0416             pll_div->postscale = post_table[i].postscale;
0417             target *= post_table[i].div;
0418             break;
0419         }
0420     }
0421 
0422     if (i == ARRAY_SIZE(post_table)) {
0423         printk(KERN_ERR "wm8580: Unable to scale output frequency "
0424                "%u\n", target);
0425         return -EINVAL;
0426     }
0427 
0428     Ndiv = target / source;
0429 
0430     if (Ndiv < 5) {
0431         source /= 2;
0432         pll_div->prescale = 1;
0433         Ndiv = target / source;
0434     } else
0435         pll_div->prescale = 0;
0436 
0437     if ((Ndiv < 5) || (Ndiv > 13)) {
0438         printk(KERN_ERR
0439             "WM8580 N=%u outside supported range\n", Ndiv);
0440         return -EINVAL;
0441     }
0442 
0443     pll_div->n = Ndiv;
0444     Nmod = target % source;
0445     Kpart = FIXED_PLL_SIZE * (long long)Nmod;
0446 
0447     do_div(Kpart, source);
0448 
0449     K = Kpart & 0xFFFFFFFF;
0450 
0451     pll_div->k = K;
0452 
0453     pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
0454          pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
0455          pll_div->postscale);
0456 
0457     return 0;
0458 }
0459 
0460 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
0461         int source, unsigned int freq_in, unsigned int freq_out)
0462 {
0463     int offset;
0464     struct snd_soc_component *component = codec_dai->component;
0465     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0466     struct pll_state *state;
0467     struct _pll_div pll_div;
0468     unsigned int reg;
0469     unsigned int pwr_mask;
0470     int ret;
0471 
0472     /* GCC isn't able to work out the ifs below for initialising/using
0473      * pll_div so suppress warnings.
0474      */
0475     memset(&pll_div, 0, sizeof(pll_div));
0476 
0477     switch (pll_id) {
0478     case WM8580_PLLA:
0479         state = &wm8580->a;
0480         offset = 0;
0481         pwr_mask = WM8580_PWRDN2_PLLAPD;
0482         break;
0483     case WM8580_PLLB:
0484         state = &wm8580->b;
0485         offset = 4;
0486         pwr_mask = WM8580_PWRDN2_PLLBPD;
0487         break;
0488     default:
0489         return -ENODEV;
0490     }
0491 
0492     if (freq_in && freq_out) {
0493         ret = pll_factors(&pll_div, freq_out, freq_in);
0494         if (ret != 0)
0495             return ret;
0496     }
0497 
0498     state->in = freq_in;
0499     state->out = freq_out;
0500 
0501     /* Always disable the PLL - it is not safe to leave it running
0502      * while reprogramming it.
0503      */
0504     snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, pwr_mask);
0505 
0506     if (!freq_in || !freq_out)
0507         return 0;
0508 
0509     snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
0510     snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
0511     snd_soc_component_write(component, WM8580_PLLA3 + offset,
0512              (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
0513 
0514     reg = snd_soc_component_read(component, WM8580_PLLA4 + offset);
0515     reg &= ~0x1b;
0516     reg |= pll_div.prescale | pll_div.postscale << 1 |
0517         pll_div.freqmode << 3;
0518 
0519     snd_soc_component_write(component, WM8580_PLLA4 + offset, reg);
0520 
0521     /* All done, turn it on */
0522     snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, 0);
0523 
0524     return 0;
0525 }
0526 
0527 static const int wm8580_sysclk_ratios[] = {
0528     128, 192, 256, 384, 512, 768, 1152,
0529 };
0530 
0531 /*
0532  * Set PCM DAI bit size and sample rate.
0533  */
0534 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
0535                  struct snd_pcm_hw_params *params,
0536                  struct snd_soc_dai *dai)
0537 {
0538     struct snd_soc_component *component = dai->component;
0539     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0540     u16 paifa = 0;
0541     u16 paifb = 0;
0542     int i, ratio, osr;
0543 
0544     /* bit size */
0545     switch (params_width(params)) {
0546     case 16:
0547         paifa |= 0x8;
0548         break;
0549     case 20:
0550         paifa |= 0x0;
0551         paifb |= WM8580_AIF_LENGTH_20;
0552         break;
0553     case 24:
0554         paifa |= 0x0;
0555         paifb |= WM8580_AIF_LENGTH_24;
0556         break;
0557     case 32:
0558         paifa |= 0x0;
0559         paifb |= WM8580_AIF_LENGTH_32;
0560         break;
0561     default:
0562         return -EINVAL;
0563     }
0564 
0565     /* Look up the SYSCLK ratio; accept only exact matches */
0566     ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
0567     for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
0568         if (ratio == wm8580_sysclk_ratios[i])
0569             break;
0570     if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
0571         dev_err(component->dev, "Invalid clock ratio %d/%d\n",
0572             wm8580->sysclk[dai->driver->id], params_rate(params));
0573         return -EINVAL;
0574     }
0575     paifa |= i;
0576     dev_dbg(component->dev, "Running at %dfs with %dHz clock\n",
0577         wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
0578 
0579     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0580         switch (ratio) {
0581         case 128:
0582         case 192:
0583             osr = WM8580_DACOSR;
0584             dev_dbg(component->dev, "Selecting 64x OSR\n");
0585             break;
0586         default:
0587             osr = 0;
0588             dev_dbg(component->dev, "Selecting 128x OSR\n");
0589             break;
0590         }
0591 
0592         snd_soc_component_update_bits(component, WM8580_PAIF3, WM8580_DACOSR, osr);
0593     }
0594 
0595     snd_soc_component_update_bits(component, WM8580_PAIF1 + dai->driver->id,
0596                 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
0597                 paifa);
0598     snd_soc_component_update_bits(component, WM8580_PAIF3 + dai->driver->id,
0599                 WM8580_AIF_LENGTH_MASK, paifb);
0600     return 0;
0601 }
0602 
0603 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
0604                       unsigned int fmt)
0605 {
0606     struct snd_soc_component *component = codec_dai->component;
0607     unsigned int aifa;
0608     unsigned int aifb;
0609     int can_invert_lrclk;
0610 
0611     aifa = snd_soc_component_read(component, WM8580_PAIF1 + codec_dai->driver->id);
0612     aifb = snd_soc_component_read(component, WM8580_PAIF3 + codec_dai->driver->id);
0613 
0614     aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
0615 
0616     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0617     case SND_SOC_DAIFMT_CBS_CFS:
0618         aifa &= ~WM8580_AIF_MS;
0619         break;
0620     case SND_SOC_DAIFMT_CBM_CFM:
0621         aifa |= WM8580_AIF_MS;
0622         break;
0623     default:
0624         return -EINVAL;
0625     }
0626 
0627     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0628     case SND_SOC_DAIFMT_I2S:
0629         can_invert_lrclk = 1;
0630         aifb |= WM8580_AIF_FMT_I2S;
0631         break;
0632     case SND_SOC_DAIFMT_RIGHT_J:
0633         can_invert_lrclk = 1;
0634         aifb |= WM8580_AIF_FMT_RIGHTJ;
0635         break;
0636     case SND_SOC_DAIFMT_LEFT_J:
0637         can_invert_lrclk = 1;
0638         aifb |= WM8580_AIF_FMT_LEFTJ;
0639         break;
0640     case SND_SOC_DAIFMT_DSP_A:
0641         can_invert_lrclk = 0;
0642         aifb |= WM8580_AIF_FMT_DSP;
0643         break;
0644     case SND_SOC_DAIFMT_DSP_B:
0645         can_invert_lrclk = 0;
0646         aifb |= WM8580_AIF_FMT_DSP;
0647         aifb |= WM8580_AIF_LRP;
0648         break;
0649     default:
0650         return -EINVAL;
0651     }
0652 
0653     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0654     case SND_SOC_DAIFMT_NB_NF:
0655         break;
0656 
0657     case SND_SOC_DAIFMT_IB_IF:
0658         if (!can_invert_lrclk)
0659             return -EINVAL;
0660         aifb |= WM8580_AIF_BCP;
0661         aifb |= WM8580_AIF_LRP;
0662         break;
0663 
0664     case SND_SOC_DAIFMT_IB_NF:
0665         aifb |= WM8580_AIF_BCP;
0666         break;
0667 
0668     case SND_SOC_DAIFMT_NB_IF:
0669         if (!can_invert_lrclk)
0670             return -EINVAL;
0671         aifb |= WM8580_AIF_LRP;
0672         break;
0673 
0674     default:
0675         return -EINVAL;
0676     }
0677 
0678     snd_soc_component_write(component, WM8580_PAIF1 + codec_dai->driver->id, aifa);
0679     snd_soc_component_write(component, WM8580_PAIF3 + codec_dai->driver->id, aifb);
0680 
0681     return 0;
0682 }
0683 
0684 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
0685                  int div_id, int div)
0686 {
0687     struct snd_soc_component *component = codec_dai->component;
0688     unsigned int reg;
0689 
0690     switch (div_id) {
0691     case WM8580_MCLK:
0692         reg = snd_soc_component_read(component, WM8580_PLLB4);
0693         reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
0694 
0695         switch (div) {
0696         case WM8580_CLKSRC_MCLK:
0697             /* Input */
0698             break;
0699 
0700         case WM8580_CLKSRC_PLLA:
0701             reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
0702             break;
0703         case WM8580_CLKSRC_PLLB:
0704             reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
0705             break;
0706 
0707         case WM8580_CLKSRC_OSC:
0708             reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
0709             break;
0710 
0711         default:
0712             return -EINVAL;
0713         }
0714         snd_soc_component_write(component, WM8580_PLLB4, reg);
0715         break;
0716 
0717     case WM8580_CLKOUTSRC:
0718         reg = snd_soc_component_read(component, WM8580_PLLB4);
0719         reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
0720 
0721         switch (div) {
0722         case WM8580_CLKSRC_NONE:
0723             break;
0724 
0725         case WM8580_CLKSRC_PLLA:
0726             reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
0727             break;
0728 
0729         case WM8580_CLKSRC_PLLB:
0730             reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
0731             break;
0732 
0733         case WM8580_CLKSRC_OSC:
0734             reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
0735             break;
0736 
0737         default:
0738             return -EINVAL;
0739         }
0740         snd_soc_component_write(component, WM8580_PLLB4, reg);
0741         break;
0742 
0743     default:
0744         return -EINVAL;
0745     }
0746 
0747     return 0;
0748 }
0749 
0750 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
0751                  unsigned int freq, int dir)
0752 {
0753     struct snd_soc_component *component = dai->component;
0754     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0755     int ret, sel, sel_mask, sel_shift;
0756 
0757     switch (dai->driver->id) {
0758     case WM8580_DAI_PAIFRX:
0759         sel_mask = 0x3;
0760         sel_shift = 0;
0761         break;
0762 
0763     case WM8580_DAI_PAIFTX:
0764         sel_mask = 0xc;
0765         sel_shift = 2;
0766         break;
0767 
0768     default:
0769         WARN(1, "Unknown DAI driver ID\n");
0770         return -EINVAL;
0771     }
0772 
0773     switch (clk_id) {
0774     case WM8580_CLKSRC_ADCMCLK:
0775         if (dai->driver->id != WM8580_DAI_PAIFTX)
0776             return -EINVAL;
0777         sel = 0 << sel_shift;
0778         break;
0779     case WM8580_CLKSRC_PLLA:
0780         sel = 1 << sel_shift;
0781         break;
0782     case WM8580_CLKSRC_PLLB:
0783         sel = 2 << sel_shift;
0784         break;
0785     case WM8580_CLKSRC_MCLK:
0786         sel = 3 << sel_shift;
0787         break;
0788     default:
0789         dev_err(component->dev, "Unknown clock %d\n", clk_id);
0790         return -EINVAL;
0791     }
0792 
0793     /* We really should validate PLL settings but not yet */
0794     wm8580->sysclk[dai->driver->id] = freq;
0795 
0796     ret = snd_soc_component_update_bits(component, WM8580_CLKSEL, sel_mask, sel);
0797     if (ret < 0)
0798         return ret;
0799 
0800     return 0;
0801 }
0802 
0803 static int wm8580_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
0804 {
0805     struct snd_soc_component *component = codec_dai->component;
0806     unsigned int reg;
0807 
0808     reg = snd_soc_component_read(component, WM8580_DAC_CONTROL5);
0809 
0810     if (mute)
0811         reg |= WM8580_DAC_CONTROL5_MUTEALL;
0812     else
0813         reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
0814 
0815     snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg);
0816 
0817     return 0;
0818 }
0819 
0820 static int wm8580_set_bias_level(struct snd_soc_component *component,
0821     enum snd_soc_bias_level level)
0822 {
0823     switch (level) {
0824     case SND_SOC_BIAS_ON:
0825     case SND_SOC_BIAS_PREPARE:
0826         break;
0827 
0828     case SND_SOC_BIAS_STANDBY:
0829         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0830             /* Power up and get individual control of the DACs */
0831             snd_soc_component_update_bits(component, WM8580_PWRDN1,
0832                         WM8580_PWRDN1_PWDN |
0833                         WM8580_PWRDN1_ALLDACPD, 0);
0834 
0835             /* Make VMID high impedance */
0836             snd_soc_component_update_bits(component, WM8580_ADC_CONTROL1,
0837                         0x100, 0);
0838         }
0839         break;
0840 
0841     case SND_SOC_BIAS_OFF:
0842         snd_soc_component_update_bits(component, WM8580_PWRDN1,
0843                     WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
0844         break;
0845     }
0846     return 0;
0847 }
0848 
0849 static int wm8580_playback_startup(struct snd_pcm_substream *substream,
0850                struct snd_soc_dai *dai)
0851 {
0852     struct snd_soc_component *component = dai->component;
0853     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0854 
0855     return snd_pcm_hw_constraint_minmax(substream->runtime,
0856         SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2);
0857 }
0858 
0859 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
0860             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
0861 
0862 static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
0863     .startup    = wm8580_playback_startup,
0864     .set_sysclk = wm8580_set_sysclk,
0865     .hw_params  = wm8580_paif_hw_params,
0866     .set_fmt    = wm8580_set_paif_dai_fmt,
0867     .set_clkdiv = wm8580_set_dai_clkdiv,
0868     .set_pll    = wm8580_set_dai_pll,
0869     .mute_stream    = wm8580_mute,
0870     .no_capture_mute = 1,
0871 };
0872 
0873 static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
0874     .set_sysclk = wm8580_set_sysclk,
0875     .hw_params  = wm8580_paif_hw_params,
0876     .set_fmt    = wm8580_set_paif_dai_fmt,
0877     .set_clkdiv = wm8580_set_dai_clkdiv,
0878     .set_pll    = wm8580_set_dai_pll,
0879 };
0880 
0881 static struct snd_soc_dai_driver wm8580_dai[] = {
0882     {
0883         .name = "wm8580-hifi-playback",
0884         .id = WM8580_DAI_PAIFRX,
0885         .playback = {
0886             .stream_name = "Playback",
0887             .channels_min = 1,
0888             .rates = SNDRV_PCM_RATE_8000_192000,
0889             .formats = WM8580_FORMATS,
0890         },
0891         .ops = &wm8580_dai_ops_playback,
0892     },
0893     {
0894         .name = "wm8580-hifi-capture",
0895         .id =   WM8580_DAI_PAIFTX,
0896         .capture = {
0897             .stream_name = "Capture",
0898             .channels_min = 2,
0899             .channels_max = 2,
0900             .rates = SNDRV_PCM_RATE_8000_192000,
0901             .formats = WM8580_FORMATS,
0902         },
0903         .ops = &wm8580_dai_ops_capture,
0904     },
0905 };
0906 
0907 static int wm8580_probe(struct snd_soc_component *component)
0908 {
0909     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0910     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
0911     int ret = 0;
0912 
0913     switch (wm8580->drvdata->num_dacs) {
0914     case 4:
0915         snd_soc_add_component_controls(component, wm8581_snd_controls,
0916                     ARRAY_SIZE(wm8581_snd_controls));
0917         snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets,
0918                     ARRAY_SIZE(wm8581_dapm_widgets));
0919         snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes,
0920                     ARRAY_SIZE(wm8581_dapm_routes));
0921         break;
0922     default:
0923         break;
0924     }
0925 
0926     ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
0927                     wm8580->supplies);
0928     if (ret != 0) {
0929         dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
0930         goto err_regulator_get;
0931     }
0932 
0933     /* Get the codec into a known state */
0934     ret = snd_soc_component_write(component, WM8580_RESET, 0);
0935     if (ret != 0) {
0936         dev_err(component->dev, "Failed to reset component: %d\n", ret);
0937         goto err_regulator_enable;
0938     }
0939 
0940     return 0;
0941 
0942 err_regulator_enable:
0943     regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
0944 err_regulator_get:
0945     return ret;
0946 }
0947 
0948 /* power down chip */
0949 static void wm8580_remove(struct snd_soc_component *component)
0950 {
0951     struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component);
0952 
0953     regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
0954 }
0955 
0956 static const struct snd_soc_component_driver soc_component_dev_wm8580 = {
0957     .probe          = wm8580_probe,
0958     .remove         = wm8580_remove,
0959     .set_bias_level     = wm8580_set_bias_level,
0960     .controls       = wm8580_snd_controls,
0961     .num_controls       = ARRAY_SIZE(wm8580_snd_controls),
0962     .dapm_widgets       = wm8580_dapm_widgets,
0963     .num_dapm_widgets   = ARRAY_SIZE(wm8580_dapm_widgets),
0964     .dapm_routes        = wm8580_dapm_routes,
0965     .num_dapm_routes    = ARRAY_SIZE(wm8580_dapm_routes),
0966     .idle_bias_on       = 1,
0967     .use_pmdown_time    = 1,
0968     .endianness     = 1,
0969 };
0970 
0971 static const struct regmap_config wm8580_regmap = {
0972     .reg_bits = 7,
0973     .val_bits = 9,
0974     .max_register = WM8580_MAX_REGISTER,
0975 
0976     .reg_defaults = wm8580_reg_defaults,
0977     .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults),
0978     .cache_type = REGCACHE_RBTREE,
0979 
0980     .volatile_reg = wm8580_volatile,
0981 };
0982 
0983 static const struct wm8580_driver_data wm8580_data = {
0984     .num_dacs = 3,
0985 };
0986 
0987 static const struct wm8580_driver_data wm8581_data = {
0988     .num_dacs = 4,
0989 };
0990 
0991 static const struct of_device_id wm8580_of_match[] = {
0992     { .compatible = "wlf,wm8580", .data = &wm8580_data },
0993     { .compatible = "wlf,wm8581", .data = &wm8581_data },
0994     { },
0995 };
0996 MODULE_DEVICE_TABLE(of, wm8580_of_match);
0997 
0998 static int wm8580_i2c_probe(struct i2c_client *i2c)
0999 {
1000     const struct of_device_id *of_id;
1001     struct wm8580_priv *wm8580;
1002     int ret, i;
1003 
1004     wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv),
1005                   GFP_KERNEL);
1006     if (wm8580 == NULL)
1007         return -ENOMEM;
1008 
1009     wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap);
1010     if (IS_ERR(wm8580->regmap))
1011         return PTR_ERR(wm8580->regmap);
1012 
1013     for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
1014         wm8580->supplies[i].supply = wm8580_supply_names[i];
1015 
1016     ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies),
1017                       wm8580->supplies);
1018     if (ret != 0) {
1019         dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1020         return ret;
1021     }
1022 
1023     i2c_set_clientdata(i2c, wm8580);
1024 
1025     of_id = of_match_device(wm8580_of_match, &i2c->dev);
1026     if (of_id)
1027         wm8580->drvdata = of_id->data;
1028 
1029     if (!wm8580->drvdata) {
1030         dev_err(&i2c->dev, "failed to find driver data\n");
1031         return -EINVAL;
1032     }
1033 
1034     ret = devm_snd_soc_register_component(&i2c->dev,
1035             &soc_component_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
1036 
1037     return ret;
1038 }
1039 
1040 static const struct i2c_device_id wm8580_i2c_id[] = {
1041     { "wm8580", (kernel_ulong_t)&wm8580_data },
1042     { "wm8581", (kernel_ulong_t)&wm8581_data },
1043     { }
1044 };
1045 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
1046 
1047 static struct i2c_driver wm8580_i2c_driver = {
1048     .driver = {
1049         .name = "wm8580",
1050         .of_match_table = wm8580_of_match,
1051     },
1052     .probe_new = wm8580_i2c_probe,
1053     .id_table = wm8580_i2c_id,
1054 };
1055 
1056 module_i2c_driver(wm8580_i2c_driver);
1057 
1058 MODULE_DESCRIPTION("ASoC WM8580 driver");
1059 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1060 MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
1061 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!