soc/codecs/wm8400.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * wm8400.h  --  audio driver for WM8400
0004  *
0005  * Copyright 2008 Wolfson Microelectronics PLC.
0006  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0007  */
0008
0009 #ifndef _WM8400_CODEC_H
0010 #define _WM8400_CODEC_H
0011
0012 #define WM8400_MCLK_DIV 0
0013 #define WM8400_DACCLK_DIV 1
0014 #define WM8400_ADCCLK_DIV 2
0015 #define WM8400_BCLK_DIV 3
0016
0017 #define WM8400_MCLK_DIV_1 0x400
0018 #define WM8400_MCLK_DIV_2 0x800
0019
0020 #define WM8400_DAC_CLKDIV_1    0x00
0021 #define WM8400_DAC_CLKDIV_1_5  0x04
0022 #define WM8400_DAC_CLKDIV_2    0x08
0023 #define WM8400_DAC_CLKDIV_3    0x0c
0024 #define WM8400_DAC_CLKDIV_4    0x10
0025 #define WM8400_DAC_CLKDIV_5_5  0x14
0026 #define WM8400_DAC_CLKDIV_6    0x18
0027
0028 #define WM8400_ADC_CLKDIV_1    0x00
0029 #define WM8400_ADC_CLKDIV_1_5  0x20
0030 #define WM8400_ADC_CLKDIV_2    0x40
0031 #define WM8400_ADC_CLKDIV_3    0x60
0032 #define WM8400_ADC_CLKDIV_4    0x80
0033 #define WM8400_ADC_CLKDIV_5_5  0xa0
0034 #define WM8400_ADC_CLKDIV_6    0xc0
0035
0036
0037 #define WM8400_BCLK_DIV_1                       (0x0 << 1)
0038 #define WM8400_BCLK_DIV_1_5                     (0x1 << 1)
0039 #define WM8400_BCLK_DIV_2                       (0x2 << 1)
0040 #define WM8400_BCLK_DIV_3                       (0x3 << 1)
0041 #define WM8400_BCLK_DIV_4                       (0x4 << 1)
0042 #define WM8400_BCLK_DIV_5_5                     (0x5 << 1)
0043 #define WM8400_BCLK_DIV_6                       (0x6 << 1)
0044 #define WM8400_BCLK_DIV_8                       (0x7 << 1)
0045 #define WM8400_BCLK_DIV_11                      (0x8 << 1)
0046 #define WM8400_BCLK_DIV_12                      (0x9 << 1)
0047 #define WM8400_BCLK_DIV_16                      (0xA << 1)
0048 #define WM8400_BCLK_DIV_22                      (0xB << 1)
0049 #define WM8400_BCLK_DIV_24                      (0xC << 1)
0050 #define WM8400_BCLK_DIV_32                      (0xD << 1)
0051 #define WM8400_BCLK_DIV_44                      (0xE << 1)
0052 #define WM8400_BCLK_DIV_48                      (0xF << 1)
0053
0054 #endif