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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm8350.c -- WM8350 ALSA SoC audio driver
0004  *
0005  * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
0006  *
0007  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/slab.h>
0014 #include <linux/delay.h>
0015 #include <linux/pm.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/mfd/wm8350/audio.h>
0018 #include <linux/mfd/wm8350/core.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/initval.h>
0025 #include <sound/tlv.h>
0026 #include <trace/events/asoc.h>
0027 
0028 #include "wm8350.h"
0029 
0030 #define WM8350_OUTn_0dB 0x39
0031 
0032 #define WM8350_RAMP_NONE    0
0033 #define WM8350_RAMP_UP      1
0034 #define WM8350_RAMP_DOWN    2
0035 
0036 /* We only include the analogue supplies here; the digital supplies
0037  * need to be available well before this driver can be probed.
0038  */
0039 static const char *supply_names[] = {
0040     "AVDD",
0041     "HPVDD",
0042 };
0043 
0044 struct wm8350_output {
0045     u16 active;
0046     u16 left_vol;
0047     u16 right_vol;
0048     u16 ramp;
0049     u16 mute;
0050 };
0051 
0052 struct wm8350_jack_data {
0053     struct snd_soc_jack *jack;
0054     struct delayed_work work;
0055     int report;
0056     int short_report;
0057 };
0058 
0059 struct wm8350_data {
0060     struct wm8350 *wm8350;
0061     struct wm8350_output out1;
0062     struct wm8350_output out2;
0063     struct wm8350_jack_data hpl;
0064     struct wm8350_jack_data hpr;
0065     struct wm8350_jack_data mic;
0066     struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
0067     int fll_freq_out;
0068     int fll_freq_in;
0069     struct delayed_work pga_work;
0070 };
0071 
0072 /*
0073  * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
0074  */
0075 static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
0076 {
0077     struct wm8350_output *out1 = &wm8350_data->out1;
0078     struct wm8350 *wm8350 = wm8350_data->wm8350;
0079     int left_complete = 0, right_complete = 0;
0080     u16 reg, val;
0081 
0082     /* left channel */
0083     reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
0084     val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
0085 
0086     if (out1->ramp == WM8350_RAMP_UP) {
0087         /* ramp step up */
0088         if (val < out1->left_vol) {
0089             val++;
0090             reg &= ~WM8350_OUT1L_VOL_MASK;
0091             wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
0092                      reg | (val << WM8350_OUT1L_VOL_SHIFT));
0093         } else
0094             left_complete = 1;
0095     } else if (out1->ramp == WM8350_RAMP_DOWN) {
0096         /* ramp step down */
0097         if (val > 0) {
0098             val--;
0099             reg &= ~WM8350_OUT1L_VOL_MASK;
0100             wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
0101                      reg | (val << WM8350_OUT1L_VOL_SHIFT));
0102         } else
0103             left_complete = 1;
0104     } else
0105         return 1;
0106 
0107     /* right channel */
0108     reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
0109     val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
0110     if (out1->ramp == WM8350_RAMP_UP) {
0111         /* ramp step up */
0112         if (val < out1->right_vol) {
0113             val++;
0114             reg &= ~WM8350_OUT1R_VOL_MASK;
0115             wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
0116                      reg | (val << WM8350_OUT1R_VOL_SHIFT));
0117         } else
0118             right_complete = 1;
0119     } else if (out1->ramp == WM8350_RAMP_DOWN) {
0120         /* ramp step down */
0121         if (val > 0) {
0122             val--;
0123             reg &= ~WM8350_OUT1R_VOL_MASK;
0124             wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
0125                      reg | (val << WM8350_OUT1R_VOL_SHIFT));
0126         } else
0127             right_complete = 1;
0128     }
0129 
0130     /* only hit the update bit if either volume has changed this step */
0131     if (!left_complete || !right_complete)
0132         wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
0133 
0134     return left_complete & right_complete;
0135 }
0136 
0137 /*
0138  * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
0139  */
0140 static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
0141 {
0142     struct wm8350_output *out2 = &wm8350_data->out2;
0143     struct wm8350 *wm8350 = wm8350_data->wm8350;
0144     int left_complete = 0, right_complete = 0;
0145     u16 reg, val;
0146 
0147     /* left channel */
0148     reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
0149     val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
0150     if (out2->ramp == WM8350_RAMP_UP) {
0151         /* ramp step up */
0152         if (val < out2->left_vol) {
0153             val++;
0154             reg &= ~WM8350_OUT2L_VOL_MASK;
0155             wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
0156                      reg | (val << WM8350_OUT1L_VOL_SHIFT));
0157         } else
0158             left_complete = 1;
0159     } else if (out2->ramp == WM8350_RAMP_DOWN) {
0160         /* ramp step down */
0161         if (val > 0) {
0162             val--;
0163             reg &= ~WM8350_OUT2L_VOL_MASK;
0164             wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
0165                      reg | (val << WM8350_OUT1L_VOL_SHIFT));
0166         } else
0167             left_complete = 1;
0168     } else
0169         return 1;
0170 
0171     /* right channel */
0172     reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
0173     val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
0174     if (out2->ramp == WM8350_RAMP_UP) {
0175         /* ramp step up */
0176         if (val < out2->right_vol) {
0177             val++;
0178             reg &= ~WM8350_OUT2R_VOL_MASK;
0179             wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
0180                      reg | (val << WM8350_OUT1R_VOL_SHIFT));
0181         } else
0182             right_complete = 1;
0183     } else if (out2->ramp == WM8350_RAMP_DOWN) {
0184         /* ramp step down */
0185         if (val > 0) {
0186             val--;
0187             reg &= ~WM8350_OUT2R_VOL_MASK;
0188             wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
0189                      reg | (val << WM8350_OUT1R_VOL_SHIFT));
0190         } else
0191             right_complete = 1;
0192     }
0193 
0194     /* only hit the update bit if either volume has changed this step */
0195     if (!left_complete || !right_complete)
0196         wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
0197 
0198     return left_complete & right_complete;
0199 }
0200 
0201 /*
0202  * This work ramps both output PGAs at stream start/stop time to
0203  * minimise pop associated with DAPM power switching.
0204  * It's best to enable Zero Cross when ramping occurs to minimise any
0205  * zipper noises.
0206  */
0207 static void wm8350_pga_work(struct work_struct *work)
0208 {
0209     struct wm8350_data *wm8350_data =
0210         container_of(work, struct wm8350_data, pga_work.work);
0211     struct wm8350_output *out1 = &wm8350_data->out1,
0212         *out2 = &wm8350_data->out2;
0213     int i, out1_complete, out2_complete;
0214 
0215     /* do we need to ramp at all ? */
0216     if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
0217         return;
0218 
0219     /* PGA volumes have 6 bits of resolution to ramp */
0220     for (i = 0; i <= 63; i++) {
0221         out1_complete = 1;
0222         out2_complete = 1;
0223         if (out1->ramp != WM8350_RAMP_NONE)
0224             out1_complete = wm8350_out1_ramp_step(wm8350_data);
0225         if (out2->ramp != WM8350_RAMP_NONE)
0226             out2_complete = wm8350_out2_ramp_step(wm8350_data);
0227 
0228         /* ramp finished ? */
0229         if (out1_complete && out2_complete)
0230             break;
0231 
0232         /* we need to delay longer on the up ramp */
0233         if (out1->ramp == WM8350_RAMP_UP ||
0234             out2->ramp == WM8350_RAMP_UP) {
0235             /* delay is longer over 0dB as increases are larger */
0236             if (i >= WM8350_OUTn_0dB)
0237                 schedule_timeout_interruptible(msecs_to_jiffies
0238                                    (2));
0239             else
0240                 schedule_timeout_interruptible(msecs_to_jiffies
0241                                    (1));
0242         } else
0243             udelay(50); /* doesn't matter if we delay longer */
0244     }
0245 
0246     out1->ramp = WM8350_RAMP_NONE;
0247     out2->ramp = WM8350_RAMP_NONE;
0248 }
0249 
0250 /*
0251  * WM8350 Controls
0252  */
0253 
0254 static int pga_event(struct snd_soc_dapm_widget *w,
0255              struct snd_kcontrol *kcontrol, int event)
0256 {
0257     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0258     struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
0259     struct wm8350_output *out;
0260 
0261     switch (w->shift) {
0262     case 0:
0263     case 1:
0264         out = &wm8350_data->out1;
0265         break;
0266     case 2:
0267     case 3:
0268         out = &wm8350_data->out2;
0269         break;
0270 
0271     default:
0272         WARN(1, "Invalid shift %d\n", w->shift);
0273         return -1;
0274     }
0275 
0276     switch (event) {
0277     case SND_SOC_DAPM_POST_PMU:
0278         out->ramp = WM8350_RAMP_UP;
0279         out->active = 1;
0280 
0281         schedule_delayed_work(&wm8350_data->pga_work,
0282                       msecs_to_jiffies(1));
0283         break;
0284 
0285     case SND_SOC_DAPM_PRE_PMD:
0286         out->ramp = WM8350_RAMP_DOWN;
0287         out->active = 0;
0288 
0289         schedule_delayed_work(&wm8350_data->pga_work,
0290                       msecs_to_jiffies(1));
0291         break;
0292     }
0293 
0294     return 0;
0295 }
0296 
0297 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
0298                   struct snd_ctl_elem_value *ucontrol)
0299 {
0300     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0301     struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
0302     struct wm8350_output *out = NULL;
0303     struct soc_mixer_control *mc =
0304         (struct soc_mixer_control *)kcontrol->private_value;
0305     int ret;
0306     unsigned int reg = mc->reg;
0307     u16 val;
0308 
0309     /* For OUT1 and OUT2 we shadow the values and only actually write
0310      * them out when active in order to ensure the amplifier comes on
0311      * as quietly as possible. */
0312     switch (reg) {
0313     case WM8350_LOUT1_VOLUME:
0314         out = &wm8350_priv->out1;
0315         break;
0316     case WM8350_LOUT2_VOLUME:
0317         out = &wm8350_priv->out2;
0318         break;
0319     default:
0320         break;
0321     }
0322 
0323     if (out) {
0324         out->left_vol = ucontrol->value.integer.value[0];
0325         out->right_vol = ucontrol->value.integer.value[1];
0326         if (!out->active)
0327             return 1;
0328     }
0329 
0330     ret = snd_soc_put_volsw(kcontrol, ucontrol);
0331     if (ret < 0)
0332         return ret;
0333 
0334     /* now hit the volume update bits (always bit 8) */
0335     val = snd_soc_component_read(component, reg);
0336     snd_soc_component_write(component, reg, val | WM8350_OUT1_VU);
0337     return 1;
0338 }
0339 
0340 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
0341                    struct snd_ctl_elem_value *ucontrol)
0342 {
0343     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0344     struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);
0345     struct wm8350_output *out1 = &wm8350_priv->out1;
0346     struct wm8350_output *out2 = &wm8350_priv->out2;
0347     struct soc_mixer_control *mc =
0348         (struct soc_mixer_control *)kcontrol->private_value;
0349     unsigned int reg = mc->reg;
0350 
0351     /* If these are cached registers use the cache */
0352     switch (reg) {
0353     case WM8350_LOUT1_VOLUME:
0354         ucontrol->value.integer.value[0] = out1->left_vol;
0355         ucontrol->value.integer.value[1] = out1->right_vol;
0356         return 0;
0357 
0358     case WM8350_LOUT2_VOLUME:
0359         ucontrol->value.integer.value[0] = out2->left_vol;
0360         ucontrol->value.integer.value[1] = out2->right_vol;
0361         return 0;
0362 
0363     default:
0364         break;
0365     }
0366 
0367     return snd_soc_get_volsw(kcontrol, ucontrol);
0368 }
0369 
0370 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
0371 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
0372 static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
0373 static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
0374 static const char *wm8350_adcfilter[] = { "None", "High Pass" };
0375 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
0376 static const char *wm8350_lr[] = { "Left", "Right" };
0377 
0378 static const struct soc_enum wm8350_enum[] = {
0379     SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
0380     SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
0381     SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
0382     SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
0383     SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
0384     SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
0385     SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
0386     SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
0387 };
0388 
0389 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
0390 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
0391 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
0392 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
0393 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
0394 
0395 static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,
0396     0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
0397     13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)
0398 );
0399 
0400 static const struct snd_kcontrol_new wm8350_snd_controls[] = {
0401     SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
0402     SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
0403     SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
0404                 WM8350_DAC_DIGITAL_VOLUME_L,
0405                 WM8350_DAC_DIGITAL_VOLUME_R,
0406                 0, 255, 0, wm8350_get_volsw_2r,
0407                 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
0408     SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
0409     SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
0410     SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
0411     SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
0412     SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
0413     SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
0414                 WM8350_ADC_DIGITAL_VOLUME_L,
0415                 WM8350_ADC_DIGITAL_VOLUME_R,
0416                 0, 255, 0, wm8350_get_volsw_2r,
0417                 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
0418     SOC_DOUBLE_TLV("Capture Sidetone Volume",
0419                WM8350_ADC_DIVIDER,
0420                8, 4, 15, 1, capture_sd_tlv),
0421     SOC_DOUBLE_R_EXT_TLV("Capture Volume",
0422                 WM8350_LEFT_INPUT_VOLUME,
0423                 WM8350_RIGHT_INPUT_VOLUME,
0424                 2, 63, 0, wm8350_get_volsw_2r,
0425                 wm8350_put_volsw_2r_vu, pre_amp_tlv),
0426     SOC_DOUBLE_R("Capture ZC Switch",
0427              WM8350_LEFT_INPUT_VOLUME,
0428              WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
0429     SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
0430                WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
0431     SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
0432                WM8350_OUTPUT_LEFT_MIXER_VOLUME,
0433                5, 7, 0, out_mix_tlv),
0434     SOC_SINGLE_TLV("Left Input Bypass Volume",
0435                WM8350_OUTPUT_LEFT_MIXER_VOLUME,
0436                9, 7, 0, out_mix_tlv),
0437     SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
0438                WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
0439                1, 7, 0, out_mix_tlv),
0440     SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
0441                WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
0442                5, 7, 0, out_mix_tlv),
0443     SOC_SINGLE_TLV("Right Input Bypass Volume",
0444                WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
0445                13, 7, 0, out_mix_tlv),
0446     SOC_SINGLE("Left Input Mixer +20dB Switch",
0447            WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
0448     SOC_SINGLE("Right Input Mixer +20dB Switch",
0449            WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
0450     SOC_SINGLE_TLV("Out4 Capture Volume",
0451                WM8350_INPUT_MIXER_VOLUME,
0452                1, 7, 0, out_mix_tlv),
0453     SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
0454                 WM8350_LOUT1_VOLUME,
0455                 WM8350_ROUT1_VOLUME,
0456                 2, 63, 0, wm8350_get_volsw_2r,
0457                 wm8350_put_volsw_2r_vu, out_pga_tlv),
0458     SOC_DOUBLE_R("Out1 Playback ZC Switch",
0459              WM8350_LOUT1_VOLUME,
0460              WM8350_ROUT1_VOLUME, 13, 1, 0),
0461     SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
0462                 WM8350_LOUT2_VOLUME,
0463                 WM8350_ROUT2_VOLUME,
0464                 2, 63, 0, wm8350_get_volsw_2r,
0465                 wm8350_put_volsw_2r_vu, out_pga_tlv),
0466     SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
0467              WM8350_ROUT2_VOLUME, 13, 1, 0),
0468     SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
0469     SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
0470                5, 7, 0, out_mix_tlv),
0471 
0472     SOC_DOUBLE_R("Out1 Playback Switch",
0473              WM8350_LOUT1_VOLUME,
0474              WM8350_ROUT1_VOLUME,
0475              14, 1, 1),
0476     SOC_DOUBLE_R("Out2 Playback Switch",
0477              WM8350_LOUT2_VOLUME,
0478              WM8350_ROUT2_VOLUME,
0479              14, 1, 1),
0480 };
0481 
0482 /*
0483  * DAPM Controls
0484  */
0485 
0486 /* Left Playback Mixer */
0487 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
0488     SOC_DAPM_SINGLE("Playback Switch",
0489             WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
0490     SOC_DAPM_SINGLE("Left Bypass Switch",
0491             WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
0492     SOC_DAPM_SINGLE("Right Playback Switch",
0493             WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
0494     SOC_DAPM_SINGLE("Left Sidetone Switch",
0495             WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
0496     SOC_DAPM_SINGLE("Right Sidetone Switch",
0497             WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
0498 };
0499 
0500 /* Right Playback Mixer */
0501 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
0502     SOC_DAPM_SINGLE("Playback Switch",
0503             WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
0504     SOC_DAPM_SINGLE("Right Bypass Switch",
0505             WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
0506     SOC_DAPM_SINGLE("Left Playback Switch",
0507             WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
0508     SOC_DAPM_SINGLE("Left Sidetone Switch",
0509             WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
0510     SOC_DAPM_SINGLE("Right Sidetone Switch",
0511             WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
0512 };
0513 
0514 /* Out4 Mixer */
0515 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
0516     SOC_DAPM_SINGLE("Right Playback Switch",
0517             WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
0518     SOC_DAPM_SINGLE("Left Playback Switch",
0519             WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
0520     SOC_DAPM_SINGLE("Right Capture Switch",
0521             WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
0522     SOC_DAPM_SINGLE("Out3 Playback Switch",
0523             WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
0524     SOC_DAPM_SINGLE("Right Mixer Switch",
0525             WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
0526     SOC_DAPM_SINGLE("Left Mixer Switch",
0527             WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
0528 };
0529 
0530 /* Out3 Mixer */
0531 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
0532     SOC_DAPM_SINGLE("Left Playback Switch",
0533             WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
0534     SOC_DAPM_SINGLE("Left Capture Switch",
0535             WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
0536     SOC_DAPM_SINGLE("Out4 Playback Switch",
0537             WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
0538     SOC_DAPM_SINGLE("Left Mixer Switch",
0539             WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
0540 };
0541 
0542 /* Left Input Mixer */
0543 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
0544     SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
0545                 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
0546     SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
0547                 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
0548     SOC_DAPM_SINGLE("PGA Capture Switch",
0549             WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
0550 };
0551 
0552 /* Right Input Mixer */
0553 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
0554     SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
0555                 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
0556     SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
0557                 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
0558     SOC_DAPM_SINGLE("PGA Capture Switch",
0559             WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
0560 };
0561 
0562 /* Left Mic Mixer */
0563 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
0564     SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
0565     SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
0566     SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
0567 };
0568 
0569 /* Right Mic Mixer */
0570 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
0571     SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
0572     SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
0573     SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
0574 };
0575 
0576 /* Beep Switch */
0577 static const struct snd_kcontrol_new wm8350_beep_switch_controls =
0578 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
0579 
0580 /* Out4 Capture Mux */
0581 static const struct snd_kcontrol_new wm8350_out4_capture_controls =
0582 SOC_DAPM_ENUM("Route", wm8350_enum[7]);
0583 
0584 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
0585 
0586     SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
0587     SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
0588     SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
0589                0, pga_event,
0590                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0591     SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
0592                pga_event,
0593                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0594     SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
0595                0, pga_event,
0596                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0597     SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
0598                pga_event,
0599                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0600 
0601     SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
0602                7, 0, &wm8350_right_capt_mixer_controls[0],
0603                ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
0604 
0605     SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
0606                6, 0, &wm8350_left_capt_mixer_controls[0],
0607                ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
0608 
0609     SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
0610                &wm8350_out4_mixer_controls[0],
0611                ARRAY_SIZE(wm8350_out4_mixer_controls)),
0612 
0613     SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
0614                &wm8350_out3_mixer_controls[0],
0615                ARRAY_SIZE(wm8350_out3_mixer_controls)),
0616 
0617     SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
0618                &wm8350_right_play_mixer_controls[0],
0619                ARRAY_SIZE(wm8350_right_play_mixer_controls)),
0620 
0621     SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
0622                &wm8350_left_play_mixer_controls[0],
0623                ARRAY_SIZE(wm8350_left_play_mixer_controls)),
0624 
0625     SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
0626                &wm8350_left_mic_mixer_controls[0],
0627                ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
0628 
0629     SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
0630                &wm8350_right_mic_mixer_controls[0],
0631                ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
0632 
0633     /* virtual mixer for Beep and Out2R */
0634     SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
0635 
0636     SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
0637                 &wm8350_beep_switch_controls),
0638 
0639     SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
0640              WM8350_POWER_MGMT_4, 3, 0),
0641     SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
0642              WM8350_POWER_MGMT_4, 2, 0),
0643     SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
0644              WM8350_POWER_MGMT_4, 5, 0),
0645     SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
0646              WM8350_POWER_MGMT_4, 4, 0),
0647 
0648     SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
0649 
0650     SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
0651              &wm8350_out4_capture_controls),
0652 
0653     SND_SOC_DAPM_OUTPUT("OUT1R"),
0654     SND_SOC_DAPM_OUTPUT("OUT1L"),
0655     SND_SOC_DAPM_OUTPUT("OUT2R"),
0656     SND_SOC_DAPM_OUTPUT("OUT2L"),
0657     SND_SOC_DAPM_OUTPUT("OUT3"),
0658     SND_SOC_DAPM_OUTPUT("OUT4"),
0659 
0660     SND_SOC_DAPM_INPUT("IN1RN"),
0661     SND_SOC_DAPM_INPUT("IN1RP"),
0662     SND_SOC_DAPM_INPUT("IN2R"),
0663     SND_SOC_DAPM_INPUT("IN1LP"),
0664     SND_SOC_DAPM_INPUT("IN1LN"),
0665     SND_SOC_DAPM_INPUT("IN2L"),
0666     SND_SOC_DAPM_INPUT("IN3R"),
0667     SND_SOC_DAPM_INPUT("IN3L"),
0668 };
0669 
0670 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
0671 
0672     /* left playback mixer */
0673     {"Left Playback Mixer", "Playback Switch", "Left DAC"},
0674     {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
0675     {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
0676     {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
0677     {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
0678 
0679     /* right playback mixer */
0680     {"Right Playback Mixer", "Playback Switch", "Right DAC"},
0681     {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
0682     {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
0683     {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
0684     {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
0685 
0686     /* out4 playback mixer */
0687     {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
0688     {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
0689     {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
0690     {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
0691     {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
0692     {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
0693     {"OUT4", NULL, "Out4 Mixer"},
0694 
0695     /* out3 playback mixer */
0696     {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
0697     {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
0698     {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
0699     {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
0700     {"OUT3", NULL, "Out3 Mixer"},
0701 
0702     /* out2 */
0703     {"Right Out2 PGA", NULL, "Right Playback Mixer"},
0704     {"Left Out2 PGA", NULL, "Left Playback Mixer"},
0705     {"OUT2L", NULL, "Left Out2 PGA"},
0706     {"OUT2R", NULL, "Right Out2 PGA"},
0707 
0708     /* out1 */
0709     {"Right Out1 PGA", NULL, "Right Playback Mixer"},
0710     {"Left Out1 PGA", NULL, "Left Playback Mixer"},
0711     {"OUT1L", NULL, "Left Out1 PGA"},
0712     {"OUT1R", NULL, "Right Out1 PGA"},
0713 
0714     /* ADCs */
0715     {"Left ADC", NULL, "Left Capture Mixer"},
0716     {"Right ADC", NULL, "Right Capture Mixer"},
0717 
0718     /* Left capture mixer */
0719     {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
0720     {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
0721     {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
0722     {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
0723 
0724     /* Right capture mixer */
0725     {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
0726     {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
0727     {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
0728     {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
0729 
0730     /* L3 Inputs */
0731     {"IN3L PGA", NULL, "IN3L"},
0732     {"IN3R PGA", NULL, "IN3R"},
0733 
0734     /* Left Mic mixer */
0735     {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
0736     {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
0737     {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
0738 
0739     /* Right Mic mixer */
0740     {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
0741     {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
0742     {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
0743 
0744     /* out 4 capture */
0745     {"Out4 Capture Channel", NULL, "Out4 Mixer"},
0746 
0747     /* Beep */
0748     {"Beep", NULL, "IN3R PGA"},
0749 };
0750 
0751 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
0752                  int clk_id, unsigned int freq, int dir)
0753 {
0754     struct snd_soc_component *component = codec_dai->component;
0755     struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
0756     struct wm8350 *wm8350 = wm8350_data->wm8350;
0757     u16 fll_4;
0758 
0759     switch (clk_id) {
0760     case WM8350_MCLK_SEL_MCLK:
0761         wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
0762                   WM8350_MCLK_SEL);
0763         break;
0764     case WM8350_MCLK_SEL_PLL_MCLK:
0765     case WM8350_MCLK_SEL_PLL_DAC:
0766     case WM8350_MCLK_SEL_PLL_ADC:
0767     case WM8350_MCLK_SEL_PLL_32K:
0768         wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
0769                 WM8350_MCLK_SEL);
0770         fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
0771             ~WM8350_FLL_CLK_SRC_MASK;
0772         snd_soc_component_write(component, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
0773         break;
0774     }
0775 
0776     /* MCLK direction */
0777     if (dir == SND_SOC_CLOCK_OUT)
0778         wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
0779                 WM8350_MCLK_DIR);
0780     else
0781         wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
0782                   WM8350_MCLK_DIR);
0783 
0784     return 0;
0785 }
0786 
0787 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
0788 {
0789     struct snd_soc_component *component = codec_dai->component;
0790     u16 val;
0791 
0792     switch (div_id) {
0793     case WM8350_ADC_CLKDIV:
0794         val = snd_soc_component_read(component, WM8350_ADC_DIVIDER) &
0795             ~WM8350_ADC_CLKDIV_MASK;
0796         snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div);
0797         break;
0798     case WM8350_DAC_CLKDIV:
0799         val = snd_soc_component_read(component, WM8350_DAC_CLOCK_CONTROL) &
0800             ~WM8350_DAC_CLKDIV_MASK;
0801         snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div);
0802         break;
0803     case WM8350_BCLK_CLKDIV:
0804         val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
0805             ~WM8350_BCLK_DIV_MASK;
0806         snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
0807         break;
0808     case WM8350_OPCLK_CLKDIV:
0809         val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
0810             ~WM8350_OPCLK_DIV_MASK;
0811         snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
0812         break;
0813     case WM8350_SYS_CLKDIV:
0814         val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &
0815             ~WM8350_MCLK_DIV_MASK;
0816         snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);
0817         break;
0818     case WM8350_DACLR_CLKDIV:
0819         val = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
0820             ~WM8350_DACLRC_RATE_MASK;
0821         snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div);
0822         break;
0823     case WM8350_ADCLR_CLKDIV:
0824         val = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
0825             ~WM8350_ADCLRC_RATE_MASK;
0826         snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div);
0827         break;
0828     default:
0829         return -EINVAL;
0830     }
0831 
0832     return 0;
0833 }
0834 
0835 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
0836 {
0837     struct snd_soc_component *component = codec_dai->component;
0838     u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
0839         ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
0840     u16 master = snd_soc_component_read(component, WM8350_AI_DAC_CONTROL) &
0841         ~WM8350_BCLK_MSTR;
0842     u16 dac_lrc = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &
0843         ~WM8350_DACLRC_ENA;
0844     u16 adc_lrc = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &
0845         ~WM8350_ADCLRC_ENA;
0846 
0847     /* set master/slave audio interface */
0848     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
0849     case SND_SOC_DAIFMT_CBM_CFM:
0850         master |= WM8350_BCLK_MSTR;
0851         dac_lrc |= WM8350_DACLRC_ENA;
0852         adc_lrc |= WM8350_ADCLRC_ENA;
0853         break;
0854     case SND_SOC_DAIFMT_CBS_CFS:
0855         break;
0856     default:
0857         return -EINVAL;
0858     }
0859 
0860     /* interface format */
0861     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0862     case SND_SOC_DAIFMT_I2S:
0863         iface |= 0x2 << 8;
0864         break;
0865     case SND_SOC_DAIFMT_RIGHT_J:
0866         break;
0867     case SND_SOC_DAIFMT_LEFT_J:
0868         iface |= 0x1 << 8;
0869         break;
0870     case SND_SOC_DAIFMT_DSP_A:
0871         iface |= 0x3 << 8;
0872         break;
0873     case SND_SOC_DAIFMT_DSP_B:
0874         iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
0875         break;
0876     default:
0877         return -EINVAL;
0878     }
0879 
0880     /* clock inversion */
0881     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
0882     case SND_SOC_DAIFMT_NB_NF:
0883         break;
0884     case SND_SOC_DAIFMT_IB_IF:
0885         iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
0886         break;
0887     case SND_SOC_DAIFMT_IB_NF:
0888         iface |= WM8350_AIF_BCLK_INV;
0889         break;
0890     case SND_SOC_DAIFMT_NB_IF:
0891         iface |= WM8350_AIF_LRCLK_INV;
0892         break;
0893     default:
0894         return -EINVAL;
0895     }
0896 
0897     snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
0898     snd_soc_component_write(component, WM8350_AI_DAC_CONTROL, master);
0899     snd_soc_component_write(component, WM8350_DAC_LR_RATE, dac_lrc);
0900     snd_soc_component_write(component, WM8350_ADC_LR_RATE, adc_lrc);
0901     return 0;
0902 }
0903 
0904 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
0905                 struct snd_pcm_hw_params *params,
0906                 struct snd_soc_dai *codec_dai)
0907 {
0908     struct snd_soc_component *component = codec_dai->component;
0909     struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);
0910     struct wm8350 *wm8350 = wm8350_data->wm8350;
0911     u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &
0912         ~WM8350_AIF_WL_MASK;
0913 
0914     /* bit size */
0915     switch (params_width(params)) {
0916     case 16:
0917         break;
0918     case 20:
0919         iface |= 0x1 << 10;
0920         break;
0921     case 24:
0922         iface |= 0x2 << 10;
0923         break;
0924     case 32:
0925         iface |= 0x3 << 10;
0926         break;
0927     }
0928 
0929     snd_soc_component_write(component, WM8350_AI_FORMATING, iface);
0930 
0931     /* The sloping stopband filter is recommended for use with
0932      * lower sample rates to improve performance.
0933      */
0934     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0935         if (params_rate(params) < 24000)
0936             wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
0937                     WM8350_DAC_SB_FILT);
0938         else
0939             wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
0940                       WM8350_DAC_SB_FILT);
0941     }
0942 
0943     return 0;
0944 }
0945 
0946 static int wm8350_mute(struct snd_soc_dai *dai, int mute, int direction)
0947 {
0948     struct snd_soc_component *component = dai->component;
0949     unsigned int val;
0950 
0951     if (mute)
0952         val = WM8350_DAC_MUTE_ENA;
0953     else
0954         val = 0;
0955 
0956     snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
0957 
0958     return 0;
0959 }
0960 
0961 /* FLL divisors */
0962 struct _fll_div {
0963     int div;        /* FLL_OUTDIV */
0964     int n;
0965     int k;
0966     int ratio;      /* FLL_FRATIO */
0967 };
0968 
0969 /* The size in bits of the fll divide multiplied by 10
0970  * to allow rounding later */
0971 #define FIXED_FLL_SIZE ((1 << 16) * 10)
0972 
0973 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
0974                   unsigned int output)
0975 {
0976     u64 Kpart;
0977     unsigned int t1, t2, K, Nmod;
0978 
0979     if (output >= 2815250 && output <= 3125000)
0980         fll_div->div = 0x4;
0981     else if (output >= 5625000 && output <= 6250000)
0982         fll_div->div = 0x3;
0983     else if (output >= 11250000 && output <= 12500000)
0984         fll_div->div = 0x2;
0985     else if (output >= 22500000 && output <= 25000000)
0986         fll_div->div = 0x1;
0987     else {
0988         printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
0989         return -EINVAL;
0990     }
0991 
0992     if (input > 48000)
0993         fll_div->ratio = 1;
0994     else
0995         fll_div->ratio = 8;
0996 
0997     t1 = output * (1 << (fll_div->div + 1));
0998     t2 = input * fll_div->ratio;
0999 
1000     fll_div->n = t1 / t2;
1001     Nmod = t1 % t2;
1002 
1003     if (Nmod) {
1004         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1005         do_div(Kpart, t2);
1006         K = Kpart & 0xFFFFFFFF;
1007 
1008         /* Check if we need to round */
1009         if ((K % 10) >= 5)
1010             K += 5;
1011 
1012         /* Move down to proper range now rounding is done */
1013         K /= 10;
1014         fll_div->k = K;
1015     } else
1016         fll_div->k = 0;
1017 
1018     return 0;
1019 }
1020 
1021 static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1022               int pll_id, int source, unsigned int freq_in,
1023               unsigned int freq_out)
1024 {
1025     struct snd_soc_component *component = codec_dai->component;
1026     struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1027     struct wm8350 *wm8350 = priv->wm8350;
1028     struct _fll_div fll_div;
1029     int ret = 0;
1030     u16 fll_1, fll_4;
1031 
1032     if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1033         return 0;
1034 
1035     /* power down FLL - we need to do this for reconfiguration */
1036     wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1037               WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1038 
1039     if (freq_out == 0 || freq_in == 0)
1040         return ret;
1041 
1042     ret = fll_factors(&fll_div, freq_in, freq_out);
1043     if (ret < 0)
1044         return ret;
1045     dev_dbg(wm8350->dev,
1046         "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1047         freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1048         fll_div.ratio);
1049 
1050     /* set up N.K & dividers */
1051     fll_1 = snd_soc_component_read(component, WM8350_FLL_CONTROL_1) &
1052         ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1053     snd_soc_component_write(component, WM8350_FLL_CONTROL_1,
1054                fll_1 | (fll_div.div << 8) | 0x50);
1055     snd_soc_component_write(component, WM8350_FLL_CONTROL_2,
1056                (fll_div.ratio << 11) | (fll_div.
1057                             n & WM8350_FLL_N_MASK));
1058     snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);
1059     fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &
1060         ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1061     snd_soc_component_write(component, WM8350_FLL_CONTROL_4,
1062                fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1063                (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1064 
1065     /* power FLL on */
1066     wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1067     wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1068 
1069     priv->fll_freq_out = freq_out;
1070     priv->fll_freq_in = freq_in;
1071 
1072     return 0;
1073 }
1074 
1075 static int wm8350_set_bias_level(struct snd_soc_component *component,
1076                  enum snd_soc_bias_level level)
1077 {
1078     struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1079     struct wm8350 *wm8350 = priv->wm8350;
1080     struct wm8350_audio_platform_data *platform =
1081         wm8350->codec.platform_data;
1082     u16 pm1;
1083     int ret;
1084 
1085     switch (level) {
1086     case SND_SOC_BIAS_ON:
1087         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1088             ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1089         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1090                  pm1 | WM8350_VMID_50K |
1091                  platform->codec_current_on << 14);
1092         break;
1093 
1094     case SND_SOC_BIAS_PREPARE:
1095         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1096         pm1 &= ~WM8350_VMID_MASK;
1097         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1098                  pm1 | WM8350_VMID_50K);
1099         break;
1100 
1101     case SND_SOC_BIAS_STANDBY:
1102         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1103             ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1104                             priv->supplies);
1105             if (ret != 0)
1106                 return ret;
1107 
1108             /* Enable the system clock */
1109             wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1110                     WM8350_SYSCLK_ENA);
1111 
1112             /* mute DAC & outputs */
1113             wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1114                     WM8350_DAC_MUTE_ENA);
1115 
1116             /* discharge cap memory */
1117             wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1118                      platform->dis_out1 |
1119                      (platform->dis_out2 << 2) |
1120                      (platform->dis_out3 << 4) |
1121                      (platform->dis_out4 << 6));
1122 
1123             /* wait for discharge */
1124             schedule_timeout_interruptible(msecs_to_jiffies
1125                                (platform->
1126                             cap_discharge_msecs));
1127 
1128             /* enable antipop */
1129             wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1130                      (platform->vmid_s_curve << 8));
1131 
1132             /* ramp up vmid */
1133             wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1134                      (platform->
1135                       codec_current_charge << 14) |
1136                      WM8350_VMID_5K | WM8350_VMIDEN |
1137                      WM8350_VBUFEN);
1138 
1139             /* wait for vmid */
1140             schedule_timeout_interruptible(msecs_to_jiffies
1141                                (platform->
1142                             vmid_charge_msecs));
1143 
1144             /* turn on vmid 300k  */
1145             pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1146                 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1147             pm1 |= WM8350_VMID_300K |
1148                 (platform->codec_current_standby << 14);
1149             wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1150                      pm1);
1151 
1152 
1153             /* enable analogue bias */
1154             pm1 |= WM8350_BIASEN;
1155             wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1156 
1157             /* disable antipop */
1158             wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1159 
1160         } else {
1161             /* turn on vmid 300k and reduce current */
1162             pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1163                 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1164             wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1165                      pm1 | WM8350_VMID_300K |
1166                      (platform->
1167                       codec_current_standby << 14));
1168 
1169         }
1170         break;
1171 
1172     case SND_SOC_BIAS_OFF:
1173 
1174         /* mute DAC & enable outputs */
1175         wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1176 
1177         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1178                 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1179                 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1180 
1181         /* enable anti pop S curve */
1182         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1183                  (platform->vmid_s_curve << 8));
1184 
1185         /* turn off vmid  */
1186         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1187             ~WM8350_VMIDEN;
1188         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1189 
1190         /* wait */
1191         schedule_timeout_interruptible(msecs_to_jiffies
1192                            (platform->
1193                         vmid_discharge_msecs));
1194 
1195         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1196                  (platform->vmid_s_curve << 8) |
1197                  platform->dis_out1 |
1198                  (platform->dis_out2 << 2) |
1199                  (platform->dis_out3 << 4) |
1200                  (platform->dis_out4 << 6));
1201 
1202         /* turn off VBuf and drain */
1203         pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1204             ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1205         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1206                  pm1 | WM8350_OUTPUT_DRAIN_EN);
1207 
1208         /* wait */
1209         schedule_timeout_interruptible(msecs_to_jiffies
1210                            (platform->drain_msecs));
1211 
1212         pm1 &= ~WM8350_BIASEN;
1213         wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1214 
1215         /* disable anti-pop */
1216         wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1217 
1218         wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1219                   WM8350_OUT1L_ENA);
1220         wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1221                   WM8350_OUT1R_ENA);
1222         wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1223                   WM8350_OUT2L_ENA);
1224         wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1225                   WM8350_OUT2R_ENA);
1226 
1227         /* disable clock gen */
1228         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1229                   WM8350_SYSCLK_ENA);
1230 
1231         regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1232                        priv->supplies);
1233         break;
1234     }
1235     return 0;
1236 }
1237 
1238 static void wm8350_hp_work(struct wm8350_data *priv,
1239                struct wm8350_jack_data *jack,
1240                u16 mask)
1241 {
1242     struct wm8350 *wm8350 = priv->wm8350;
1243     u16 reg;
1244     int report;
1245 
1246     reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1247     if (reg & mask)
1248         report = jack->report;
1249     else
1250         report = 0;
1251 
1252     snd_soc_jack_report(jack->jack, report, jack->report);
1253 
1254 }
1255 
1256 static void wm8350_hpl_work(struct work_struct *work)
1257 {
1258     struct wm8350_data *priv =
1259         container_of(work, struct wm8350_data, hpl.work.work);
1260 
1261     wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1262 }
1263 
1264 static void wm8350_hpr_work(struct work_struct *work)
1265 {
1266     struct wm8350_data *priv =
1267         container_of(work, struct wm8350_data, hpr.work.work);
1268     
1269     wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1270 }
1271 
1272 static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
1273 {
1274     struct wm8350_data *priv = data;
1275     struct wm8350 *wm8350 = priv->wm8350;
1276 
1277 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1278     trace_snd_soc_jack_irq("WM8350 HPL");
1279 #endif
1280 
1281     if (device_may_wakeup(wm8350->dev))
1282         pm_wakeup_event(wm8350->dev, 250);
1283 
1284     queue_delayed_work(system_power_efficient_wq,
1285                &priv->hpl.work, msecs_to_jiffies(200));
1286 
1287     return IRQ_HANDLED;
1288 }
1289 
1290 static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1291 {
1292     struct wm8350_data *priv = data;
1293     struct wm8350 *wm8350 = priv->wm8350;
1294 
1295 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1296     trace_snd_soc_jack_irq("WM8350 HPR");
1297 #endif
1298 
1299     if (device_may_wakeup(wm8350->dev))
1300         pm_wakeup_event(wm8350->dev, 250);
1301 
1302     queue_delayed_work(system_power_efficient_wq,
1303                &priv->hpr.work, msecs_to_jiffies(200));
1304 
1305     return IRQ_HANDLED;
1306 }
1307 
1308 /**
1309  * wm8350_hp_jack_detect - Enable headphone jack detection.
1310  *
1311  * @component:  WM8350 component
1312  * @which:  left or right jack detect signal
1313  * @jack:   jack to report detection events on
1314  * @report: value to report
1315  *
1316  * Enables the headphone jack detection of the WM8350.  If no report
1317  * is specified then detection is disabled.
1318  */
1319 int wm8350_hp_jack_detect(struct snd_soc_component *component, enum wm8350_jack which,
1320               struct snd_soc_jack *jack, int report)
1321 {
1322     struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1323     struct wm8350 *wm8350 = priv->wm8350;
1324     int ena;
1325 
1326     switch (which) {
1327     case WM8350_JDL:
1328         priv->hpl.jack = jack;
1329         priv->hpl.report = report;
1330         ena = WM8350_JDL_ENA;
1331         break;
1332 
1333     case WM8350_JDR:
1334         priv->hpr.jack = jack;
1335         priv->hpr.report = report;
1336         ena = WM8350_JDR_ENA;
1337         break;
1338 
1339     default:
1340         return -EINVAL;
1341     }
1342 
1343     if (report) {
1344         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1345         wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1346     } else {
1347         wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1348     }
1349 
1350     /* Sync status */
1351     switch (which) {
1352     case WM8350_JDL:
1353         wm8350_hpl_jack_handler(0, priv);
1354         break;
1355     case WM8350_JDR:
1356         wm8350_hpr_jack_handler(0, priv);
1357         break;
1358     }
1359 
1360     return 0;
1361 }
1362 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1363 
1364 static irqreturn_t wm8350_mic_handler(int irq, void *data)
1365 {
1366     struct wm8350_data *priv = data;
1367     struct wm8350 *wm8350 = priv->wm8350;
1368     u16 reg;
1369     int report = 0;
1370 
1371 #ifndef CONFIG_SND_SOC_WM8350_MODULE
1372     trace_snd_soc_jack_irq("WM8350 mic");
1373 #endif
1374 
1375     reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1376     if (reg & WM8350_JACK_MICSCD_LVL)
1377         report |= priv->mic.short_report;
1378     if (reg & WM8350_JACK_MICSD_LVL)
1379         report |= priv->mic.report;
1380 
1381     snd_soc_jack_report(priv->mic.jack, report,
1382                 priv->mic.report | priv->mic.short_report);
1383 
1384     return IRQ_HANDLED;
1385 }
1386 
1387 /**
1388  * wm8350_mic_jack_detect - Enable microphone jack detection.
1389  *
1390  * @component:         WM8350 component
1391  * @jack:          jack to report detection events on
1392  * @detect_report: value to report when presence detected
1393  * @short_report:  value to report when microphone short detected
1394  *
1395  * Enables the microphone jack detection of the WM8350.  If both reports
1396  * are specified as zero then detection is disabled.
1397  */
1398 int wm8350_mic_jack_detect(struct snd_soc_component *component,
1399                struct snd_soc_jack *jack,
1400                int detect_report, int short_report)
1401 {
1402     struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1403     struct wm8350 *wm8350 = priv->wm8350;
1404 
1405     priv->mic.jack = jack;
1406     priv->mic.report = detect_report;
1407     priv->mic.short_report = short_report;
1408 
1409     if (detect_report || short_report) {
1410         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1411         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1412                 WM8350_MIC_DET_ENA);
1413     } else {
1414         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1415                   WM8350_MIC_DET_ENA);
1416     }
1417 
1418     return 0;
1419 }
1420 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1421 
1422 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1423 
1424 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1425             SNDRV_PCM_FMTBIT_S20_3LE |\
1426             SNDRV_PCM_FMTBIT_S24_LE)
1427 
1428 static const struct snd_soc_dai_ops wm8350_dai_ops = {
1429      .hw_params = wm8350_pcm_hw_params,
1430      .mute_stream   = wm8350_mute,
1431      .set_fmt   = wm8350_set_dai_fmt,
1432      .set_sysclk    = wm8350_set_dai_sysclk,
1433      .set_pll   = wm8350_set_fll,
1434      .set_clkdiv    = wm8350_set_clkdiv,
1435      .no_capture_mute = 1,
1436 };
1437 
1438 static struct snd_soc_dai_driver wm8350_dai = {
1439     .name = "wm8350-hifi",
1440     .playback = {
1441         .stream_name = "Playback",
1442         .channels_min = 1,
1443         .channels_max = 2,
1444         .rates = WM8350_RATES,
1445         .formats = WM8350_FORMATS,
1446     },
1447     .capture = {
1448          .stream_name = "Capture",
1449          .channels_min = 1,
1450          .channels_max = 2,
1451          .rates = WM8350_RATES,
1452          .formats = WM8350_FORMATS,
1453      },
1454     .ops = &wm8350_dai_ops,
1455 };
1456 
1457 static  int wm8350_component_probe(struct snd_soc_component *component)
1458 {
1459     struct wm8350 *wm8350 = dev_get_platdata(component->dev);
1460     struct wm8350_data *priv;
1461     struct wm8350_output *out1;
1462     struct wm8350_output *out2;
1463     int ret, i;
1464 
1465     if (wm8350->codec.platform_data == NULL) {
1466         dev_err(component->dev, "No audio platform data supplied\n");
1467         return -EINVAL;
1468     }
1469 
1470     priv = devm_kzalloc(component->dev, sizeof(struct wm8350_data),
1471                 GFP_KERNEL);
1472     if (priv == NULL)
1473         return -ENOMEM;
1474 
1475     snd_soc_component_init_regmap(component, wm8350->regmap);
1476     snd_soc_component_set_drvdata(component, priv);
1477 
1478     priv->wm8350 = wm8350;
1479 
1480     for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1481         priv->supplies[i].supply = supply_names[i];
1482 
1483     ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1484                  priv->supplies);
1485     if (ret != 0)
1486         return ret;
1487 
1488     /* Put the codec into reset if it wasn't already */
1489     wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1490 
1491     INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
1492     INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1493     INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1494 
1495     /* Enable the codec */
1496     wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1497 
1498     /* Enable robust clocking mode in ADC */
1499     snd_soc_component_write(component, WM8350_SECURITY, 0xa7);
1500     snd_soc_component_write(component, 0xde, 0x13);
1501     snd_soc_component_write(component, WM8350_SECURITY, 0);
1502 
1503     /* read OUT1 & OUT2 volumes */
1504     out1 = &priv->out1;
1505     out2 = &priv->out2;
1506     out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1507               WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1508     out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1509                WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1510     out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1511               WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1512     out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1513                WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1514     wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1515     wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1516     wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1517     wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1518 
1519     /* Latch VU bits & mute */
1520     wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1521             WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1522     wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1523             WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1524     wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1525             WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1526     wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1527             WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1528 
1529     /* Make sure AIF tristating is disabled by default */
1530     wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1531 
1532     /* Make sure we've got a sane companding setup too */
1533     wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1534               WM8350_DAC_COMP | WM8350_LOOPBACK);
1535 
1536     /* Make sure jack detect is disabled to start off with */
1537     wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1538               WM8350_JDL_ENA | WM8350_JDR_ENA);
1539 
1540     ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1541                 wm8350_hpl_jack_handler, 0, "Left jack detect",
1542                 priv);
1543     if (ret != 0)
1544         goto err;
1545 
1546     ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1547                 wm8350_hpr_jack_handler, 0, "Right jack detect",
1548                 priv);
1549     if (ret != 0)
1550         goto free_jck_det_l;
1551 
1552     ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1553                 wm8350_mic_handler, 0, "Microphone short", priv);
1554     if (ret != 0)
1555         goto free_jck_det_r;
1556 
1557     ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1558                 wm8350_mic_handler, 0, "Microphone detect", priv);
1559     if (ret != 0)
1560         goto free_micscd;
1561 
1562     return 0;
1563 
1564 free_micscd:
1565     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1566 free_jck_det_r:
1567     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1568 free_jck_det_l:
1569     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1570 err:
1571     return ret;
1572 }
1573 
1574 static void wm8350_component_remove(struct snd_soc_component *component)
1575 {
1576     struct wm8350_data *priv = snd_soc_component_get_drvdata(component);
1577     struct wm8350 *wm8350 = dev_get_platdata(component->dev);
1578 
1579     wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1580               WM8350_JDL_ENA | WM8350_JDR_ENA);
1581     wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1582 
1583     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1584     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1585     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1586     wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1587 
1588     priv->hpl.jack = NULL;
1589     priv->hpr.jack = NULL;
1590     priv->mic.jack = NULL;
1591 
1592     cancel_delayed_work_sync(&priv->hpl.work);
1593     cancel_delayed_work_sync(&priv->hpr.work);
1594 
1595     /* if there was any work waiting then we run it now and
1596      * wait for its completion */
1597     flush_delayed_work(&priv->pga_work);
1598 
1599     wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1600 }
1601 
1602 static const struct snd_soc_component_driver soc_component_dev_wm8350 = {
1603     .probe          = wm8350_component_probe,
1604     .remove         = wm8350_component_remove,
1605     .set_bias_level     = wm8350_set_bias_level,
1606     .controls       = wm8350_snd_controls,
1607     .num_controls       = ARRAY_SIZE(wm8350_snd_controls),
1608     .dapm_widgets       = wm8350_dapm_widgets,
1609     .num_dapm_widgets   = ARRAY_SIZE(wm8350_dapm_widgets),
1610     .dapm_routes        = wm8350_dapm_routes,
1611     .num_dapm_routes    = ARRAY_SIZE(wm8350_dapm_routes),
1612     .suspend_bias_off   = 1,
1613     .idle_bias_on       = 1,
1614     .use_pmdown_time    = 1,
1615     .endianness     = 1,
1616 };
1617 
1618 static int wm8350_probe(struct platform_device *pdev)
1619 {
1620     return devm_snd_soc_register_component(&pdev->dev,
1621             &soc_component_dev_wm8350,
1622             &wm8350_dai, 1);
1623 }
1624 
1625 static struct platform_driver wm8350_codec_driver = {
1626     .driver = {
1627            .name = "wm8350-codec",
1628            },
1629     .probe = wm8350_probe,
1630 };
1631 
1632 module_platform_driver(wm8350_codec_driver);
1633 
1634 MODULE_DESCRIPTION("ASoC WM8350 driver");
1635 MODULE_AUTHOR("Liam Girdwood");
1636 MODULE_LICENSE("GPL");
1637 MODULE_ALIAS("platform:wm8350-codec");
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