soc/codecs/wm5100.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm5100.c  --  WM5100 ALSA SoC Audio driver
0004  *
0005  * Copyright 2011-2 Wolfson Microelectronics plc
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/export.h>
0015 #include <linux/pm.h>
0016 #include <linux/gcd.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/gpio.h>
0019 #include <linux/i2c.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/regulator/consumer.h>
0022 #include <linux/regulator/fixed.h>
0023 #include <linux/slab.h>
0024 #include <sound/core.h>
0025 #include <sound/pcm.h>
0026 #include <sound/pcm_params.h>
0027 #include <sound/soc.h>
0028 #include <sound/jack.h>
0029 #include <sound/initval.h>
0030 #include <sound/tlv.h>
0031 #include <sound/wm5100.h>
0032
0033 #include "wm5100.h"
0034
0035 #define WM5100_NUM_CORE_SUPPLIES 2
0036 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
0037     "DBVDD1",
0038     "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
0039 };
0040
0041 #define WM5100_AIFS     3
0042 #define WM5100_SYNC_SRS 3
0043
0044 struct wm5100_fll {
0045     int fref;
0046     int fout;
0047     int src;
0048     struct completion lock;
0049 };
0050
0051 /* codec private data */
0052 struct wm5100_priv {
0053     struct device *dev;
0054     struct regmap *regmap;
0055     struct snd_soc_component *component;
0056
0057     struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
0058
0059     int rev;
0060
0061     int sysclk;
0062     int asyncclk;
0063
0064     bool aif_async[WM5100_AIFS];
0065     bool aif_symmetric[WM5100_AIFS];
0066     int sr_ref[WM5100_SYNC_SRS];
0067
0068     bool out_ena[2];
0069
0070     struct snd_soc_jack *jack;
0071     bool jack_detecting;
0072     bool jack_mic;
0073     int jack_mode;
0074     int jack_flips;
0075
0076     struct wm5100_fll fll[2];
0077
0078     struct wm5100_pdata pdata;
0079
0080 #ifdef CONFIG_GPIOLIB
0081     struct gpio_chip gpio_chip;
0082 #endif
0083 };
0084
0085 static int wm5100_sr_code[] = {
0086     0,
0087     12000,
0088     24000,
0089     48000,
0090     96000,
0091     192000,
0092     384000,
0093     768000,
0094     0,
0095     11025,
0096     22050,
0097     44100,
0098     88200,
0099     176400,
0100     352800,
0101     705600,
0102     4000,
0103     8000,
0104     16000,
0105     32000,
0106     64000,
0107     128000,
0108     256000,
0109     512000,
0110 };
0111
0112 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
0113     WM5100_CLOCKING_4,
0114     WM5100_CLOCKING_5,
0115     WM5100_CLOCKING_6,
0116 };
0117
0118 static int wm5100_alloc_sr(struct snd_soc_component *component, int rate)
0119 {
0120     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
0121     int sr_code, sr_free, i;
0122
0123     for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
0124         if (wm5100_sr_code[i] == rate)
0125             break;
0126     if (i == ARRAY_SIZE(wm5100_sr_code)) {
0127         dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate);
0128         return -EINVAL;
0129     }
0130     sr_code = i;
0131
0132     if ((wm5100->sysclk % rate) == 0) {
0133         /* Is this rate already in use? */
0134         sr_free = -1;
0135         for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
0136             if (!wm5100->sr_ref[i] && sr_free == -1) {
0137                 sr_free = i;
0138                 continue;
0139             }
0140             if ((snd_soc_component_read(component, wm5100_sr_regs[i]) &
0141                  WM5100_SAMPLE_RATE_1_MASK) == sr_code)
0142                 break;
0143         }
0144
0145         if (i < ARRAY_SIZE(wm5100_sr_regs)) {
0146             wm5100->sr_ref[i]++;
0147             dev_dbg(component->dev, "SR %dHz, slot %d, ref %d\n",
0148                 rate, i, wm5100->sr_ref[i]);
0149             return i;
0150         }
0151
0152         if (sr_free == -1) {
0153             dev_err(component->dev, "All SR slots already in use\n");
0154             return -EBUSY;
0155         }
0156
0157         dev_dbg(component->dev, "Allocating SR slot %d for %dHz\n",
0158             sr_free, rate);
0159         wm5100->sr_ref[sr_free]++;
0160         snd_soc_component_update_bits(component, wm5100_sr_regs[sr_free],
0161                     WM5100_SAMPLE_RATE_1_MASK,
0162                     sr_code);
0163
0164         return sr_free;
0165
0166     } else {
0167         dev_err(component->dev,
0168             "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
0169             rate, wm5100->sysclk, wm5100->asyncclk);
0170         return -EINVAL;
0171     }
0172 }
0173
0174 static void wm5100_free_sr(struct snd_soc_component *component, int rate)
0175 {
0176     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
0177     int i, sr_code;
0178
0179     for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
0180         if (wm5100_sr_code[i] == rate)
0181             break;
0182     if (i == ARRAY_SIZE(wm5100_sr_code)) {
0183         dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate);
0184         return;
0185     }
0186     sr_code = wm5100_sr_code[i];
0187
0188     for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
0189         if (!wm5100->sr_ref[i])
0190             continue;
0191
0192         if ((snd_soc_component_read(component, wm5100_sr_regs[i]) &
0193              WM5100_SAMPLE_RATE_1_MASK) == sr_code)
0194             break;
0195     }
0196     if (i < ARRAY_SIZE(wm5100_sr_regs)) {
0197         wm5100->sr_ref[i]--;
0198         dev_dbg(component->dev, "Dereference SR %dHz, count now %d\n",
0199             rate, wm5100->sr_ref[i]);
0200     } else {
0201         dev_warn(component->dev, "Freeing unreferenced sample rate %dHz\n",
0202              rate);
0203     }
0204 }
0205
0206 static int wm5100_reset(struct wm5100_priv *wm5100)
0207 {
0208     if (wm5100->pdata.reset) {
0209         gpio_set_value_cansleep(wm5100->pdata.reset, 0);
0210         gpio_set_value_cansleep(wm5100->pdata.reset, 1);
0211
0212         return 0;
0213     } else {
0214         return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
0215     }
0216 }
0217
0218 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
0219 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
0220 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
0221 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
0222 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
0223
0224 static const char *wm5100_mixer_texts[] = {
0225     "None",
0226     "Tone Generator 1",
0227     "Tone Generator 2",
0228     "AEC loopback",
0229     "IN1L",
0230     "IN1R",
0231     "IN2L",
0232     "IN2R",
0233     "IN3L",
0234     "IN3R",
0235     "IN4L",
0236     "IN4R",
0237     "AIF1RX1",
0238     "AIF1RX2",
0239     "AIF1RX3",
0240     "AIF1RX4",
0241     "AIF1RX5",
0242     "AIF1RX6",
0243     "AIF1RX7",
0244     "AIF1RX8",
0245     "AIF2RX1",
0246     "AIF2RX2",
0247     "AIF3RX1",
0248     "AIF3RX2",
0249     "EQ1",
0250     "EQ2",
0251     "EQ3",
0252     "EQ4",
0253     "DRC1L",
0254     "DRC1R",
0255     "LHPF1",
0256     "LHPF2",
0257     "LHPF3",
0258     "LHPF4",
0259     "DSP1.1",
0260     "DSP1.2",
0261     "DSP1.3",
0262     "DSP1.4",
0263     "DSP1.5",
0264     "DSP1.6",
0265     "DSP2.1",
0266     "DSP2.2",
0267     "DSP2.3",
0268     "DSP2.4",
0269     "DSP2.5",
0270     "DSP2.6",
0271     "DSP3.1",
0272     "DSP3.2",
0273     "DSP3.3",
0274     "DSP3.4",
0275     "DSP3.5",
0276     "DSP3.6",
0277     "ASRC1L",
0278     "ASRC1R",
0279     "ASRC2L",
0280     "ASRC2R",
0281     "ISRC1INT1",
0282     "ISRC1INT2",
0283     "ISRC1INT3",
0284     "ISRC1INT4",
0285     "ISRC2INT1",
0286     "ISRC2INT2",
0287     "ISRC2INT3",
0288     "ISRC2INT4",
0289     "ISRC1DEC1",
0290     "ISRC1DEC2",
0291     "ISRC1DEC3",
0292     "ISRC1DEC4",
0293     "ISRC2DEC1",
0294     "ISRC2DEC2",
0295     "ISRC2DEC3",
0296     "ISRC2DEC4",
0297 };
0298
0299 static int wm5100_mixer_values[] = {
0300     0x00,
0301     0x04,   /* Tone */
0302     0x05,
0303     0x08,   /* AEC */
0304     0x10,   /* Input */
0305     0x11,
0306     0x12,
0307     0x13,
0308     0x14,
0309     0x15,
0310     0x16,
0311     0x17,
0312     0x20,   /* AIF */
0313     0x21,
0314     0x22,
0315     0x23,
0316     0x24,
0317     0x25,
0318     0x26,
0319     0x27,
0320     0x28,
0321     0x29,
0322     0x30,   /* AIF3 - check */
0323     0x31,
0324     0x50,   /* EQ */
0325     0x51,
0326     0x52,
0327     0x53,
0328     0x54,
0329     0x58,   /* DRC */
0330     0x59,
0331     0x60,   /* LHPF1 */
0332     0x61,   /* LHPF2 */
0333     0x62,   /* LHPF3 */
0334     0x63,   /* LHPF4 */
0335     0x68,   /* DSP1 */
0336     0x69,
0337     0x6a,
0338     0x6b,
0339     0x6c,
0340     0x6d,
0341     0x70,   /* DSP2 */
0342     0x71,
0343     0x72,
0344     0x73,
0345     0x74,
0346     0x75,
0347     0x78,   /* DSP3 */
0348     0x79,
0349     0x7a,
0350     0x7b,
0351     0x7c,
0352     0x7d,
0353     0x90,   /* ASRC1 */
0354     0x91,
0355     0x92,   /* ASRC2 */
0356     0x93,
0357     0xa0,   /* ISRC1DEC1 */
0358     0xa1,
0359     0xa2,
0360     0xa3,
0361     0xa4,   /* ISRC1INT1 */
0362     0xa5,
0363     0xa6,
0364     0xa7,
0365     0xa8,   /* ISRC2DEC1 */
0366     0xa9,
0367     0xaa,
0368     0xab,
0369     0xac,   /* ISRC2INT1 */
0370     0xad,
0371     0xae,
0372     0xaf,
0373 };
0374
0375 #define WM5100_MIXER_CONTROLS(name, base) \
0376     SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
0377                WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
0378     SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
0379                WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
0380     SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
0381                WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
0382     SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
0383                WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
0384
0385 #define WM5100_MUX_ENUM_DECL(name, reg) \
0386     SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff,          \
0387                    wm5100_mixer_texts, wm5100_mixer_values)
0388
0389 #define WM5100_MUX_CTL_DECL(name) \
0390     const struct snd_kcontrol_new name##_mux =  \
0391         SOC_DAPM_ENUM("Route", name##_enum)
0392
0393 #define WM5100_MIXER_ENUMS(name, base_reg) \
0394     static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg);      \
0395     static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2);  \
0396     static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4);  \
0397     static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6);  \
0398     static WM5100_MUX_CTL_DECL(name##_in1); \
0399     static WM5100_MUX_CTL_DECL(name##_in2); \
0400     static WM5100_MUX_CTL_DECL(name##_in3); \
0401     static WM5100_MUX_CTL_DECL(name##_in4)
0402
0403 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
0404 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
0405 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
0406 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
0407 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
0408 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
0409
0410 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
0411 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
0412 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
0413 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
0414 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
0415 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
0416
0417 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
0418 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
0419
0420 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
0421 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
0422 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
0423 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
0424 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
0425 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
0426 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
0427 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
0428
0429 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
0430 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
0431
0432 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
0433 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
0434
0435 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
0436 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
0437 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
0438 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
0439
0440 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
0441 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
0442
0443 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
0444 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
0445 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
0446 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
0447
0448 #define WM5100_MUX(name, ctrl) \
0449     SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
0450
0451 #define WM5100_MIXER_WIDGETS(name, name_str)    \
0452     WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
0453     WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
0454     WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
0455     WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
0456     SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
0457
0458 #define WM5100_MIXER_INPUT_ROUTES(name) \
0459     { name, "Tone Generator 1", "Tone Generator 1" }, \
0460         { name, "Tone Generator 2", "Tone Generator 2" }, \
0461         { name, "IN1L", "IN1L PGA" }, \
0462         { name, "IN1R", "IN1R PGA" }, \
0463         { name, "IN2L", "IN2L PGA" }, \
0464         { name, "IN2R", "IN2R PGA" }, \
0465         { name, "IN3L", "IN3L PGA" }, \
0466         { name, "IN3R", "IN3R PGA" }, \
0467         { name, "IN4L", "IN4L PGA" }, \
0468         { name, "IN4R", "IN4R PGA" }, \
0469         { name, "AIF1RX1", "AIF1RX1" }, \
0470         { name, "AIF1RX2", "AIF1RX2" }, \
0471         { name, "AIF1RX3", "AIF1RX3" }, \
0472         { name, "AIF1RX4", "AIF1RX4" }, \
0473         { name, "AIF1RX5", "AIF1RX5" }, \
0474         { name, "AIF1RX6", "AIF1RX6" }, \
0475         { name, "AIF1RX7", "AIF1RX7" }, \
0476         { name, "AIF1RX8", "AIF1RX8" }, \
0477         { name, "AIF2RX1", "AIF2RX1" }, \
0478         { name, "AIF2RX2", "AIF2RX2" }, \
0479         { name, "AIF3RX1", "AIF3RX1" }, \
0480         { name, "AIF3RX2", "AIF3RX2" }, \
0481         { name, "EQ1", "EQ1" }, \
0482         { name, "EQ2", "EQ2" }, \
0483         { name, "EQ3", "EQ3" }, \
0484         { name, "EQ4", "EQ4" }, \
0485         { name, "DRC1L", "DRC1L" }, \
0486         { name, "DRC1R", "DRC1R" }, \
0487         { name, "LHPF1", "LHPF1" }, \
0488         { name, "LHPF2", "LHPF2" }, \
0489         { name, "LHPF3", "LHPF3" }, \
0490         { name, "LHPF4", "LHPF4" }
0491
0492 #define WM5100_MIXER_ROUTES(widget, name) \
0493     { widget, NULL, name " Mixer" },         \
0494     { name " Mixer", NULL, name " Input 1" }, \
0495     { name " Mixer", NULL, name " Input 2" }, \
0496     { name " Mixer", NULL, name " Input 3" }, \
0497     { name " Mixer", NULL, name " Input 4" }, \
0498     WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
0499     WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
0500     WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
0501     WM5100_MIXER_INPUT_ROUTES(name " Input 4")
0502
0503 static const char *wm5100_lhpf_mode_text[] = {
0504     "Low-pass", "High-pass"
0505 };
0506
0507 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf1_mode,
0508                 WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT,
0509                 wm5100_lhpf_mode_text);
0510
0511 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf2_mode,
0512                 WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT,
0513                 wm5100_lhpf_mode_text);
0514
0515 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf3_mode,
0516                 WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT,
0517                 wm5100_lhpf_mode_text);
0518
0519 static SOC_ENUM_SINGLE_DECL(wm5100_lhpf4_mode,
0520                 WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT,
0521                 wm5100_lhpf_mode_text);
0522
0523 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
0524 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
0525        WM5100_IN1_OSR_SHIFT, 1, 0),
0526 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
0527        WM5100_IN2_OSR_SHIFT, 1, 0),
0528 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
0529        WM5100_IN3_OSR_SHIFT, 1, 0),
0530 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
0531        WM5100_IN4_OSR_SHIFT, 1, 0),
0532
0533 /* Only applicable for analogue inputs */
0534 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
0535          WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
0536 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
0537          WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
0538 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
0539          WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
0540 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
0541          WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
0542
0543 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
0544          WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
0545          0, digital_tlv),
0546 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
0547          WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
0548          0, digital_tlv),
0549 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
0550          WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
0551          0, digital_tlv),
0552 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
0553          WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
0554          0, digital_tlv),
0555
0556 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
0557          WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
0558 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
0559          WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
0560 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
0561          WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
0562 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
0563          WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
0564
0565 SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
0566 SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
0567 SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
0568 SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
0569
0570 SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
0571            WM5100_DRCL_ENA | WM5100_DRCR_ENA),
0572
0573 SND_SOC_BYTES("LHPF1 Coefficients", WM5100_HPLPF1_2, 1),
0574 SND_SOC_BYTES("LHPF2 Coefficients", WM5100_HPLPF2_2, 1),
0575 SND_SOC_BYTES("LHPF3 Coefficients", WM5100_HPLPF3_2, 1),
0576 SND_SOC_BYTES("LHPF4 Coefficients", WM5100_HPLPF4_2, 1),
0577
0578 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
0579        WM5100_OUT1_OSR_SHIFT, 1, 0),
0580 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
0581        WM5100_OUT2_OSR_SHIFT, 1, 0),
0582 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
0583        WM5100_OUT3_OSR_SHIFT, 1, 0),
0584 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
0585        WM5100_OUT4_OSR_SHIFT, 1, 0),
0586 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
0587        WM5100_OUT5_OSR_SHIFT, 1, 0),
0588 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
0589        WM5100_OUT6_OSR_SHIFT, 1, 0),
0590
0591 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
0592          WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
0593          digital_tlv),
0594 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
0595          WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
0596          digital_tlv),
0597 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
0598          WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
0599          digital_tlv),
0600 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
0601          WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
0602          digital_tlv),
0603 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
0604          WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
0605          digital_tlv),
0606 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
0607          WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
0608          digital_tlv),
0609
0610 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
0611          WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
0612 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
0613          WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
0614 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
0615          WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
0616 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
0617          WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
0618 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
0619          WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
0620 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
0621          WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
0622
0623 /* FIXME: Only valid from -12dB to 0dB (52-64) */
0624 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
0625          WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
0626 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
0627          WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
0628 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
0629          WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
0630
0631 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
0632        WM5100_SPK1R_MUTE_SHIFT, 1, 1),
0633 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
0634        WM5100_SPK2R_MUTE_SHIFT, 1, 1),
0635
0636 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
0637            24, 0, eq_tlv),
0638 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
0639            24, 0, eq_tlv),
0640 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
0641            24, 0, eq_tlv),
0642 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
0643            24, 0, eq_tlv),
0644 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
0645            24, 0, eq_tlv),
0646
0647 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
0648            24, 0, eq_tlv),
0649 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
0650            24, 0, eq_tlv),
0651 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
0652            24, 0, eq_tlv),
0653 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
0654            24, 0, eq_tlv),
0655 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
0656            24, 0, eq_tlv),
0657
0658 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
0659            24, 0, eq_tlv),
0660 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
0661            24, 0, eq_tlv),
0662 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
0663            24, 0, eq_tlv),
0664 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
0665            24, 0, eq_tlv),
0666 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
0667            24, 0, eq_tlv),
0668
0669 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
0670            24, 0, eq_tlv),
0671 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
0672            24, 0, eq_tlv),
0673 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
0674            24, 0, eq_tlv),
0675 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
0676            24, 0, eq_tlv),
0677 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
0678            24, 0, eq_tlv),
0679
0680 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
0681 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
0682 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
0683 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
0684
0685 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
0686 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
0687 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
0688 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
0689 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
0690 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
0691
0692 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
0693 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
0694 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
0695 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
0696 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
0697 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
0698
0699 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
0700 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
0701
0702 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
0703 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
0704 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
0705 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
0706 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
0707 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
0708 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
0709 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
0710
0711 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
0712 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
0713
0714 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
0715 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
0716
0717 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
0718 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
0719 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
0720 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
0721
0722 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
0723 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
0724 SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
0725            WM5100_DRCL_ENA | WM5100_DRCR_ENA),
0726
0727 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
0728 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
0729 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
0730 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
0731 };
0732
0733 static void wm5100_seq_notifier(struct snd_soc_component *component,
0734                 enum snd_soc_dapm_type event, int subseq)
0735 {
0736     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
0737     u16 val, expect, i;
0738
0739     /* Wait for the outputs to flag themselves as enabled */
0740     if (wm5100->out_ena[0]) {
0741         expect = snd_soc_component_read(component, WM5100_CHANNEL_ENABLES_1);
0742         for (i = 0; i < 200; i++) {
0743             val = snd_soc_component_read(component, WM5100_OUTPUT_STATUS_1);
0744             if (val == expect) {
0745                 wm5100->out_ena[0] = false;
0746                 break;
0747             }
0748         }
0749         if (i == 200) {
0750             dev_err(component->dev, "Timeout waiting for OUTPUT1 %x\n",
0751                 expect);
0752         }
0753     }
0754
0755     if (wm5100->out_ena[1]) {
0756         expect = snd_soc_component_read(component, WM5100_OUTPUT_ENABLES_2);
0757         for (i = 0; i < 200; i++) {
0758             val = snd_soc_component_read(component, WM5100_OUTPUT_STATUS_2);
0759             if (val == expect) {
0760                 wm5100->out_ena[1] = false;
0761                 break;
0762             }
0763         }
0764         if (i == 200) {
0765             dev_err(component->dev, "Timeout waiting for OUTPUT2 %x\n",
0766                 expect);
0767         }
0768     }
0769 }
0770
0771 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
0772              struct snd_kcontrol *kcontrol,
0773              int event)
0774 {
0775     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0776     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
0777
0778     switch (w->reg) {
0779     case WM5100_CHANNEL_ENABLES_1:
0780         wm5100->out_ena[0] = true;
0781         break;
0782     case WM5100_OUTPUT_ENABLES_2:
0783         wm5100->out_ena[0] = true;
0784         break;
0785     default:
0786         break;
0787     }
0788
0789     return 0;
0790 }
0791
0792 static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
0793 {
0794     if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
0795         dev_crit(wm5100->dev, "Speaker shutdown warning\n");
0796     if (val & WM5100_SPK_SHUTDOWN_EINT)
0797         dev_crit(wm5100->dev, "Speaker shutdown\n");
0798     if (val & WM5100_CLKGEN_ERR_EINT)
0799         dev_crit(wm5100->dev, "SYSCLK underclocked\n");
0800     if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
0801         dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
0802 }
0803
0804 static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
0805 {
0806     if (val & WM5100_AIF3_ERR_EINT)
0807         dev_err(wm5100->dev, "AIF3 configuration error\n");
0808     if (val & WM5100_AIF2_ERR_EINT)
0809         dev_err(wm5100->dev, "AIF2 configuration error\n");
0810     if (val & WM5100_AIF1_ERR_EINT)
0811         dev_err(wm5100->dev, "AIF1 configuration error\n");
0812     if (val & WM5100_CTRLIF_ERR_EINT)
0813         dev_err(wm5100->dev, "Control interface error\n");
0814     if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
0815         dev_err(wm5100->dev, "ISRC2 underclocked\n");
0816     if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
0817         dev_err(wm5100->dev, "ISRC1 underclocked\n");
0818     if (val & WM5100_FX_UNDERCLOCKED_EINT)
0819         dev_err(wm5100->dev, "FX underclocked\n");
0820     if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
0821         dev_err(wm5100->dev, "AIF3 underclocked\n");
0822     if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
0823         dev_err(wm5100->dev, "AIF2 underclocked\n");
0824     if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
0825         dev_err(wm5100->dev, "AIF1 underclocked\n");
0826     if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
0827         dev_err(wm5100->dev, "ASRC underclocked\n");
0828     if (val & WM5100_DAC_UNDERCLOCKED_EINT)
0829         dev_err(wm5100->dev, "DAC underclocked\n");
0830     if (val & WM5100_ADC_UNDERCLOCKED_EINT)
0831         dev_err(wm5100->dev, "ADC underclocked\n");
0832     if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
0833         dev_err(wm5100->dev, "Mixer underclocked\n");
0834 }
0835
0836 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
0837               struct snd_kcontrol *kcontrol,
0838               int event)
0839 {
0840     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0841     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
0842     int ret;
0843
0844     ret = snd_soc_component_read(component, WM5100_INTERRUPT_RAW_STATUS_3);
0845     ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
0846         WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
0847         WM5100_CLKGEN_ERR_ASYNC_STS;
0848     wm5100_log_status3(wm5100, ret);
0849
0850     ret = snd_soc_component_read(component, WM5100_INTERRUPT_RAW_STATUS_4);
0851     wm5100_log_status4(wm5100, ret);
0852
0853     return 0;
0854 }
0855
0856 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
0857 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
0858             NULL, 0),
0859 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
0860             0, NULL, 0),
0861
0862 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
0863 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
0864 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
0865
0866 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
0867             NULL, 0),
0868 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
0869             NULL, 0),
0870 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
0871             WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
0872
0873 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
0874             0, NULL, 0),
0875 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
0876             0, NULL, 0),
0877 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
0878             0, NULL, 0),
0879
0880 SND_SOC_DAPM_INPUT("IN1L"),
0881 SND_SOC_DAPM_INPUT("IN1R"),
0882 SND_SOC_DAPM_INPUT("IN2L"),
0883 SND_SOC_DAPM_INPUT("IN2R"),
0884 SND_SOC_DAPM_INPUT("IN3L"),
0885 SND_SOC_DAPM_INPUT("IN3R"),
0886 SND_SOC_DAPM_INPUT("IN4L"),
0887 SND_SOC_DAPM_INPUT("IN4R"),
0888 SND_SOC_DAPM_SIGGEN("TONE"),
0889
0890 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
0891            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0892 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
0893            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0894 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
0895            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0896 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
0897            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0898 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
0899            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0900 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
0901            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0902 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
0903            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0904 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
0905            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0906
0907 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
0908          WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
0909 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
0910          WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
0911
0912 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
0913             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
0914 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
0915             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
0916 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
0917             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
0918 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
0919             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
0920 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
0921             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
0922 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
0923             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
0924 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
0925             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
0926 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
0927             WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
0928
0929 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
0930             WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
0931 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
0932             WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
0933
0934 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
0935             WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
0936 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
0937             WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
0938
0939 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
0940             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
0941 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
0942             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
0943 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
0944             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
0945 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
0946             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
0947 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
0948             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
0949 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
0950             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
0951 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
0952             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
0953 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
0954             WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
0955
0956 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
0957             WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
0958 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
0959             WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
0960
0961 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
0962             WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
0963 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
0964             WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
0965
0966 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
0967            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0968 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
0969            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0970 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
0971            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0972 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
0973            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0974 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
0975            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0976 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
0977            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0978 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
0979            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0980 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
0981            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0982 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
0983            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0984 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
0985            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0986 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
0987            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0988 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
0989            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0990 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
0991            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0992 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
0993            NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
0994
0995 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
0996 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
0997 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
0998 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
0999
1000 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1001          NULL, 0),
1002 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1003          NULL, 0),
1004
1005 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1006          NULL, 0),
1007 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1008          NULL, 0),
1009 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1010          NULL, 0),
1011 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1012          NULL, 0),
1013
1014 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1015 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1016 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1017 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1018
1019 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1020 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1021
1022 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1023 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1024 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1025 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1026
1027 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1028 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1029 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1030 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1031 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1032 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1033 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1034 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1035
1036 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1037 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1038
1039 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1040 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1041
1042 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1043 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1044 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1045 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1046 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1047 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1048
1049 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1050 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1051 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1052 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1053 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1054 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1055
1056 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1057 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1058
1059 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1060 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1061 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1062 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1063 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1065 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1066 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1067 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1068 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1069 SND_SOC_DAPM_OUTPUT("PWM1"),
1070 SND_SOC_DAPM_OUTPUT("PWM2"),
1071 };
1072
1073 /* We register a _POST event if we don't have IRQ support so we can
1074  * look at the error status from the CODEC - if we've got the IRQ
1075  * hooked up then we will get prompted to look by an interrupt.
1076  */
1077 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1078 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1079 };
1080
1081 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1082     { "CP1", NULL, "CPVDD" },
1083     { "CP2 Active", NULL, "CPVDD" },
1084
1085     { "IN1L", NULL, "SYSCLK" },
1086     { "IN1R", NULL, "SYSCLK" },
1087     { "IN2L", NULL, "SYSCLK" },
1088     { "IN2R", NULL, "SYSCLK" },
1089     { "IN3L", NULL, "SYSCLK" },
1090     { "IN3R", NULL, "SYSCLK" },
1091     { "IN4L", NULL, "SYSCLK" },
1092     { "IN4R", NULL, "SYSCLK" },
1093
1094     { "OUT1L", NULL, "SYSCLK" },
1095     { "OUT1R", NULL, "SYSCLK" },
1096     { "OUT2L", NULL, "SYSCLK" },
1097     { "OUT2R", NULL, "SYSCLK" },
1098     { "OUT3L", NULL, "SYSCLK" },
1099     { "OUT3R", NULL, "SYSCLK" },
1100     { "OUT4L", NULL, "SYSCLK" },
1101     { "OUT4R", NULL, "SYSCLK" },
1102     { "OUT5L", NULL, "SYSCLK" },
1103     { "OUT5R", NULL, "SYSCLK" },
1104     { "OUT6L", NULL, "SYSCLK" },
1105     { "OUT6R", NULL, "SYSCLK" },
1106
1107     { "AIF1RX1", NULL, "SYSCLK" },
1108     { "AIF1RX2", NULL, "SYSCLK" },
1109     { "AIF1RX3", NULL, "SYSCLK" },
1110     { "AIF1RX4", NULL, "SYSCLK" },
1111     { "AIF1RX5", NULL, "SYSCLK" },
1112     { "AIF1RX6", NULL, "SYSCLK" },
1113     { "AIF1RX7", NULL, "SYSCLK" },
1114     { "AIF1RX8", NULL, "SYSCLK" },
1115
1116     { "AIF2RX1", NULL, "SYSCLK" },
1117     { "AIF2RX1", NULL, "DBVDD2" },
1118     { "AIF2RX2", NULL, "SYSCLK" },
1119     { "AIF2RX2", NULL, "DBVDD2" },
1120
1121     { "AIF3RX1", NULL, "SYSCLK" },
1122     { "AIF3RX1", NULL, "DBVDD3" },
1123     { "AIF3RX2", NULL, "SYSCLK" },
1124     { "AIF3RX2", NULL, "DBVDD3" },
1125
1126     { "AIF1TX1", NULL, "SYSCLK" },
1127     { "AIF1TX2", NULL, "SYSCLK" },
1128     { "AIF1TX3", NULL, "SYSCLK" },
1129     { "AIF1TX4", NULL, "SYSCLK" },
1130     { "AIF1TX5", NULL, "SYSCLK" },
1131     { "AIF1TX6", NULL, "SYSCLK" },
1132     { "AIF1TX7", NULL, "SYSCLK" },
1133     { "AIF1TX8", NULL, "SYSCLK" },
1134
1135     { "AIF2TX1", NULL, "SYSCLK" },
1136     { "AIF2TX1", NULL, "DBVDD2" },
1137     { "AIF2TX2", NULL, "SYSCLK" },
1138     { "AIF2TX2", NULL, "DBVDD2" },
1139
1140     { "AIF3TX1", NULL, "SYSCLK" },
1141     { "AIF3TX1", NULL, "DBVDD3" },
1142     { "AIF3TX2", NULL, "SYSCLK" },
1143     { "AIF3TX2", NULL, "DBVDD3" },
1144
1145     { "MICBIAS1", NULL, "CP2" },
1146     { "MICBIAS2", NULL, "CP2" },
1147     { "MICBIAS3", NULL, "CP2" },
1148
1149     { "IN1L PGA", NULL, "CP2" },
1150     { "IN1R PGA", NULL, "CP2" },
1151     { "IN2L PGA", NULL, "CP2" },
1152     { "IN2R PGA", NULL, "CP2" },
1153     { "IN3L PGA", NULL, "CP2" },
1154     { "IN3R PGA", NULL, "CP2" },
1155     { "IN4L PGA", NULL, "CP2" },
1156     { "IN4R PGA", NULL, "CP2" },
1157
1158     { "IN1L PGA", NULL, "CP2 Active" },
1159     { "IN1R PGA", NULL, "CP2 Active" },
1160     { "IN2L PGA", NULL, "CP2 Active" },
1161     { "IN2R PGA", NULL, "CP2 Active" },
1162     { "IN3L PGA", NULL, "CP2 Active" },
1163     { "IN3R PGA", NULL, "CP2 Active" },
1164     { "IN4L PGA", NULL, "CP2 Active" },
1165     { "IN4R PGA", NULL, "CP2 Active" },
1166
1167     { "OUT1L", NULL, "CP1" },
1168     { "OUT1R", NULL, "CP1" },
1169     { "OUT2L", NULL, "CP1" },
1170     { "OUT2R", NULL, "CP1" },
1171     { "OUT3L", NULL, "CP1" },
1172     { "OUT3R", NULL, "CP1" },
1173
1174     { "Tone Generator 1", NULL, "TONE" },
1175     { "Tone Generator 2", NULL, "TONE" },
1176
1177     { "IN1L PGA", NULL, "IN1L" },
1178     { "IN1R PGA", NULL, "IN1R" },
1179     { "IN2L PGA", NULL, "IN2L" },
1180     { "IN2R PGA", NULL, "IN2R" },
1181     { "IN3L PGA", NULL, "IN3L" },
1182     { "IN3R PGA", NULL, "IN3R" },
1183     { "IN4L PGA", NULL, "IN4L" },
1184     { "IN4R PGA", NULL, "IN4R" },
1185
1186     WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1187     WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1188     WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1189     WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1190     WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1191     WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1192
1193     WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1194     WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1195     WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1196     WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1197     WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1198     WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1199
1200     WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1201     WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1202
1203     WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1204     WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1205     WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1206     WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1207     WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1208     WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1209     WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1210     WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1211
1212     WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1213     WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1214
1215     WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1216     WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1217
1218     WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1219     WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1220     WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1221     WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1222
1223     WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1224     WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1225
1226     WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1227     WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1228     WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1229     WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1230
1231     { "HPOUT1L", NULL, "OUT1L" },
1232     { "HPOUT1R", NULL, "OUT1R" },
1233     { "HPOUT2L", NULL, "OUT2L" },
1234     { "HPOUT2R", NULL, "OUT2R" },
1235     { "HPOUT3L", NULL, "OUT3L" },
1236     { "HPOUT3R", NULL, "OUT3R" },
1237     { "SPKOUTL", NULL, "OUT4L" },
1238     { "SPKOUTR", NULL, "OUT4R" },
1239     { "SPKDAT1", NULL, "OUT5L" },
1240     { "SPKDAT1", NULL, "OUT5R" },
1241     { "SPKDAT2", NULL, "OUT6L" },
1242     { "SPKDAT2", NULL, "OUT6R" },
1243     { "PWM1", NULL, "PWM1 Driver" },
1244     { "PWM2", NULL, "PWM2 Driver" },
1245 };
1246
1247 static const struct reg_sequence wm5100_reva_patches[] = {
1248     { WM5100_AUDIO_IF_1_10, 0 },
1249     { WM5100_AUDIO_IF_1_11, 1 },
1250     { WM5100_AUDIO_IF_1_12, 2 },
1251     { WM5100_AUDIO_IF_1_13, 3 },
1252     { WM5100_AUDIO_IF_1_14, 4 },
1253     { WM5100_AUDIO_IF_1_15, 5 },
1254     { WM5100_AUDIO_IF_1_16, 6 },
1255     { WM5100_AUDIO_IF_1_17, 7 },
1256
1257     { WM5100_AUDIO_IF_1_18, 0 },
1258     { WM5100_AUDIO_IF_1_19, 1 },
1259     { WM5100_AUDIO_IF_1_20, 2 },
1260     { WM5100_AUDIO_IF_1_21, 3 },
1261     { WM5100_AUDIO_IF_1_22, 4 },
1262     { WM5100_AUDIO_IF_1_23, 5 },
1263     { WM5100_AUDIO_IF_1_24, 6 },
1264     { WM5100_AUDIO_IF_1_25, 7 },
1265
1266     { WM5100_AUDIO_IF_2_10, 0 },
1267     { WM5100_AUDIO_IF_2_11, 1 },
1268
1269     { WM5100_AUDIO_IF_2_18, 0 },
1270     { WM5100_AUDIO_IF_2_19, 1 },
1271
1272     { WM5100_AUDIO_IF_3_10, 0 },
1273     { WM5100_AUDIO_IF_3_11, 1 },
1274
1275     { WM5100_AUDIO_IF_3_18, 0 },
1276     { WM5100_AUDIO_IF_3_19, 1 },
1277 };
1278
1279 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1280 {
1281     struct snd_soc_component *component = dai->component;
1282     int lrclk, bclk, mask, base;
1283
1284     base = dai->driver->base;
1285
1286     lrclk = 0;
1287     bclk = 0;
1288
1289     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1290     case SND_SOC_DAIFMT_DSP_A:
1291         mask = 0;
1292         break;
1293     case SND_SOC_DAIFMT_I2S:
1294         mask = 2;
1295         break;
1296     default:
1297         dev_err(component->dev, "Unsupported DAI format %d\n",
1298             fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1299         return -EINVAL;
1300     }
1301
1302     switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1303     case SND_SOC_DAIFMT_CBS_CFS:
1304         break;
1305     case SND_SOC_DAIFMT_CBS_CFM:
1306         lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1307         break;
1308     case SND_SOC_DAIFMT_CBM_CFS:
1309         bclk |= WM5100_AIF1_BCLK_MSTR;
1310         break;
1311     case SND_SOC_DAIFMT_CBM_CFM:
1312         lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1313         bclk |= WM5100_AIF1_BCLK_MSTR;
1314         break;
1315     default:
1316         dev_err(component->dev, "Unsupported master mode %d\n",
1317             fmt & SND_SOC_DAIFMT_MASTER_MASK);
1318         return -EINVAL;
1319     }
1320
1321     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1322     case SND_SOC_DAIFMT_NB_NF:
1323         break;
1324     case SND_SOC_DAIFMT_IB_IF:
1325         bclk |= WM5100_AIF1_BCLK_INV;
1326         lrclk |= WM5100_AIF1TX_LRCLK_INV;
1327         break;
1328     case SND_SOC_DAIFMT_IB_NF:
1329         bclk |= WM5100_AIF1_BCLK_INV;
1330         break;
1331     case SND_SOC_DAIFMT_NB_IF:
1332         lrclk |= WM5100_AIF1TX_LRCLK_INV;
1333         break;
1334     default:
1335         return -EINVAL;
1336     }
1337
1338     snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_MSTR |
1339                 WM5100_AIF1_BCLK_INV, bclk);
1340     snd_soc_component_update_bits(component, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1341                 WM5100_AIF1TX_LRCLK_INV, lrclk);
1342     snd_soc_component_update_bits(component, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1343                 WM5100_AIF1TX_LRCLK_INV, lrclk);
1344     snd_soc_component_update_bits(component, base + 5, WM5100_AIF1_FMT_MASK, mask);
1345
1346     return 0;
1347 }
1348
1349 #define WM5100_NUM_BCLK_RATES 19
1350
1351 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1352     32000,
1353     48000,
1354     64000,
1355     96000,
1356     128000,
1357     192000,
1358     256000,
1359     384000,
1360     512000,
1361     768000,
1362     1024000,
1363     1536000,
1364     2048000,
1365     3072000,
1366     4096000,
1367     6144000,
1368     8192000,
1369     12288000,
1370     24576000,
1371 };
1372
1373 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1374     29400,
1375     44100,
1376     58800,
1377     88200,
1378     117600,
1379     176400,
1380     235200,
1381     352800,
1382     470400,
1383     705600,
1384     940800,
1385     1411200,
1386     1881600,
1387     2882400,
1388     3763200,
1389     5644800,
1390     7526400,
1391     11289600,
1392     22579600,
1393 };
1394
1395 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1396                 struct snd_pcm_hw_params *params,
1397                 struct snd_soc_dai *dai)
1398 {
1399     struct snd_soc_component *component = dai->component;
1400     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
1401     bool async = wm5100->aif_async[dai->id];
1402     int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1403     int *bclk_rates;
1404
1405     base = dai->driver->base;
1406
1407     /* Data sizes if not using TDM */
1408     wl = params_width(params);
1409     if (wl < 0)
1410         return wl;
1411     fl = snd_soc_params_to_frame_size(params);
1412     if (fl < 0)
1413         return fl;
1414
1415     dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n",
1416         wl, fl);
1417
1418     /* Target BCLK rate */
1419     bclk = snd_soc_params_to_bclk(params);
1420     if (bclk < 0)
1421         return bclk;
1422
1423     /* Root for BCLK depends on SYS/ASYNCCLK */
1424     if (!async) {
1425         aif_rate = wm5100->sysclk;
1426         sr = wm5100_alloc_sr(component, params_rate(params));
1427         if (sr < 0)
1428             return sr;
1429     } else {
1430         /* If we're in ASYNCCLK set the ASYNC sample rate */
1431         aif_rate = wm5100->asyncclk;
1432         sr = 3;
1433
1434         for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1435             if (params_rate(params) == wm5100_sr_code[i])
1436                 break;
1437         if (i == ARRAY_SIZE(wm5100_sr_code)) {
1438             dev_err(component->dev, "Invalid rate %dHzn",
1439                 params_rate(params));
1440             return -EINVAL;
1441         }
1442
1443         /* TODO: We should really check for symmetry */
1444         snd_soc_component_update_bits(component, WM5100_CLOCKING_8,
1445                     WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1446     }
1447
1448     if (!aif_rate) {
1449         dev_err(component->dev, "%s has no rate set\n",
1450             async ? "ASYNCCLK" : "SYSCLK");
1451         return -EINVAL;
1452     }
1453
1454     dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz %s\n",
1455         bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1456
1457     if (aif_rate % 4000)
1458         bclk_rates = wm5100_bclk_rates_cd;
1459     else
1460         bclk_rates = wm5100_bclk_rates_dat;
1461
1462     for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1463         if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1464             break;
1465     if (i == WM5100_NUM_BCLK_RATES) {
1466         dev_err(component->dev,
1467             "No valid BCLK for %dHz found from %dHz %s\n",
1468             bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1469         return -EINVAL;
1470     }
1471
1472     bclk = i;
1473     dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1474     snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1475
1476     lrclk = bclk_rates[bclk] / params_rate(params);
1477     dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1478     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1479         wm5100->aif_symmetric[dai->id])
1480         snd_soc_component_update_bits(component, base + 7,
1481                     WM5100_AIF1RX_BCPF_MASK, lrclk);
1482     else
1483         snd_soc_component_update_bits(component, base + 6,
1484                     WM5100_AIF1TX_BCPF_MASK, lrclk);
1485
1486     i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1487     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1488         snd_soc_component_update_bits(component, base + 9,
1489                     WM5100_AIF1RX_WL_MASK |
1490                     WM5100_AIF1RX_SLOT_LEN_MASK, i);
1491     else
1492         snd_soc_component_update_bits(component, base + 8,
1493                     WM5100_AIF1TX_WL_MASK |
1494                     WM5100_AIF1TX_SLOT_LEN_MASK, i);
1495
1496     snd_soc_component_update_bits(component, base + 4, WM5100_AIF1_RATE_MASK, sr);
1497
1498     return 0;
1499 }
1500
1501 static const struct snd_soc_dai_ops wm5100_dai_ops = {
1502     .set_fmt = wm5100_set_fmt,
1503     .hw_params = wm5100_hw_params,
1504 };
1505
1506 static int wm5100_set_sysclk(struct snd_soc_component *component, int clk_id,
1507                  int source, unsigned int freq, int dir)
1508 {
1509     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
1510     int *rate_store;
1511     int fval, audio_rate, ret, reg;
1512
1513     switch (clk_id) {
1514     case WM5100_CLK_SYSCLK:
1515         reg = WM5100_CLOCKING_3;
1516         rate_store = &wm5100->sysclk;
1517         break;
1518     case WM5100_CLK_ASYNCCLK:
1519         reg = WM5100_CLOCKING_7;
1520         rate_store = &wm5100->asyncclk;
1521         break;
1522     case WM5100_CLK_32KHZ:
1523         /* The 32kHz clock is slightly different to the others */
1524         switch (source) {
1525         case WM5100_CLKSRC_MCLK1:
1526         case WM5100_CLKSRC_MCLK2:
1527         case WM5100_CLKSRC_SYSCLK:
1528             snd_soc_component_update_bits(component, WM5100_CLOCKING_1,
1529                         WM5100_CLK_32K_SRC_MASK,
1530                         source);
1531             break;
1532         default:
1533             return -EINVAL;
1534         }
1535         return 0;
1536
1537     case WM5100_CLK_AIF1:
1538     case WM5100_CLK_AIF2:
1539     case WM5100_CLK_AIF3:
1540         /* Not real clocks, record which clock domain they're in */
1541         switch (source) {
1542         case WM5100_CLKSRC_SYSCLK:
1543             wm5100->aif_async[clk_id - 1] = false;
1544             break;
1545         case WM5100_CLKSRC_ASYNCCLK:
1546             wm5100->aif_async[clk_id - 1] = true;
1547             break;
1548         default:
1549             dev_err(component->dev, "Invalid source %d\n", source);
1550             return -EINVAL;
1551         }
1552         return 0;
1553
1554     case WM5100_CLK_OPCLK:
1555         switch (freq) {
1556         case 5644800:
1557         case 6144000:
1558             snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
1559                         WM5100_OPCLK_SEL_MASK, 0);
1560             break;
1561         case 11289600:
1562         case 12288000:
1563             snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
1564                         WM5100_OPCLK_SEL_MASK, 0);
1565             break;
1566         case 22579200:
1567         case 24576000:
1568             snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
1569                         WM5100_OPCLK_SEL_MASK, 0);
1570             break;
1571         default:
1572             dev_err(component->dev, "Unsupported OPCLK %dHz\n",
1573                 freq);
1574             return -EINVAL;
1575         }
1576         return 0;
1577
1578     default:
1579         dev_err(component->dev, "Unknown clock %d\n", clk_id);
1580         return -EINVAL;
1581     }
1582
1583     switch (source) {
1584     case WM5100_CLKSRC_SYSCLK:
1585     case WM5100_CLKSRC_ASYNCCLK:
1586         dev_err(component->dev, "Invalid source %d\n", source);
1587         return -EINVAL;
1588     }
1589
1590     switch (freq) {
1591     case 5644800:
1592     case 6144000:
1593         fval = 0;
1594         break;
1595     case 11289600:
1596     case 12288000:
1597         fval = 1;
1598         break;
1599     case 22579200:
1600     case 24576000:
1601         fval = 2;
1602         break;
1603     default:
1604         dev_err(component->dev, "Invalid clock rate: %d\n", freq);
1605         return -EINVAL;
1606     }
1607
1608     switch (freq) {
1609     case 5644800:
1610     case 11289600:
1611     case 22579200:
1612         audio_rate = 44100;
1613         break;
1614
1615     case 6144000:
1616     case 12288000:
1617     case 24576000:
1618         audio_rate = 48000;
1619         break;
1620
1621     default:
1622         BUG();
1623         audio_rate = 0;
1624         break;
1625     }
1626
1627     /* TODO: Check if MCLKs are in use and enable/disable pulls to
1628      * match.
1629      */
1630
1631     snd_soc_component_update_bits(component, reg, WM5100_SYSCLK_FREQ_MASK |
1632                 WM5100_SYSCLK_SRC_MASK,
1633                 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1634
1635     /* If this is SYSCLK then configure the clock rate for the
1636      * internal audio functions to the natural sample rate for
1637      * this clock rate.
1638      */
1639     if (clk_id == WM5100_CLK_SYSCLK) {
1640         dev_dbg(component->dev, "Setting primary audio rate to %dHz",
1641             audio_rate);
1642         if (0 && *rate_store)
1643             wm5100_free_sr(component, audio_rate);
1644         ret = wm5100_alloc_sr(component, audio_rate);
1645         if (ret != 0)
1646             dev_warn(component->dev, "Primary audio slot is %d\n",
1647                  ret);
1648     }
1649
1650     *rate_store = freq;
1651
1652     return 0;
1653 }
1654
1655 struct _fll_div {
1656     u16 fll_fratio;
1657     u16 fll_outdiv;
1658     u16 fll_refclk_div;
1659     u16 n;
1660     u16 theta;
1661     u16 lambda;
1662 };
1663
1664 static struct {
1665     unsigned int min;
1666     unsigned int max;
1667     u16 fll_fratio;
1668     int ratio;
1669 } fll_fratios[] = {
1670     {       0,    64000, 4, 16 },
1671     {   64000,   128000, 3,  8 },
1672     {  128000,   256000, 2,  4 },
1673     {  256000,  1000000, 1,  2 },
1674     { 1000000, 13500000, 0,  1 },
1675 };
1676
1677 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1678                unsigned int Fout)
1679 {
1680     unsigned int target;
1681     unsigned int div;
1682     unsigned int fratio, gcd_fll;
1683     int i;
1684
1685     /* Fref must be <=13.5MHz */
1686     div = 1;
1687     fll_div->fll_refclk_div = 0;
1688     while ((Fref / div) > 13500000) {
1689         div *= 2;
1690         fll_div->fll_refclk_div++;
1691
1692         if (div > 8) {
1693             pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1694                    Fref);
1695             return -EINVAL;
1696         }
1697     }
1698
1699     pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1700
1701     /* Apply the division for our remaining calculations */
1702     Fref /= div;
1703
1704     /* Fvco should be 90-100MHz; don't check the upper bound */
1705     div = 2;
1706     while (Fout * div < 90000000) {
1707         div++;
1708         if (div > 64) {
1709             pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1710                    Fout);
1711             return -EINVAL;
1712         }
1713     }
1714     target = Fout * div;
1715     fll_div->fll_outdiv = div - 1;
1716
1717     pr_debug("FLL Fvco=%dHz\n", target);
1718
1719     /* Find an appropraite FLL_FRATIO and factor it out of the target */
1720     for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1721         if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1722             fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1723             fratio = fll_fratios[i].ratio;
1724             break;
1725         }
1726     }
1727     if (i == ARRAY_SIZE(fll_fratios)) {
1728         pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1729         return -EINVAL;
1730     }
1731
1732     fll_div->n = target / (fratio * Fref);
1733
1734     if (target % Fref == 0) {
1735         fll_div->theta = 0;
1736         fll_div->lambda = 0;
1737     } else {
1738         gcd_fll = gcd(target, fratio * Fref);
1739
1740         fll_div->theta = (target - (fll_div->n * fratio * Fref))
1741             / gcd_fll;
1742         fll_div->lambda = (fratio * Fref) / gcd_fll;
1743     }
1744
1745     pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1746          fll_div->n, fll_div->theta, fll_div->lambda);
1747     pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1748          fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1749          fll_div->fll_refclk_div);
1750
1751     return 0;
1752 }
1753
1754 static int wm5100_set_fll(struct snd_soc_component *component, int fll_id, int source,
1755               unsigned int Fref, unsigned int Fout)
1756 {
1757     struct i2c_client *i2c = to_i2c_client(component->dev);
1758     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
1759     struct _fll_div factors;
1760     struct wm5100_fll *fll;
1761     int ret, base, lock, i, timeout;
1762     unsigned long time_left;
1763
1764     switch (fll_id) {
1765     case WM5100_FLL1:
1766         fll = &wm5100->fll[0];
1767         base = WM5100_FLL1_CONTROL_1 - 1;
1768         lock = WM5100_FLL1_LOCK_STS;
1769         break;
1770     case WM5100_FLL2:
1771         fll = &wm5100->fll[1];
1772         base = WM5100_FLL2_CONTROL_2 - 1;
1773         lock = WM5100_FLL2_LOCK_STS;
1774         break;
1775     default:
1776         dev_err(component->dev, "Unknown FLL %d\n",fll_id);
1777         return -EINVAL;
1778     }
1779
1780     if (!Fout) {
1781         dev_dbg(component->dev, "FLL%d disabled", fll_id);
1782         if (fll->fout)
1783             pm_runtime_put(component->dev);
1784         fll->fout = 0;
1785         snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0);
1786         return 0;
1787     }
1788
1789     switch (source) {
1790     case WM5100_FLL_SRC_MCLK1:
1791     case WM5100_FLL_SRC_MCLK2:
1792     case WM5100_FLL_SRC_FLL1:
1793     case WM5100_FLL_SRC_FLL2:
1794     case WM5100_FLL_SRC_AIF1BCLK:
1795     case WM5100_FLL_SRC_AIF2BCLK:
1796     case WM5100_FLL_SRC_AIF3BCLK:
1797         break;
1798     default:
1799         dev_err(component->dev, "Invalid FLL source %d\n", source);
1800         return -EINVAL;
1801     }
1802
1803     ret = fll_factors(&factors, Fref, Fout);
1804     if (ret < 0)
1805         return ret;
1806
1807     /* Disable the FLL while we reconfigure */
1808     snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0);
1809
1810     snd_soc_component_update_bits(component, base + 2,
1811                 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1812                 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1813                 factors.fll_fratio);
1814     snd_soc_component_update_bits(component, base + 3, WM5100_FLL1_THETA_MASK,
1815                 factors.theta);
1816     snd_soc_component_update_bits(component, base + 5, WM5100_FLL1_N_MASK, factors.n);
1817     snd_soc_component_update_bits(component, base + 6,
1818                 WM5100_FLL1_REFCLK_DIV_MASK |
1819                 WM5100_FLL1_REFCLK_SRC_MASK,
1820                 (factors.fll_refclk_div
1821                  << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1822     snd_soc_component_update_bits(component, base + 7, WM5100_FLL1_LAMBDA_MASK,
1823                 factors.lambda);
1824
1825     /* Clear any pending completions */
1826     try_wait_for_completion(&fll->lock);
1827
1828     pm_runtime_get_sync(component->dev);
1829
1830     snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1831
1832     if (i2c->irq)
1833         timeout = 2;
1834     else
1835         timeout = 50;
1836
1837     snd_soc_component_update_bits(component, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1838                 WM5100_SYSCLK_ENA);
1839
1840     /* Poll for the lock; will use interrupt when we can test */
1841     for (i = 0; i < timeout; i++) {
1842         if (i2c->irq) {
1843             time_left = wait_for_completion_timeout(&fll->lock,
1844                             msecs_to_jiffies(25));
1845             if (time_left > 0)
1846                 break;
1847         } else {
1848             msleep(1);
1849         }
1850
1851         ret = snd_soc_component_read(component,
1852                    WM5100_INTERRUPT_RAW_STATUS_3);
1853         if (ret < 0) {
1854             dev_err(component->dev,
1855                 "Failed to read FLL status: %d\n",
1856                 ret);
1857             continue;
1858         }
1859         if (ret & lock)
1860             break;
1861     }
1862     if (i == timeout) {
1863         dev_err(component->dev, "FLL%d lock timed out\n", fll_id);
1864         pm_runtime_put(component->dev);
1865         return -ETIMEDOUT;
1866     }
1867
1868     fll->src = source;
1869     fll->fref = Fref;
1870     fll->fout = Fout;
1871
1872     dev_dbg(component->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1873         Fref, Fout);
1874
1875     return 0;
1876 }
1877
1878 /* Actually go much higher */
1879 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1880
1881 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1882             SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1883
1884 static struct snd_soc_dai_driver wm5100_dai[] = {
1885     {
1886         .name = "wm5100-aif1",
1887         .base = WM5100_AUDIO_IF_1_1 - 1,
1888         .playback = {
1889             .stream_name = "AIF1 Playback",
1890             .channels_min = 2,
1891             .channels_max = 2,
1892             .rates = WM5100_RATES,
1893             .formats = WM5100_FORMATS,
1894         },
1895         .capture = {
1896              .stream_name = "AIF1 Capture",
1897              .channels_min = 2,
1898              .channels_max = 2,
1899              .rates = WM5100_RATES,
1900              .formats = WM5100_FORMATS,
1901          },
1902         .ops = &wm5100_dai_ops,
1903     },
1904     {
1905         .name = "wm5100-aif2",
1906         .id = 1,
1907         .base = WM5100_AUDIO_IF_2_1 - 1,
1908         .playback = {
1909             .stream_name = "AIF2 Playback",
1910             .channels_min = 2,
1911             .channels_max = 2,
1912             .rates = WM5100_RATES,
1913             .formats = WM5100_FORMATS,
1914         },
1915         .capture = {
1916              .stream_name = "AIF2 Capture",
1917              .channels_min = 2,
1918              .channels_max = 2,
1919              .rates = WM5100_RATES,
1920              .formats = WM5100_FORMATS,
1921          },
1922         .ops = &wm5100_dai_ops,
1923     },
1924     {
1925         .name = "wm5100-aif3",
1926         .id = 2,
1927         .base = WM5100_AUDIO_IF_3_1 - 1,
1928         .playback = {
1929             .stream_name = "AIF3 Playback",
1930             .channels_min = 2,
1931             .channels_max = 2,
1932             .rates = WM5100_RATES,
1933             .formats = WM5100_FORMATS,
1934         },
1935         .capture = {
1936              .stream_name = "AIF3 Capture",
1937              .channels_min = 2,
1938              .channels_max = 2,
1939              .rates = WM5100_RATES,
1940              .formats = WM5100_FORMATS,
1941          },
1942         .ops = &wm5100_dai_ops,
1943     },
1944 };
1945
1946 static int wm5100_dig_vu[] = {
1947     WM5100_ADC_DIGITAL_VOLUME_1L,
1948     WM5100_ADC_DIGITAL_VOLUME_1R,
1949     WM5100_ADC_DIGITAL_VOLUME_2L,
1950     WM5100_ADC_DIGITAL_VOLUME_2R,
1951     WM5100_ADC_DIGITAL_VOLUME_3L,
1952     WM5100_ADC_DIGITAL_VOLUME_3R,
1953     WM5100_ADC_DIGITAL_VOLUME_4L,
1954     WM5100_ADC_DIGITAL_VOLUME_4R,
1955
1956     WM5100_DAC_DIGITAL_VOLUME_1L,
1957     WM5100_DAC_DIGITAL_VOLUME_1R,
1958     WM5100_DAC_DIGITAL_VOLUME_2L,
1959     WM5100_DAC_DIGITAL_VOLUME_2R,
1960     WM5100_DAC_DIGITAL_VOLUME_3L,
1961     WM5100_DAC_DIGITAL_VOLUME_3R,
1962     WM5100_DAC_DIGITAL_VOLUME_4L,
1963     WM5100_DAC_DIGITAL_VOLUME_4R,
1964     WM5100_DAC_DIGITAL_VOLUME_5L,
1965     WM5100_DAC_DIGITAL_VOLUME_5R,
1966     WM5100_DAC_DIGITAL_VOLUME_6L,
1967     WM5100_DAC_DIGITAL_VOLUME_6R,
1968 };
1969
1970 static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
1971 {
1972     struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1973
1974     if (WARN_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)))
1975         return;
1976
1977     gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
1978     regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1979                WM5100_ACCDET_BIAS_SRC_MASK |
1980                WM5100_ACCDET_SRC,
1981                (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1982                mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1983     regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1984                WM5100_HPCOM_SRC,
1985                mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
1986
1987     wm5100->jack_mode = the_mode;
1988
1989     dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
1990         wm5100->jack_mode);
1991 }
1992
1993 static void wm5100_report_headphone(struct wm5100_priv *wm5100)
1994 {
1995     dev_dbg(wm5100->dev, "Headphone detected\n");
1996     wm5100->jack_detecting = false;
1997     snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
1998                 SND_JACK_HEADPHONE);
1999
2000     /* Increase the detection rate a bit for responsiveness. */
2001     regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2002                WM5100_ACCDET_RATE_MASK,
2003                7 << WM5100_ACCDET_RATE_SHIFT);
2004 }
2005
2006 static void wm5100_micd_irq(struct wm5100_priv *wm5100)
2007 {
2008     unsigned int val;
2009     int ret;
2010
2011     ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2012     if (ret != 0) {
2013         dev_err(wm5100->dev, "Failed to read microphone status: %d\n",
2014             ret);
2015         return;
2016     }
2017
2018     dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
2019
2020     if (!(val & WM5100_ACCDET_VALID)) {
2021         dev_warn(wm5100->dev, "Microphone detection state invalid\n");
2022         return;
2023     }
2024
2025     /* No accessory, reset everything and report removal */
2026     if (!(val & WM5100_ACCDET_STS)) {
2027         dev_dbg(wm5100->dev, "Jack removal detected\n");
2028         wm5100->jack_mic = false;
2029         wm5100->jack_detecting = true;
2030         wm5100->jack_flips = 0;
2031         snd_soc_jack_report(wm5100->jack, 0,
2032                     SND_JACK_LINEOUT | SND_JACK_HEADSET |
2033                     SND_JACK_BTN_0);
2034
2035         regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2036                    WM5100_ACCDET_RATE_MASK,
2037                    WM5100_ACCDET_RATE_MASK);
2038         return;
2039     }
2040
2041     /* If the measurement is very high we've got a microphone,
2042      * either we just detected one or if we already reported then
2043      * we've got a button release event.
2044      */
2045     if (val & 0x400) {
2046         if (wm5100->jack_detecting) {
2047             dev_dbg(wm5100->dev, "Microphone detected\n");
2048             wm5100->jack_mic = true;
2049             wm5100->jack_detecting = false;
2050             snd_soc_jack_report(wm5100->jack,
2051                         SND_JACK_HEADSET,
2052                         SND_JACK_HEADSET | SND_JACK_BTN_0);
2053
2054             /* Increase poll rate to give better responsiveness
2055              * for buttons */
2056             regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2057                        WM5100_ACCDET_RATE_MASK,
2058                        5 << WM5100_ACCDET_RATE_SHIFT);
2059         } else {
2060             dev_dbg(wm5100->dev, "Mic button up\n");
2061             snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2062         }
2063
2064         return;
2065     }
2066
2067     /* If we detected a lower impedence during initial startup
2068      * then we probably have the wrong polarity, flip it.  Don't
2069      * do this for the lowest impedences to speed up detection of
2070      * plain headphones and give up if neither polarity looks
2071      * sensible.
2072      */
2073     if (wm5100->jack_detecting && (val & 0x3f8)) {
2074         wm5100->jack_flips++;
2075
2076         if (wm5100->jack_flips > 1)
2077             wm5100_report_headphone(wm5100);
2078         else
2079             wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
2080
2081         return;
2082     }
2083
2084     /* Don't distinguish between buttons, just report any low
2085      * impedence as BTN_0.
2086      */
2087     if (val & 0x3fc) {
2088         if (wm5100->jack_mic) {
2089             dev_dbg(wm5100->dev, "Mic button detected\n");
2090             snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2091                         SND_JACK_BTN_0);
2092         } else if (wm5100->jack_detecting) {
2093             wm5100_report_headphone(wm5100);
2094         }
2095     }
2096 }
2097
2098 int wm5100_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
2099 {
2100     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
2101     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2102
2103     if (jack) {
2104         wm5100->jack = jack;
2105         wm5100->jack_detecting = true;
2106         wm5100->jack_flips = 0;
2107
2108         wm5100_set_detect_mode(wm5100, 0);
2109
2110         /* Slowest detection rate, gives debounce for initial
2111          * detection */
2112         snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
2113                     WM5100_ACCDET_BIAS_STARTTIME_MASK |
2114                     WM5100_ACCDET_RATE_MASK,
2115                     (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2116                     WM5100_ACCDET_RATE_MASK);
2117
2118         /* We need the charge pump to power MICBIAS */
2119         snd_soc_dapm_mutex_lock(dapm);
2120
2121         snd_soc_dapm_force_enable_pin_unlocked(dapm, "CP2");
2122         snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2123
2124         snd_soc_dapm_sync_unlocked(dapm);
2125
2126         snd_soc_dapm_mutex_unlock(dapm);
2127
2128         /* We start off just enabling microphone detection - even a
2129          * plain headphone will trigger detection.
2130          */
2131         snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
2132                     WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2133
2134         snd_soc_component_update_bits(component, WM5100_INTERRUPT_STATUS_3_MASK,
2135                     WM5100_IM_ACCDET_EINT, 0);
2136     } else {
2137         snd_soc_component_update_bits(component, WM5100_INTERRUPT_STATUS_3_MASK,
2138                     WM5100_IM_HPDET_EINT |
2139                     WM5100_IM_ACCDET_EINT,
2140                     WM5100_IM_HPDET_EINT |
2141                     WM5100_IM_ACCDET_EINT);
2142         snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
2143                     WM5100_ACCDET_ENA, 0);
2144         wm5100->jack = NULL;
2145     }
2146
2147     return 0;
2148 }
2149 EXPORT_SYMBOL_GPL(wm5100_detect);
2150
2151 static irqreturn_t wm5100_irq(int irq, void *data)
2152 {
2153     struct wm5100_priv *wm5100 = data;
2154     irqreturn_t status = IRQ_NONE;
2155     unsigned int irq_val, mask_val;
2156     int ret;
2157
2158     ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2159     if (ret < 0) {
2160         dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2161             ret);
2162         irq_val = 0;
2163     }
2164
2165     ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2166               &mask_val);
2167     if (ret < 0) {
2168         dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2169             ret);
2170         mask_val = 0xffff;
2171     }
2172
2173     irq_val &= ~mask_val;
2174
2175     regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
2176
2177     if (irq_val)
2178         status = IRQ_HANDLED;
2179
2180     wm5100_log_status3(wm5100, irq_val);
2181
2182     if (irq_val & WM5100_FLL1_LOCK_EINT) {
2183         dev_dbg(wm5100->dev, "FLL1 locked\n");
2184         complete(&wm5100->fll[0].lock);
2185     }
2186     if (irq_val & WM5100_FLL2_LOCK_EINT) {
2187         dev_dbg(wm5100->dev, "FLL2 locked\n");
2188         complete(&wm5100->fll[1].lock);
2189     }
2190
2191     if (irq_val & WM5100_ACCDET_EINT)
2192         wm5100_micd_irq(wm5100);
2193
2194     ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2195     if (ret < 0) {
2196         dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2197             ret);
2198         irq_val = 0;
2199     }
2200
2201     ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2202               &mask_val);
2203     if (ret < 0) {
2204         dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2205             ret);
2206         mask_val = 0xffff;
2207     }
2208
2209     irq_val &= ~mask_val;
2210
2211     if (irq_val)
2212         status = IRQ_HANDLED;
2213
2214     regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
2215
2216     wm5100_log_status4(wm5100, irq_val);
2217
2218     return status;
2219 }
2220
2221 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2222 {
2223     irqreturn_t ret = IRQ_NONE;
2224     irqreturn_t val;
2225
2226     do {
2227         val = wm5100_irq(irq, data);
2228         if (val != IRQ_NONE)
2229             ret = val;
2230     } while (val != IRQ_NONE);
2231
2232     return ret;
2233 }
2234
2235 #ifdef CONFIG_GPIOLIB
2236 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2237 {
2238     struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2239
2240     regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2241                WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2242 }
2243
2244 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2245                      unsigned offset, int value)
2246 {
2247     struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2248     int val, ret;
2249
2250     val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2251
2252     ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2253                  WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2254                  WM5100_GP1_LVL, val);
2255     if (ret < 0)
2256         return ret;
2257     else
2258         return 0;
2259 }
2260
2261 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2262 {
2263     struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2264     unsigned int reg;
2265     int ret;
2266
2267     ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
2268     if (ret < 0)
2269         return ret;
2270
2271     return (reg & WM5100_GP1_LVL) != 0;
2272 }
2273
2274 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2275 {
2276     struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
2277
2278     return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2279                   WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2280                   (1 << WM5100_GP1_FN_SHIFT) |
2281                   (1 << WM5100_GP1_DIR_SHIFT));
2282 }
2283
2284 static const struct gpio_chip wm5100_template_chip = {
2285     .label          = "wm5100",
2286     .owner          = THIS_MODULE,
2287     .direction_output   = wm5100_gpio_direction_out,
2288     .set            = wm5100_gpio_set,
2289     .direction_input    = wm5100_gpio_direction_in,
2290     .get            = wm5100_gpio_get,
2291     .can_sleep      = 1,
2292 };
2293
2294 static void wm5100_init_gpio(struct i2c_client *i2c)
2295 {
2296     struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2297     int ret;
2298
2299     wm5100->gpio_chip = wm5100_template_chip;
2300     wm5100->gpio_chip.ngpio = 6;
2301     wm5100->gpio_chip.parent = &i2c->dev;
2302
2303     if (wm5100->pdata.gpio_base)
2304         wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2305     else
2306         wm5100->gpio_chip.base = -1;
2307
2308     ret = gpiochip_add_data(&wm5100->gpio_chip, wm5100);
2309     if (ret != 0)
2310         dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
2311 }
2312
2313 static void wm5100_free_gpio(struct i2c_client *i2c)
2314 {
2315     struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2316
2317     gpiochip_remove(&wm5100->gpio_chip);
2318 }
2319 #else
2320 static void wm5100_init_gpio(struct i2c_client *i2c)
2321 {
2322 }
2323
2324 static void wm5100_free_gpio(struct i2c_client *i2c)
2325 {
2326 }
2327 #endif
2328
2329 static int wm5100_probe(struct snd_soc_component *component)
2330 {
2331     struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2332     struct i2c_client *i2c = to_i2c_client(component->dev);
2333     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
2334     int ret, i;
2335
2336     wm5100->component = component;
2337
2338     for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2339         snd_soc_component_update_bits(component, wm5100_dig_vu[i], WM5100_OUT_VU,
2340                     WM5100_OUT_VU);
2341
2342     /* Don't debounce interrupts to support use of SYSCLK only */
2343     snd_soc_component_write(component, WM5100_IRQ_DEBOUNCE_1, 0);
2344     snd_soc_component_write(component, WM5100_IRQ_DEBOUNCE_2, 0);
2345
2346     /* TODO: check if we're symmetric */
2347
2348     if (i2c->irq)
2349         snd_soc_dapm_new_controls(dapm, wm5100_dapm_widgets_noirq,
2350                       ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2351
2352     if (wm5100->pdata.hp_pol) {
2353         ret = gpio_request_one(wm5100->pdata.hp_pol,
2354                        GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2355         if (ret < 0) {
2356             dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2357                 wm5100->pdata.hp_pol, ret);
2358             goto err_gpio;
2359         }
2360     }
2361
2362     return 0;
2363
2364 err_gpio:
2365
2366     return ret;
2367 }
2368
2369 static void wm5100_remove(struct snd_soc_component *component)
2370 {
2371     struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
2372
2373     if (wm5100->pdata.hp_pol) {
2374         gpio_free(wm5100->pdata.hp_pol);
2375     }
2376 }
2377
2378 static const struct snd_soc_component_driver soc_component_dev_wm5100 = {
2379     .probe          = wm5100_probe,
2380     .remove         = wm5100_remove,
2381     .set_sysclk     = wm5100_set_sysclk,
2382     .set_pll        = wm5100_set_fll,
2383     .seq_notifier       = wm5100_seq_notifier,
2384     .controls       = wm5100_snd_controls,
2385     .num_controls       = ARRAY_SIZE(wm5100_snd_controls),
2386     .dapm_widgets       = wm5100_dapm_widgets,
2387     .num_dapm_widgets   = ARRAY_SIZE(wm5100_dapm_widgets),
2388     .dapm_routes        = wm5100_dapm_routes,
2389     .num_dapm_routes    = ARRAY_SIZE(wm5100_dapm_routes),
2390     .use_pmdown_time    = 1,
2391     .endianness     = 1,
2392 };
2393
2394 static const struct regmap_config wm5100_regmap = {
2395     .reg_bits = 16,
2396     .val_bits = 16,
2397
2398     .max_register = WM5100_MAX_REGISTER,
2399     .reg_defaults = wm5100_reg_defaults,
2400     .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2401     .volatile_reg = wm5100_volatile_register,
2402     .readable_reg = wm5100_readable_register,
2403     .cache_type = REGCACHE_RBTREE,
2404 };
2405
2406 static const unsigned int wm5100_mic_ctrl_reg[] = {
2407     WM5100_IN1L_CONTROL,
2408     WM5100_IN2L_CONTROL,
2409     WM5100_IN3L_CONTROL,
2410     WM5100_IN4L_CONTROL,
2411 };
2412
2413 static int wm5100_i2c_probe(struct i2c_client *i2c)
2414 {
2415     struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2416     struct wm5100_priv *wm5100;
2417     unsigned int reg;
2418     int ret, i, irq_flags;
2419
2420     wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2421                   GFP_KERNEL);
2422     if (wm5100 == NULL)
2423         return -ENOMEM;
2424
2425     wm5100->dev = &i2c->dev;
2426
2427     wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
2428     if (IS_ERR(wm5100->regmap)) {
2429         ret = PTR_ERR(wm5100->regmap);
2430         dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2431             ret);
2432         goto err;
2433     }
2434
2435     for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2436         init_completion(&wm5100->fll[i].lock);
2437
2438     if (pdata)
2439         wm5100->pdata = *pdata;
2440
2441     i2c_set_clientdata(i2c, wm5100);
2442
2443     for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2444         wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2445
2446     ret = devm_regulator_bulk_get(&i2c->dev,
2447                       ARRAY_SIZE(wm5100->core_supplies),
2448                       wm5100->core_supplies);
2449     if (ret != 0) {
2450         dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2451             ret);
2452         goto err;
2453     }
2454
2455     ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2456                     wm5100->core_supplies);
2457     if (ret != 0) {
2458         dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2459             ret);
2460         goto err;
2461     }
2462
2463     if (wm5100->pdata.ldo_ena) {
2464         ret = gpio_request_one(wm5100->pdata.ldo_ena,
2465                        GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2466         if (ret < 0) {
2467             dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2468                 wm5100->pdata.ldo_ena, ret);
2469             goto err_enable;
2470         }
2471         msleep(2);
2472     }
2473
2474     if (wm5100->pdata.reset) {
2475         ret = gpio_request_one(wm5100->pdata.reset,
2476                        GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2477         if (ret < 0) {
2478             dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2479                 wm5100->pdata.reset, ret);
2480             goto err_ldo;
2481         }
2482     }
2483
2484     ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2485     if (ret < 0) {
2486         dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2487         goto err_reset;
2488     }
2489     switch (reg) {
2490     case 0x8997:
2491     case 0x5100:
2492         break;
2493
2494     default:
2495         dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2496         ret = -EINVAL;
2497         goto err_reset;
2498     }
2499
2500     ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2501     if (ret < 0) {
2502         dev_err(&i2c->dev, "Failed to read revision register\n");
2503         goto err_reset;
2504     }
2505     wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2506
2507     dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2508
2509     ret = wm5100_reset(wm5100);
2510     if (ret < 0) {
2511         dev_err(&i2c->dev, "Failed to issue reset\n");
2512         goto err_reset;
2513     }
2514
2515     switch (wm5100->rev) {
2516     case 0:
2517         ret = regmap_register_patch(wm5100->regmap,
2518                         wm5100_reva_patches,
2519                         ARRAY_SIZE(wm5100_reva_patches));
2520         if (ret != 0) {
2521             dev_err(&i2c->dev, "Failed to register patches: %d\n",
2522                 ret);
2523             goto err_reset;
2524         }
2525         break;
2526     default:
2527         break;
2528     }
2529
2530
2531     wm5100_init_gpio(i2c);
2532
2533     for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2534         if (!wm5100->pdata.gpio_defaults[i])
2535             continue;
2536
2537         regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2538                  wm5100->pdata.gpio_defaults[i]);
2539     }
2540
2541     for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2542         regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
2543                    WM5100_IN1_MODE_MASK |
2544                    WM5100_IN1_DMIC_SUP_MASK,
2545                    (wm5100->pdata.in_mode[i] <<
2546                     WM5100_IN1_MODE_SHIFT) |
2547                    (wm5100->pdata.dmic_sup[i] <<
2548                     WM5100_IN1_DMIC_SUP_SHIFT));
2549     }
2550
2551     if (i2c->irq) {
2552         if (wm5100->pdata.irq_flags)
2553             irq_flags = wm5100->pdata.irq_flags;
2554         else
2555             irq_flags = IRQF_TRIGGER_LOW;
2556
2557         irq_flags |= IRQF_ONESHOT;
2558
2559         if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2560             ret = request_threaded_irq(i2c->irq, NULL,
2561                            wm5100_edge_irq, irq_flags,
2562                            "wm5100", wm5100);
2563         else
2564             ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2565                            irq_flags, "wm5100",
2566                            wm5100);
2567
2568         if (ret != 0) {
2569             dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2570                 i2c->irq, ret);
2571         } else {
2572             /* Enable default interrupts */
2573             regmap_update_bits(wm5100->regmap,
2574                        WM5100_INTERRUPT_STATUS_3_MASK,
2575                        WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2576                        WM5100_IM_SPK_SHUTDOWN_EINT |
2577                        WM5100_IM_ASRC2_LOCK_EINT |
2578                        WM5100_IM_ASRC1_LOCK_EINT |
2579                        WM5100_IM_FLL2_LOCK_EINT |
2580                        WM5100_IM_FLL1_LOCK_EINT |
2581                        WM5100_CLKGEN_ERR_EINT |
2582                        WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2583
2584             regmap_update_bits(wm5100->regmap,
2585                        WM5100_INTERRUPT_STATUS_4_MASK,
2586                        WM5100_AIF3_ERR_EINT |
2587                        WM5100_AIF2_ERR_EINT |
2588                        WM5100_AIF1_ERR_EINT |
2589                        WM5100_CTRLIF_ERR_EINT |
2590                        WM5100_ISRC2_UNDERCLOCKED_EINT |
2591                        WM5100_ISRC1_UNDERCLOCKED_EINT |
2592                        WM5100_FX_UNDERCLOCKED_EINT |
2593                        WM5100_AIF3_UNDERCLOCKED_EINT |
2594                        WM5100_AIF2_UNDERCLOCKED_EINT |
2595                        WM5100_AIF1_UNDERCLOCKED_EINT |
2596                        WM5100_ASRC_UNDERCLOCKED_EINT |
2597                        WM5100_DAC_UNDERCLOCKED_EINT |
2598                        WM5100_ADC_UNDERCLOCKED_EINT |
2599                        WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2600         }
2601     }
2602
2603     pm_runtime_set_active(&i2c->dev);
2604     pm_runtime_enable(&i2c->dev);
2605     pm_request_idle(&i2c->dev);
2606
2607     ret = devm_snd_soc_register_component(&i2c->dev,
2608                      &soc_component_dev_wm5100, wm5100_dai,
2609                      ARRAY_SIZE(wm5100_dai));
2610     if (ret < 0) {
2611         dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2612         goto err_reset;
2613     }
2614
2615     return ret;
2616
2617 err_reset:
2618     pm_runtime_disable(&i2c->dev);
2619     if (i2c->irq)
2620         free_irq(i2c->irq, wm5100);
2621     wm5100_free_gpio(i2c);
2622     if (wm5100->pdata.reset) {
2623         gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2624         gpio_free(wm5100->pdata.reset);
2625     }
2626 err_ldo:
2627     if (wm5100->pdata.ldo_ena) {
2628         gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2629         gpio_free(wm5100->pdata.ldo_ena);
2630     }
2631 err_enable:
2632     regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2633                    wm5100->core_supplies);
2634 err:
2635     return ret;
2636 }
2637
2638 static int wm5100_i2c_remove(struct i2c_client *i2c)
2639 {
2640     struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2641
2642     pm_runtime_disable(&i2c->dev);
2643     if (i2c->irq)
2644         free_irq(i2c->irq, wm5100);
2645     wm5100_free_gpio(i2c);
2646     if (wm5100->pdata.reset) {
2647         gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2648         gpio_free(wm5100->pdata.reset);
2649     }
2650     if (wm5100->pdata.ldo_ena) {
2651         gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2652         gpio_free(wm5100->pdata.ldo_ena);
2653     }
2654
2655     return 0;
2656 }
2657
2658 #ifdef CONFIG_PM
2659 static int wm5100_runtime_suspend(struct device *dev)
2660 {
2661     struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2662
2663     regcache_cache_only(wm5100->regmap, true);
2664     regcache_mark_dirty(wm5100->regmap);
2665     if (wm5100->pdata.ldo_ena)
2666         gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2667     regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2668                    wm5100->core_supplies);
2669
2670     return 0;
2671 }
2672
2673 static int wm5100_runtime_resume(struct device *dev)
2674 {
2675     struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2676     int ret;
2677
2678     ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2679                     wm5100->core_supplies);
2680     if (ret != 0) {
2681         dev_err(dev, "Failed to enable supplies: %d\n",
2682             ret);
2683         return ret;
2684     }
2685
2686     if (wm5100->pdata.ldo_ena) {
2687         gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
2688         msleep(2);
2689     }
2690
2691     regcache_cache_only(wm5100->regmap, false);
2692     regcache_sync(wm5100->regmap);
2693
2694     return 0;
2695 }
2696 #endif
2697
2698 static const struct dev_pm_ops wm5100_pm = {
2699     SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2700                NULL)
2701 };
2702
2703 static const struct i2c_device_id wm5100_i2c_id[] = {
2704     { "wm5100", 0 },
2705     { }
2706 };
2707 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2708
2709 static struct i2c_driver wm5100_i2c_driver = {
2710     .driver = {
2711         .name = "wm5100",
2712         .pm = &wm5100_pm,
2713     },
2714     .probe_new = wm5100_i2c_probe,
2715     .remove =   wm5100_i2c_remove,
2716     .id_table = wm5100_i2c_id,
2717 };
2718
2719 module_i2c_driver(wm5100_i2c_driver);
2720
2721 MODULE_DESCRIPTION("ASoC WM5100 driver");
2722 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2723 MODULE_LICENSE("GPL");