soc/codecs/wm0010.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * wm0010.c  --  WM0010 DSP Driver
0004  *
0005  * Copyright 2012 Wolfson Microelectronics PLC.
0006  *
0007  * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  *          Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
0009  *          Scott Ling <sl@opensource.wolfsonmicro.com>
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/moduleparam.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/irqreturn.h>
0016 #include <linux/init.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/firmware.h>
0019 #include <linux/delay.h>
0020 #include <linux/fs.h>
0021 #include <linux/gpio.h>
0022 #include <linux/regulator/consumer.h>
0023 #include <linux/mutex.h>
0024 #include <linux/workqueue.h>
0025
0026 #include <sound/soc.h>
0027 #include <sound/wm0010.h>
0028
0029 #define DEVICE_ID_WM0010    10
0030
0031 /* We only support v1 of the .dfw INFO record */
0032 #define INFO_VERSION        1
0033
0034 enum dfw_cmd {
0035     DFW_CMD_FUSE = 0x01,
0036     DFW_CMD_CODE_HDR,
0037     DFW_CMD_CODE_DATA,
0038     DFW_CMD_PLL,
0039     DFW_CMD_INFO = 0xff
0040 };
0041
0042 struct dfw_binrec {
0043     u8 command;
0044     u32 length:24;
0045     u32 address;
0046     uint8_t data[];
0047 } __packed;
0048
0049 struct dfw_inforec {
0050     u8 info_version;
0051     u8 tool_major_version;
0052     u8 tool_minor_version;
0053     u8 dsp_target;
0054 };
0055
0056 struct dfw_pllrec {
0057     u8 command;
0058     u32 length:24;
0059     u32 address;
0060     u32 clkctrl1;
0061     u32 clkctrl2;
0062     u32 clkctrl3;
0063     u32 ldetctrl;
0064     u32 uart_div;
0065     u32 spi_div;
0066 } __packed;
0067
0068 static struct pll_clock_map {
0069     int max_sysclk;
0070     int max_pll_spi_speed;
0071     u32 pll_clkctrl1;
0072 } pll_clock_map[] = {              /* Dividers */
0073     { 22000000, 26000000, 0x00201f11 }, /* 2,32,2  */
0074     { 18000000, 26000000, 0x00203f21 }, /* 2,64,4  */
0075     { 14000000, 26000000, 0x00202620 }, /* 1,39,4  */
0076     { 10000000, 22000000, 0x00203120 }, /* 1,50,4  */
0077     {  6500000, 22000000, 0x00204520 }, /* 1,70,4  */
0078     {  5500000, 22000000, 0x00103f10 }, /* 1,64,2  */
0079 };
0080
0081 enum wm0010_state {
0082     WM0010_POWER_OFF,
0083     WM0010_OUT_OF_RESET,
0084     WM0010_BOOTROM,
0085     WM0010_STAGE2,
0086     WM0010_FIRMWARE,
0087 };
0088
0089 struct wm0010_priv {
0090     struct snd_soc_component *component;
0091
0092     struct mutex lock;
0093     struct device *dev;
0094
0095     struct wm0010_pdata pdata;
0096
0097     int gpio_reset;
0098     int gpio_reset_value;
0099
0100     struct regulator_bulk_data core_supplies[2];
0101     struct regulator *dbvdd;
0102
0103     int sysclk;
0104
0105     enum wm0010_state state;
0106     bool boot_failed;
0107     bool ready;
0108     bool pll_running;
0109     int max_spi_freq;
0110     int board_max_spi_speed;
0111     u32 pll_clkctrl1;
0112
0113     spinlock_t irq_lock;
0114     int irq;
0115
0116     struct completion boot_completion;
0117 };
0118
0119 struct wm0010_spi_msg {
0120     struct spi_message m;
0121     struct spi_transfer t;
0122     u8 *tx_buf;
0123     u8 *rx_buf;
0124     size_t len;
0125 };
0126
0127 static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
0128 SND_SOC_DAPM_SUPPLY("CLKIN",  SND_SOC_NOPM, 0, 0, NULL, 0),
0129 };
0130
0131 static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
0132     { "SDI2 Capture", NULL, "SDI1 Playback" },
0133     { "SDI1 Capture", NULL, "SDI2 Playback" },
0134
0135     { "SDI1 Capture", NULL, "CLKIN" },
0136     { "SDI2 Capture", NULL, "CLKIN" },
0137     { "SDI1 Playback", NULL, "CLKIN" },
0138     { "SDI2 Playback", NULL, "CLKIN" },
0139 };
0140
0141 static const char *wm0010_state_to_str(enum wm0010_state state)
0142 {
0143     static const char * const state_to_str[] = {
0144         "Power off",
0145         "Out of reset",
0146         "Boot ROM",
0147         "Stage2",
0148         "Firmware"
0149     };
0150
0151     if (state < 0 || state >= ARRAY_SIZE(state_to_str))
0152         return "null";
0153     return state_to_str[state];
0154 }
0155
0156 /* Called with wm0010->lock held */
0157 static void wm0010_halt(struct snd_soc_component *component)
0158 {
0159     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0160     unsigned long flags;
0161     enum wm0010_state state;
0162
0163     /* Fetch the wm0010 state */
0164     spin_lock_irqsave(&wm0010->irq_lock, flags);
0165     state = wm0010->state;
0166     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0167
0168     switch (state) {
0169     case WM0010_POWER_OFF:
0170         /* If there's nothing to do, bail out */
0171         return;
0172     case WM0010_OUT_OF_RESET:
0173     case WM0010_BOOTROM:
0174     case WM0010_STAGE2:
0175     case WM0010_FIRMWARE:
0176         /* Remember to put chip back into reset */
0177         gpio_set_value_cansleep(wm0010->gpio_reset,
0178                     wm0010->gpio_reset_value);
0179         /* Disable the regulators */
0180         regulator_disable(wm0010->dbvdd);
0181         regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
0182                        wm0010->core_supplies);
0183         break;
0184     }
0185
0186     spin_lock_irqsave(&wm0010->irq_lock, flags);
0187     wm0010->state = WM0010_POWER_OFF;
0188     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0189 }
0190
0191 struct wm0010_boot_xfer {
0192     struct list_head list;
0193     struct snd_soc_component *component;
0194     struct completion *done;
0195     struct spi_message m;
0196     struct spi_transfer t;
0197 };
0198
0199 /* Called with wm0010->lock held */
0200 static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
0201 {
0202     enum wm0010_state state;
0203     unsigned long flags;
0204
0205     spin_lock_irqsave(&wm0010->irq_lock, flags);
0206     state = wm0010->state;
0207     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0208
0209     dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
0210         wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
0211
0212     wm0010->boot_failed = true;
0213 }
0214
0215 static void wm0010_boot_xfer_complete(void *data)
0216 {
0217     struct wm0010_boot_xfer *xfer = data;
0218     struct snd_soc_component *component = xfer->component;
0219     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0220     u32 *out32 = xfer->t.rx_buf;
0221     int i;
0222
0223     if (xfer->m.status != 0) {
0224         dev_err(component->dev, "SPI transfer failed: %d\n",
0225             xfer->m.status);
0226         wm0010_mark_boot_failure(wm0010);
0227         if (xfer->done)
0228             complete(xfer->done);
0229         return;
0230     }
0231
0232     for (i = 0; i < xfer->t.len / 4; i++) {
0233         dev_dbg(component->dev, "%d: %04x\n", i, out32[i]);
0234
0235         switch (be32_to_cpu(out32[i])) {
0236         case 0xe0e0e0e0:
0237             dev_err(component->dev,
0238                 "%d: ROM error reported in stage 2\n", i);
0239             wm0010_mark_boot_failure(wm0010);
0240             break;
0241
0242         case 0x55555555:
0243             if (wm0010->state < WM0010_STAGE2)
0244                 break;
0245             dev_err(component->dev,
0246                 "%d: ROM bootloader running in stage 2\n", i);
0247             wm0010_mark_boot_failure(wm0010);
0248             break;
0249
0250         case 0x0fed0000:
0251             dev_dbg(component->dev, "Stage2 loader running\n");
0252             break;
0253
0254         case 0x0fed0007:
0255             dev_dbg(component->dev, "CODE_HDR packet received\n");
0256             break;
0257
0258         case 0x0fed0008:
0259             dev_dbg(component->dev, "CODE_DATA packet received\n");
0260             break;
0261
0262         case 0x0fed0009:
0263             dev_dbg(component->dev, "Download complete\n");
0264             break;
0265
0266         case 0x0fed000c:
0267             dev_dbg(component->dev, "Application start\n");
0268             break;
0269
0270         case 0x0fed000e:
0271             dev_dbg(component->dev, "PLL packet received\n");
0272             wm0010->pll_running = true;
0273             break;
0274
0275         case 0x0fed0025:
0276             dev_err(component->dev, "Device reports image too long\n");
0277             wm0010_mark_boot_failure(wm0010);
0278             break;
0279
0280         case 0x0fed002c:
0281             dev_err(component->dev, "Device reports bad SPI packet\n");
0282             wm0010_mark_boot_failure(wm0010);
0283             break;
0284
0285         case 0x0fed0031:
0286             dev_err(component->dev, "Device reports SPI read overflow\n");
0287             wm0010_mark_boot_failure(wm0010);
0288             break;
0289
0290         case 0x0fed0032:
0291             dev_err(component->dev, "Device reports SPI underclock\n");
0292             wm0010_mark_boot_failure(wm0010);
0293             break;
0294
0295         case 0x0fed0033:
0296             dev_err(component->dev, "Device reports bad header packet\n");
0297             wm0010_mark_boot_failure(wm0010);
0298             break;
0299
0300         case 0x0fed0034:
0301             dev_err(component->dev, "Device reports invalid packet type\n");
0302             wm0010_mark_boot_failure(wm0010);
0303             break;
0304
0305         case 0x0fed0035:
0306             dev_err(component->dev, "Device reports data before header error\n");
0307             wm0010_mark_boot_failure(wm0010);
0308             break;
0309
0310         case 0x0fed0038:
0311             dev_err(component->dev, "Device reports invalid PLL packet\n");
0312             break;
0313
0314         case 0x0fed003a:
0315             dev_err(component->dev, "Device reports packet alignment error\n");
0316             wm0010_mark_boot_failure(wm0010);
0317             break;
0318
0319         default:
0320             dev_err(component->dev, "Unrecognised return 0x%x\n",
0321                 be32_to_cpu(out32[i]));
0322             wm0010_mark_boot_failure(wm0010);
0323             break;
0324         }
0325
0326         if (wm0010->boot_failed)
0327             break;
0328     }
0329
0330     if (xfer->done)
0331         complete(xfer->done);
0332 }
0333
0334 static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
0335 {
0336     int i;
0337
0338     for (i = 0; i < len / 8; i++)
0339         data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
0340 }
0341
0342 static int wm0010_firmware_load(const char *name, struct snd_soc_component *component)
0343 {
0344     struct spi_device *spi = to_spi_device(component->dev);
0345     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0346     struct list_head xfer_list;
0347     struct wm0010_boot_xfer *xfer;
0348     int ret;
0349     DECLARE_COMPLETION_ONSTACK(done);
0350     const struct firmware *fw;
0351     const struct dfw_binrec *rec;
0352     const struct dfw_inforec *inforec;
0353     u64 *img;
0354     u8 *out, dsp;
0355     u32 len, offset;
0356
0357     INIT_LIST_HEAD(&xfer_list);
0358
0359     ret = request_firmware(&fw, name, component->dev);
0360     if (ret != 0) {
0361         dev_err(component->dev, "Failed to request application(%s): %d\n",
0362             name, ret);
0363         return ret;
0364     }
0365
0366     rec = (const struct dfw_binrec *)fw->data;
0367     inforec = (const struct dfw_inforec *)rec->data;
0368     offset = 0;
0369     dsp = inforec->dsp_target;
0370     wm0010->boot_failed = false;
0371     if (WARN_ON(!list_empty(&xfer_list)))
0372         return -EINVAL;
0373
0374     /* First record should be INFO */
0375     if (rec->command != DFW_CMD_INFO) {
0376         dev_err(component->dev, "First record not INFO\r\n");
0377         ret = -EINVAL;
0378         goto abort;
0379     }
0380
0381     if (inforec->info_version != INFO_VERSION) {
0382         dev_err(component->dev,
0383             "Unsupported version (%02d) of INFO record\r\n",
0384             inforec->info_version);
0385         ret = -EINVAL;
0386         goto abort;
0387     }
0388
0389     dev_dbg(component->dev, "Version v%02d INFO record found\r\n",
0390         inforec->info_version);
0391
0392     /* Check it's a DSP file */
0393     if (dsp != DEVICE_ID_WM0010) {
0394         dev_err(component->dev, "Not a WM0010 firmware file.\r\n");
0395         ret = -EINVAL;
0396         goto abort;
0397     }
0398
0399     /* Skip the info record as we don't need to send it */
0400     offset += ((rec->length) + 8);
0401     rec = (void *)&rec->data[rec->length];
0402
0403     while (offset < fw->size) {
0404         dev_dbg(component->dev,
0405             "Packet: command %d, data length = 0x%x\r\n",
0406             rec->command, rec->length);
0407         len = rec->length + 8;
0408
0409         xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
0410         if (!xfer) {
0411             ret = -ENOMEM;
0412             goto abort;
0413         }
0414
0415         xfer->component = component;
0416         list_add_tail(&xfer->list, &xfer_list);
0417
0418         out = kzalloc(len, GFP_KERNEL | GFP_DMA);
0419         if (!out) {
0420             ret = -ENOMEM;
0421             goto abort1;
0422         }
0423         xfer->t.rx_buf = out;
0424
0425         img = kzalloc(len, GFP_KERNEL | GFP_DMA);
0426         if (!img) {
0427             ret = -ENOMEM;
0428             goto abort1;
0429         }
0430         xfer->t.tx_buf = img;
0431
0432         byte_swap_64((u64 *)&rec->command, img, len);
0433
0434         spi_message_init(&xfer->m);
0435         xfer->m.complete = wm0010_boot_xfer_complete;
0436         xfer->m.context = xfer;
0437         xfer->t.len = len;
0438         xfer->t.bits_per_word = 8;
0439
0440         if (!wm0010->pll_running) {
0441             xfer->t.speed_hz = wm0010->sysclk / 6;
0442         } else {
0443             xfer->t.speed_hz = wm0010->max_spi_freq;
0444
0445             if (wm0010->board_max_spi_speed &&
0446                (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
0447                     xfer->t.speed_hz = wm0010->board_max_spi_speed;
0448         }
0449
0450         /* Store max usable spi frequency for later use */
0451         wm0010->max_spi_freq = xfer->t.speed_hz;
0452
0453         spi_message_add_tail(&xfer->t, &xfer->m);
0454
0455         offset += ((rec->length) + 8);
0456         rec = (void *)&rec->data[rec->length];
0457
0458         if (offset >= fw->size) {
0459             dev_dbg(component->dev, "All transfers scheduled\n");
0460             xfer->done = &done;
0461         }
0462
0463         ret = spi_async(spi, &xfer->m);
0464         if (ret != 0) {
0465             dev_err(component->dev, "Write failed: %d\n", ret);
0466             goto abort1;
0467         }
0468
0469         if (wm0010->boot_failed) {
0470             dev_dbg(component->dev, "Boot fail!\n");
0471             ret = -EINVAL;
0472             goto abort1;
0473         }
0474     }
0475
0476     wait_for_completion(&done);
0477
0478     ret = 0;
0479
0480 abort1:
0481     while (!list_empty(&xfer_list)) {
0482         xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
0483                     list);
0484         kfree(xfer->t.rx_buf);
0485         kfree(xfer->t.tx_buf);
0486         list_del(&xfer->list);
0487         kfree(xfer);
0488     }
0489
0490 abort:
0491     release_firmware(fw);
0492     return ret;
0493 }
0494
0495 static int wm0010_stage2_load(struct snd_soc_component *component)
0496 {
0497     struct spi_device *spi = to_spi_device(component->dev);
0498     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0499     const struct firmware *fw;
0500     struct spi_message m;
0501     struct spi_transfer t;
0502     u32 *img;
0503     u8 *out;
0504     int i;
0505     int ret = 0;
0506
0507     ret = request_firmware(&fw, "wm0010_stage2.bin", component->dev);
0508     if (ret != 0) {
0509         dev_err(component->dev, "Failed to request stage2 loader: %d\n",
0510             ret);
0511         return ret;
0512     }
0513
0514     dev_dbg(component->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
0515
0516     /* Copy to local buffer first as vmalloc causes problems for dma */
0517     img = kmemdup(&fw->data[0], fw->size, GFP_KERNEL | GFP_DMA);
0518     if (!img) {
0519         ret = -ENOMEM;
0520         goto abort2;
0521     }
0522
0523     out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
0524     if (!out) {
0525         ret = -ENOMEM;
0526         goto abort1;
0527     }
0528
0529     spi_message_init(&m);
0530     memset(&t, 0, sizeof(t));
0531     t.rx_buf = out;
0532     t.tx_buf = img;
0533     t.len = fw->size;
0534     t.bits_per_word = 8;
0535     t.speed_hz = wm0010->sysclk / 10;
0536     spi_message_add_tail(&t, &m);
0537
0538     dev_dbg(component->dev, "Starting initial download at %dHz\n",
0539         t.speed_hz);
0540
0541     ret = spi_sync(spi, &m);
0542     if (ret != 0) {
0543         dev_err(component->dev, "Initial download failed: %d\n", ret);
0544         goto abort;
0545     }
0546
0547     /* Look for errors from the boot ROM */
0548     for (i = 0; i < fw->size; i++) {
0549         if (out[i] != 0x55) {
0550             dev_err(component->dev, "Boot ROM error: %x in %d\n",
0551                 out[i], i);
0552             wm0010_mark_boot_failure(wm0010);
0553             ret = -EBUSY;
0554             goto abort;
0555         }
0556     }
0557 abort:
0558     kfree(out);
0559 abort1:
0560     kfree(img);
0561 abort2:
0562     release_firmware(fw);
0563
0564     return ret;
0565 }
0566
0567 static int wm0010_boot(struct snd_soc_component *component)
0568 {
0569     struct spi_device *spi = to_spi_device(component->dev);
0570     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0571     unsigned long flags;
0572     int ret;
0573     struct spi_message m;
0574     struct spi_transfer t;
0575     struct dfw_pllrec pll_rec;
0576     u32 *p, len;
0577     u64 *img_swap;
0578     u8 *out;
0579     int i;
0580
0581     spin_lock_irqsave(&wm0010->irq_lock, flags);
0582     if (wm0010->state != WM0010_POWER_OFF)
0583         dev_warn(wm0010->dev, "DSP already powered up!\n");
0584     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0585
0586     if (wm0010->sysclk > 26000000) {
0587         dev_err(component->dev, "Max DSP clock frequency is 26MHz\n");
0588         ret = -ECANCELED;
0589         goto err;
0590     }
0591
0592     mutex_lock(&wm0010->lock);
0593     wm0010->pll_running = false;
0594
0595     dev_dbg(component->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
0596
0597     ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
0598                     wm0010->core_supplies);
0599     if (ret != 0) {
0600         dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
0601             ret);
0602         mutex_unlock(&wm0010->lock);
0603         goto err;
0604     }
0605
0606     ret = regulator_enable(wm0010->dbvdd);
0607     if (ret != 0) {
0608         dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
0609         goto err_core;
0610     }
0611
0612     /* Release reset */
0613     gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
0614     spin_lock_irqsave(&wm0010->irq_lock, flags);
0615     wm0010->state = WM0010_OUT_OF_RESET;
0616     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0617
0618     if (!wait_for_completion_timeout(&wm0010->boot_completion,
0619                      msecs_to_jiffies(20)))
0620         dev_err(component->dev, "Failed to get interrupt from DSP\n");
0621
0622     spin_lock_irqsave(&wm0010->irq_lock, flags);
0623     wm0010->state = WM0010_BOOTROM;
0624     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0625
0626     ret = wm0010_stage2_load(component);
0627     if (ret)
0628         goto abort;
0629
0630     if (!wait_for_completion_timeout(&wm0010->boot_completion,
0631                      msecs_to_jiffies(20)))
0632         dev_err(component->dev, "Failed to get interrupt from DSP loader.\n");
0633
0634     spin_lock_irqsave(&wm0010->irq_lock, flags);
0635     wm0010->state = WM0010_STAGE2;
0636     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0637
0638     /* Only initialise PLL if max_spi_freq initialised */
0639     if (wm0010->max_spi_freq) {
0640
0641         /* Initialise a PLL record */
0642         memset(&pll_rec, 0, sizeof(pll_rec));
0643         pll_rec.command = DFW_CMD_PLL;
0644         pll_rec.length = (sizeof(pll_rec) - 8);
0645
0646         /* On wm0010 only the CLKCTRL1 value is used */
0647         pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
0648
0649         ret = -ENOMEM;
0650         len = pll_rec.length + 8;
0651         out = kzalloc(len, GFP_KERNEL | GFP_DMA);
0652         if (!out)
0653             goto abort;
0654
0655         img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
0656         if (!img_swap)
0657             goto abort_out;
0658
0659         /* We need to re-order for 0010 */
0660         byte_swap_64((u64 *)&pll_rec, img_swap, len);
0661
0662         spi_message_init(&m);
0663         memset(&t, 0, sizeof(t));
0664         t.rx_buf = out;
0665         t.tx_buf = img_swap;
0666         t.len = len;
0667         t.bits_per_word = 8;
0668         t.speed_hz = wm0010->sysclk / 6;
0669         spi_message_add_tail(&t, &m);
0670
0671         ret = spi_sync(spi, &m);
0672         if (ret) {
0673             dev_err(component->dev, "First PLL write failed: %d\n", ret);
0674             goto abort_swap;
0675         }
0676
0677         /* Use a second send of the message to get the return status */
0678         ret = spi_sync(spi, &m);
0679         if (ret) {
0680             dev_err(component->dev, "Second PLL write failed: %d\n", ret);
0681             goto abort_swap;
0682         }
0683
0684         p = (u32 *)out;
0685
0686         /* Look for PLL active code from the DSP */
0687         for (i = 0; i < len / 4; i++) {
0688             if (*p == 0x0e00ed0f) {
0689                 dev_dbg(component->dev, "PLL packet received\n");
0690                 wm0010->pll_running = true;
0691                 break;
0692             }
0693             p++;
0694         }
0695
0696         kfree(img_swap);
0697         kfree(out);
0698     } else
0699         dev_dbg(component->dev, "Not enabling DSP PLL.");
0700
0701     ret = wm0010_firmware_load("wm0010.dfw", component);
0702
0703     if (ret != 0)
0704         goto abort;
0705
0706     spin_lock_irqsave(&wm0010->irq_lock, flags);
0707     wm0010->state = WM0010_FIRMWARE;
0708     spin_unlock_irqrestore(&wm0010->irq_lock, flags);
0709
0710     mutex_unlock(&wm0010->lock);
0711
0712     return 0;
0713
0714 abort_swap:
0715     kfree(img_swap);
0716 abort_out:
0717     kfree(out);
0718 abort:
0719     /* Put the chip back into reset */
0720     wm0010_halt(component);
0721     mutex_unlock(&wm0010->lock);
0722     return ret;
0723
0724 err_core:
0725     mutex_unlock(&wm0010->lock);
0726     regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
0727                    wm0010->core_supplies);
0728 err:
0729     return ret;
0730 }
0731
0732 static int wm0010_set_bias_level(struct snd_soc_component *component,
0733                  enum snd_soc_bias_level level)
0734 {
0735     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0736
0737     switch (level) {
0738     case SND_SOC_BIAS_ON:
0739         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
0740             wm0010_boot(component);
0741         break;
0742     case SND_SOC_BIAS_PREPARE:
0743         break;
0744     case SND_SOC_BIAS_STANDBY:
0745         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {
0746             mutex_lock(&wm0010->lock);
0747             wm0010_halt(component);
0748             mutex_unlock(&wm0010->lock);
0749         }
0750         break;
0751     case SND_SOC_BIAS_OFF:
0752         break;
0753     }
0754
0755     return 0;
0756 }
0757
0758 static int wm0010_set_sysclk(struct snd_soc_component *component, int source,
0759                  int clk_id, unsigned int freq, int dir)
0760 {
0761     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0762     unsigned int i;
0763
0764     wm0010->sysclk = freq;
0765
0766     if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
0767         wm0010->max_spi_freq = 0;
0768     } else {
0769         for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
0770             if (freq >= pll_clock_map[i].max_sysclk) {
0771                 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
0772                 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
0773                 break;
0774             }
0775     }
0776
0777     return 0;
0778 }
0779
0780 static int wm0010_probe(struct snd_soc_component *component);
0781
0782 static const struct snd_soc_component_driver soc_component_dev_wm0010 = {
0783     .probe          = wm0010_probe,
0784     .set_bias_level     = wm0010_set_bias_level,
0785     .set_sysclk     = wm0010_set_sysclk,
0786     .dapm_widgets       = wm0010_dapm_widgets,
0787     .num_dapm_widgets   = ARRAY_SIZE(wm0010_dapm_widgets),
0788     .dapm_routes        = wm0010_dapm_routes,
0789     .num_dapm_routes    = ARRAY_SIZE(wm0010_dapm_routes),
0790     .use_pmdown_time    = 1,
0791     .endianness     = 1,
0792 };
0793
0794 #define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
0795 #define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
0796             SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
0797             SNDRV_PCM_FMTBIT_S32_LE)
0798
0799 static struct snd_soc_dai_driver wm0010_dai[] = {
0800     {
0801         .name = "wm0010-sdi1",
0802         .playback = {
0803             .stream_name = "SDI1 Playback",
0804             .channels_min = 1,
0805             .channels_max = 2,
0806             .rates = WM0010_RATES,
0807             .formats = WM0010_FORMATS,
0808         },
0809         .capture = {
0810              .stream_name = "SDI1 Capture",
0811              .channels_min = 1,
0812              .channels_max = 2,
0813              .rates = WM0010_RATES,
0814              .formats = WM0010_FORMATS,
0815          },
0816     },
0817     {
0818         .name = "wm0010-sdi2",
0819         .playback = {
0820             .stream_name = "SDI2 Playback",
0821             .channels_min = 1,
0822             .channels_max = 2,
0823             .rates = WM0010_RATES,
0824             .formats = WM0010_FORMATS,
0825         },
0826         .capture = {
0827              .stream_name = "SDI2 Capture",
0828              .channels_min = 1,
0829              .channels_max = 2,
0830              .rates = WM0010_RATES,
0831              .formats = WM0010_FORMATS,
0832          },
0833     },
0834 };
0835
0836 static irqreturn_t wm0010_irq(int irq, void *data)
0837 {
0838     struct wm0010_priv *wm0010 = data;
0839
0840     switch (wm0010->state) {
0841     case WM0010_OUT_OF_RESET:
0842     case WM0010_BOOTROM:
0843     case WM0010_STAGE2:
0844         spin_lock(&wm0010->irq_lock);
0845         complete(&wm0010->boot_completion);
0846         spin_unlock(&wm0010->irq_lock);
0847         return IRQ_HANDLED;
0848     default:
0849         return IRQ_NONE;
0850     }
0851
0852     return IRQ_NONE;
0853 }
0854
0855 static int wm0010_probe(struct snd_soc_component *component)
0856 {
0857     struct wm0010_priv *wm0010 = snd_soc_component_get_drvdata(component);
0858
0859     wm0010->component = component;
0860
0861     return 0;
0862 }
0863
0864 static int wm0010_spi_probe(struct spi_device *spi)
0865 {
0866     unsigned long gpio_flags;
0867     int ret;
0868     int trigger;
0869     int irq;
0870     struct wm0010_priv *wm0010;
0871
0872     wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
0873                   GFP_KERNEL);
0874     if (!wm0010)
0875         return -ENOMEM;
0876
0877     mutex_init(&wm0010->lock);
0878     spin_lock_init(&wm0010->irq_lock);
0879
0880     spi_set_drvdata(spi, wm0010);
0881     wm0010->dev = &spi->dev;
0882
0883     if (dev_get_platdata(&spi->dev))
0884         memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
0885                sizeof(wm0010->pdata));
0886
0887     init_completion(&wm0010->boot_completion);
0888
0889     wm0010->core_supplies[0].supply = "AVDD";
0890     wm0010->core_supplies[1].supply = "DCVDD";
0891     ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
0892                       wm0010->core_supplies);
0893     if (ret != 0) {
0894         dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
0895             ret);
0896         return ret;
0897     }
0898
0899     wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
0900     if (IS_ERR(wm0010->dbvdd)) {
0901         ret = PTR_ERR(wm0010->dbvdd);
0902         dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
0903         return ret;
0904     }
0905
0906     if (wm0010->pdata.gpio_reset) {
0907         wm0010->gpio_reset = wm0010->pdata.gpio_reset;
0908
0909         if (wm0010->pdata.reset_active_high)
0910             wm0010->gpio_reset_value = 1;
0911         else
0912             wm0010->gpio_reset_value = 0;
0913
0914         if (wm0010->gpio_reset_value)
0915             gpio_flags = GPIOF_OUT_INIT_HIGH;
0916         else
0917             gpio_flags = GPIOF_OUT_INIT_LOW;
0918
0919         ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
0920                         gpio_flags, "wm0010 reset");
0921         if (ret < 0) {
0922             dev_err(wm0010->dev,
0923                 "Failed to request GPIO for DSP reset: %d\n",
0924                 ret);
0925             return ret;
0926         }
0927     } else {
0928         dev_err(wm0010->dev, "No reset GPIO configured\n");
0929         return -EINVAL;
0930     }
0931
0932     wm0010->state = WM0010_POWER_OFF;
0933
0934     irq = spi->irq;
0935     if (wm0010->pdata.irq_flags)
0936         trigger = wm0010->pdata.irq_flags;
0937     else
0938         trigger = IRQF_TRIGGER_FALLING;
0939     trigger |= IRQF_ONESHOT;
0940
0941     ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
0942                    "wm0010", wm0010);
0943     if (ret) {
0944         dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
0945             irq, ret);
0946         return ret;
0947     }
0948     wm0010->irq = irq;
0949
0950     ret = irq_set_irq_wake(irq, 1);
0951     if (ret) {
0952         dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
0953             irq, ret);
0954         return ret;
0955     }
0956
0957     if (spi->max_speed_hz)
0958         wm0010->board_max_spi_speed = spi->max_speed_hz;
0959     else
0960         wm0010->board_max_spi_speed = 0;
0961
0962     ret = devm_snd_soc_register_component(&spi->dev,
0963                      &soc_component_dev_wm0010, wm0010_dai,
0964                      ARRAY_SIZE(wm0010_dai));
0965     if (ret < 0)
0966         return ret;
0967
0968     return 0;
0969 }
0970
0971 static void wm0010_spi_remove(struct spi_device *spi)
0972 {
0973     struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
0974
0975     gpio_set_value_cansleep(wm0010->gpio_reset,
0976                 wm0010->gpio_reset_value);
0977
0978     irq_set_irq_wake(wm0010->irq, 0);
0979
0980     if (wm0010->irq)
0981         free_irq(wm0010->irq, wm0010);
0982 }
0983
0984 static struct spi_driver wm0010_spi_driver = {
0985     .driver = {
0986         .name   = "wm0010",
0987     },
0988     .probe      = wm0010_spi_probe,
0989     .remove     = wm0010_spi_remove,
0990 };
0991
0992 module_spi_driver(wm0010_spi_driver);
0993
0994 MODULE_DESCRIPTION("ASoC WM0010 driver");
0995 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
0996 MODULE_LICENSE("GPL");