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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2019, Linaro Limited
0003 
0004 #include <linux/clk.h>
0005 #include <linux/clk-provider.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/kernel.h>
0008 #include <linux/mfd/wcd934x/registers.h>
0009 #include <linux/mfd/wcd934x/wcd934x.h>
0010 #include <linux/module.h>
0011 #include <linux/mutex.h>
0012 #include <linux/of_clk.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/slab.h>
0018 #include <linux/slimbus.h>
0019 #include <sound/pcm_params.h>
0020 #include <sound/soc.h>
0021 #include <sound/soc-dapm.h>
0022 #include <sound/tlv.h>
0023 #include "wcd-clsh-v2.h"
0024 #include "wcd-mbhc-v2.h"
0025 
0026 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
0027                 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
0028                 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
0029 /* Fractional Rates */
0030 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
0031                  SNDRV_PCM_RATE_176400)
0032 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
0033                     SNDRV_PCM_FMTBIT_S24_LE)
0034 
0035 /* slave port water mark level
0036  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
0037  */
0038 #define SLAVE_PORT_WATER_MARK_6BYTES    0
0039 #define SLAVE_PORT_WATER_MARK_9BYTES    1
0040 #define SLAVE_PORT_WATER_MARK_12BYTES   2
0041 #define SLAVE_PORT_WATER_MARK_15BYTES   3
0042 #define SLAVE_PORT_WATER_MARK_SHIFT 1
0043 #define SLAVE_PORT_ENABLE       1
0044 #define SLAVE_PORT_DISABLE      0
0045 #define WCD934X_SLIM_WATER_MARK_VAL \
0046     ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
0047      (SLAVE_PORT_ENABLE))
0048 
0049 #define WCD934X_SLIM_NUM_PORT_REG   3
0050 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
0051 #define WCD934X_SLIM_IRQ_OVERFLOW   BIT(0)
0052 #define WCD934X_SLIM_IRQ_UNDERFLOW  BIT(1)
0053 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
0054 
0055 #define WCD934X_MCLK_CLK_12P288MHZ  12288000
0056 #define WCD934X_MCLK_CLK_9P6MHZ     9600000
0057 
0058 /* Only valid for 9.6 MHz mclk */
0059 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
0060 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
0061 
0062 /* Only valid for 12.288 MHz mclk */
0063 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
0064 
0065 #define WCD934X_DMIC_CLK_DIV_2      0x0
0066 #define WCD934X_DMIC_CLK_DIV_3      0x1
0067 #define WCD934X_DMIC_CLK_DIV_4      0x2
0068 #define WCD934X_DMIC_CLK_DIV_6      0x3
0069 #define WCD934X_DMIC_CLK_DIV_8      0x4
0070 #define WCD934X_DMIC_CLK_DIV_16     0x5
0071 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
0072 
0073 #define TX_HPF_CUT_OFF_FREQ_MASK    0x60
0074 #define CF_MIN_3DB_4HZ          0x0
0075 #define CF_MIN_3DB_75HZ         0x1
0076 #define CF_MIN_3DB_150HZ        0x2
0077 
0078 #define WCD934X_RX_START        16
0079 #define WCD934X_NUM_INTERPOLATORS   9
0080 #define WCD934X_RX_PATH_CTL_OFFSET  20
0081 #define WCD934X_MAX_VALID_ADC_MUX   13
0082 #define WCD934X_INVALID_ADC_MUX     9
0083 
0084 #define WCD934X_SLIM_RX_CH(p) \
0085     {.port = p + WCD934X_RX_START, .shift = p,}
0086 
0087 #define WCD934X_SLIM_TX_CH(p) \
0088     {.port = p, .shift = p,}
0089 
0090 /* Feature masks to distinguish codec version */
0091 #define DSD_DISABLED_MASK   0
0092 #define SLNQ_DISABLED_MASK  1
0093 
0094 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
0095 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
0096 
0097 /* As fine version info cannot be retrieved before wcd probe.
0098  * Define three coarse versions for possible future use before wcd probe.
0099  */
0100 #define WCD_VERSION_WCD9340_1_0     0x400
0101 #define WCD_VERSION_WCD9341_1_0     0x410
0102 #define WCD_VERSION_WCD9340_1_1     0x401
0103 #define WCD_VERSION_WCD9341_1_1     0x411
0104 #define WCD934X_AMIC_PWR_LEVEL_LP   0
0105 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
0106 #define WCD934X_AMIC_PWR_LEVEL_HP   2
0107 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
0108 #define WCD934X_AMIC_PWR_LVL_MASK   0x60
0109 #define WCD934X_AMIC_PWR_LVL_SHIFT  0x5
0110 
0111 #define WCD934X_DEC_PWR_LVL_MASK    0x06
0112 #define WCD934X_DEC_PWR_LVL_LP      0x02
0113 #define WCD934X_DEC_PWR_LVL_HP      0x04
0114 #define WCD934X_DEC_PWR_LVL_DF      0x00
0115 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
0116 
0117 #define WCD934X_DEF_MICBIAS_MV  1800
0118 #define WCD934X_MAX_MICBIAS_MV  2850
0119 
0120 #define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
0121 
0122 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
0123 { \
0124     .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0125     .info = wcd934x_iir_filter_info, \
0126     .get = wcd934x_get_iir_band_audio_mixer, \
0127     .put = wcd934x_put_iir_band_audio_mixer, \
0128     .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
0129         .iir_idx = iidx, \
0130         .band_idx = bidx, \
0131         .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
0132     } \
0133 }
0134 
0135 /* Z value defined in milliohm */
0136 #define WCD934X_ZDET_VAL_32             32000
0137 #define WCD934X_ZDET_VAL_400            400000
0138 #define WCD934X_ZDET_VAL_1200           1200000
0139 #define WCD934X_ZDET_VAL_100K           100000000
0140 /* Z floating defined in ohms */
0141 #define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
0142 
0143 #define WCD934X_ZDET_NUM_MEASUREMENTS   900
0144 #define WCD934X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
0145 #define WCD934X_MBHC_GET_X1(x)          (x & 0x3FFF)
0146 /* Z value compared in milliOhm */
0147 #define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
0148 #define WCD934X_MBHC_ZDET_CONST         (86 * 16384)
0149 #define WCD934X_MBHC_MOISTURE_RREF      R_24_KOHM
0150 #define WCD934X_MBHC_MAX_BUTTONS    (8)
0151 #define WCD_MBHC_HS_V_MAX           1600
0152 
0153 #define WCD934X_INTERPOLATOR_PATH(id)           \
0154     {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},   \
0155     {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},   \
0156     {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},   \
0157     {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},   \
0158     {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},   \
0159     {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},   \
0160     {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},   \
0161     {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},   \
0162     {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},  \
0163     {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},  \
0164     {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},   \
0165     {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},   \
0166     {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},   \
0167     {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},   \
0168     {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},   \
0169     {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},   \
0170     {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},   \
0171     {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},   \
0172     {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},  \
0173     {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},  \
0174     {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},   \
0175     {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},   \
0176     {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},   \
0177     {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},   \
0178     {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},   \
0179     {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},   \
0180     {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},   \
0181     {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},   \
0182     {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},      \
0183     {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},      \
0184     {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
0185     {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
0186     {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
0187     {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
0188     {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
0189     {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
0190     {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
0191     {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
0192     {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
0193     {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
0194     {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
0195     {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
0196     {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
0197     {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},    \
0198     {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},  \
0199     {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},   \
0200     {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
0201     {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},  \
0202     {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
0203 
0204 #define WCD934X_INTERPOLATOR_MIX2(id)           \
0205     {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
0206     {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
0207 
0208 #define WCD934X_SLIM_RX_AIF_PATH(id)    \
0209     {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
0210     {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
0211     {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
0212     {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \
0213     {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
0214 
0215 #define WCD934X_ADC_MUX(id) \
0216     {"ADC MUX" #id, "DMIC", "DMIC MUX" #id },   \
0217     {"ADC MUX" #id, "AMIC", "AMIC MUX" #id },   \
0218     {"DMIC MUX" #id, "DMIC0", "DMIC0"},     \
0219     {"DMIC MUX" #id, "DMIC1", "DMIC1"},     \
0220     {"DMIC MUX" #id, "DMIC2", "DMIC2"},     \
0221     {"DMIC MUX" #id, "DMIC3", "DMIC3"},     \
0222     {"DMIC MUX" #id, "DMIC4", "DMIC4"},     \
0223     {"DMIC MUX" #id, "DMIC5", "DMIC5"},     \
0224     {"AMIC MUX" #id, "ADC1", "ADC1"},       \
0225     {"AMIC MUX" #id, "ADC2", "ADC2"},       \
0226     {"AMIC MUX" #id, "ADC3", "ADC3"},       \
0227     {"AMIC MUX" #id, "ADC4", "ADC4"}
0228 
0229 #define WCD934X_IIR_INP_MUX(id) \
0230     {"IIR" #id, NULL, "IIR" #id " INP0 MUX"},   \
0231     {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},    \
0232     {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},    \
0233     {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},    \
0234     {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},    \
0235     {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},    \
0236     {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},    \
0237     {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},    \
0238     {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},    \
0239     {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},    \
0240     {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
0241     {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
0242     {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
0243     {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
0244     {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
0245     {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
0246     {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
0247     {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
0248     {"IIR" #id, NULL, "IIR" #id " INP1 MUX"},   \
0249     {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},    \
0250     {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},    \
0251     {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},    \
0252     {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},    \
0253     {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},    \
0254     {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},    \
0255     {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},    \
0256     {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},    \
0257     {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},    \
0258     {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
0259     {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
0260     {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
0261     {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
0262     {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
0263     {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
0264     {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
0265     {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
0266     {"IIR" #id, NULL, "IIR" #id " INP2 MUX"},   \
0267     {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},    \
0268     {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},    \
0269     {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},    \
0270     {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},    \
0271     {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},    \
0272     {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},    \
0273     {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},    \
0274     {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},    \
0275     {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},    \
0276     {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
0277     {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
0278     {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
0279     {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
0280     {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
0281     {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
0282     {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
0283     {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
0284     {"IIR" #id, NULL, "IIR" #id " INP3 MUX"},   \
0285     {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},    \
0286     {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},    \
0287     {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},    \
0288     {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},    \
0289     {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},    \
0290     {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},    \
0291     {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},    \
0292     {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},    \
0293     {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},    \
0294     {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
0295     {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
0296     {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
0297     {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
0298     {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
0299     {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
0300     {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
0301     {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
0302 
0303 #define WCD934X_SLIM_TX_AIF_PATH(id)    \
0304     {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },  \
0305     {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },  \
0306     {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },  \
0307     {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
0308 
0309 #define WCD934X_MAX_MICBIAS MIC_BIAS_4
0310 
0311 enum {
0312     SIDO_SOURCE_INTERNAL,
0313     SIDO_SOURCE_RCO_BG,
0314 };
0315 
0316 enum {
0317     INTERP_EAR = 0,
0318     INTERP_HPHL,
0319     INTERP_HPHR,
0320     INTERP_LO1,
0321     INTERP_LO2,
0322     INTERP_LO3_NA, /* LO3 not avalible in Tavil */
0323     INTERP_LO4_NA,
0324     INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
0325     INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
0326     INTERP_MAX,
0327 };
0328 
0329 enum {
0330     WCD934X_RX0 = 0,
0331     WCD934X_RX1,
0332     WCD934X_RX2,
0333     WCD934X_RX3,
0334     WCD934X_RX4,
0335     WCD934X_RX5,
0336     WCD934X_RX6,
0337     WCD934X_RX7,
0338     WCD934X_RX8,
0339     WCD934X_RX9,
0340     WCD934X_RX10,
0341     WCD934X_RX11,
0342     WCD934X_RX12,
0343     WCD934X_RX_MAX,
0344 };
0345 
0346 enum {
0347     WCD934X_TX0 = 0,
0348     WCD934X_TX1,
0349     WCD934X_TX2,
0350     WCD934X_TX3,
0351     WCD934X_TX4,
0352     WCD934X_TX5,
0353     WCD934X_TX6,
0354     WCD934X_TX7,
0355     WCD934X_TX8,
0356     WCD934X_TX9,
0357     WCD934X_TX10,
0358     WCD934X_TX11,
0359     WCD934X_TX12,
0360     WCD934X_TX13,
0361     WCD934X_TX14,
0362     WCD934X_TX15,
0363     WCD934X_TX_MAX,
0364 };
0365 
0366 struct wcd934x_slim_ch {
0367     u32 ch_num;
0368     u16 port;
0369     u16 shift;
0370     struct list_head list;
0371 };
0372 
0373 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
0374     WCD934X_SLIM_TX_CH(0),
0375     WCD934X_SLIM_TX_CH(1),
0376     WCD934X_SLIM_TX_CH(2),
0377     WCD934X_SLIM_TX_CH(3),
0378     WCD934X_SLIM_TX_CH(4),
0379     WCD934X_SLIM_TX_CH(5),
0380     WCD934X_SLIM_TX_CH(6),
0381     WCD934X_SLIM_TX_CH(7),
0382     WCD934X_SLIM_TX_CH(8),
0383     WCD934X_SLIM_TX_CH(9),
0384     WCD934X_SLIM_TX_CH(10),
0385     WCD934X_SLIM_TX_CH(11),
0386     WCD934X_SLIM_TX_CH(12),
0387     WCD934X_SLIM_TX_CH(13),
0388     WCD934X_SLIM_TX_CH(14),
0389     WCD934X_SLIM_TX_CH(15),
0390 };
0391 
0392 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
0393     WCD934X_SLIM_RX_CH(0),   /* 16 */
0394     WCD934X_SLIM_RX_CH(1),   /* 17 */
0395     WCD934X_SLIM_RX_CH(2),
0396     WCD934X_SLIM_RX_CH(3),
0397     WCD934X_SLIM_RX_CH(4),
0398     WCD934X_SLIM_RX_CH(5),
0399     WCD934X_SLIM_RX_CH(6),
0400     WCD934X_SLIM_RX_CH(7),
0401     WCD934X_SLIM_RX_CH(8),
0402     WCD934X_SLIM_RX_CH(9),
0403     WCD934X_SLIM_RX_CH(10),
0404     WCD934X_SLIM_RX_CH(11),
0405     WCD934X_SLIM_RX_CH(12),
0406 };
0407 
0408 /* Codec supports 2 IIR filters */
0409 enum {
0410     IIR0 = 0,
0411     IIR1,
0412     IIR_MAX,
0413 };
0414 
0415 /* Each IIR has 5 Filter Stages */
0416 enum {
0417     BAND1 = 0,
0418     BAND2,
0419     BAND3,
0420     BAND4,
0421     BAND5,
0422     BAND_MAX,
0423 };
0424 
0425 enum {
0426     COMPANDER_1, /* HPH_L */
0427     COMPANDER_2, /* HPH_R */
0428     COMPANDER_3, /* LO1_DIFF */
0429     COMPANDER_4, /* LO2_DIFF */
0430     COMPANDER_5, /* LO3_SE - not used in Tavil */
0431     COMPANDER_6, /* LO4_SE - not used in Tavil */
0432     COMPANDER_7, /* SWR SPK CH1 */
0433     COMPANDER_8, /* SWR SPK CH2 */
0434     COMPANDER_MAX,
0435 };
0436 
0437 enum {
0438     AIF1_PB = 0,
0439     AIF1_CAP,
0440     AIF2_PB,
0441     AIF2_CAP,
0442     AIF3_PB,
0443     AIF3_CAP,
0444     AIF4_PB,
0445     AIF4_VIFEED,
0446     AIF4_MAD_TX,
0447     NUM_CODEC_DAIS,
0448 };
0449 
0450 enum {
0451     INTn_1_INP_SEL_ZERO = 0,
0452     INTn_1_INP_SEL_DEC0,
0453     INTn_1_INP_SEL_DEC1,
0454     INTn_1_INP_SEL_IIR0,
0455     INTn_1_INP_SEL_IIR1,
0456     INTn_1_INP_SEL_RX0,
0457     INTn_1_INP_SEL_RX1,
0458     INTn_1_INP_SEL_RX2,
0459     INTn_1_INP_SEL_RX3,
0460     INTn_1_INP_SEL_RX4,
0461     INTn_1_INP_SEL_RX5,
0462     INTn_1_INP_SEL_RX6,
0463     INTn_1_INP_SEL_RX7,
0464 };
0465 
0466 enum {
0467     INTn_2_INP_SEL_ZERO = 0,
0468     INTn_2_INP_SEL_RX0,
0469     INTn_2_INP_SEL_RX1,
0470     INTn_2_INP_SEL_RX2,
0471     INTn_2_INP_SEL_RX3,
0472     INTn_2_INP_SEL_RX4,
0473     INTn_2_INP_SEL_RX5,
0474     INTn_2_INP_SEL_RX6,
0475     INTn_2_INP_SEL_RX7,
0476     INTn_2_INP_SEL_PROXIMITY,
0477 };
0478 
0479 enum {
0480     INTERP_MAIN_PATH,
0481     INTERP_MIX_PATH,
0482 };
0483 
0484 struct interp_sample_rate {
0485     int sample_rate;
0486     int rate_val;
0487 };
0488 
0489 static struct interp_sample_rate sr_val_tbl[] = {
0490     {8000, 0x0},
0491     {16000, 0x1},
0492     {32000, 0x3},
0493     {48000, 0x4},
0494     {96000, 0x5},
0495     {192000, 0x6},
0496     {384000, 0x7},
0497     {44100, 0x9},
0498     {88200, 0xA},
0499     {176400, 0xB},
0500     {352800, 0xC},
0501 };
0502 
0503 struct wcd934x_mbhc_zdet_param {
0504     u16 ldo_ctl;
0505     u16 noff;
0506     u16 nshift;
0507     u16 btn5;
0508     u16 btn6;
0509     u16 btn7;
0510 };
0511 
0512 struct wcd_slim_codec_dai_data {
0513     struct list_head slim_ch_list;
0514     struct slim_stream_config sconfig;
0515     struct slim_stream_runtime *sruntime;
0516 };
0517 
0518 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
0519     {
0520         .name = "WCD9335-IFC-DEV",
0521         .range_min =  0x0,
0522         .range_max = 0xffff,
0523         .selector_reg = 0x800,
0524         .selector_mask = 0xfff,
0525         .selector_shift = 0,
0526         .window_start = 0x800,
0527         .window_len = 0x400,
0528     },
0529 };
0530 
0531 static struct regmap_config wcd934x_ifc_regmap_config = {
0532     .reg_bits = 16,
0533     .val_bits = 8,
0534     .max_register = 0xffff,
0535     .ranges = wcd934x_ifc_ranges,
0536     .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
0537 };
0538 
0539 struct wcd934x_codec {
0540     struct device *dev;
0541     struct clk_hw hw;
0542     struct clk *extclk;
0543     struct regmap *regmap;
0544     struct regmap *if_regmap;
0545     struct slim_device *sdev;
0546     struct slim_device *sidev;
0547     struct wcd_clsh_ctrl *clsh_ctrl;
0548     struct snd_soc_component *component;
0549     struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
0550     struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
0551     struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
0552     int rate;
0553     u32 version;
0554     u32 hph_mode;
0555     int num_rx_port;
0556     int num_tx_port;
0557     u32 tx_port_value[WCD934X_TX_MAX];
0558     u32 rx_port_value[WCD934X_RX_MAX];
0559     int sido_input_src;
0560     int dmic_0_1_clk_cnt;
0561     int dmic_2_3_clk_cnt;
0562     int dmic_4_5_clk_cnt;
0563     int dmic_sample_rate;
0564     int comp_enabled[COMPANDER_MAX];
0565     int sysclk_users;
0566     struct mutex sysclk_mutex;
0567     /* mbhc module */
0568     struct wcd_mbhc *mbhc;
0569     struct wcd_mbhc_config mbhc_cfg;
0570     struct wcd_mbhc_intr intr_ids;
0571     bool mbhc_started;
0572     struct mutex micb_lock;
0573     u32 micb_ref[WCD934X_MAX_MICBIAS];
0574     u32 pullup_ref[WCD934X_MAX_MICBIAS];
0575     u32 micb1_mv;
0576     u32 micb2_mv;
0577     u32 micb3_mv;
0578     u32 micb4_mv;
0579 };
0580 
0581 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
0582 
0583 struct wcd_iir_filter_ctl {
0584     unsigned int iir_idx;
0585     unsigned int band_idx;
0586     struct soc_bytes_ext bytes_ext;
0587 };
0588 
0589 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
0590 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
0591 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
0592 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
0593 
0594 /* Cutoff frequency for high pass filter */
0595 static const char * const cf_text[] = {
0596     "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
0597 };
0598 
0599 static const char * const rx_cf_text[] = {
0600     "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
0601     "CF_NEG_3DB_0P48HZ"
0602 };
0603 
0604 static const char * const rx_hph_mode_mux_text[] = {
0605     "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
0606     "Class-H Hi-Fi Low Power"
0607 };
0608 
0609 static const char *const slim_rx_mux_text[] = {
0610     "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
0611 };
0612 
0613 static const char * const rx_int0_7_mix_mux_text[] = {
0614     "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
0615     "RX6", "RX7", "PROXIMITY"
0616 };
0617 
0618 static const char * const rx_int_mix_mux_text[] = {
0619     "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
0620     "RX6", "RX7"
0621 };
0622 
0623 static const char * const rx_prim_mix_text[] = {
0624     "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
0625     "RX3", "RX4", "RX5", "RX6", "RX7"
0626 };
0627 
0628 static const char * const rx_sidetone_mix_text[] = {
0629     "ZERO", "SRC0", "SRC1", "SRC_SUM"
0630 };
0631 
0632 static const char * const iir_inp_mux_text[] = {
0633     "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
0634     "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
0635 };
0636 
0637 static const char * const rx_int_dem_inp_mux_text[] = {
0638     "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
0639 };
0640 
0641 static const char * const rx_int0_1_interp_mux_text[] = {
0642     "ZERO", "RX INT0_1 MIX1",
0643 };
0644 
0645 static const char * const rx_int1_1_interp_mux_text[] = {
0646     "ZERO", "RX INT1_1 MIX1",
0647 };
0648 
0649 static const char * const rx_int2_1_interp_mux_text[] = {
0650     "ZERO", "RX INT2_1 MIX1",
0651 };
0652 
0653 static const char * const rx_int3_1_interp_mux_text[] = {
0654     "ZERO", "RX INT3_1 MIX1",
0655 };
0656 
0657 static const char * const rx_int4_1_interp_mux_text[] = {
0658     "ZERO", "RX INT4_1 MIX1",
0659 };
0660 
0661 static const char * const rx_int7_1_interp_mux_text[] = {
0662     "ZERO", "RX INT7_1 MIX1",
0663 };
0664 
0665 static const char * const rx_int8_1_interp_mux_text[] = {
0666     "ZERO", "RX INT8_1 MIX1",
0667 };
0668 
0669 static const char * const rx_int0_2_interp_mux_text[] = {
0670     "ZERO", "RX INT0_2 MUX",
0671 };
0672 
0673 static const char * const rx_int1_2_interp_mux_text[] = {
0674     "ZERO", "RX INT1_2 MUX",
0675 };
0676 
0677 static const char * const rx_int2_2_interp_mux_text[] = {
0678     "ZERO", "RX INT2_2 MUX",
0679 };
0680 
0681 static const char * const rx_int3_2_interp_mux_text[] = {
0682     "ZERO", "RX INT3_2 MUX",
0683 };
0684 
0685 static const char * const rx_int4_2_interp_mux_text[] = {
0686     "ZERO", "RX INT4_2 MUX",
0687 };
0688 
0689 static const char * const rx_int7_2_interp_mux_text[] = {
0690     "ZERO", "RX INT7_2 MUX",
0691 };
0692 
0693 static const char * const rx_int8_2_interp_mux_text[] = {
0694     "ZERO", "RX INT8_2 MUX",
0695 };
0696 
0697 static const char * const dmic_mux_text[] = {
0698     "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
0699 };
0700 
0701 static const char * const amic_mux_text[] = {
0702     "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
0703 };
0704 
0705 static const char * const amic4_5_sel_text[] = {
0706     "AMIC4", "AMIC5"
0707 };
0708 
0709 static const char * const adc_mux_text[] = {
0710     "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
0711 };
0712 
0713 static const char * const cdc_if_tx0_mux_text[] = {
0714     "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
0715 };
0716 
0717 static const char * const cdc_if_tx1_mux_text[] = {
0718     "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
0719 };
0720 
0721 static const char * const cdc_if_tx2_mux_text[] = {
0722     "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
0723 };
0724 
0725 static const char * const cdc_if_tx3_mux_text[] = {
0726     "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
0727 };
0728 
0729 static const char * const cdc_if_tx4_mux_text[] = {
0730     "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
0731 };
0732 
0733 static const char * const cdc_if_tx5_mux_text[] = {
0734     "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
0735 };
0736 
0737 static const char * const cdc_if_tx6_mux_text[] = {
0738     "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
0739 };
0740 
0741 static const char * const cdc_if_tx7_mux_text[] = {
0742     "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
0743 };
0744 
0745 static const char * const cdc_if_tx8_mux_text[] = {
0746     "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
0747 };
0748 
0749 static const char * const cdc_if_tx9_mux_text[] = {
0750     "ZERO", "DEC7", "DEC7_192"
0751 };
0752 
0753 static const char * const cdc_if_tx10_mux_text[] = {
0754     "ZERO", "DEC6", "DEC6_192"
0755 };
0756 
0757 static const char * const cdc_if_tx11_mux_text[] = {
0758     "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
0759 };
0760 
0761 static const char * const cdc_if_tx11_inp1_mux_text[] = {
0762     "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
0763     "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
0764 };
0765 
0766 static const char * const cdc_if_tx13_mux_text[] = {
0767     "CDC_DEC_5", "MAD_BRDCST"
0768 };
0769 
0770 static const char * const cdc_if_tx13_inp1_mux_text[] = {
0771     "ZERO", "DEC5", "DEC5_192"
0772 };
0773 
0774 static const struct soc_enum cf_dec0_enum =
0775     SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
0776 
0777 static const struct soc_enum cf_dec1_enum =
0778     SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
0779 
0780 static const struct soc_enum cf_dec2_enum =
0781     SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
0782 
0783 static const struct soc_enum cf_dec3_enum =
0784     SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
0785 
0786 static const struct soc_enum cf_dec4_enum =
0787     SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
0788 
0789 static const struct soc_enum cf_dec5_enum =
0790     SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
0791 
0792 static const struct soc_enum cf_dec6_enum =
0793     SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
0794 
0795 static const struct soc_enum cf_dec7_enum =
0796     SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
0797 
0798 static const struct soc_enum cf_dec8_enum =
0799     SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
0800 
0801 static const struct soc_enum cf_int0_1_enum =
0802     SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
0803 
0804 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
0805              rx_cf_text);
0806 
0807 static const struct soc_enum cf_int1_1_enum =
0808     SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
0809 
0810 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
0811              rx_cf_text);
0812 
0813 static const struct soc_enum cf_int2_1_enum =
0814     SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
0815 
0816 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
0817              rx_cf_text);
0818 
0819 static const struct soc_enum cf_int3_1_enum =
0820     SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
0821 
0822 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
0823                 rx_cf_text);
0824 
0825 static const struct soc_enum cf_int4_1_enum =
0826     SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
0827 
0828 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
0829                 rx_cf_text);
0830 
0831 static const struct soc_enum cf_int7_1_enum =
0832     SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
0833 
0834 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
0835                 rx_cf_text);
0836 
0837 static const struct soc_enum cf_int8_1_enum =
0838     SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
0839 
0840 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
0841                 rx_cf_text);
0842 
0843 static const struct soc_enum rx_hph_mode_mux_enum =
0844     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
0845                 rx_hph_mode_mux_text);
0846 
0847 static const struct soc_enum slim_rx_mux_enum =
0848     SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
0849 
0850 static const struct soc_enum rx_int0_2_mux_chain_enum =
0851     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
0852             rx_int0_7_mix_mux_text);
0853 
0854 static const struct soc_enum rx_int1_2_mux_chain_enum =
0855     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
0856             rx_int_mix_mux_text);
0857 
0858 static const struct soc_enum rx_int2_2_mux_chain_enum =
0859     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
0860             rx_int_mix_mux_text);
0861 
0862 static const struct soc_enum rx_int3_2_mux_chain_enum =
0863     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
0864             rx_int_mix_mux_text);
0865 
0866 static const struct soc_enum rx_int4_2_mux_chain_enum =
0867     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
0868             rx_int_mix_mux_text);
0869 
0870 static const struct soc_enum rx_int7_2_mux_chain_enum =
0871     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
0872             rx_int0_7_mix_mux_text);
0873 
0874 static const struct soc_enum rx_int8_2_mux_chain_enum =
0875     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
0876             rx_int_mix_mux_text);
0877 
0878 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
0879     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
0880             rx_prim_mix_text);
0881 
0882 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
0883     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
0884             rx_prim_mix_text);
0885 
0886 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
0887     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
0888             rx_prim_mix_text);
0889 
0890 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
0891     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
0892             rx_prim_mix_text);
0893 
0894 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
0895     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
0896             rx_prim_mix_text);
0897 
0898 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
0899     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
0900             rx_prim_mix_text);
0901 
0902 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
0903     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
0904             rx_prim_mix_text);
0905 
0906 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
0907     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
0908             rx_prim_mix_text);
0909 
0910 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
0911     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
0912             rx_prim_mix_text);
0913 
0914 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
0915     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
0916             rx_prim_mix_text);
0917 
0918 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
0919     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
0920             rx_prim_mix_text);
0921 
0922 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
0923     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
0924             rx_prim_mix_text);
0925 
0926 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
0927     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
0928             rx_prim_mix_text);
0929 
0930 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
0931     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
0932             rx_prim_mix_text);
0933 
0934 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
0935     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
0936             rx_prim_mix_text);
0937 
0938 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
0939     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
0940             rx_prim_mix_text);
0941 
0942 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
0943     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
0944             rx_prim_mix_text);
0945 
0946 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
0947     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
0948             rx_prim_mix_text);
0949 
0950 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
0951     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
0952             rx_prim_mix_text);
0953 
0954 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
0955     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
0956             rx_prim_mix_text);
0957 
0958 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
0959     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
0960             rx_prim_mix_text);
0961 
0962 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
0963     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
0964             rx_sidetone_mix_text);
0965 
0966 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
0967     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
0968             rx_sidetone_mix_text);
0969 
0970 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
0971     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
0972             rx_sidetone_mix_text);
0973 
0974 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
0975     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
0976             rx_sidetone_mix_text);
0977 
0978 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
0979     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
0980             rx_sidetone_mix_text);
0981 
0982 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
0983     SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
0984             rx_sidetone_mix_text);
0985 
0986 static const struct soc_enum iir0_inp0_mux_enum =
0987     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
0988             0, 18, iir_inp_mux_text);
0989 
0990 static const struct soc_enum iir0_inp1_mux_enum =
0991     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
0992             0, 18, iir_inp_mux_text);
0993 
0994 static const struct soc_enum iir0_inp2_mux_enum =
0995     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
0996             0, 18, iir_inp_mux_text);
0997 
0998 static const struct soc_enum iir0_inp3_mux_enum =
0999     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
1000             0, 18, iir_inp_mux_text);
1001 
1002 static const struct soc_enum iir1_inp0_mux_enum =
1003     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
1004             0, 18, iir_inp_mux_text);
1005 
1006 static const struct soc_enum iir1_inp1_mux_enum =
1007     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
1008             0, 18, iir_inp_mux_text);
1009 
1010 static const struct soc_enum iir1_inp2_mux_enum =
1011     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
1012             0, 18, iir_inp_mux_text);
1013 
1014 static const struct soc_enum iir1_inp3_mux_enum =
1015     SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
1016             0, 18, iir_inp_mux_text);
1017 
1018 static const struct soc_enum rx_int0_dem_inp_mux_enum =
1019     SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
1020             ARRAY_SIZE(rx_int_dem_inp_mux_text),
1021             rx_int_dem_inp_mux_text);
1022 
1023 static const struct soc_enum rx_int1_dem_inp_mux_enum =
1024     SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
1025             ARRAY_SIZE(rx_int_dem_inp_mux_text),
1026             rx_int_dem_inp_mux_text);
1027 
1028 static const struct soc_enum rx_int2_dem_inp_mux_enum =
1029     SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
1030             ARRAY_SIZE(rx_int_dem_inp_mux_text),
1031             rx_int_dem_inp_mux_text);
1032 
1033 static const struct soc_enum tx_adc_mux0_enum =
1034     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1035             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1036 static const struct soc_enum tx_adc_mux1_enum =
1037     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1038             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1039 static const struct soc_enum tx_adc_mux2_enum =
1040     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1041             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1042 static const struct soc_enum tx_adc_mux3_enum =
1043     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1044             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1045 static const struct soc_enum tx_adc_mux4_enum =
1046     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1047             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1048 static const struct soc_enum tx_adc_mux5_enum =
1049     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1050             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1051 static const struct soc_enum tx_adc_mux6_enum =
1052     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1053             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1054 static const struct soc_enum tx_adc_mux7_enum =
1055     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1056             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1057 static const struct soc_enum tx_adc_mux8_enum =
1058     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1059             ARRAY_SIZE(adc_mux_text), adc_mux_text);
1060 
1061 static const struct soc_enum rx_int0_1_interp_mux_enum =
1062     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1063             rx_int0_1_interp_mux_text);
1064 
1065 static const struct soc_enum rx_int1_1_interp_mux_enum =
1066     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1067             rx_int1_1_interp_mux_text);
1068 
1069 static const struct soc_enum rx_int2_1_interp_mux_enum =
1070     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1071             rx_int2_1_interp_mux_text);
1072 
1073 static const struct soc_enum rx_int3_1_interp_mux_enum =
1074     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_1_interp_mux_text);
1075 
1076 static const struct soc_enum rx_int4_1_interp_mux_enum =
1077     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_1_interp_mux_text);
1078 
1079 static const struct soc_enum rx_int7_1_interp_mux_enum =
1080     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_1_interp_mux_text);
1081 
1082 static const struct soc_enum rx_int8_1_interp_mux_enum =
1083     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_1_interp_mux_text);
1084 
1085 static const struct soc_enum rx_int0_2_interp_mux_enum =
1086     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int0_2_interp_mux_text);
1087 
1088 static const struct soc_enum rx_int1_2_interp_mux_enum =
1089     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int1_2_interp_mux_text);
1090 
1091 static const struct soc_enum rx_int2_2_interp_mux_enum =
1092     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int2_2_interp_mux_text);
1093 
1094 static const struct soc_enum rx_int3_2_interp_mux_enum =
1095     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_2_interp_mux_text);
1096 
1097 static const struct soc_enum rx_int4_2_interp_mux_enum =
1098     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_2_interp_mux_text);
1099 
1100 static const struct soc_enum rx_int7_2_interp_mux_enum =
1101     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_2_interp_mux_text);
1102 
1103 static const struct soc_enum rx_int8_2_interp_mux_enum =
1104     SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_2_interp_mux_text);
1105 
1106 static const struct soc_enum tx_dmic_mux0_enum =
1107     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1108             dmic_mux_text);
1109 
1110 static const struct soc_enum tx_dmic_mux1_enum =
1111     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1112             dmic_mux_text);
1113 
1114 static const struct soc_enum tx_dmic_mux2_enum =
1115     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1116             dmic_mux_text);
1117 
1118 static const struct soc_enum tx_dmic_mux3_enum =
1119     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1120             dmic_mux_text);
1121 
1122 static const struct soc_enum tx_dmic_mux4_enum =
1123     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1124             dmic_mux_text);
1125 
1126 static const struct soc_enum tx_dmic_mux5_enum =
1127     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1128             dmic_mux_text);
1129 
1130 static const struct soc_enum tx_dmic_mux6_enum =
1131     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1132             dmic_mux_text);
1133 
1134 static const struct soc_enum tx_dmic_mux7_enum =
1135     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1136             dmic_mux_text);
1137 
1138 static const struct soc_enum tx_dmic_mux8_enum =
1139     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1140             dmic_mux_text);
1141 
1142 static const struct soc_enum tx_amic_mux0_enum =
1143     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1144             amic_mux_text);
1145 static const struct soc_enum tx_amic_mux1_enum =
1146     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1147             amic_mux_text);
1148 static const struct soc_enum tx_amic_mux2_enum =
1149     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1150             amic_mux_text);
1151 static const struct soc_enum tx_amic_mux3_enum =
1152     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1153             amic_mux_text);
1154 static const struct soc_enum tx_amic_mux4_enum =
1155     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1156             amic_mux_text);
1157 static const struct soc_enum tx_amic_mux5_enum =
1158     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1159             amic_mux_text);
1160 static const struct soc_enum tx_amic_mux6_enum =
1161     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1162             amic_mux_text);
1163 static const struct soc_enum tx_amic_mux7_enum =
1164     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1165             amic_mux_text);
1166 static const struct soc_enum tx_amic_mux8_enum =
1167     SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1168             amic_mux_text);
1169 
1170 static const struct soc_enum tx_amic4_5_enum =
1171     SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1172 
1173 static const struct soc_enum cdc_if_tx0_mux_enum =
1174     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1175             ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1176 static const struct soc_enum cdc_if_tx1_mux_enum =
1177     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1178             ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1179 static const struct soc_enum cdc_if_tx2_mux_enum =
1180     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1181             ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1182 static const struct soc_enum cdc_if_tx3_mux_enum =
1183     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1184             ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1185 static const struct soc_enum cdc_if_tx4_mux_enum =
1186     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1187             ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1188 static const struct soc_enum cdc_if_tx5_mux_enum =
1189     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1190             ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1191 static const struct soc_enum cdc_if_tx6_mux_enum =
1192     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1193             ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1194 static const struct soc_enum cdc_if_tx7_mux_enum =
1195     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1196             ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1197 static const struct soc_enum cdc_if_tx8_mux_enum =
1198     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1199             ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1200 static const struct soc_enum cdc_if_tx9_mux_enum =
1201     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1202             ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1203 static const struct soc_enum cdc_if_tx10_mux_enum =
1204     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1205             ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1206 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1207     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1208             ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1209             cdc_if_tx11_inp1_mux_text);
1210 static const struct soc_enum cdc_if_tx11_mux_enum =
1211     SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1212             ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1213 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1214     SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1215             ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1216             cdc_if_tx13_inp1_mux_text);
1217 static const struct soc_enum cdc_if_tx13_mux_enum =
1218     SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1219             ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1220 
1221 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
1222     WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
1223     WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
1224     WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
1225     WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
1226     WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
1227     WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
1228     WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
1229     WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
1230     WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
1231     WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
1232     WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
1233     WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
1234     WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
1235     WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
1236     WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
1237     WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
1238     WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1239     WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
1240     WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
1241     WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
1242     WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
1243     WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
1244     WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
1245     WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
1246     WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
1247     WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
1248     WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
1249     WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
1250     WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
1251     WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1252     WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
1253     WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
1254     WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
1255     WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
1256     WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
1257     WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
1258     WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
1259     WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
1260     WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
1261     WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
1262     WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
1263     WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
1264     WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
1265     WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
1266     WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
1267     WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
1268     WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
1269     WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
1270 };
1271 
1272 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1273 {
1274     if (sido_src == wcd->sido_input_src)
1275         return 0;
1276 
1277     if (sido_src == SIDO_SOURCE_RCO_BG) {
1278         regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1279                    WCD934X_ANA_RCO_BG_EN_MASK,
1280                    WCD934X_ANA_RCO_BG_ENABLE);
1281         usleep_range(100, 110);
1282     }
1283     wcd->sido_input_src = sido_src;
1284 
1285     return 0;
1286 }
1287 
1288 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1289 {
1290     mutex_lock(&wcd->sysclk_mutex);
1291 
1292     if (++wcd->sysclk_users != 1) {
1293         mutex_unlock(&wcd->sysclk_mutex);
1294         return 0;
1295     }
1296     mutex_unlock(&wcd->sysclk_mutex);
1297 
1298     regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1299                WCD934X_ANA_BIAS_EN_MASK,
1300                WCD934X_ANA_BIAS_EN);
1301     regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302                WCD934X_ANA_PRECHRG_EN_MASK,
1303                WCD934X_ANA_PRECHRG_EN);
1304     /*
1305      * 1ms delay is required after pre-charge is enabled
1306      * as per HW requirement
1307      */
1308     usleep_range(1000, 1100);
1309     regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1310                WCD934X_ANA_PRECHRG_EN_MASK, 0);
1311     regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1312                WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1313 
1314     /*
1315      * In data clock contrl register is changed
1316      * to CLK_SYS_MCLK_PRG
1317      */
1318 
1319     regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1320                WCD934X_EXT_CLK_BUF_EN_MASK,
1321                WCD934X_EXT_CLK_BUF_EN);
1322     regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1323                WCD934X_EXT_CLK_DIV_RATIO_MASK,
1324                WCD934X_EXT_CLK_DIV_BY_2);
1325     regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1326                WCD934X_MCLK_SRC_MASK,
1327                WCD934X_MCLK_SRC_EXT_CLK);
1328     regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1329                WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1330     regmap_update_bits(wcd->regmap,
1331                WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1332                WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1333                WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1334     regmap_update_bits(wcd->regmap,
1335                WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1336                WCD934X_MCLK_EN_MASK,
1337                WCD934X_MCLK_EN);
1338     regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1339                WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1340     /*
1341      * 10us sleep is required after clock is enabled
1342      * as per HW requirement
1343      */
1344     usleep_range(10, 15);
1345 
1346     wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1347 
1348     return 0;
1349 }
1350 
1351 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1352 {
1353     mutex_lock(&wcd->sysclk_mutex);
1354     if (--wcd->sysclk_users != 0) {
1355         mutex_unlock(&wcd->sysclk_mutex);
1356         return 0;
1357     }
1358     mutex_unlock(&wcd->sysclk_mutex);
1359 
1360     regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1361                WCD934X_EXT_CLK_BUF_EN_MASK |
1362                WCD934X_MCLK_EN_MASK, 0x0);
1363     regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1364                WCD934X_ANA_BIAS_EN_MASK, 0);
1365     regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1366                WCD934X_ANA_PRECHRG_EN_MASK, 0);
1367 
1368     return 0;
1369 }
1370 
1371 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1372 {
1373     int ret = 0;
1374 
1375     if (enable) {
1376         ret = clk_prepare_enable(wcd->extclk);
1377 
1378         if (ret) {
1379             dev_err(wcd->dev, "%s: ext clk enable failed\n",
1380                 __func__);
1381             return ret;
1382         }
1383         ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1384     } else {
1385         int val;
1386 
1387         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1388                 &val);
1389 
1390         /* Don't disable clock if soundwire using it.*/
1391         if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1392             return 0;
1393 
1394         wcd934x_disable_ana_bias_and_syclk(wcd);
1395         clk_disable_unprepare(wcd->extclk);
1396     }
1397 
1398     return ret;
1399 }
1400 
1401 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1402                      struct snd_kcontrol *kc, int event)
1403 {
1404     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1405     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1406 
1407     switch (event) {
1408     case SND_SOC_DAPM_PRE_PMU:
1409         return __wcd934x_cdc_mclk_enable(wcd, true);
1410     case SND_SOC_DAPM_POST_PMD:
1411         return __wcd934x_cdc_mclk_enable(wcd, false);
1412     }
1413 
1414     return 0;
1415 }
1416 
1417 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1418 {
1419     int val1, val2, ver, ret;
1420     struct regmap *regmap;
1421     u16 id_minor;
1422     u32 version_mask = 0;
1423 
1424     regmap = wcd->regmap;
1425     ver = 0;
1426 
1427     ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1428                    (u8 *)&id_minor, sizeof(u16));
1429 
1430     if (ret)
1431         return ret;
1432 
1433     regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1434     regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1435 
1436     version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1437     version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1438 
1439     switch (version_mask) {
1440     case DSD_DISABLED | SLNQ_DISABLED:
1441         if (id_minor == 0)
1442             ver = WCD_VERSION_WCD9340_1_0;
1443         else if (id_minor == 0x01)
1444             ver = WCD_VERSION_WCD9340_1_1;
1445         break;
1446     case SLNQ_DISABLED:
1447         if (id_minor == 0)
1448             ver = WCD_VERSION_WCD9341_1_0;
1449         else if (id_minor == 0x01)
1450             ver = WCD_VERSION_WCD9341_1_1;
1451         break;
1452     }
1453 
1454     wcd->version = ver;
1455     dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1456 
1457     return 0;
1458 }
1459 
1460 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1461 {
1462     int rc, val;
1463 
1464     __wcd934x_cdc_mclk_enable(wcd, true);
1465 
1466     regmap_update_bits(wcd->regmap,
1467                WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1468                WCD934X_EFUSE_SENSE_STATE_MASK,
1469                WCD934X_EFUSE_SENSE_STATE_DEF);
1470     regmap_update_bits(wcd->regmap,
1471                WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1472                WCD934X_EFUSE_SENSE_EN_MASK,
1473                WCD934X_EFUSE_SENSE_ENABLE);
1474     /*
1475      * 5ms sleep required after enabling efuse control
1476      * before checking the status.
1477      */
1478     usleep_range(5000, 5500);
1479     wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1480 
1481     rc = regmap_read(wcd->regmap,
1482              WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1483     if (rc || (!(val & 0x01)))
1484         WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1485              __func__, val, rc);
1486 
1487     __wcd934x_cdc_mclk_enable(wcd, false);
1488 }
1489 
1490 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1491 {
1492     if (enable) {
1493         __wcd934x_cdc_mclk_enable(wcd, true);
1494         regmap_update_bits(wcd->regmap,
1495                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1496                    WCD934X_CDC_SWR_CLK_EN_MASK,
1497                    WCD934X_CDC_SWR_CLK_ENABLE);
1498     } else {
1499         regmap_update_bits(wcd->regmap,
1500                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1501                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1502         __wcd934x_cdc_mclk_enable(wcd, false);
1503     }
1504 
1505     return 0;
1506 }
1507 
1508 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1509                           u8 rate_val, u32 rate)
1510 {
1511     struct snd_soc_component *comp = dai->component;
1512     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1513     struct wcd934x_slim_ch *ch;
1514     u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1515     int inp, j;
1516 
1517     list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1518         inp = ch->shift + INTn_1_INP_SEL_RX0;
1519         /*
1520          * Loop through all interpolator MUX inputs and find out
1521          * to which interpolator input, the slim rx port
1522          * is connected
1523          */
1524         for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1525             /* Interpolators 5 and 6 are not aviliable in Tavil */
1526             if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1527                 continue;
1528 
1529             cfg0 = snd_soc_component_read(comp,
1530                     WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1531             cfg1 = snd_soc_component_read(comp,
1532                     WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1533 
1534             inp0_sel = cfg0 &
1535                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1536             inp1_sel = (cfg0 >> 4) &
1537                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1538             inp2_sel = (cfg1 >> 4) &
1539                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1540 
1541             if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1542                 (inp2_sel == inp)) {
1543                 /* rate is in Hz */
1544                 /*
1545                  * Ear and speaker primary path does not support
1546                  * native sample rates
1547                  */
1548                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1549                      j == INTERP_SPKR2) && rate == 44100)
1550                     dev_err(wcd->dev,
1551                         "Cannot set 44.1KHz on INT%d\n",
1552                         j);
1553                 else
1554                     snd_soc_component_update_bits(comp,
1555                           WCD934X_CDC_RX_PATH_CTL(j),
1556                           WCD934X_CDC_MIX_PCM_RATE_MASK,
1557                           rate_val);
1558             }
1559         }
1560     }
1561 
1562     return 0;
1563 }
1564 
1565 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1566                          int rate_val, u32 rate)
1567 {
1568     struct snd_soc_component *component = dai->component;
1569     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1570     struct wcd934x_slim_ch *ch;
1571     int val, j;
1572 
1573     list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1574         for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1575             /* Interpolators 5 and 6 are not aviliable in Tavil */
1576             if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1577                 continue;
1578             val = snd_soc_component_read(component,
1579                     WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1580                     WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1581 
1582             if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1583                 /*
1584                  * Ear mix path supports only 48, 96, 192,
1585                  * 384KHz only
1586                  */
1587                 if ((j == INTERP_EAR) &&
1588                     (rate_val < 0x4 ||
1589                      rate_val > 0x7)) {
1590                     dev_err(component->dev,
1591                         "Invalid rate for AIF_PB DAI(%d)\n",
1592                         dai->id);
1593                     return -EINVAL;
1594                 }
1595 
1596                 snd_soc_component_update_bits(component,
1597                           WCD934X_CDC_RX_PATH_MIX_CTL(j),
1598                           WCD934X_CDC_MIX_PCM_RATE_MASK,
1599                           rate_val);
1600             }
1601         }
1602     }
1603 
1604     return 0;
1605 }
1606 
1607 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1608                      u32 sample_rate)
1609 {
1610     int rate_val = 0;
1611     int i, ret;
1612 
1613     for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1614         if (sample_rate == sr_val_tbl[i].sample_rate) {
1615             rate_val = sr_val_tbl[i].rate_val;
1616             break;
1617         }
1618     }
1619     if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1620         dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1621         return -EINVAL;
1622     }
1623 
1624     ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1625                          sample_rate);
1626     if (ret)
1627         return ret;
1628     ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1629                         sample_rate);
1630 
1631     return ret;
1632 }
1633 
1634 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1635                       u8 rate_val, u32 rate)
1636 {
1637     struct snd_soc_component *comp = dai->component;
1638     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1639     u8 shift = 0, shift_val = 0, tx_mux_sel;
1640     struct wcd934x_slim_ch *ch;
1641     int tx_port, tx_port_reg;
1642     int decimator = -1;
1643 
1644     list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1645         tx_port = ch->port;
1646         /* Find the SB TX MUX input - which decimator is connected */
1647         switch (tx_port) {
1648         case 0 ...  3:
1649             tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1650             shift = (tx_port << 1);
1651             shift_val = 0x03;
1652             break;
1653         case 4 ... 7:
1654             tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1655             shift = ((tx_port - 4) << 1);
1656             shift_val = 0x03;
1657             break;
1658         case 8 ... 10:
1659             tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1660             shift = ((tx_port - 8) << 1);
1661             shift_val = 0x03;
1662             break;
1663         case 11:
1664             tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1665             shift = 0;
1666             shift_val = 0x0F;
1667             break;
1668         case 13:
1669             tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1670             shift = 4;
1671             shift_val = 0x03;
1672             break;
1673         default:
1674             dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1675                 tx_port, dai->id);
1676             return -EINVAL;
1677         }
1678 
1679         tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1680                               (shift_val << shift);
1681 
1682         tx_mux_sel = tx_mux_sel >> shift;
1683         switch (tx_port) {
1684         case 0 ... 8:
1685             if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1686                 decimator = tx_port;
1687             break;
1688         case 9 ... 10:
1689             if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1690                 decimator = ((tx_port == 9) ? 7 : 6);
1691             break;
1692         case 11:
1693             if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1694                 decimator = tx_mux_sel - 1;
1695             break;
1696         case 13:
1697             if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1698                 decimator = 5;
1699             break;
1700         default:
1701             dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1702                 tx_port);
1703             return -EINVAL;
1704         }
1705 
1706         snd_soc_component_update_bits(comp,
1707                       WCD934X_CDC_TX_PATH_CTL(decimator),
1708                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1709                       rate_val);
1710     }
1711 
1712     return 0;
1713 }
1714 
1715 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1716                       struct wcd_slim_codec_dai_data *dai_data,
1717                       int direction)
1718 {
1719     struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1720     struct slim_stream_config *cfg = &dai_data->sconfig;
1721     struct wcd934x_slim_ch *ch;
1722     u16 payload = 0;
1723     int ret, i;
1724 
1725     cfg->ch_count = 0;
1726     cfg->direction = direction;
1727     cfg->port_mask = 0;
1728 
1729     /* Configure slave interface device */
1730     list_for_each_entry(ch, slim_ch_list, list) {
1731         cfg->ch_count++;
1732         payload |= 1 << ch->shift;
1733         cfg->port_mask |= BIT(ch->port);
1734     }
1735 
1736     cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1737     if (!cfg->chs)
1738         return -ENOMEM;
1739 
1740     i = 0;
1741     list_for_each_entry(ch, slim_ch_list, list) {
1742         cfg->chs[i++] = ch->ch_num;
1743         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1744             /* write to interface device */
1745             ret = regmap_write(wcd->if_regmap,
1746                WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1747                payload);
1748 
1749             if (ret < 0)
1750                 goto err;
1751 
1752             /* configure the slave port for water mark and enable*/
1753             ret = regmap_write(wcd->if_regmap,
1754                     WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1755                     WCD934X_SLIM_WATER_MARK_VAL);
1756             if (ret < 0)
1757                 goto err;
1758         } else {
1759             ret = regmap_write(wcd->if_regmap,
1760                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1761                 payload & 0x00FF);
1762             if (ret < 0)
1763                 goto err;
1764 
1765             /* ports 8,9 */
1766             ret = regmap_write(wcd->if_regmap,
1767                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1768                 (payload & 0xFF00) >> 8);
1769             if (ret < 0)
1770                 goto err;
1771 
1772             /* configure the slave port for water mark and enable*/
1773             ret = regmap_write(wcd->if_regmap,
1774                     WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1775                     WCD934X_SLIM_WATER_MARK_VAL);
1776 
1777             if (ret < 0)
1778                 goto err;
1779         }
1780     }
1781 
1782     dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1783 
1784     return 0;
1785 
1786 err:
1787     dev_err(wcd->dev, "Error Setting slim hw params\n");
1788     kfree(cfg->chs);
1789     cfg->chs = NULL;
1790 
1791     return ret;
1792 }
1793 
1794 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1795                  struct snd_pcm_hw_params *params,
1796                  struct snd_soc_dai *dai)
1797 {
1798     struct wcd934x_codec *wcd;
1799     int ret, tx_fs_rate = 0;
1800 
1801     wcd = snd_soc_component_get_drvdata(dai->component);
1802 
1803     switch (substream->stream) {
1804     case SNDRV_PCM_STREAM_PLAYBACK:
1805         ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1806         if (ret) {
1807             dev_err(wcd->dev, "cannot set sample rate: %u\n",
1808                 params_rate(params));
1809             return ret;
1810         }
1811         switch (params_width(params)) {
1812         case 16 ... 24:
1813             wcd->dai[dai->id].sconfig.bps = params_width(params);
1814             break;
1815         default:
1816             dev_err(wcd->dev, "Invalid format 0x%x\n",
1817                 params_width(params));
1818             return -EINVAL;
1819         }
1820         break;
1821 
1822     case SNDRV_PCM_STREAM_CAPTURE:
1823         switch (params_rate(params)) {
1824         case 8000:
1825             tx_fs_rate = 0;
1826             break;
1827         case 16000:
1828             tx_fs_rate = 1;
1829             break;
1830         case 32000:
1831             tx_fs_rate = 3;
1832             break;
1833         case 48000:
1834             tx_fs_rate = 4;
1835             break;
1836         case 96000:
1837             tx_fs_rate = 5;
1838             break;
1839         case 192000:
1840             tx_fs_rate = 6;
1841             break;
1842         case 384000:
1843             tx_fs_rate = 7;
1844             break;
1845         default:
1846             dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1847                 params_rate(params));
1848             return -EINVAL;
1849 
1850         }
1851 
1852         ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1853                          params_rate(params));
1854         if (ret < 0) {
1855             dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1856             return ret;
1857         }
1858         switch (params_width(params)) {
1859         case 16 ... 32:
1860             wcd->dai[dai->id].sconfig.bps = params_width(params);
1861             break;
1862         default:
1863             dev_err(wcd->dev, "Invalid format 0x%x\n",
1864                 params_width(params));
1865             return -EINVAL;
1866         }
1867         break;
1868     default:
1869         dev_err(wcd->dev, "Invalid stream type %d\n",
1870             substream->stream);
1871         return -EINVAL;
1872     }
1873 
1874     wcd->dai[dai->id].sconfig.rate = params_rate(params);
1875 
1876     return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1877 }
1878 
1879 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1880                struct snd_soc_dai *dai)
1881 {
1882     struct wcd_slim_codec_dai_data *dai_data;
1883     struct wcd934x_codec *wcd;
1884 
1885     wcd = snd_soc_component_get_drvdata(dai->component);
1886 
1887     dai_data = &wcd->dai[dai->id];
1888 
1889     kfree(dai_data->sconfig.chs);
1890 
1891     return 0;
1892 }
1893 
1894 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1895                struct snd_soc_dai *dai)
1896 {
1897     struct wcd_slim_codec_dai_data *dai_data;
1898     struct wcd934x_codec *wcd;
1899     struct slim_stream_config *cfg;
1900 
1901     wcd = snd_soc_component_get_drvdata(dai->component);
1902 
1903     dai_data = &wcd->dai[dai->id];
1904 
1905     switch (cmd) {
1906     case SNDRV_PCM_TRIGGER_START:
1907     case SNDRV_PCM_TRIGGER_RESUME:
1908     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1909         cfg = &dai_data->sconfig;
1910         slim_stream_prepare(dai_data->sruntime, cfg);
1911         slim_stream_enable(dai_data->sruntime);
1912         break;
1913     case SNDRV_PCM_TRIGGER_STOP:
1914     case SNDRV_PCM_TRIGGER_SUSPEND:
1915     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1916         slim_stream_unprepare(dai_data->sruntime);
1917         slim_stream_disable(dai_data->sruntime);
1918         break;
1919     default:
1920         break;
1921     }
1922 
1923     return 0;
1924 }
1925 
1926 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1927                    unsigned int tx_num, unsigned int *tx_slot,
1928                    unsigned int rx_num, unsigned int *rx_slot)
1929 {
1930     struct wcd934x_codec *wcd;
1931     int i;
1932 
1933     wcd = snd_soc_component_get_drvdata(dai->component);
1934 
1935     if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1936         dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1937             tx_num, rx_num);
1938         return -EINVAL;
1939     }
1940 
1941     if (!tx_slot || !rx_slot) {
1942         dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1943             tx_slot, rx_slot);
1944         return -EINVAL;
1945     }
1946 
1947     wcd->num_rx_port = rx_num;
1948     for (i = 0; i < rx_num; i++) {
1949         wcd->rx_chs[i].ch_num = rx_slot[i];
1950         INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1951     }
1952 
1953     wcd->num_tx_port = tx_num;
1954     for (i = 0; i < tx_num; i++) {
1955         wcd->tx_chs[i].ch_num = tx_slot[i];
1956         INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1957     }
1958 
1959     return 0;
1960 }
1961 
1962 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1963                    unsigned int *tx_num, unsigned int *tx_slot,
1964                    unsigned int *rx_num, unsigned int *rx_slot)
1965 {
1966     struct wcd934x_slim_ch *ch;
1967     struct wcd934x_codec *wcd;
1968     int i = 0;
1969 
1970     wcd = snd_soc_component_get_drvdata(dai->component);
1971 
1972     switch (dai->id) {
1973     case AIF1_PB:
1974     case AIF2_PB:
1975     case AIF3_PB:
1976     case AIF4_PB:
1977         if (!rx_slot || !rx_num) {
1978             dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1979                 rx_slot, rx_num);
1980             return -EINVAL;
1981         }
1982 
1983         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1984             rx_slot[i++] = ch->ch_num;
1985 
1986         *rx_num = i;
1987         break;
1988     case AIF1_CAP:
1989     case AIF2_CAP:
1990     case AIF3_CAP:
1991         if (!tx_slot || !tx_num) {
1992             dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1993                 tx_slot, tx_num);
1994             return -EINVAL;
1995         }
1996 
1997         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1998             tx_slot[i++] = ch->ch_num;
1999 
2000         *tx_num = i;
2001         break;
2002     default:
2003         dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2004         break;
2005     }
2006 
2007     return 0;
2008 }
2009 
2010 static const struct snd_soc_dai_ops wcd934x_dai_ops = {
2011     .hw_params = wcd934x_hw_params,
2012     .hw_free = wcd934x_hw_free,
2013     .trigger = wcd934x_trigger,
2014     .set_channel_map = wcd934x_set_channel_map,
2015     .get_channel_map = wcd934x_get_channel_map,
2016 };
2017 
2018 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
2019     [0] = {
2020         .name = "wcd934x_rx1",
2021         .id = AIF1_PB,
2022         .playback = {
2023             .stream_name = "AIF1 Playback",
2024             .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2025             .formats = WCD934X_FORMATS_S16_S24_LE,
2026             .rate_max = 192000,
2027             .rate_min = 8000,
2028             .channels_min = 1,
2029             .channels_max = 2,
2030         },
2031         .ops = &wcd934x_dai_ops,
2032     },
2033     [1] = {
2034         .name = "wcd934x_tx1",
2035         .id = AIF1_CAP,
2036         .capture = {
2037             .stream_name = "AIF1 Capture",
2038             .rates = WCD934X_RATES_MASK,
2039             .formats = SNDRV_PCM_FMTBIT_S16_LE,
2040             .rate_min = 8000,
2041             .rate_max = 192000,
2042             .channels_min = 1,
2043             .channels_max = 4,
2044         },
2045         .ops = &wcd934x_dai_ops,
2046     },
2047     [2] = {
2048         .name = "wcd934x_rx2",
2049         .id = AIF2_PB,
2050         .playback = {
2051             .stream_name = "AIF2 Playback",
2052             .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2053             .formats = WCD934X_FORMATS_S16_S24_LE,
2054             .rate_min = 8000,
2055             .rate_max = 192000,
2056             .channels_min = 1,
2057             .channels_max = 2,
2058         },
2059         .ops = &wcd934x_dai_ops,
2060     },
2061     [3] = {
2062         .name = "wcd934x_tx2",
2063         .id = AIF2_CAP,
2064         .capture = {
2065             .stream_name = "AIF2 Capture",
2066             .rates = WCD934X_RATES_MASK,
2067             .formats = SNDRV_PCM_FMTBIT_S16_LE,
2068             .rate_min = 8000,
2069             .rate_max = 192000,
2070             .channels_min = 1,
2071             .channels_max = 4,
2072         },
2073         .ops = &wcd934x_dai_ops,
2074     },
2075     [4] = {
2076         .name = "wcd934x_rx3",
2077         .id = AIF3_PB,
2078         .playback = {
2079             .stream_name = "AIF3 Playback",
2080             .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2081             .formats = WCD934X_FORMATS_S16_S24_LE,
2082             .rate_min = 8000,
2083             .rate_max = 192000,
2084             .channels_min = 1,
2085             .channels_max = 2,
2086         },
2087         .ops = &wcd934x_dai_ops,
2088     },
2089     [5] = {
2090         .name = "wcd934x_tx3",
2091         .id = AIF3_CAP,
2092         .capture = {
2093             .stream_name = "AIF3 Capture",
2094             .rates = WCD934X_RATES_MASK,
2095             .formats = SNDRV_PCM_FMTBIT_S16_LE,
2096             .rate_min = 8000,
2097             .rate_max = 192000,
2098             .channels_min = 1,
2099             .channels_max = 4,
2100         },
2101         .ops = &wcd934x_dai_ops,
2102     },
2103     [6] = {
2104         .name = "wcd934x_rx4",
2105         .id = AIF4_PB,
2106         .playback = {
2107             .stream_name = "AIF4 Playback",
2108             .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2109             .formats = WCD934X_FORMATS_S16_S24_LE,
2110             .rate_min = 8000,
2111             .rate_max = 192000,
2112             .channels_min = 1,
2113             .channels_max = 2,
2114         },
2115         .ops = &wcd934x_dai_ops,
2116     },
2117 };
2118 
2119 static int swclk_gate_enable(struct clk_hw *hw)
2120 {
2121     return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2122 }
2123 
2124 static void swclk_gate_disable(struct clk_hw *hw)
2125 {
2126     wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2127 }
2128 
2129 static int swclk_gate_is_enabled(struct clk_hw *hw)
2130 {
2131     struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2132     int ret, val;
2133 
2134     regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2135     ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2136 
2137     return ret;
2138 }
2139 
2140 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2141                        unsigned long parent_rate)
2142 {
2143     return parent_rate / 2;
2144 }
2145 
2146 static const struct clk_ops swclk_gate_ops = {
2147     .prepare = swclk_gate_enable,
2148     .unprepare = swclk_gate_disable,
2149     .is_enabled = swclk_gate_is_enabled,
2150     .recalc_rate = swclk_recalc_rate,
2151 
2152 };
2153 
2154 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2155 {
2156     struct clk *parent = wcd->extclk;
2157     struct device *dev = wcd->dev;
2158     struct device_node *np = dev->parent->of_node;
2159     const char *parent_clk_name = NULL;
2160     const char *clk_name = "mclk";
2161     struct clk_hw *hw;
2162     struct clk_init_data init;
2163     int ret;
2164 
2165     if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2166         return NULL;
2167 
2168     parent_clk_name = __clk_get_name(parent);
2169 
2170     of_property_read_string(np, "clock-output-names", &clk_name);
2171 
2172     init.name = clk_name;
2173     init.ops = &swclk_gate_ops;
2174     init.flags = 0;
2175     init.parent_names = &parent_clk_name;
2176     init.num_parents = 1;
2177     wcd->hw.init = &init;
2178 
2179     hw = &wcd->hw;
2180     ret = devm_clk_hw_register(wcd->dev->parent, hw);
2181     if (ret)
2182         return ERR_PTR(ret);
2183 
2184     ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2185     if (ret)
2186         return ERR_PTR(ret);
2187 
2188     return NULL;
2189 }
2190 
2191 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
2192                    u32 *micb_mv)
2193 {
2194     int mv;
2195 
2196     if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2197         dev_err(dev, "%s value not found, using default\n", micbias);
2198         mv = WCD934X_DEF_MICBIAS_MV;
2199     } else {
2200         /* convert it to milli volts */
2201         mv = mv/1000;
2202     }
2203 
2204     if (mv < 1000 || mv > 2850) {
2205         dev_err(dev, "%s value not in valid range, using default\n",
2206             micbias);
2207         mv = WCD934X_DEF_MICBIAS_MV;
2208     }
2209 
2210     *micb_mv = mv;
2211 
2212     return (mv - 1000) / 50;
2213 }
2214 
2215 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2216 {
2217     int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2218     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2219     u32 def_dmic_rate, dmic_clk_drv;
2220 
2221     vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2222                          "qcom,micbias1-microvolt",
2223                          &wcd->micb1_mv);
2224     vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2225                          "qcom,micbias2-microvolt",
2226                          &wcd->micb2_mv);
2227     vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2228                          "qcom,micbias3-microvolt",
2229                          &wcd->micb3_mv);
2230     vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2231                          "qcom,micbias4-microvolt",
2232                          &wcd->micb4_mv);
2233 
2234     snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2235                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
2236     snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2237                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
2238     snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2239                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
2240     snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2241                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
2242 
2243     if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2244         def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2245     else
2246         def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2247 
2248     wcd->dmic_sample_rate = def_dmic_rate;
2249 
2250     dmic_clk_drv = 0;
2251     snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2252                       0x0C, dmic_clk_drv << 2);
2253 
2254     return 0;
2255 }
2256 
2257 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2258 {
2259     struct regmap *rm = wcd->regmap;
2260 
2261     /* set SPKR rate to FS_2P4_3P072 */
2262     regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2263     regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2264 
2265     /* Take DMICs out of reset */
2266     regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2267 }
2268 
2269 static int wcd934x_comp_init(struct snd_soc_component *component)
2270 {
2271     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2272 
2273     wcd934x_hw_init(wcd);
2274     wcd934x_enable_efuse_sensing(wcd);
2275     wcd934x_get_version(wcd);
2276 
2277     return 0;
2278 }
2279 
2280 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2281 {
2282     struct wcd934x_codec *wcd = data;
2283     unsigned long status = 0;
2284     int i, j, port_id;
2285     unsigned int val, int_val = 0;
2286     irqreturn_t ret = IRQ_NONE;
2287     bool tx;
2288     unsigned short reg = 0;
2289 
2290     for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2291          i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2292         regmap_read(wcd->if_regmap, i, &val);
2293         status |= ((u32)val << (8 * j));
2294     }
2295 
2296     for_each_set_bit(j, &status, 32) {
2297         tx = false;
2298         port_id = j;
2299 
2300         if (j >= 16) {
2301             tx = true;
2302             port_id = j - 16;
2303         }
2304 
2305         regmap_read(wcd->if_regmap,
2306                 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2307         if (val) {
2308             if (!tx)
2309                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2310                     (port_id / 8);
2311             else
2312                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2313                     (port_id / 8);
2314             regmap_read(wcd->if_regmap, reg, &int_val);
2315         }
2316 
2317         if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2318             dev_err_ratelimited(wcd->dev,
2319                         "overflow error on %s port %d, value %x\n",
2320                         (tx ? "TX" : "RX"), port_id, val);
2321 
2322         if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2323             dev_err_ratelimited(wcd->dev,
2324                         "underflow error on %s port %d, value %x\n",
2325                         (tx ? "TX" : "RX"), port_id, val);
2326 
2327         if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2328             (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2329             if (!tx)
2330                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2331                     (port_id / 8);
2332             else
2333                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2334                     (port_id / 8);
2335             regmap_read(
2336                 wcd->if_regmap, reg, &int_val);
2337             if (int_val & (1 << (port_id % 8))) {
2338                 int_val = int_val ^ (1 << (port_id % 8));
2339                 regmap_write(wcd->if_regmap,
2340                          reg, int_val);
2341             }
2342         }
2343 
2344         if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2345             dev_err_ratelimited(wcd->dev,
2346                         "Port Closed %s port %d, value %x\n",
2347                         (tx ? "TX" : "RX"), port_id, val);
2348 
2349         regmap_write(wcd->if_regmap,
2350                  WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2351                 BIT(j % 8));
2352         ret = IRQ_HANDLED;
2353     }
2354 
2355     return ret;
2356 }
2357 
2358 static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
2359                    bool enable)
2360 {
2361     snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
2362                       WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
2363 }
2364 
2365 static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2366                        bool enable)
2367 {
2368     snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
2369                       WCD934X_ANA_MBHC_BIAS_EN, enable);
2370 }
2371 
2372 static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
2373                      int *btn_low, int *btn_high,
2374                      int num_btn, bool is_micbias)
2375 {
2376     int i, vth;
2377 
2378     if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2379         dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2380             __func__, num_btn);
2381         return;
2382     }
2383 
2384     for (i = 0; i < num_btn; i++) {
2385         vth = ((btn_high[i] * 2) / 25) & 0x3F;
2386         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
2387                        WCD934X_MBHC_BTN_VTH_MASK, vth);
2388     }
2389 }
2390 
2391 static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2392 {
2393     u8 val;
2394 
2395     if (micb_num == MIC_BIAS_2) {
2396         val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2397                            WCD934X_ANA_MICB2_ENABLE_MASK);
2398         if (val == WCD934X_MICB_ENABLE)
2399             return true;
2400     }
2401     return false;
2402 }
2403 
2404 static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2405                            enum mbhc_hs_pullup_iref pull_up_cur)
2406 {
2407     /* Default pull up current to 2uA */
2408     if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
2409         pull_up_cur == I_DEFAULT)
2410         pull_up_cur = I_2P0_UA;
2411 
2412 
2413     snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
2414                       WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
2415 }
2416 
2417 static int wcd934x_micbias_control(struct snd_soc_component *component,
2418                 int micb_num, int req, bool is_dapm)
2419 {
2420     struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2421     int micb_index = micb_num - 1;
2422     u16 micb_reg;
2423 
2424     switch (micb_num) {
2425     case MIC_BIAS_1:
2426         micb_reg = WCD934X_ANA_MICB1;
2427         break;
2428     case MIC_BIAS_2:
2429         micb_reg = WCD934X_ANA_MICB2;
2430         break;
2431     case MIC_BIAS_3:
2432         micb_reg = WCD934X_ANA_MICB3;
2433         break;
2434     case MIC_BIAS_4:
2435         micb_reg = WCD934X_ANA_MICB4;
2436         break;
2437     default:
2438         dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2439             __func__, micb_num);
2440         return -EINVAL;
2441     }
2442     mutex_lock(&wcd934x->micb_lock);
2443 
2444     switch (req) {
2445     case MICB_PULLUP_ENABLE:
2446         wcd934x->pullup_ref[micb_index]++;
2447         if ((wcd934x->pullup_ref[micb_index] == 1) &&
2448             (wcd934x->micb_ref[micb_index] == 0))
2449             snd_soc_component_write_field(component, micb_reg,
2450                               WCD934X_ANA_MICB_EN_MASK,
2451                               WCD934X_MICB_PULL_UP);
2452         break;
2453     case MICB_PULLUP_DISABLE:
2454         if (wcd934x->pullup_ref[micb_index] > 0)
2455             wcd934x->pullup_ref[micb_index]--;
2456 
2457         if ((wcd934x->pullup_ref[micb_index] == 0) &&
2458             (wcd934x->micb_ref[micb_index] == 0))
2459             snd_soc_component_write_field(component, micb_reg,
2460                               WCD934X_ANA_MICB_EN_MASK, 0);
2461         break;
2462     case MICB_ENABLE:
2463         wcd934x->micb_ref[micb_index]++;
2464         if (wcd934x->micb_ref[micb_index] == 1) {
2465             snd_soc_component_write_field(component, micb_reg,
2466                               WCD934X_ANA_MICB_EN_MASK,
2467                               WCD934X_MICB_ENABLE);
2468             if (micb_num  == MIC_BIAS_2)
2469                 wcd_mbhc_event_notify(wcd934x->mbhc,
2470                               WCD_EVENT_POST_MICBIAS_2_ON);
2471         }
2472 
2473         if (micb_num  == MIC_BIAS_2 && is_dapm)
2474             wcd_mbhc_event_notify(wcd934x->mbhc,
2475                           WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2476         break;
2477     case MICB_DISABLE:
2478         if (wcd934x->micb_ref[micb_index] > 0)
2479             wcd934x->micb_ref[micb_index]--;
2480 
2481         if ((wcd934x->micb_ref[micb_index] == 0) &&
2482             (wcd934x->pullup_ref[micb_index] > 0))
2483             snd_soc_component_write_field(component, micb_reg,
2484                               WCD934X_ANA_MICB_EN_MASK,
2485                               WCD934X_MICB_PULL_UP);
2486         else if ((wcd934x->micb_ref[micb_index] == 0) &&
2487              (wcd934x->pullup_ref[micb_index] == 0)) {
2488             if (micb_num  == MIC_BIAS_2)
2489                 wcd_mbhc_event_notify(wcd934x->mbhc,
2490                               WCD_EVENT_PRE_MICBIAS_2_OFF);
2491 
2492             snd_soc_component_write_field(component, micb_reg,
2493                               WCD934X_ANA_MICB_EN_MASK, 0);
2494             if (micb_num  == MIC_BIAS_2)
2495                 wcd_mbhc_event_notify(wcd934x->mbhc,
2496                               WCD_EVENT_POST_MICBIAS_2_OFF);
2497         }
2498         if (is_dapm && micb_num  == MIC_BIAS_2)
2499             wcd_mbhc_event_notify(wcd934x->mbhc,
2500                           WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2501         break;
2502     }
2503 
2504     mutex_unlock(&wcd934x->micb_lock);
2505 
2506     return 0;
2507 }
2508 
2509 static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
2510                     int micb_num, int req)
2511 {
2512     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2513     int ret;
2514 
2515     if (req == MICB_ENABLE)
2516         __wcd934x_cdc_mclk_enable(wcd, true);
2517 
2518     ret = wcd934x_micbias_control(component, micb_num, req, false);
2519 
2520     if (req == MICB_DISABLE)
2521         __wcd934x_cdc_mclk_enable(wcd, false);
2522 
2523     return ret;
2524 }
2525 
2526 static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2527                        bool enable)
2528 {
2529     if (enable) {
2530         snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2531                     WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
2532         snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2533                     WCD934X_RAMP_EN_MASK, 1);
2534     } else {
2535         snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2536                     WCD934X_RAMP_EN_MASK, 0);
2537         snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2538                     WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
2539     }
2540 }
2541 
2542 static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
2543 {
2544     /* min micbias voltage is 1V and maximum is 2.85V */
2545     if (micb_mv < 1000 || micb_mv > 2850)
2546         return -EINVAL;
2547 
2548     return (micb_mv - 1000) / 50;
2549 }
2550 
2551 static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
2552                         int req_volt, int micb_num)
2553 {
2554     struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2555     int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
2556 
2557     switch (micb_num) {
2558     case MIC_BIAS_1:
2559         micb_reg = WCD934X_ANA_MICB1;
2560         break;
2561     case MIC_BIAS_2:
2562         micb_reg = WCD934X_ANA_MICB2;
2563         break;
2564     case MIC_BIAS_3:
2565         micb_reg = WCD934X_ANA_MICB3;
2566         break;
2567     case MIC_BIAS_4:
2568         micb_reg = WCD934X_ANA_MICB4;
2569         break;
2570     default:
2571         return -EINVAL;
2572     }
2573     mutex_lock(&wcd934x->micb_lock);
2574     /*
2575      * If requested micbias voltage is same as current micbias
2576      * voltage, then just return. Otherwise, adjust voltage as
2577      * per requested value. If micbias is already enabled, then
2578      * to avoid slow micbias ramp-up or down enable pull-up
2579      * momentarily, change the micbias value and then re-enable
2580      * micbias.
2581      */
2582     micb_en = snd_soc_component_read_field(component, micb_reg,
2583                         WCD934X_ANA_MICB_EN_MASK);
2584     cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2585                             WCD934X_MICB_VAL_MASK);
2586 
2587     req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
2588     if (req_vout_ctl < 0) {
2589         ret = -EINVAL;
2590         goto exit;
2591     }
2592 
2593     if (cur_vout_ctl == req_vout_ctl) {
2594         ret = 0;
2595         goto exit;
2596     }
2597 
2598     if (micb_en == WCD934X_MICB_ENABLE)
2599         snd_soc_component_write_field(component, micb_reg,
2600                           WCD934X_ANA_MICB_EN_MASK,
2601                           WCD934X_MICB_PULL_UP);
2602 
2603     snd_soc_component_write_field(component, micb_reg,
2604                       WCD934X_MICB_VAL_MASK,
2605                       req_vout_ctl);
2606 
2607     if (micb_en == WCD934X_MICB_ENABLE) {
2608         snd_soc_component_write_field(component, micb_reg,
2609                           WCD934X_ANA_MICB_EN_MASK,
2610                           WCD934X_MICB_ENABLE);
2611         /*
2612          * Add 2ms delay as per HW requirement after enabling
2613          * micbias
2614          */
2615         usleep_range(2000, 2100);
2616     }
2617 exit:
2618     mutex_unlock(&wcd934x->micb_lock);
2619     return ret;
2620 }
2621 
2622 static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2623                         int micb_num, bool req_en)
2624 {
2625     struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2626     int rc, micb_mv;
2627 
2628     if (micb_num != MIC_BIAS_2)
2629         return -EINVAL;
2630     /*
2631      * If device tree micbias level is already above the minimum
2632      * voltage needed to detect threshold microphone, then do
2633      * not change the micbias, just return.
2634      */
2635     if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2636         return 0;
2637 
2638     micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
2639 
2640     rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2641 
2642     return rc;
2643 }
2644 
2645 static inline void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
2646                         s16 *d1_a, u16 noff,
2647                         int32_t *zdet)
2648 {
2649     int i;
2650     int val, val1;
2651     s16 c1;
2652     s32 x1, d1;
2653     int32_t denom;
2654     int minCode_param[] = {
2655             3277, 1639, 820, 410, 205, 103, 52, 26
2656     };
2657 
2658     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
2659     for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
2660         regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2661         if (val & 0x80)
2662             break;
2663     }
2664     val = val << 0x8;
2665     regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
2666     val |= val1;
2667     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
2668     x1 = WCD934X_MBHC_GET_X1(val);
2669     c1 = WCD934X_MBHC_GET_C1(val);
2670     /* If ramp is not complete, give additional 5ms */
2671     if ((c1 < 2) && x1)
2672         usleep_range(5000, 5050);
2673 
2674     if (!c1 || !x1) {
2675         dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2676             __func__, c1, x1);
2677         goto ramp_down;
2678     }
2679     d1 = d1_a[c1];
2680     denom = (x1 * d1) - (1 << (14 - noff));
2681     if (denom > 0)
2682         *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
2683     else if (x1 < minCode_param[noff])
2684         *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
2685 
2686     dev_info(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2687         __func__, d1, c1, x1, *zdet);
2688 ramp_down:
2689     i = 0;
2690 
2691     while (x1) {
2692         regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2693         regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
2694         val = val << 0x08;
2695         val |= val1;
2696         x1 = WCD934X_MBHC_GET_X1(val);
2697         i++;
2698         if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
2699             break;
2700     }
2701 }
2702 
2703 static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
2704                  struct wcd934x_mbhc_zdet_param *zdet_param,
2705                  int32_t *zl, int32_t *zr, s16 *d1_a)
2706 {
2707     struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2708     int32_t zdet = 0;
2709 
2710     snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2711                 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2712     snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
2713                     WCD934X_VTH_MASK, zdet_param->btn5);
2714     snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
2715                       WCD934X_VTH_MASK, zdet_param->btn6);
2716     snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
2717                      WCD934X_VTH_MASK, zdet_param->btn7);
2718     snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2719                 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2720     snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
2721                 0x0F, zdet_param->nshift);
2722 
2723     if (!zl)
2724         goto z_right;
2725     /* Start impedance measurement for HPH_L */
2726     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
2727     wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2728     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
2729 
2730     *zl = zdet;
2731 
2732 z_right:
2733     if (!zr)
2734         return;
2735     /* Start impedance measurement for HPH_R */
2736     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
2737     wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2738     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
2739 
2740     *zr = zdet;
2741 }
2742 
2743 static inline void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2744                           int32_t *z_val, int flag_l_r)
2745 {
2746     s16 q1;
2747     int q1_cal;
2748 
2749     if (*z_val < (WCD934X_ZDET_VAL_400/1000))
2750         q1 = snd_soc_component_read(component,
2751             WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
2752     else
2753         q1 = snd_soc_component_read(component,
2754             WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
2755     if (q1 & 0x80)
2756         q1_cal = (10000 - ((q1 & 0x7F) * 25));
2757     else
2758         q1_cal = (10000 + (q1 * 25));
2759     if (q1_cal > 0)
2760         *z_val = ((*z_val) * 10000) / q1_cal;
2761 }
2762 
2763 static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2764                         uint32_t *zl, uint32_t *zr)
2765 {
2766     struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2767     s16 reg0, reg1, reg2, reg3, reg4;
2768     int32_t z1L, z1R, z1Ls;
2769     int zMono, z_diff1, z_diff2;
2770     bool is_fsm_disable = false;
2771     struct wcd934x_mbhc_zdet_param zdet_param[] = {
2772         {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2773         {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2774         {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2775         {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2776     };
2777     struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
2778     s16 d1_a[][4] = {
2779         {0, 30, 90, 30},
2780         {0, 30, 30, 5},
2781         {0, 30, 30, 5},
2782         {0, 30, 30, 5},
2783     };
2784     s16 *d1 = NULL;
2785 
2786     reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
2787     reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2788     reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
2789     reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
2790     reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
2791 
2792     if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
2793         is_fsm_disable = true;
2794         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
2795     }
2796 
2797     /* For NO-jack, disable L_DET_EN before Z-det measurements */
2798     if (wcd934x->mbhc_cfg.hphl_swh)
2799         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
2800 
2801     /* Turn off 100k pull down on HPHL */
2802     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
2803 
2804     /* First get impedance on Left */
2805     d1 = d1_a[1];
2806     zdet_param_ptr = &zdet_param[1];
2807     wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2808 
2809     if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2810         goto left_ch_impedance;
2811 
2812     /* Second ramp for left ch */
2813     if (z1L < WCD934X_ZDET_VAL_32) {
2814         zdet_param_ptr = &zdet_param[0];
2815         d1 = d1_a[0];
2816     } else if ((z1L > WCD934X_ZDET_VAL_400) &&
2817           (z1L <= WCD934X_ZDET_VAL_1200)) {
2818         zdet_param_ptr = &zdet_param[2];
2819         d1 = d1_a[2];
2820     } else if (z1L > WCD934X_ZDET_VAL_1200) {
2821         zdet_param_ptr = &zdet_param[3];
2822         d1 = d1_a[3];
2823     }
2824     wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2825 
2826 left_ch_impedance:
2827     if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2828         (z1L > WCD934X_ZDET_VAL_100K)) {
2829         *zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
2830         zdet_param_ptr = &zdet_param[1];
2831         d1 = d1_a[1];
2832     } else {
2833         *zl = z1L/1000;
2834         wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
2835     }
2836     dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2837         __func__, *zl);
2838 
2839     /* Start of right impedance ramp and calculation */
2840     wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2841     if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2842         if (((z1R > WCD934X_ZDET_VAL_1200) &&
2843             (zdet_param_ptr->noff == 0x6)) ||
2844             ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
2845             goto right_ch_impedance;
2846         /* Second ramp for right ch */
2847         if (z1R < WCD934X_ZDET_VAL_32) {
2848             zdet_param_ptr = &zdet_param[0];
2849             d1 = d1_a[0];
2850         } else if ((z1R > WCD934X_ZDET_VAL_400) &&
2851             (z1R <= WCD934X_ZDET_VAL_1200)) {
2852             zdet_param_ptr = &zdet_param[2];
2853             d1 = d1_a[2];
2854         } else if (z1R > WCD934X_ZDET_VAL_1200) {
2855             zdet_param_ptr = &zdet_param[3];
2856             d1 = d1_a[3];
2857         }
2858         wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2859     }
2860 right_ch_impedance:
2861     if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2862         (z1R > WCD934X_ZDET_VAL_100K)) {
2863         *zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
2864     } else {
2865         *zr = z1R/1000;
2866         wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
2867     }
2868     dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2869         __func__, *zr);
2870 
2871     /* Mono/stereo detection */
2872     if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
2873         (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
2874         dev_dbg(component->dev,
2875             "%s: plug type is invalid or extension cable\n",
2876             __func__);
2877         goto zdet_complete;
2878     }
2879     if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2880         (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2881         ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2882         ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2883         dev_dbg(component->dev,
2884             "%s: Mono plug type with one ch floating or shorted to GND\n",
2885             __func__);
2886         wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2887         goto zdet_complete;
2888     }
2889     snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2890                       WCD934X_HPHPA_GND_OVR_MASK, 1);
2891     snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2892                       WCD934X_HPHPA_GND_R_MASK, 1);
2893     if (*zl < (WCD934X_ZDET_VAL_32/1000))
2894         wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2895     else
2896         wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2897     snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2898                       WCD934X_HPHPA_GND_R_MASK, 0);
2899     snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2900                       WCD934X_HPHPA_GND_OVR_MASK, 0);
2901     z1Ls /= 1000;
2902     wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2903     /* Parallel of left Z and 9 ohm pull down resistor */
2904     zMono = ((*zl) * 9) / ((*zl) + 9);
2905     z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2906     z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2907     if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2908         dev_err(component->dev, "%s: stereo plug type detected\n",
2909             __func__);
2910         wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
2911     } else {
2912         dev_err(component->dev, "%s: MONO plug type detected\n",
2913             __func__);
2914         wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2915     }
2916 
2917 zdet_complete:
2918     snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
2919     snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
2920     snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
2921     /* Turn on 100k pull down on HPHL */
2922     regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
2923 
2924     /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2925     if (wcd934x->mbhc_cfg.hphl_swh)
2926         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
2927 
2928     snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2929     snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
2930     if (is_fsm_disable)
2931         regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
2932 }
2933 
2934 static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2935             bool enable)
2936 {
2937     if (enable) {
2938         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2939                           WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
2940         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2941                           WCD934X_MBHC_GND_DET_EN_MASK, 1);
2942     } else {
2943         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2944                           WCD934X_MBHC_GND_DET_EN_MASK, 0);
2945         snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2946                           WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
2947     }
2948 }
2949 
2950 static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2951                       bool enable)
2952 {
2953     snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2954                       WCD934X_HPHPA_GND_R_MASK, enable);
2955     snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2956                       WCD934X_HPHPA_GND_L_MASK, enable);
2957 }
2958 
2959 static const struct wcd_mbhc_cb mbhc_cb = {
2960     .clk_setup = wcd934x_mbhc_clk_setup,
2961     .mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
2962     .set_btn_thr = wcd934x_mbhc_program_btn_thr,
2963     .micbias_enable_status = wcd934x_mbhc_micb_en_status,
2964     .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
2965     .mbhc_micbias_control = wcd934x_mbhc_request_micbias,
2966     .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
2967     .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
2968     .compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
2969     .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
2970     .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
2971 };
2972 
2973 static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
2974                   struct snd_ctl_elem_value *ucontrol)
2975 {
2976     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2977     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2978 
2979     ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
2980 
2981     return 0;
2982 }
2983 
2984 static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2985                    struct snd_ctl_elem_value *ucontrol)
2986 {
2987     uint32_t zl, zr;
2988     bool hphr;
2989     struct soc_mixer_control *mc;
2990     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2991     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2992 
2993     mc = (struct soc_mixer_control *)(kcontrol->private_value);
2994     hphr = mc->shift;
2995     wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
2996     dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2997     ucontrol->value.integer.value[0] = hphr ? zr : zl;
2998 
2999     return 0;
3000 }
3001 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3002     SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
3003                wcd934x_get_hph_type, NULL),
3004 };
3005 
3006 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3007     SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3008                wcd934x_hph_impedance_get, NULL),
3009     SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3010                wcd934x_hph_impedance_get, NULL),
3011 };
3012 
3013 static int wcd934x_mbhc_init(struct snd_soc_component *component)
3014 {
3015     struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
3016     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3017     struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
3018 
3019     intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
3020                              WCD934X_IRQ_MBHC_SW_DET);
3021     intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
3022                                 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
3023     intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
3024                                   WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
3025     intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
3026                              WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3027     intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
3028                              WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
3029     intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
3030                              WCD934X_IRQ_HPH_PA_OCPL_FAULT);
3031     intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
3032                               WCD934X_IRQ_HPH_PA_OCPR_FAULT);
3033 
3034     wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3035     if (IS_ERR(wcd->mbhc)) {
3036         wcd->mbhc = NULL;
3037         return -EINVAL;
3038     }
3039 
3040     snd_soc_add_component_controls(component, impedance_detect_controls,
3041                        ARRAY_SIZE(impedance_detect_controls));
3042     snd_soc_add_component_controls(component, hph_type_detect_controls,
3043                        ARRAY_SIZE(hph_type_detect_controls));
3044 
3045     return 0;
3046 }
3047 static int wcd934x_comp_probe(struct snd_soc_component *component)
3048 {
3049     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3050     int i;
3051 
3052     snd_soc_component_init_regmap(component, wcd->regmap);
3053     wcd->component = component;
3054 
3055     /* Class-H Init*/
3056     wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
3057     if (IS_ERR(wcd->clsh_ctrl))
3058         return PTR_ERR(wcd->clsh_ctrl);
3059 
3060     /* Default HPH Mode to Class-H Low HiFi */
3061     wcd->hph_mode = CLS_H_LOHIFI;
3062 
3063     wcd934x_comp_init(component);
3064 
3065     for (i = 0; i < NUM_CODEC_DAIS; i++)
3066         INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
3067 
3068     wcd934x_init_dmic(component);
3069 
3070     if (wcd934x_mbhc_init(component))
3071         dev_err(component->dev, "Failed to Initialize MBHC\n");
3072 
3073     return 0;
3074 }
3075 
3076 static void wcd934x_comp_remove(struct snd_soc_component *comp)
3077 {
3078     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3079 
3080     wcd_clsh_ctrl_free(wcd->clsh_ctrl);
3081 }
3082 
3083 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
3084                    int clk_id, int source,
3085                    unsigned int freq, int dir)
3086 {
3087     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3088     int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3089 
3090     wcd->rate = freq;
3091 
3092     if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
3093         val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3094 
3095     snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
3096                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
3097                       val);
3098 
3099     return clk_set_rate(wcd->extclk, freq);
3100 }
3101 
3102 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
3103                    int iir_idx, int band_idx, int coeff_idx)
3104 {
3105     u32 value = 0;
3106     int reg, b2_reg;
3107 
3108     /* Address does not automatically update if reading */
3109     reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3110     b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3111 
3112     snd_soc_component_write(component, reg,
3113                 ((band_idx * BAND_MAX + coeff_idx) *
3114                  sizeof(uint32_t)) & 0x7F);
3115 
3116     value |= snd_soc_component_read(component, b2_reg);
3117     snd_soc_component_write(component, reg,
3118                 ((band_idx * BAND_MAX + coeff_idx)
3119                  * sizeof(uint32_t) + 1) & 0x7F);
3120 
3121     value |= (snd_soc_component_read(component, b2_reg) << 8);
3122     snd_soc_component_write(component, reg,
3123                 ((band_idx * BAND_MAX + coeff_idx)
3124                  * sizeof(uint32_t) + 2) & 0x7F);
3125 
3126     value |= (snd_soc_component_read(component, b2_reg) << 16);
3127     snd_soc_component_write(component, reg,
3128         ((band_idx * BAND_MAX + coeff_idx)
3129         * sizeof(uint32_t) + 3) & 0x7F);
3130 
3131     /* Mask bits top 2 bits since they are reserved */
3132     value |= (snd_soc_component_read(component, b2_reg) << 24);
3133     return value;
3134 }
3135 
3136 static void set_iir_band_coeff(struct snd_soc_component *component,
3137                    int iir_idx, int band_idx, uint32_t value)
3138 {
3139     int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3140 
3141     snd_soc_component_write(component, reg, (value & 0xFF));
3142     snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
3143     snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
3144     /* Mask top 2 bits, 7-8 are reserved */
3145     snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
3146 }
3147 
3148 static int wcd934x_put_iir_band_audio_mixer(
3149                     struct snd_kcontrol *kcontrol,
3150                     struct snd_ctl_elem_value *ucontrol)
3151 {
3152     struct snd_soc_component *component =
3153             snd_soc_kcontrol_component(kcontrol);
3154     struct wcd_iir_filter_ctl *ctl =
3155             (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3156     struct soc_bytes_ext *params = &ctl->bytes_ext;
3157     int iir_idx = ctl->iir_idx;
3158     int band_idx = ctl->band_idx;
3159     u32 coeff[BAND_MAX];
3160     int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3161 
3162     memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
3163 
3164     /* Mask top bit it is reserved */
3165     /* Updates addr automatically for each B2 write */
3166     snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
3167                          sizeof(uint32_t)) & 0x7F);
3168 
3169     set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
3170     set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
3171     set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
3172     set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
3173     set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
3174 
3175     return 0;
3176 }
3177 
3178 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
3179                     struct snd_ctl_elem_value *ucontrol)
3180 {
3181     struct snd_soc_component *component =
3182             snd_soc_kcontrol_component(kcontrol);
3183     struct wcd_iir_filter_ctl *ctl =
3184             (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3185     struct soc_bytes_ext *params = &ctl->bytes_ext;
3186     int iir_idx = ctl->iir_idx;
3187     int band_idx = ctl->band_idx;
3188     u32 coeff[BAND_MAX];
3189 
3190     coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
3191     coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
3192     coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
3193     coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
3194     coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
3195 
3196     memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
3197 
3198     return 0;
3199 }
3200 
3201 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
3202                    struct snd_ctl_elem_info *ucontrol)
3203 {
3204     struct wcd_iir_filter_ctl *ctl =
3205         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3206     struct soc_bytes_ext *params = &ctl->bytes_ext;
3207 
3208     ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3209     ucontrol->count = params->max;
3210 
3211     return 0;
3212 }
3213 
3214 static int wcd934x_compander_get(struct snd_kcontrol *kc,
3215                  struct snd_ctl_elem_value *ucontrol)
3216 {
3217     struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3218     int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3219     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3220 
3221     ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
3222 
3223     return 0;
3224 }
3225 
3226 static int wcd934x_compander_set(struct snd_kcontrol *kc,
3227                  struct snd_ctl_elem_value *ucontrol)
3228 {
3229     struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3230     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3231     int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3232     int value = ucontrol->value.integer.value[0];
3233     int sel;
3234 
3235     if (wcd->comp_enabled[comp] == value)
3236         return 0;
3237 
3238     wcd->comp_enabled[comp] = value;
3239     sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
3240         WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
3241 
3242     /* Any specific register configuration for compander */
3243     switch (comp) {
3244     case COMPANDER_1:
3245         /* Set Gain Source Select based on compander enable/disable */
3246         snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
3247                           WCD934X_HPH_GAIN_SRC_SEL_MASK,
3248                           sel);
3249         break;
3250     case COMPANDER_2:
3251         snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
3252                           WCD934X_HPH_GAIN_SRC_SEL_MASK,
3253                           sel);
3254         break;
3255     case COMPANDER_3:
3256     case COMPANDER_4:
3257     case COMPANDER_7:
3258     case COMPANDER_8:
3259         break;
3260     default:
3261         return 0;
3262     }
3263 
3264     return 1;
3265 }
3266 
3267 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
3268                    struct snd_ctl_elem_value *ucontrol)
3269 {
3270     struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3271     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3272 
3273     ucontrol->value.enumerated.item[0] = wcd->hph_mode;
3274 
3275     return 0;
3276 }
3277 
3278 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
3279                    struct snd_ctl_elem_value *ucontrol)
3280 {
3281     struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3282     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3283     u32 mode_val;
3284 
3285     mode_val = ucontrol->value.enumerated.item[0];
3286 
3287     if (mode_val == wcd->hph_mode)
3288         return 0;
3289 
3290     if (mode_val == 0) {
3291         dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
3292         mode_val = CLS_H_LOHIFI;
3293     }
3294     wcd->hph_mode = mode_val;
3295 
3296     return 1;
3297 }
3298 
3299 static int slim_rx_mux_get(struct snd_kcontrol *kc,
3300                struct snd_ctl_elem_value *ucontrol)
3301 {
3302     struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3303     struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3304     struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3305 
3306     ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
3307 
3308     return 0;
3309 }
3310 
3311 static int slim_rx_mux_to_dai_id(int mux)
3312 {
3313     int aif_id;
3314 
3315     switch (mux) {
3316     case 1:
3317         aif_id = AIF1_PB;
3318         break;
3319     case 2:
3320         aif_id = AIF2_PB;
3321         break;
3322     case 3:
3323         aif_id = AIF3_PB;
3324         break;
3325     case 4:
3326         aif_id = AIF4_PB;
3327         break;
3328     default:
3329         aif_id = -1;
3330         break;
3331     }
3332 
3333     return aif_id;
3334 }
3335 
3336 static int slim_rx_mux_put(struct snd_kcontrol *kc,
3337                struct snd_ctl_elem_value *ucontrol)
3338 {
3339     struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3340     struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
3341     struct soc_enum *e = (struct soc_enum *)kc->private_value;
3342     struct snd_soc_dapm_update *update = NULL;
3343     struct wcd934x_slim_ch *ch, *c;
3344     u32 port_id = w->shift;
3345     bool found = false;
3346     int mux_idx;
3347     int prev_mux_idx = wcd->rx_port_value[port_id];
3348     int aif_id;
3349 
3350     mux_idx = ucontrol->value.enumerated.item[0];
3351 
3352     if (mux_idx == prev_mux_idx)
3353         return 0;
3354 
3355     switch(mux_idx) {
3356     case 0:
3357         aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
3358         if (aif_id < 0)
3359             return 0;
3360 
3361         list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
3362             if (ch->port == port_id + WCD934X_RX_START) {
3363                 found = true;
3364                 list_del_init(&ch->list);
3365                 break;
3366             }
3367         }
3368         if (!found)
3369             return 0;
3370 
3371         break;
3372     case 1 ... 4:
3373         aif_id = slim_rx_mux_to_dai_id(mux_idx);
3374         if (aif_id < 0)
3375             return 0;
3376 
3377         if (list_empty(&wcd->rx_chs[port_id].list)) {
3378             list_add_tail(&wcd->rx_chs[port_id].list,
3379                       &wcd->dai[aif_id].slim_ch_list);
3380         } else {
3381             dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
3382             return 0;
3383         }
3384         break;
3385 
3386     default:
3387         dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
3388         goto err;
3389     }
3390 
3391     wcd->rx_port_value[port_id] = mux_idx;
3392     snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
3393                       e, update);
3394 
3395     return 1;
3396 err:
3397     return -EINVAL;
3398 }
3399 
3400 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
3401                        struct snd_ctl_elem_value *ucontrol)
3402 {
3403     struct soc_enum *e = (struct soc_enum *)kc->private_value;
3404     struct snd_soc_component *component;
3405     int reg, val;
3406 
3407     component = snd_soc_dapm_kcontrol_component(kc);
3408     val = ucontrol->value.enumerated.item[0];
3409     if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
3410         reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
3411     else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
3412         reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3413     else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
3414         reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3415     else
3416         return -EINVAL;
3417 
3418     /* Set Look Ahead Delay */
3419     if (val)
3420         snd_soc_component_update_bits(component, reg,
3421                           WCD934X_RX_DLY_ZN_EN_MASK,
3422                           WCD934X_RX_DLY_ZN_ENABLE);
3423     else
3424         snd_soc_component_update_bits(component, reg,
3425                           WCD934X_RX_DLY_ZN_EN_MASK,
3426                           WCD934X_RX_DLY_ZN_DISABLE);
3427 
3428     return snd_soc_dapm_put_enum_double(kc, ucontrol);
3429 }
3430 
3431 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
3432                 struct snd_ctl_elem_value *ucontrol)
3433 {
3434     struct snd_soc_component *comp;
3435     struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3436     unsigned int val;
3437     u16 mic_sel_reg = 0;
3438     u8 mic_sel;
3439 
3440     comp = snd_soc_dapm_kcontrol_component(kcontrol);
3441 
3442     val = ucontrol->value.enumerated.item[0];
3443     if (val > e->items - 1)
3444         return -EINVAL;
3445 
3446     switch (e->reg) {
3447     case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
3448         if (e->shift_l == 0)
3449             mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
3450         else if (e->shift_l == 2)
3451             mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
3452         else if (e->shift_l == 4)
3453             mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
3454         break;
3455     case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
3456         if (e->shift_l == 0)
3457             mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
3458         else if (e->shift_l == 2)
3459             mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
3460         break;
3461     case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
3462         if (e->shift_l == 0)
3463             mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
3464         else if (e->shift_l == 2)
3465             mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
3466         break;
3467     case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
3468         if (e->shift_l == 0)
3469             mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
3470         else if (e->shift_l == 2)
3471             mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
3472         break;
3473     default:
3474         dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
3475             __func__, e->reg);
3476         return -EINVAL;
3477     }
3478 
3479     /* ADC: 0, DMIC: 1 */
3480     mic_sel = val ? 0x0 : 0x1;
3481     if (mic_sel_reg)
3482         snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
3483                           mic_sel << 7);
3484 
3485     return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
3486 }
3487 
3488 static const struct snd_kcontrol_new rx_int0_2_mux =
3489     SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
3490 
3491 static const struct snd_kcontrol_new rx_int1_2_mux =
3492     SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
3493 
3494 static const struct snd_kcontrol_new rx_int2_2_mux =
3495     SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
3496 
3497 static const struct snd_kcontrol_new rx_int3_2_mux =
3498     SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
3499 
3500 static const struct snd_kcontrol_new rx_int4_2_mux =
3501     SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
3502 
3503 static const struct snd_kcontrol_new rx_int7_2_mux =
3504     SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
3505 
3506 static const struct snd_kcontrol_new rx_int8_2_mux =
3507     SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
3508 
3509 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
3510     SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
3511 
3512 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
3513     SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
3514 
3515 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
3516     SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
3517 
3518 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
3519     SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
3520 
3521 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
3522     SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
3523 
3524 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
3525     SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
3526 
3527 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
3528     SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
3529 
3530 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
3531     SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
3532 
3533 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
3534     SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
3535 
3536 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
3537     SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
3538 
3539 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
3540     SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
3541 
3542 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
3543     SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
3544 
3545 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
3546     SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
3547 
3548 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
3549     SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
3550 
3551 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
3552     SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
3553 
3554 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
3555     SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
3556 
3557 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
3558     SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
3559 
3560 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
3561     SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
3562 
3563 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
3564     SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
3565 
3566 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
3567     SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
3568 
3569 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
3570     SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
3571 
3572 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
3573     SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
3574 
3575 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
3576     SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
3577 
3578 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
3579     SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
3580 
3581 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
3582     SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
3583 
3584 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
3585     SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
3586 
3587 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
3588     SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
3589 
3590 static const struct snd_kcontrol_new iir0_inp0_mux =
3591     SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
3592 static const struct snd_kcontrol_new iir0_inp1_mux =
3593     SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
3594 static const struct snd_kcontrol_new iir0_inp2_mux =
3595     SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
3596 static const struct snd_kcontrol_new iir0_inp3_mux =
3597     SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
3598 
3599 static const struct snd_kcontrol_new iir1_inp0_mux =
3600     SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3601 static const struct snd_kcontrol_new iir1_inp1_mux =
3602     SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3603 static const struct snd_kcontrol_new iir1_inp2_mux =
3604     SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3605 static const struct snd_kcontrol_new iir1_inp3_mux =
3606     SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3607 
3608 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
3609     SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
3610               slim_rx_mux_get, slim_rx_mux_put),
3611     SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
3612               slim_rx_mux_get, slim_rx_mux_put),
3613     SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
3614               slim_rx_mux_get, slim_rx_mux_put),
3615     SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
3616               slim_rx_mux_get, slim_rx_mux_put),
3617     SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
3618               slim_rx_mux_get, slim_rx_mux_put),
3619     SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
3620               slim_rx_mux_get, slim_rx_mux_put),
3621     SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
3622               slim_rx_mux_get, slim_rx_mux_put),
3623     SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
3624               slim_rx_mux_get, slim_rx_mux_put),
3625 };
3626 
3627 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
3628     SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
3629 };
3630 
3631 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
3632     SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
3633 };
3634 
3635 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
3636     SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
3637 };
3638 
3639 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
3640     SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
3641 };
3642 
3643 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
3644     SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
3645               snd_soc_dapm_get_enum_double,
3646               wcd934x_int_dem_inp_mux_put);
3647 
3648 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
3649     SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
3650               snd_soc_dapm_get_enum_double,
3651               wcd934x_int_dem_inp_mux_put);
3652 
3653 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
3654     SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
3655               snd_soc_dapm_get_enum_double,
3656               wcd934x_int_dem_inp_mux_put);
3657 
3658 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
3659     SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
3660 
3661 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
3662     SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
3663 
3664 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
3665     SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
3666 
3667 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
3668     SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
3669 
3670 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
3671     SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
3672 
3673 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
3674     SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
3675 
3676 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
3677     SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
3678 
3679 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
3680     SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
3681 
3682 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
3683     SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
3684 
3685 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
3686     SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
3687 
3688 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
3689     SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
3690 
3691 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
3692     SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
3693 
3694 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
3695     SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
3696 
3697 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
3698     SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
3699 
3700 static const struct snd_kcontrol_new tx_dmic_mux0 =
3701     SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
3702 
3703 static const struct snd_kcontrol_new tx_dmic_mux1 =
3704     SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
3705 
3706 static const struct snd_kcontrol_new tx_dmic_mux2 =
3707     SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
3708 
3709 static const struct snd_kcontrol_new tx_dmic_mux3 =
3710     SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
3711 
3712 static const struct snd_kcontrol_new tx_dmic_mux4 =
3713     SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
3714 
3715 static const struct snd_kcontrol_new tx_dmic_mux5 =
3716     SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
3717 
3718 static const struct snd_kcontrol_new tx_dmic_mux6 =
3719     SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
3720 
3721 static const struct snd_kcontrol_new tx_dmic_mux7 =
3722     SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
3723 
3724 static const struct snd_kcontrol_new tx_dmic_mux8 =
3725     SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
3726 
3727 static const struct snd_kcontrol_new tx_amic_mux0 =
3728     SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
3729 
3730 static const struct snd_kcontrol_new tx_amic_mux1 =
3731     SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
3732 
3733 static const struct snd_kcontrol_new tx_amic_mux2 =
3734     SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
3735 
3736 static const struct snd_kcontrol_new tx_amic_mux3 =
3737     SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
3738 
3739 static const struct snd_kcontrol_new tx_amic_mux4 =
3740     SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
3741 
3742 static const struct snd_kcontrol_new tx_amic_mux5 =
3743     SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
3744 
3745 static const struct snd_kcontrol_new tx_amic_mux6 =
3746     SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
3747 
3748 static const struct snd_kcontrol_new tx_amic_mux7 =
3749     SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
3750 
3751 static const struct snd_kcontrol_new tx_amic_mux8 =
3752     SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
3753 
3754 static const struct snd_kcontrol_new tx_amic4_5 =
3755     SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
3756 
3757 static const struct snd_kcontrol_new tx_adc_mux0_mux =
3758     SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
3759               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3760 static const struct snd_kcontrol_new tx_adc_mux1_mux =
3761     SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
3762               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3763 static const struct snd_kcontrol_new tx_adc_mux2_mux =
3764     SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3765               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3766 static const struct snd_kcontrol_new tx_adc_mux3_mux =
3767     SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3768               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3769 static const struct snd_kcontrol_new tx_adc_mux4_mux =
3770     SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3771               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3772 static const struct snd_kcontrol_new tx_adc_mux5_mux =
3773     SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3774               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3775 static const struct snd_kcontrol_new tx_adc_mux6_mux =
3776     SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3777               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3778 static const struct snd_kcontrol_new tx_adc_mux7_mux =
3779     SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3780               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3781 static const struct snd_kcontrol_new tx_adc_mux8_mux =
3782     SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3783               snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3784 
3785 static const struct snd_kcontrol_new cdc_if_tx0_mux =
3786     SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3787 static const struct snd_kcontrol_new cdc_if_tx1_mux =
3788     SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3789 static const struct snd_kcontrol_new cdc_if_tx2_mux =
3790     SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3791 static const struct snd_kcontrol_new cdc_if_tx3_mux =
3792     SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3793 static const struct snd_kcontrol_new cdc_if_tx4_mux =
3794     SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3795 static const struct snd_kcontrol_new cdc_if_tx5_mux =
3796     SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3797 static const struct snd_kcontrol_new cdc_if_tx6_mux =
3798     SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3799 static const struct snd_kcontrol_new cdc_if_tx7_mux =
3800     SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3801 static const struct snd_kcontrol_new cdc_if_tx8_mux =
3802     SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3803 static const struct snd_kcontrol_new cdc_if_tx9_mux =
3804     SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3805 static const struct snd_kcontrol_new cdc_if_tx10_mux =
3806     SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3807 static const struct snd_kcontrol_new cdc_if_tx11_mux =
3808     SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3809 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3810     SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3811 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3812     SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3813 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3814     SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3815 
3816 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3817                  struct snd_ctl_elem_value *ucontrol)
3818 {
3819     struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3820     struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3821     struct soc_mixer_control *mixer =
3822             (struct soc_mixer_control *)kc->private_value;
3823     int port_id = mixer->shift;
3824 
3825     ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3826 
3827     return 0;
3828 }
3829 
3830 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3831                  struct snd_ctl_elem_value *ucontrol)
3832 {
3833     struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3834     struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3835     struct snd_soc_dapm_update *update = NULL;
3836     struct soc_mixer_control *mixer =
3837             (struct soc_mixer_control *)kc->private_value;
3838     int enable = ucontrol->value.integer.value[0];
3839     struct wcd934x_slim_ch *ch, *c;
3840     int dai_id = widget->shift;
3841     int port_id = mixer->shift;
3842 
3843     /* only add to the list if value not set */
3844     if (enable == wcd->tx_port_value[port_id])
3845         return 0;
3846 
3847     if (enable) {
3848         if (list_empty(&wcd->tx_chs[port_id].list)) {
3849             list_add_tail(&wcd->tx_chs[port_id].list,
3850                       &wcd->dai[dai_id].slim_ch_list);
3851         } else {
3852             dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3853             return 0;
3854         }
3855      } else {
3856         bool found = false;
3857 
3858         list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3859             if (ch->port == port_id) {
3860                 found = true;
3861                 list_del_init(&wcd->tx_chs[port_id].list);
3862                 break;
3863             }
3864         }
3865         if (!found)
3866             return 0;
3867      }
3868 
3869     wcd->tx_port_value[port_id] = enable;
3870     snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3871 
3872     return 1;
3873 }
3874 
3875 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3876     SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3877                slim_tx_mixer_get, slim_tx_mixer_put),
3878     SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3879                slim_tx_mixer_get, slim_tx_mixer_put),
3880     SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3881                slim_tx_mixer_get, slim_tx_mixer_put),
3882     SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3883                slim_tx_mixer_get, slim_tx_mixer_put),
3884     SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3885                slim_tx_mixer_get, slim_tx_mixer_put),
3886     SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3887                slim_tx_mixer_get, slim_tx_mixer_put),
3888     SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3889                slim_tx_mixer_get, slim_tx_mixer_put),
3890     SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3891                slim_tx_mixer_get, slim_tx_mixer_put),
3892     SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3893                slim_tx_mixer_get, slim_tx_mixer_put),
3894     SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3895                slim_tx_mixer_get, slim_tx_mixer_put),
3896     SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3897                slim_tx_mixer_get, slim_tx_mixer_put),
3898     SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3899                slim_tx_mixer_get, slim_tx_mixer_put),
3900     SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3901                slim_tx_mixer_get, slim_tx_mixer_put),
3902 };
3903 
3904 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3905     SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3906                slim_tx_mixer_get, slim_tx_mixer_put),
3907     SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3908                slim_tx_mixer_get, slim_tx_mixer_put),
3909     SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3910                slim_tx_mixer_get, slim_tx_mixer_put),
3911     SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3912                slim_tx_mixer_get, slim_tx_mixer_put),
3913     SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3914                slim_tx_mixer_get, slim_tx_mixer_put),
3915     SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3916                slim_tx_mixer_get, slim_tx_mixer_put),
3917     SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3918                slim_tx_mixer_get, slim_tx_mixer_put),
3919     SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3920                slim_tx_mixer_get, slim_tx_mixer_put),
3921     SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3922                slim_tx_mixer_get, slim_tx_mixer_put),
3923     SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3924                slim_tx_mixer_get, slim_tx_mixer_put),
3925     SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3926                slim_tx_mixer_get, slim_tx_mixer_put),
3927     SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3928                slim_tx_mixer_get, slim_tx_mixer_put),
3929     SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3930                slim_tx_mixer_get, slim_tx_mixer_put),
3931 };
3932 
3933 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3934     SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3935                slim_tx_mixer_get, slim_tx_mixer_put),
3936     SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3937                slim_tx_mixer_get, slim_tx_mixer_put),
3938     SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3939                slim_tx_mixer_get, slim_tx_mixer_put),
3940     SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3941                slim_tx_mixer_get, slim_tx_mixer_put),
3942     SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3943                slim_tx_mixer_get, slim_tx_mixer_put),
3944     SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3945                slim_tx_mixer_get, slim_tx_mixer_put),
3946     SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3947                slim_tx_mixer_get, slim_tx_mixer_put),
3948     SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3949                slim_tx_mixer_get, slim_tx_mixer_put),
3950     SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3951                slim_tx_mixer_get, slim_tx_mixer_put),
3952     SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3953                slim_tx_mixer_get, slim_tx_mixer_put),
3954     SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3955                slim_tx_mixer_get, slim_tx_mixer_put),
3956     SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3957                slim_tx_mixer_get, slim_tx_mixer_put),
3958     SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3959                slim_tx_mixer_get, slim_tx_mixer_put),
3960 };
3961 
3962 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3963     /* Gain Controls */
3964     SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3965     SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3966     SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3967     SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3968                3, 16, 1, line_gain),
3969     SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3970                3, 16, 1, line_gain),
3971 
3972     SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3973     SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3974     SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3975     SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3976 
3977     SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3978               -84, 40, digital_gain), /* -84dB min - 40dB max */
3979     SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3980               -84, 40, digital_gain),
3981     SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3982               -84, 40, digital_gain),
3983     SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3984               -84, 40, digital_gain),
3985     SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3986               -84, 40, digital_gain),
3987     SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3988               -84, 40, digital_gain),
3989     SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3990               -84, 40, digital_gain),
3991     SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3992               WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3993               -84, 40, digital_gain),
3994     SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3995               WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3996               -84, 40, digital_gain),
3997     SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3998               WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3999               -84, 40, digital_gain),
4000     SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
4001               WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
4002               -84, 40, digital_gain),
4003     SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
4004               WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
4005               -84, 40, digital_gain),
4006     SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
4007               WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
4008               -84, 40, digital_gain),
4009     SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
4010               WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
4011               -84, 40, digital_gain),
4012 
4013     SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
4014               -84, 40, digital_gain),
4015     SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
4016               -84, 40, digital_gain),
4017     SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
4018               -84, 40, digital_gain),
4019     SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
4020               -84, 40, digital_gain),
4021     SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
4022               -84, 40, digital_gain),
4023     SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
4024               -84, 40, digital_gain),
4025     SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
4026               -84, 40, digital_gain),
4027     SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
4028               -84, 40, digital_gain),
4029     SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
4030               -84, 40, digital_gain),
4031 
4032     SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
4033               WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
4034               digital_gain),
4035     SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
4036               WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
4037               digital_gain),
4038     SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
4039               WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
4040               digital_gain),
4041     SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
4042               WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
4043               digital_gain),
4044     SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4045               WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
4046               digital_gain),
4047     SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4048               WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
4049               digital_gain),
4050     SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4051               WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
4052               digital_gain),
4053     SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4054               WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
4055               digital_gain),
4056 
4057     SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
4058     SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
4059     SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
4060     SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
4061     SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
4062     SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
4063     SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
4064     SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
4065     SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
4066 
4067     SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
4068     SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
4069     SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
4070     SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
4071     SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
4072     SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
4073     SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
4074     SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
4075     SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
4076     SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
4077     SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
4078     SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
4079     SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
4080     SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
4081 
4082     SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
4083              wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
4084 
4085     SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4086            0, 1, 0),
4087     SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4088            1, 1, 0),
4089     SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4090            2, 1, 0),
4091     SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4092            3, 1, 0),
4093     SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4094            4, 1, 0),
4095     SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4096            0, 1, 0),
4097     SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4098            1, 1, 0),
4099     SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4100            2, 1, 0),
4101     SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4102            3, 1, 0),
4103     SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4104            4, 1, 0),
4105     WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
4106     WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
4107     WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
4108     WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
4109     WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
4110 
4111     WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4112     WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4113     WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4114     WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4115     WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4116 
4117     SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
4118                wcd934x_compander_get, wcd934x_compander_set),
4119     SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
4120                wcd934x_compander_get, wcd934x_compander_set),
4121     SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
4122                wcd934x_compander_get, wcd934x_compander_set),
4123     SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
4124                wcd934x_compander_get, wcd934x_compander_set),
4125     SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
4126                wcd934x_compander_get, wcd934x_compander_set),
4127     SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
4128                wcd934x_compander_get, wcd934x_compander_set),
4129 };
4130 
4131 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
4132                       struct snd_soc_component *component)
4133 {
4134     int port_num = 0;
4135     unsigned short reg = 0;
4136     unsigned int val = 0;
4137     struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
4138     struct wcd934x_slim_ch *ch;
4139 
4140     list_for_each_entry(ch, &dai->slim_ch_list, list) {
4141         if (ch->port >= WCD934X_RX_START) {
4142             port_num = ch->port - WCD934X_RX_START;
4143             reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
4144         } else {
4145             port_num = ch->port;
4146             reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
4147         }
4148 
4149         regmap_read(wcd->if_regmap, reg, &val);
4150         if (!(val & BIT(port_num % 8)))
4151             regmap_write(wcd->if_regmap, reg,
4152                      val | BIT(port_num % 8));
4153     }
4154 }
4155 
4156 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
4157                      struct snd_kcontrol *kc, int event)
4158 {
4159     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4160     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4161     struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
4162 
4163     switch (event) {
4164     case SND_SOC_DAPM_POST_PMU:
4165         wcd934x_codec_enable_int_port(dai, comp);
4166         break;
4167     }
4168 
4169     return 0;
4170 }
4171 
4172 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
4173                       u16 interp_idx, int event)
4174 {
4175     u16 hd2_scale_reg;
4176     u16 hd2_enable_reg = 0;
4177 
4178     switch (interp_idx) {
4179     case INTERP_HPHL:
4180         hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
4181         hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
4182         break;
4183     case INTERP_HPHR:
4184         hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
4185         hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
4186         break;
4187     default:
4188         return;
4189     }
4190 
4191     if (SND_SOC_DAPM_EVENT_ON(event)) {
4192         snd_soc_component_update_bits(component, hd2_scale_reg,
4193                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4194                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
4195         snd_soc_component_update_bits(component, hd2_enable_reg,
4196                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4197                       WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
4198     }
4199 
4200     if (SND_SOC_DAPM_EVENT_OFF(event)) {
4201         snd_soc_component_update_bits(component, hd2_enable_reg,
4202                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4203                       WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
4204         snd_soc_component_update_bits(component, hd2_scale_reg,
4205                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4206                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
4207     }
4208 }
4209 
4210 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
4211                          u16 interp_idx, int event)
4212 {
4213     u8 hph_dly_mask;
4214     u16 hph_lut_bypass_reg = 0;
4215 
4216     switch (interp_idx) {
4217     case INTERP_HPHL:
4218         hph_dly_mask = 1;
4219         hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
4220         break;
4221     case INTERP_HPHR:
4222         hph_dly_mask = 2;
4223         hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
4224         break;
4225     default:
4226         return;
4227     }
4228 
4229     if (SND_SOC_DAPM_EVENT_ON(event)) {
4230         snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4231                           hph_dly_mask, 0x0);
4232         snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4233                           WCD934X_HPH_LUT_BYPASS_MASK,
4234                           WCD934X_HPH_LUT_BYPASS_ENABLE);
4235     }
4236 
4237     if (SND_SOC_DAPM_EVENT_OFF(event)) {
4238         snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4239                           hph_dly_mask, hph_dly_mask);
4240         snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4241                           WCD934X_HPH_LUT_BYPASS_MASK,
4242                           WCD934X_HPH_LUT_BYPASS_DISABLE);
4243     }
4244 }
4245 
4246 static int wcd934x_config_compander(struct snd_soc_component *comp,
4247                     int interp_n, int event)
4248 {
4249     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4250     int compander;
4251     u16 comp_ctl0_reg, rx_path_cfg0_reg;
4252 
4253     /* EAR does not have compander */
4254     if (!interp_n)
4255         return 0;
4256 
4257     compander = interp_n - 1;
4258     if (!wcd->comp_enabled[compander])
4259         return 0;
4260 
4261     comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
4262     rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
4263 
4264     switch (event) {
4265     case SND_SOC_DAPM_PRE_PMU:
4266         /* Enable Compander Clock */
4267         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4268                           WCD934X_COMP_CLK_EN_MASK,
4269                           WCD934X_COMP_CLK_ENABLE);
4270         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4271                           WCD934X_COMP_SOFT_RST_MASK,
4272                           WCD934X_COMP_SOFT_RST_ENABLE);
4273         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4274                           WCD934X_COMP_SOFT_RST_MASK,
4275                           WCD934X_COMP_SOFT_RST_DISABLE);
4276         snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4277                           WCD934X_HPH_CMP_EN_MASK,
4278                           WCD934X_HPH_CMP_ENABLE);
4279         break;
4280     case SND_SOC_DAPM_POST_PMD:
4281         snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4282                           WCD934X_HPH_CMP_EN_MASK,
4283                           WCD934X_HPH_CMP_DISABLE);
4284         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4285                           WCD934X_COMP_HALT_MASK,
4286                           WCD934X_COMP_HALT);
4287         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4288                           WCD934X_COMP_SOFT_RST_MASK,
4289                           WCD934X_COMP_SOFT_RST_ENABLE);
4290         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4291                           WCD934X_COMP_SOFT_RST_MASK,
4292                           WCD934X_COMP_SOFT_RST_DISABLE);
4293         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4294                           WCD934X_COMP_CLK_EN_MASK, 0x0);
4295         snd_soc_component_update_bits(comp, comp_ctl0_reg,
4296                           WCD934X_COMP_SOFT_RST_MASK, 0x0);
4297         break;
4298     }
4299 
4300     return 0;
4301 }
4302 
4303 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
4304                      struct snd_kcontrol *kc, int event)
4305 {
4306     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4307     int interp_idx = w->shift;
4308     u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
4309 
4310     switch (event) {
4311     case SND_SOC_DAPM_PRE_PMU:
4312         /* Clk enable */
4313         snd_soc_component_update_bits(comp, main_reg,
4314                          WCD934X_RX_CLK_EN_MASK,
4315                          WCD934X_RX_CLK_ENABLE);
4316         wcd934x_codec_hd2_control(comp, interp_idx, event);
4317         wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4318         wcd934x_config_compander(comp, interp_idx, event);
4319         break;
4320     case SND_SOC_DAPM_POST_PMD:
4321         wcd934x_config_compander(comp, interp_idx, event);
4322         wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4323         wcd934x_codec_hd2_control(comp, interp_idx, event);
4324         /* Clk Disable */
4325         snd_soc_component_update_bits(comp, main_reg,
4326                          WCD934X_RX_CLK_EN_MASK, 0);
4327         /* Reset enable and disable */
4328         snd_soc_component_update_bits(comp, main_reg,
4329                           WCD934X_RX_RESET_MASK,
4330                           WCD934X_RX_RESET_ENABLE);
4331         snd_soc_component_update_bits(comp, main_reg,
4332                           WCD934X_RX_RESET_MASK,
4333                           WCD934X_RX_RESET_DISABLE);
4334         /* Reset rate to 48K*/
4335         snd_soc_component_update_bits(comp, main_reg,
4336                           WCD934X_RX_PCM_RATE_MASK,
4337                           WCD934X_RX_PCM_RATE_F_48K);
4338         break;
4339     }
4340 
4341     return 0;
4342 }
4343 
4344 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
4345                      struct snd_kcontrol *kc, int event)
4346 {
4347     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4348     int offset_val = 0;
4349     u16 gain_reg, mix_reg;
4350     int val = 0;
4351 
4352     gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
4353                     (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4354     mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
4355                     (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4356 
4357     switch (event) {
4358     case SND_SOC_DAPM_PRE_PMU:
4359         /* Clk enable */
4360         snd_soc_component_update_bits(comp, mix_reg,
4361                           WCD934X_CDC_RX_MIX_CLK_EN_MASK,
4362                           WCD934X_CDC_RX_MIX_CLK_ENABLE);
4363         break;
4364 
4365     case SND_SOC_DAPM_POST_PMU:
4366         val = snd_soc_component_read(comp, gain_reg);
4367         val += offset_val;
4368         snd_soc_component_write(comp, gain_reg, val);
4369         break;
4370     }
4371 
4372     return 0;
4373 }
4374 
4375 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
4376                       struct snd_kcontrol *kcontrol, int event)
4377 {
4378     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4379     int reg = w->reg;
4380 
4381     switch (event) {
4382     case SND_SOC_DAPM_POST_PMU:
4383         /* B1 GAIN */
4384         snd_soc_component_write(comp, reg,
4385                     snd_soc_component_read(comp, reg));
4386         /* B2 GAIN */
4387         reg++;
4388         snd_soc_component_write(comp, reg,
4389                     snd_soc_component_read(comp, reg));
4390         /* B3 GAIN */
4391         reg++;
4392         snd_soc_component_write(comp, reg,
4393                     snd_soc_component_read(comp, reg));
4394         /* B4 GAIN */
4395         reg++;
4396         snd_soc_component_write(comp, reg,
4397                     snd_soc_component_read(comp, reg));
4398         /* B5 GAIN */
4399         reg++;
4400         snd_soc_component_write(comp, reg,
4401                     snd_soc_component_read(comp, reg));
4402         break;
4403     default:
4404         break;
4405     }
4406     return 0;
4407 }
4408 
4409 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
4410                       struct snd_kcontrol *kcontrol,
4411                       int event)
4412 {
4413     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4414     u16 gain_reg;
4415 
4416     gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
4417                          WCD934X_RX_PATH_CTL_OFFSET);
4418 
4419     switch (event) {
4420     case SND_SOC_DAPM_POST_PMU:
4421         snd_soc_component_write(comp, gain_reg,
4422                 snd_soc_component_read(comp, gain_reg));
4423         break;
4424     }
4425 
4426     return 0;
4427 }
4428 
4429 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4430                        struct snd_kcontrol *kc, int event)
4431 {
4432     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4433     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4434 
4435     switch (event) {
4436     case SND_SOC_DAPM_PRE_PMU:
4437         /* Disable AutoChop timer during power up */
4438         snd_soc_component_update_bits(comp,
4439                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4440                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4441         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4442                     WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4443 
4444         break;
4445     case SND_SOC_DAPM_POST_PMD:
4446         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4447                     WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4448         break;
4449     }
4450 
4451     return 0;
4452 }
4453 
4454 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4455                     struct snd_kcontrol *kcontrol,
4456                     int event)
4457 {
4458     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4459     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4460     int hph_mode = wcd->hph_mode;
4461     u8 dem_inp;
4462 
4463     switch (event) {
4464     case SND_SOC_DAPM_PRE_PMU:
4465         /* Read DEM INP Select */
4466         dem_inp = snd_soc_component_read(comp,
4467                    WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
4468 
4469         if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4470              (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4471             return -EINVAL;
4472         }
4473         if (hph_mode != CLS_H_LP)
4474             /* Ripple freq control enable */
4475             snd_soc_component_update_bits(comp,
4476                     WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4477                     WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4478                     WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4479         /* Disable AutoChop timer during power up */
4480         snd_soc_component_update_bits(comp,
4481                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4482                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4483         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4484                     WCD_CLSH_STATE_HPHL, hph_mode);
4485 
4486         break;
4487     case SND_SOC_DAPM_POST_PMD:
4488         /* 1000us required as per HW requirement */
4489         usleep_range(1000, 1100);
4490         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4491                     WCD_CLSH_STATE_HPHL, hph_mode);
4492         if (hph_mode != CLS_H_LP)
4493             /* Ripple freq control disable */
4494             snd_soc_component_update_bits(comp,
4495                     WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4496                     WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4497 
4498         break;
4499     default:
4500         break;
4501     }
4502 
4503     return 0;
4504 }
4505 
4506 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4507                     struct snd_kcontrol *kcontrol,
4508                     int event)
4509 {
4510     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4511     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4512     int hph_mode = wcd->hph_mode;
4513     u8 dem_inp;
4514 
4515     switch (event) {
4516     case SND_SOC_DAPM_PRE_PMU:
4517         dem_inp = snd_soc_component_read(comp,
4518                     WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
4519         if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4520              (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4521             return -EINVAL;
4522         }
4523         if (hph_mode != CLS_H_LP)
4524             /* Ripple freq control enable */
4525             snd_soc_component_update_bits(comp,
4526                     WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4527                     WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4528                     WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4529         /* Disable AutoChop timer during power up */
4530         snd_soc_component_update_bits(comp,
4531                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4532                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4533         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4534                     WCD_CLSH_STATE_HPHR,
4535                  hph_mode);
4536         break;
4537     case SND_SOC_DAPM_POST_PMD:
4538         /* 1000us required as per HW requirement */
4539         usleep_range(1000, 1100);
4540 
4541         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4542                     WCD_CLSH_STATE_HPHR, hph_mode);
4543         if (hph_mode != CLS_H_LP)
4544             /* Ripple freq control disable */
4545             snd_soc_component_update_bits(comp,
4546                     WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4547                     WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4548         break;
4549     default:
4550         break;
4551     }
4552 
4553     return 0;
4554 }
4555 
4556 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4557                        struct snd_kcontrol *kc, int event)
4558 {
4559     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4560     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4561 
4562     switch (event) {
4563     case SND_SOC_DAPM_PRE_PMU:
4564         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4565                     WCD_CLSH_STATE_LO, CLS_AB);
4566         break;
4567     case SND_SOC_DAPM_POST_PMD:
4568         wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4569                     WCD_CLSH_STATE_LO, CLS_AB);
4570         break;
4571     }
4572 
4573     return 0;
4574 }
4575 
4576 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4577                     struct snd_kcontrol *kcontrol,
4578                     int event)
4579 {
4580     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4581     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4582 
4583     switch (event) {
4584     case SND_SOC_DAPM_POST_PMU:
4585         /*
4586          * 7ms sleep is required after PA is enabled as per
4587          * HW requirement. If compander is disabled, then
4588          * 20ms delay is needed.
4589          */
4590         usleep_range(20000, 20100);
4591 
4592         snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4593                           WCD934X_HPH_OCP_DET_MASK,
4594                           WCD934X_HPH_OCP_DET_ENABLE);
4595         /* Remove Mute on primary path */
4596         snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4597                       WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4598                       0);
4599         /* Enable GM3 boost */
4600         snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4601                           WCD934X_HPH_GM3_BOOST_EN_MASK,
4602                           WCD934X_HPH_GM3_BOOST_ENABLE);
4603         /* Enable AutoChop timer at the end of power up */
4604         snd_soc_component_update_bits(comp,
4605                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4606                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4607                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4608         /* Remove mix path mute */
4609         snd_soc_component_update_bits(comp,
4610                 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4611                 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
4612         break;
4613     case SND_SOC_DAPM_PRE_PMD:
4614         wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4615         /* Enable DSD Mute before PA disable */
4616         snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4617                           WCD934X_HPH_OCP_DET_MASK,
4618                           WCD934X_HPH_OCP_DET_DISABLE);
4619         snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4620                           WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4621                           WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4622         snd_soc_component_update_bits(comp,
4623                           WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4624                           WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4625                           WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4626         break;
4627     case SND_SOC_DAPM_POST_PMD:
4628         /*
4629          * 5ms sleep is required after PA disable. If compander is
4630          * disabled, then 20ms delay is needed after PA disable.
4631          */
4632         usleep_range(20000, 20100);
4633         wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4634         break;
4635     }
4636 
4637     return 0;
4638 }
4639 
4640 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4641                     struct snd_kcontrol *kcontrol,
4642                     int event)
4643 {
4644     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4645     struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4646 
4647     switch (event) {
4648     case SND_SOC_DAPM_POST_PMU:
4649         /*
4650          * 7ms sleep is required after PA is enabled as per
4651          * HW requirement. If compander is disabled, then
4652          * 20ms delay is needed.
4653          */
4654         usleep_range(20000, 20100);
4655         snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4656                           WCD934X_HPH_OCP_DET_MASK,
4657                           WCD934X_HPH_OCP_DET_ENABLE);
4658         /* Remove mute */
4659         snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4660                           WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4661                           0);
4662         /* Enable GM3 boost */
4663         snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4664                           WCD934X_HPH_GM3_BOOST_EN_MASK,
4665                           WCD934X_HPH_GM3_BOOST_ENABLE);
4666         /* Enable AutoChop timer at the end of power up */
4667         snd_soc_component_update_bits(comp,
4668                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
4669                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4670                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4671         /* Remove mix path mute if it is enabled */
4672         if ((snd_soc_component_read(comp,
4673                       WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
4674             snd_soc_component_update_bits(comp,
4675                           WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4676                           WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4677                           WCD934X_CDC_RX_PGA_MUTE_DISABLE);
4678         break;
4679     case SND_SOC_DAPM_PRE_PMD:
4680         wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
4681         snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4682                           WCD934X_HPH_OCP_DET_MASK,
4683                           WCD934X_HPH_OCP_DET_DISABLE);
4684         snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4685                           WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4686                           WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4687         snd_soc_component_update_bits(comp,
4688                           WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4689                           WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4690                           WCD934X_CDC_RX_PGA_MUTE_ENABLE);
4691         break;
4692     case SND_SOC_DAPM_POST_PMD:
4693         /*
4694          * 5ms sleep is required after PA disable. If compander is
4695          * disabled, then 20ms delay is needed after PA disable.
4696          */
4697         usleep_range(20000, 20100);
4698         wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
4699         break;
4700     }
4701 
4702     return 0;
4703 }
4704 
4705 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
4706                     unsigned int dmic,
4707                       struct wcd934x_codec *wcd)
4708 {
4709     u8 tx_stream_fs;
4710     u8 adc_mux_index = 0, adc_mux_sel = 0;
4711     bool dec_found = false;
4712     u16 adc_mux_ctl_reg, tx_fs_reg;
4713     u32 dmic_fs;
4714 
4715     while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
4716         if (adc_mux_index < 4) {
4717             adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4718                         (adc_mux_index * 2);
4719         } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
4720             adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4721                         adc_mux_index - 4;
4722         } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
4723             ++adc_mux_index;
4724             continue;
4725         }
4726         adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
4727                    & 0xF8) >> 3) - 1;
4728 
4729         if (adc_mux_sel == dmic) {
4730             dec_found = true;
4731             break;
4732         }
4733 
4734         ++adc_mux_index;
4735     }
4736 
4737     if (dec_found && adc_mux_index <= 8) {
4738         tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
4739         tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
4740         if (tx_stream_fs <= 4)  {
4741             if (wcd->dmic_sample_rate <=
4742                     WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
4743                 dmic_fs = wcd->dmic_sample_rate;
4744             else
4745                 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
4746         } else
4747             dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
4748     } else {
4749         dmic_fs = wcd->dmic_sample_rate;
4750     }
4751 
4752     return dmic_fs;
4753 }
4754 
4755 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
4756                    u32 mclk_rate, u32 dmic_clk_rate)
4757 {
4758     u32 div_factor;
4759     u8 dmic_ctl_val;
4760 
4761     /* Default value to return in case of error */
4762     if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
4763         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4764     else
4765         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4766 
4767     if (dmic_clk_rate == 0) {
4768         dev_err(comp->dev,
4769             "%s: dmic_sample_rate cannot be 0\n",
4770             __func__);
4771         goto done;
4772     }
4773 
4774     div_factor = mclk_rate / dmic_clk_rate;
4775     switch (div_factor) {
4776     case 2:
4777         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4778         break;
4779     case 3:
4780         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4781         break;
4782     case 4:
4783         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4784         break;
4785     case 6:
4786         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4787         break;
4788     case 8:
4789         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4790         break;
4791     case 16:
4792         dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4793         break;
4794     default:
4795         dev_err(comp->dev,
4796             "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4797             __func__, div_factor, mclk_rate, dmic_clk_rate);
4798         break;
4799     }
4800 
4801 done:
4802     return dmic_ctl_val;
4803 }
4804 
4805 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4806                      struct snd_kcontrol *kcontrol, int event)
4807 {
4808     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4809     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4810     u8  dmic_clk_en = 0x01;
4811     u16 dmic_clk_reg;
4812     s32 *dmic_clk_cnt;
4813     u8 dmic_rate_val, dmic_rate_shift = 1;
4814     unsigned int dmic;
4815     u32 dmic_sample_rate;
4816     int ret;
4817     char *wname;
4818 
4819     wname = strpbrk(w->name, "012345");
4820     if (!wname) {
4821         dev_err(comp->dev, "%s: widget not found\n", __func__);
4822         return -EINVAL;
4823     }
4824 
4825     ret = kstrtouint(wname, 10, &dmic);
4826     if (ret < 0) {
4827         dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4828             __func__);
4829         return -EINVAL;
4830     }
4831 
4832     switch (dmic) {
4833     case 0:
4834     case 1:
4835         dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4836         dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4837         break;
4838     case 2:
4839     case 3:
4840         dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4841         dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4842         break;
4843     case 4:
4844     case 5:
4845         dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4846         dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4847         break;
4848     default:
4849         dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4850             __func__);
4851         return -EINVAL;
4852     }
4853 
4854     switch (event) {
4855     case SND_SOC_DAPM_PRE_PMU:
4856         dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4857                                 wcd);
4858         dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4859                              dmic_sample_rate);
4860         (*dmic_clk_cnt)++;
4861         if (*dmic_clk_cnt == 1) {
4862             dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4863             snd_soc_component_update_bits(comp, dmic_clk_reg,
4864                               WCD934X_DMIC_RATE_MASK,
4865                               dmic_rate_val);
4866             snd_soc_component_update_bits(comp, dmic_clk_reg,
4867                               dmic_clk_en, dmic_clk_en);
4868         }
4869 
4870         break;
4871     case SND_SOC_DAPM_POST_PMD:
4872         (*dmic_clk_cnt)--;
4873         if (*dmic_clk_cnt == 0)
4874             snd_soc_component_update_bits(comp, dmic_clk_reg,
4875                               dmic_clk_en, 0);
4876         break;
4877     }
4878 
4879     return 0;
4880 }
4881 
4882 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4883                      int adc_mux_n)
4884 {
4885     u16 mask, shift, adc_mux_in_reg;
4886     u16 amic_mux_sel_reg;
4887     bool is_amic;
4888 
4889     if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4890         adc_mux_n == WCD934X_INVALID_ADC_MUX)
4891         return 0;
4892 
4893     if (adc_mux_n < 3) {
4894         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4895                  adc_mux_n;
4896         mask = 0x03;
4897         shift = 0;
4898         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4899                    2 * adc_mux_n;
4900     } else if (adc_mux_n < 4) {
4901         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4902         mask = 0x03;
4903         shift = 0;
4904         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4905                    2 * adc_mux_n;
4906     } else if (adc_mux_n < 7) {
4907         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4908                  (adc_mux_n - 4);
4909         mask = 0x0C;
4910         shift = 2;
4911         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4912                    adc_mux_n - 4;
4913     } else if (adc_mux_n < 8) {
4914         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4915         mask = 0x0C;
4916         shift = 2;
4917         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4918                    adc_mux_n - 4;
4919     } else if (adc_mux_n < 12) {
4920         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4921                  ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4922                   (adc_mux_n - 9));
4923         mask = 0x30;
4924         shift = 4;
4925         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4926                    adc_mux_n - 4;
4927     } else if (adc_mux_n < 13) {
4928         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4929         mask = 0x30;
4930         shift = 4;
4931         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4932                    adc_mux_n - 4;
4933     } else {
4934         adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4935         mask = 0xC0;
4936         shift = 6;
4937         amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4938                    adc_mux_n - 4;
4939     }
4940 
4941     is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4942              & mask) >> shift) == 1);
4943     if (!is_amic)
4944         return 0;
4945 
4946     return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4947 }
4948 
4949 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4950                         int amic)
4951 {
4952     u16 pwr_level_reg = 0;
4953 
4954     switch (amic) {
4955     case 1:
4956     case 2:
4957         pwr_level_reg = WCD934X_ANA_AMIC1;
4958         break;
4959 
4960     case 3:
4961     case 4:
4962         pwr_level_reg = WCD934X_ANA_AMIC3;
4963         break;
4964     default:
4965         break;
4966     }
4967 
4968     return pwr_level_reg;
4969 }
4970 
4971 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4972                     struct snd_kcontrol *kcontrol, int event)
4973 {
4974     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4975     unsigned int decimator;
4976     char *dec_adc_mux_name = NULL;
4977     char *widget_name = NULL;
4978     char *wname;
4979     int ret = 0, amic_n;
4980     u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4981     u16 tx_gain_ctl_reg;
4982     char *dec;
4983     u8 hpf_coff_freq;
4984 
4985     widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4986     if (!widget_name)
4987         return -ENOMEM;
4988 
4989     wname = widget_name;
4990     dec_adc_mux_name = strsep(&widget_name, " ");
4991     if (!dec_adc_mux_name) {
4992         dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4993             __func__, w->name);
4994         ret =  -EINVAL;
4995         goto out;
4996     }
4997     dec_adc_mux_name = widget_name;
4998 
4999     dec = strpbrk(dec_adc_mux_name, "012345678");
5000     if (!dec) {
5001         dev_err(comp->dev, "%s: decimator index not found\n",
5002             __func__);
5003         ret =  -EINVAL;
5004         goto out;
5005     }
5006 
5007     ret = kstrtouint(dec, 10, &decimator);
5008     if (ret < 0) {
5009         dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5010             __func__, wname);
5011         ret =  -EINVAL;
5012         goto out;
5013     }
5014 
5015     tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
5016     hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
5017     dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5018     tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5019 
5020     switch (event) {
5021     case SND_SOC_DAPM_PRE_PMU:
5022         amic_n = wcd934x_codec_find_amic_input(comp, decimator);
5023         if (amic_n)
5024             pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
5025                                  amic_n);
5026 
5027         if (!pwr_level_reg)
5028             break;
5029 
5030         switch ((snd_soc_component_read(comp, pwr_level_reg) &
5031                       WCD934X_AMIC_PWR_LVL_MASK) >>
5032                       WCD934X_AMIC_PWR_LVL_SHIFT) {
5033         case WCD934X_AMIC_PWR_LEVEL_LP:
5034             snd_soc_component_update_bits(comp, dec_cfg_reg,
5035                     WCD934X_DEC_PWR_LVL_MASK,
5036                     WCD934X_DEC_PWR_LVL_LP);
5037             break;
5038         case WCD934X_AMIC_PWR_LEVEL_HP:
5039             snd_soc_component_update_bits(comp, dec_cfg_reg,
5040                     WCD934X_DEC_PWR_LVL_MASK,
5041                     WCD934X_DEC_PWR_LVL_HP);
5042             break;
5043         case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
5044         case WCD934X_AMIC_PWR_LEVEL_HYBRID:
5045         default:
5046             snd_soc_component_update_bits(comp, dec_cfg_reg,
5047                     WCD934X_DEC_PWR_LVL_MASK,
5048                     WCD934X_DEC_PWR_LVL_DF);
5049             break;
5050         }
5051         break;
5052     case SND_SOC_DAPM_POST_PMU:
5053         hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5054                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5055         if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5056             snd_soc_component_update_bits(comp, dec_cfg_reg,
5057                               TX_HPF_CUT_OFF_FREQ_MASK,
5058                               CF_MIN_3DB_150HZ << 5);
5059             snd_soc_component_update_bits(comp, hpf_gate_reg,
5060                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5061                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5062             /*
5063              * Minimum 1 clk cycle delay is required as per
5064              * HW spec.
5065              */
5066             usleep_range(1000, 1010);
5067             snd_soc_component_update_bits(comp, hpf_gate_reg,
5068                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5069                       0);
5070         }
5071         /* apply gain after decimator is enabled */
5072         snd_soc_component_write(comp, tx_gain_ctl_reg,
5073                     snd_soc_component_read(comp,
5074                              tx_gain_ctl_reg));
5075         break;
5076     case SND_SOC_DAPM_PRE_PMD:
5077         hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5078                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5079 
5080         if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5081             snd_soc_component_update_bits(comp, dec_cfg_reg,
5082                               TX_HPF_CUT_OFF_FREQ_MASK,
5083                               hpf_coff_freq << 5);
5084             snd_soc_component_update_bits(comp, hpf_gate_reg,
5085                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5086                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5087                 /*
5088                  * Minimum 1 clk cycle delay is required as per
5089                  * HW spec.
5090                  */
5091             usleep_range(1000, 1010);
5092             snd_soc_component_update_bits(comp, hpf_gate_reg,
5093                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5094                       0);
5095         }
5096         break;
5097     case SND_SOC_DAPM_POST_PMD:
5098         snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
5099                           0x10, 0x00);
5100         snd_soc_component_update_bits(comp, dec_cfg_reg,
5101                           WCD934X_DEC_PWR_LVL_MASK,
5102                           WCD934X_DEC_PWR_LVL_DF);
5103         break;
5104     }
5105 out:
5106     kfree(wname);
5107     return ret;
5108 }
5109 
5110 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
5111                       u16 amic_reg, bool set)
5112 {
5113     u8 mask = 0x20;
5114     u8 val;
5115 
5116     if (amic_reg == WCD934X_ANA_AMIC1 ||
5117         amic_reg == WCD934X_ANA_AMIC3)
5118         mask = 0x40;
5119 
5120     val = set ? mask : 0x00;
5121 
5122     switch (amic_reg) {
5123     case WCD934X_ANA_AMIC1:
5124     case WCD934X_ANA_AMIC2:
5125         snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
5126                           mask, val);
5127         break;
5128     case WCD934X_ANA_AMIC3:
5129     case WCD934X_ANA_AMIC4:
5130         snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
5131                           mask, val);
5132         break;
5133     default:
5134         break;
5135     }
5136 }
5137 
5138 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
5139                     struct snd_kcontrol *kcontrol, int event)
5140 {
5141     struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
5142 
5143     switch (event) {
5144     case SND_SOC_DAPM_PRE_PMU:
5145         wcd934x_codec_set_tx_hold(comp, w->reg, true);
5146         break;
5147     default:
5148         break;
5149     }
5150 
5151     return 0;
5152 }
5153 
5154 static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
5155                     struct snd_kcontrol *kcontrol,
5156                     int event)
5157 {
5158     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5159     int micb_num = w->shift;
5160 
5161     switch (event) {
5162     case SND_SOC_DAPM_PRE_PMU:
5163         wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
5164         break;
5165     case SND_SOC_DAPM_POST_PMU:
5166         /* 1 msec delay as per HW requirement */
5167         usleep_range(1000, 1100);
5168         break;
5169     case SND_SOC_DAPM_POST_PMD:
5170         wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
5171         break;
5172     }
5173 
5174     return 0;
5175 }
5176 
5177 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
5178     /* Analog Outputs */
5179     SND_SOC_DAPM_OUTPUT("EAR"),
5180     SND_SOC_DAPM_OUTPUT("HPHL"),
5181     SND_SOC_DAPM_OUTPUT("HPHR"),
5182     SND_SOC_DAPM_OUTPUT("LINEOUT1"),
5183     SND_SOC_DAPM_OUTPUT("LINEOUT2"),
5184     SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
5185     SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
5186     SND_SOC_DAPM_OUTPUT("ANC EAR"),
5187     SND_SOC_DAPM_OUTPUT("ANC HPHL"),
5188     SND_SOC_DAPM_OUTPUT("ANC HPHR"),
5189     SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
5190     SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
5191     SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
5192     SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
5193                   AIF1_PB, 0, wcd934x_codec_enable_slim,
5194                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5195     SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
5196                   AIF2_PB, 0, wcd934x_codec_enable_slim,
5197                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5198     SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
5199                   AIF3_PB, 0, wcd934x_codec_enable_slim,
5200                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5201     SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
5202                   AIF4_PB, 0, wcd934x_codec_enable_slim,
5203                   SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5204 
5205     SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
5206              &slim_rx_mux[WCD934X_RX0]),
5207     SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
5208              &slim_rx_mux[WCD934X_RX1]),
5209     SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
5210              &slim_rx_mux[WCD934X_RX2]),
5211     SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
5212              &slim_rx_mux[WCD934X_RX3]),
5213     SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
5214              &slim_rx_mux[WCD934X_RX4]),
5215     SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
5216              &slim_rx_mux[WCD934X_RX5]),
5217     SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
5218              &slim_rx_mux[WCD934X_RX6]),
5219     SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
5220              &slim_rx_mux[WCD934X_RX7]),
5221 
5222     SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5223     SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5224     SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5225     SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5226     SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5227     SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5228     SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5229     SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5230 
5231     SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
5232                &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
5233                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5234                SND_SOC_DAPM_POST_PMD),
5235     SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
5236                &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
5237                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5238                SND_SOC_DAPM_POST_PMD),
5239     SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
5240                &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
5241                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5242                SND_SOC_DAPM_POST_PMD),
5243     SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
5244                &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
5245                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5246                SND_SOC_DAPM_POST_PMD),
5247     SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
5248                &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
5249                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5250                SND_SOC_DAPM_POST_PMD),
5251     SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
5252                &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
5253                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5254                SND_SOC_DAPM_POST_PMD),
5255     SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
5256                &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
5257                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5258                SND_SOC_DAPM_POST_PMD),
5259 
5260     SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5261              &rx_int0_1_mix_inp0_mux),
5262     SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5263              &rx_int0_1_mix_inp1_mux),
5264     SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5265              &rx_int0_1_mix_inp2_mux),
5266     SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5267              &rx_int1_1_mix_inp0_mux),
5268     SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5269              &rx_int1_1_mix_inp1_mux),
5270     SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5271              &rx_int1_1_mix_inp2_mux),
5272     SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5273              &rx_int2_1_mix_inp0_mux),
5274     SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5275              &rx_int2_1_mix_inp1_mux),
5276     SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5277              &rx_int2_1_mix_inp2_mux),
5278     SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5279              &rx_int3_1_mix_inp0_mux),
5280     SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5281              &rx_int3_1_mix_inp1_mux),
5282     SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5283              &rx_int3_1_mix_inp2_mux),
5284     SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5285              &rx_int4_1_mix_inp0_mux),
5286     SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5287              &rx_int4_1_mix_inp1_mux),
5288     SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5289              &rx_int4_1_mix_inp2_mux),
5290     SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5291                &rx_int7_1_mix_inp0_mux),
5292     SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5293                &rx_int7_1_mix_inp1_mux),
5294     SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5295                &rx_int7_1_mix_inp2_mux),
5296     SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5297                &rx_int8_1_mix_inp0_mux),
5298     SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5299                &rx_int8_1_mix_inp1_mux),
5300     SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5301                &rx_int8_1_mix_inp2_mux),
5302     SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5303     SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5304     SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5305     SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
5306                rx_int1_asrc_switch,
5307                ARRAY_SIZE(rx_int1_asrc_switch)),
5308     SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5309     SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
5310                rx_int2_asrc_switch,
5311                ARRAY_SIZE(rx_int2_asrc_switch)),
5312     SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5313     SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
5314                rx_int3_asrc_switch,
5315                ARRAY_SIZE(rx_int3_asrc_switch)),
5316     SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5317     SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
5318                rx_int4_asrc_switch,
5319                ARRAY_SIZE(rx_int4_asrc_switch)),
5320     SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5321     SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5322     SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5323     SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5324     SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5325     SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5326     SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5327     SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5328     SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5329     SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5330     SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5331     SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5332     SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5333 
5334     SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5335     SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
5336                  NULL, 0, NULL, 0),
5337     SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
5338                  NULL, 0, NULL, 0),
5339     SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
5340                0,  &rx_int0_mix2_inp_mux, NULL,
5341                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5342     SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
5343                0, &rx_int1_mix2_inp_mux,  NULL,
5344                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5345     SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
5346                0, &rx_int2_mix2_inp_mux, NULL,
5347                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5348     SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
5349                0, &rx_int3_mix2_inp_mux, NULL,
5350                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5351     SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
5352                0, &rx_int4_mix2_inp_mux, NULL,
5353                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5354     SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
5355                0, &rx_int7_mix2_inp_mux, NULL,
5356                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5357 
5358     SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
5359     SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
5360     SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
5361     SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
5362     SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5363     SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5364     SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5365     SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5366 
5367     SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5368                0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5369                SND_SOC_DAPM_POST_PMU),
5370     SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5371                1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5372                SND_SOC_DAPM_POST_PMU),
5373     SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
5374                4, 0, NULL, 0),
5375     SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
5376                4, 0, NULL, 0),
5377     SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
5378              &rx_int0_dem_inp_mux),
5379     SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
5380              &rx_int1_dem_inp_mux),
5381     SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
5382              &rx_int2_dem_inp_mux),
5383 
5384     SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
5385                &rx_int0_1_interp_mux,
5386                wcd934x_codec_enable_main_path,
5387                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5388                SND_SOC_DAPM_POST_PMD),
5389     SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
5390                &rx_int1_1_interp_mux,
5391                wcd934x_codec_enable_main_path,
5392                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5393                SND_SOC_DAPM_POST_PMD),
5394     SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
5395                &rx_int2_1_interp_mux,
5396                wcd934x_codec_enable_main_path,
5397                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5398                SND_SOC_DAPM_POST_PMD),
5399     SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
5400                &rx_int3_1_interp_mux,
5401                wcd934x_codec_enable_main_path,
5402                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5403                SND_SOC_DAPM_POST_PMD),
5404     SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
5405                &rx_int4_1_interp_mux,
5406                wcd934x_codec_enable_main_path,
5407                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5408                SND_SOC_DAPM_POST_PMD),
5409     SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
5410                &rx_int7_1_interp_mux,
5411                wcd934x_codec_enable_main_path,
5412                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5413                SND_SOC_DAPM_POST_PMD),
5414     SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
5415                &rx_int8_1_interp_mux,
5416                wcd934x_codec_enable_main_path,
5417                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5418                SND_SOC_DAPM_POST_PMD),
5419 
5420     SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
5421              &rx_int0_2_interp_mux),
5422     SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
5423              &rx_int1_2_interp_mux),
5424     SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
5425              &rx_int2_2_interp_mux),
5426     SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
5427              &rx_int3_2_interp_mux),
5428     SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
5429              &rx_int4_2_interp_mux),
5430     SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
5431              &rx_int7_2_interp_mux),
5432     SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
5433              &rx_int8_2_interp_mux),
5434     SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
5435                0, 0, wcd934x_codec_ear_dac_event,
5436                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5437                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5438     SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5439                5, 0, wcd934x_codec_hphl_dac_event,
5440                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5441                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5442     SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
5443                4, 0, wcd934x_codec_hphr_dac_event,
5444                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5445                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5446     SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
5447                0, 0, wcd934x_codec_lineout_dac_event,
5448                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5449     SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
5450                0, 0, wcd934x_codec_lineout_dac_event,
5451                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5452     SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
5453     SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
5454                wcd934x_codec_enable_hphl_pa,
5455                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5456                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5457     SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
5458                wcd934x_codec_enable_hphr_pa,
5459                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5460                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5461     SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
5462                NULL, 0),
5463     SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
5464                NULL, 0),
5465     SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
5466                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5467     SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
5468              0, 0, NULL, 0),
5469     SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
5470                 0, 0, NULL, 0),
5471     SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
5472              0, 0, NULL, 0),
5473     SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
5474                 0, 0, NULL, 0),
5475     SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
5476                 wcd934x_codec_enable_interp_clk,
5477                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5478     SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
5479                 wcd934x_codec_enable_interp_clk,
5480                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5481     SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
5482                 wcd934x_codec_enable_interp_clk,
5483                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5484     SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
5485                 wcd934x_codec_enable_interp_clk,
5486                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5487     SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
5488                 wcd934x_codec_enable_interp_clk,
5489                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5490     SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
5491                 wcd934x_codec_enable_interp_clk,
5492                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5493     SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
5494                 wcd934x_codec_enable_interp_clk,
5495                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5496     SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
5497                 0, 0, NULL, 0),
5498     SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
5499                 0, 0, NULL, 0),
5500     SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
5501                 0, 0, NULL, 0),
5502     SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
5503                 0, 0, NULL, 0),
5504     SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
5505                 0, 0, NULL, 0),
5506     SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
5507                 0, 0, NULL, 0),
5508     SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
5509                 0, 0, NULL, 0),
5510     SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
5511                 wcd934x_codec_enable_mclk,
5512                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5513 
5514     /* TX */
5515     SND_SOC_DAPM_INPUT("AMIC1"),
5516     SND_SOC_DAPM_INPUT("AMIC2"),
5517     SND_SOC_DAPM_INPUT("AMIC3"),
5518     SND_SOC_DAPM_INPUT("AMIC4"),
5519     SND_SOC_DAPM_INPUT("AMIC5"),
5520     SND_SOC_DAPM_INPUT("DMIC0 Pin"),
5521     SND_SOC_DAPM_INPUT("DMIC1 Pin"),
5522     SND_SOC_DAPM_INPUT("DMIC2 Pin"),
5523     SND_SOC_DAPM_INPUT("DMIC3 Pin"),
5524     SND_SOC_DAPM_INPUT("DMIC4 Pin"),
5525     SND_SOC_DAPM_INPUT("DMIC5 Pin"),
5526 
5527     SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
5528                    AIF1_CAP, 0, wcd934x_codec_enable_slim,
5529                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5530     SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
5531                    AIF2_CAP, 0, wcd934x_codec_enable_slim,
5532                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5533     SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
5534                    AIF3_CAP, 0, wcd934x_codec_enable_slim,
5535                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5536 
5537     SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5538     SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5539     SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5540     SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5541     SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5542     SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5543     SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5544     SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5545     SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
5546     SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
5547     SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
5548     SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
5549     SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
5550 
5551     /* Digital Mic Inputs */
5552     SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
5553                wcd934x_codec_enable_dmic,
5554                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5555     SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
5556                wcd934x_codec_enable_dmic,
5557                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5558     SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
5559                wcd934x_codec_enable_dmic,
5560                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5561     SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
5562                wcd934x_codec_enable_dmic,
5563                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5564     SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
5565                wcd934x_codec_enable_dmic,
5566                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5567     SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
5568                wcd934x_codec_enable_dmic,
5569                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5570     SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
5571     SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
5572     SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
5573     SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
5574     SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
5575     SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
5576     SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
5577     SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
5578     SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
5579     SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
5580     SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
5581     SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
5582     SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
5583     SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
5584     SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
5585     SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
5586     SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
5587     SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
5588     SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
5589                &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
5590                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5591                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5592     SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
5593                &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
5594                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5595                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5596     SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
5597                &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
5598                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5599                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5600     SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
5601                &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
5602                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5603                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5604     SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
5605                &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
5606                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5607                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5608     SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
5609                &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
5610                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5611                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5612     SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
5613                &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
5614                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5615                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5616     SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
5617                &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
5618                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5619                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5620     SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
5621                &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
5622                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5623                SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5624     SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
5625                wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5626     SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
5627                wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5628     SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
5629                wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5630     SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
5631                wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5632     SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
5633                 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5634                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5635     SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
5636                 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5637                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5638     SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
5639                 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5640                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5641     SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
5642                 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5643                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5644 
5645     SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
5646     SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
5647              &cdc_if_tx0_mux),
5648     SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
5649              &cdc_if_tx1_mux),
5650     SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
5651              &cdc_if_tx2_mux),
5652     SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
5653              &cdc_if_tx3_mux),
5654     SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
5655              &cdc_if_tx4_mux),
5656     SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
5657              &cdc_if_tx5_mux),
5658     SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
5659              &cdc_if_tx6_mux),
5660     SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
5661              &cdc_if_tx7_mux),
5662     SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
5663              &cdc_if_tx8_mux),
5664     SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
5665              &cdc_if_tx9_mux),
5666     SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
5667              &cdc_if_tx10_mux),
5668     SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5669              &cdc_if_tx11_mux),
5670     SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5671              &cdc_if_tx11_inp1_mux),
5672     SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5673              &cdc_if_tx13_mux),
5674     SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5675              &cdc_if_tx13_inp1_mux),
5676     SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
5677                aif1_slim_cap_mixer,
5678                ARRAY_SIZE(aif1_slim_cap_mixer)),
5679     SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
5680                aif2_slim_cap_mixer,
5681                ARRAY_SIZE(aif2_slim_cap_mixer)),
5682     SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
5683                aif3_slim_cap_mixer,
5684                ARRAY_SIZE(aif3_slim_cap_mixer)),
5685 };
5686 
5687 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
5688     /* RX0-RX7 */
5689     WCD934X_SLIM_RX_AIF_PATH(0),
5690     WCD934X_SLIM_RX_AIF_PATH(1),
5691     WCD934X_SLIM_RX_AIF_PATH(2),
5692     WCD934X_SLIM_RX_AIF_PATH(3),
5693     WCD934X_SLIM_RX_AIF_PATH(4),
5694     WCD934X_SLIM_RX_AIF_PATH(5),
5695     WCD934X_SLIM_RX_AIF_PATH(6),
5696     WCD934X_SLIM_RX_AIF_PATH(7),
5697 
5698     /* RX0 Ear out */
5699     WCD934X_INTERPOLATOR_PATH(0),
5700     WCD934X_INTERPOLATOR_MIX2(0),
5701     {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
5702     {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
5703     {"RX INT0 DAC", NULL, "RX_BIAS"},
5704     {"EAR PA", NULL, "RX INT0 DAC"},
5705     {"EAR", NULL, "EAR PA"},
5706 
5707     /* RX1 Headphone left */
5708     WCD934X_INTERPOLATOR_PATH(1),
5709     WCD934X_INTERPOLATOR_MIX2(1),
5710     {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
5711     {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
5712     {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
5713     {"RX INT1 DAC", NULL, "RX_BIAS"},
5714     {"HPHL PA", NULL, "RX INT1 DAC"},
5715     {"HPHL", NULL, "HPHL PA"},
5716 
5717     /* RX2 Headphone right */
5718     WCD934X_INTERPOLATOR_PATH(2),
5719     WCD934X_INTERPOLATOR_MIX2(2),
5720     {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
5721     {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
5722     {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
5723     {"RX INT2 DAC", NULL, "RX_BIAS"},
5724     {"HPHR PA", NULL, "RX INT2 DAC"},
5725     {"HPHR", NULL, "HPHR PA"},
5726 
5727     /* RX3 HIFi LineOut1 */
5728     WCD934X_INTERPOLATOR_PATH(3),
5729     WCD934X_INTERPOLATOR_MIX2(3),
5730     {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
5731     {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
5732     {"RX INT3 DAC", NULL, "RX_BIAS"},
5733     {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
5734     {"LINEOUT1", NULL, "LINEOUT1 PA"},
5735 
5736     /* RX4 HIFi LineOut2 */
5737     WCD934X_INTERPOLATOR_PATH(4),
5738     WCD934X_INTERPOLATOR_MIX2(4),
5739     {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
5740     {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
5741     {"RX INT4 DAC", NULL, "RX_BIAS"},
5742     {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
5743     {"LINEOUT2", NULL, "LINEOUT2 PA"},
5744 
5745     /* RX7 Speaker Left Out PA */
5746     WCD934X_INTERPOLATOR_PATH(7),
5747     WCD934X_INTERPOLATOR_MIX2(7),
5748     {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
5749     {"RX INT7 CHAIN", NULL, "RX_BIAS"},
5750     {"RX INT7 CHAIN", NULL, "SBOOST0"},
5751     {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
5752     {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
5753 
5754     /* RX8 Speaker Right Out PA */
5755     WCD934X_INTERPOLATOR_PATH(8),
5756     {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
5757     {"RX INT8 CHAIN", NULL, "RX_BIAS"},
5758     {"RX INT8 CHAIN", NULL, "SBOOST1"},
5759     {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
5760     {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
5761 
5762     /* Tx */
5763     {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
5764     {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
5765     {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
5766 
5767     WCD934X_SLIM_TX_AIF_PATH(0),
5768     WCD934X_SLIM_TX_AIF_PATH(1),
5769     WCD934X_SLIM_TX_AIF_PATH(2),
5770     WCD934X_SLIM_TX_AIF_PATH(3),
5771     WCD934X_SLIM_TX_AIF_PATH(4),
5772     WCD934X_SLIM_TX_AIF_PATH(5),
5773     WCD934X_SLIM_TX_AIF_PATH(6),
5774     WCD934X_SLIM_TX_AIF_PATH(7),
5775     WCD934X_SLIM_TX_AIF_PATH(8),
5776 
5777     WCD934X_ADC_MUX(0),
5778     WCD934X_ADC_MUX(1),
5779     WCD934X_ADC_MUX(2),
5780     WCD934X_ADC_MUX(3),
5781     WCD934X_ADC_MUX(4),
5782     WCD934X_ADC_MUX(5),
5783     WCD934X_ADC_MUX(6),
5784     WCD934X_ADC_MUX(7),
5785     WCD934X_ADC_MUX(8),
5786 
5787     {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
5788     {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
5789     {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
5790     {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
5791     {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
5792     {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
5793     {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
5794     {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
5795     {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5796 
5797     {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5798     {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5799 
5800     { "DMIC0", NULL, "DMIC0 Pin" },
5801     { "DMIC1", NULL, "DMIC1 Pin" },
5802     { "DMIC2", NULL, "DMIC2 Pin" },
5803     { "DMIC3", NULL, "DMIC3 Pin" },
5804     { "DMIC4", NULL, "DMIC4 Pin" },
5805     { "DMIC5", NULL, "DMIC5 Pin" },
5806 
5807     {"ADC1", NULL, "AMIC1"},
5808     {"ADC2", NULL, "AMIC2"},
5809     {"ADC3", NULL, "AMIC3"},
5810     {"ADC4", NULL, "AMIC4_5 SEL"},
5811 
5812     WCD934X_IIR_INP_MUX(0),
5813     WCD934X_IIR_INP_MUX(1),
5814 
5815     {"SRC0", NULL, "IIR0"},
5816     {"SRC1", NULL, "IIR1"},
5817 };
5818 
5819 static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
5820                   struct snd_soc_jack *jack, void *data)
5821 {
5822     struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
5823     int ret = 0;
5824 
5825     if (!wcd->mbhc)
5826         return -ENOTSUPP;
5827 
5828     if (jack && !wcd->mbhc_started) {
5829         ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
5830         wcd->mbhc_started = true;
5831     } else if (wcd->mbhc_started) {
5832         wcd_mbhc_stop(wcd->mbhc);
5833         wcd->mbhc_started = false;
5834     }
5835 
5836     return ret;
5837 }
5838 
5839 static const struct snd_soc_component_driver wcd934x_component_drv = {
5840     .probe = wcd934x_comp_probe,
5841     .remove = wcd934x_comp_remove,
5842     .set_sysclk = wcd934x_comp_set_sysclk,
5843     .controls = wcd934x_snd_controls,
5844     .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5845     .dapm_widgets = wcd934x_dapm_widgets,
5846     .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5847     .dapm_routes = wcd934x_audio_map,
5848     .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5849     .set_jack = wcd934x_codec_set_jack,
5850     .endianness = 1,
5851 };
5852 
5853 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5854 {
5855     struct device *dev = &wcd->sdev->dev;
5856     struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
5857     struct device_node *ifc_dev_np;
5858 
5859     ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5860     if (!ifc_dev_np) {
5861         dev_err(dev, "No Interface device found\n");
5862         return -EINVAL;
5863     }
5864 
5865     wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5866     of_node_put(ifc_dev_np);
5867     if (!wcd->sidev) {
5868         dev_err(dev, "Unable to get SLIM Interface device\n");
5869         return -EINVAL;
5870     }
5871 
5872     slim_get_logical_addr(wcd->sidev);
5873     wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5874                   &wcd934x_ifc_regmap_config);
5875     if (IS_ERR(wcd->if_regmap)) {
5876         dev_err(dev, "Failed to allocate ifc register map\n");
5877         return PTR_ERR(wcd->if_regmap);
5878     }
5879 
5880     of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5881                  &wcd->dmic_sample_rate);
5882 
5883     cfg->mbhc_micbias = MIC_BIAS_2;
5884     cfg->anc_micbias = MIC_BIAS_2;
5885     cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
5886     cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
5887     cfg->micb_mv = wcd->micb2_mv;
5888     cfg->linein_th = 5000;
5889     cfg->hs_thr = 1700;
5890     cfg->hph_thr = 50;
5891 
5892     wcd_dt_parse_mbhc_data(dev, cfg);
5893 
5894 
5895     return 0;
5896 }
5897 
5898 static int wcd934x_codec_probe(struct platform_device *pdev)
5899 {
5900     struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5901     struct wcd934x_codec *wcd;
5902     struct device *dev = &pdev->dev;
5903     int ret, irq;
5904 
5905     wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5906     if (!wcd)
5907         return -ENOMEM;
5908 
5909     wcd->dev = dev;
5910     wcd->regmap = data->regmap;
5911     wcd->extclk = data->extclk;
5912     wcd->sdev = to_slim_device(data->dev);
5913     mutex_init(&wcd->sysclk_mutex);
5914     mutex_init(&wcd->micb_lock);
5915 
5916     ret = wcd934x_codec_parse_data(wcd);
5917     if (ret) {
5918         dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5919         return ret;
5920     }
5921 
5922     /* set default rate 9P6MHz */
5923     regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5924                WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5925                WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5926     memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5927     memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5928 
5929     irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5930     if (irq < 0) {
5931         dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5932         return irq;
5933     }
5934 
5935     ret = devm_request_threaded_irq(dev, irq, NULL,
5936                     wcd934x_slim_irq_handler,
5937                     IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5938                     "slim", wcd);
5939     if (ret) {
5940         dev_err(dev, "Failed to request slimbus irq\n");
5941         return ret;
5942     }
5943 
5944     wcd934x_register_mclk_output(wcd);
5945     platform_set_drvdata(pdev, wcd);
5946 
5947     return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5948                            wcd934x_slim_dais,
5949                            ARRAY_SIZE(wcd934x_slim_dais));
5950 }
5951 
5952 static const struct platform_device_id wcd934x_driver_id[] = {
5953     {
5954         .name = "wcd934x-codec",
5955     },
5956     {},
5957 };
5958 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5959 
5960 static struct platform_driver wcd934x_codec_driver = {
5961     .probe  = &wcd934x_codec_probe,
5962     .id_table = wcd934x_driver_id,
5963     .driver = {
5964         .name   = "wcd934x-codec",
5965     }
5966 };
5967 
5968 MODULE_ALIAS("platform:wcd934x-codec");
5969 module_platform_driver(wcd934x_codec_driver);
5970 MODULE_DESCRIPTION("WCD934x codec driver");
5971 MODULE_LICENSE("GPL v2");
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