soc/codecs/wcd9335.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002
0003 #ifndef __WCD9335_H__
0004 #define __WCD9335_H__
0005
0006 /*
0007  * WCD9335 register base can change according to the mode it works in.
0008  * In slimbus mode the reg base starts from 0x800.
0009  * In i2s/i2c mode the reg base is 0x0.
0010  */
0011 #define WCD9335_REG(pg, r)  ((pg << 8) | (r))
0012 #define WCD9335_REG_OFFSET(r)   (r & 0xFF)
0013 #define WCD9335_PAGE_OFFSET(r)  ((r >> 8) & 0xFF)
0014
0015 /* Page-0 Registers */
0016 #define WCD9335_PAGE0_PAGE_REGISTER     WCD9335_REG(0x00, 0x000)
0017 #define WCD9335_CODEC_RPM_CLK_GATE      WCD9335_REG(0x00, 0x002)
0018 #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK   GENMASK(1, 0)
0019 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG      WCD9335_REG(0x00, 0x003)
0020 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ   BIT(0)
0021 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ    BIT(0)
0022 #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK    GENMASK(1, 0)
0023 #define WCD9335_CODEC_RPM_RST_CTL       WCD9335_REG(0x00, 0x009)
0024 #define WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL    WCD9335_REG(0x00, 0x011)
0025 #define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0    WCD9335_REG(0x00, 0x021)
0026 #define WCD9335_CHIP_TIER_CTRL_EFUSE_CTL    WCD9335_REG(0x00, 0x025)
0027 #define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1)
0028 #define WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK    BIT(0)
0029 #define WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE BIT(0)
0030 #define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0   WCD9335_REG(0x00, 0x029)
0031 #define WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS WCD9335_REG(0x00, 0x039)
0032 #define WCD9335_INTR_CFG            WCD9335_REG(0x00, 0x081)
0033 #define WCD9335_INTR_CLR_COMMIT         WCD9335_REG(0x00, 0x082)
0034 #define WCD9335_INTR_PIN1_MASK0         WCD9335_REG(0x00, 0x089)
0035 #define WCD9335_INTR_PIN1_MASK1         WCD9335_REG(0x00, 0x08a)
0036 #define WCD9335_INTR_PIN1_MASK2         WCD9335_REG(0x00, 0x08b)
0037 #define WCD9335_INTR_PIN1_MASK3         WCD9335_REG(0x00, 0x08c)
0038 #define WCD9335_INTR_PIN1_STATUS0       WCD9335_REG(0x00, 0x091)
0039 #define WCD9335_INTR_PIN1_STATUS1       WCD9335_REG(0x00, 0x092)
0040 #define WCD9335_INTR_PIN1_STATUS2       WCD9335_REG(0x00, 0x093)
0041 #define WCD9335_INTR_PIN1_STATUS3       WCD9335_REG(0x00, 0x094)
0042 #define WCD9335_INTR_PIN1_CLEAR0        WCD9335_REG(0x00, 0x099)
0043 #define WCD9335_INTR_PIN1_CLEAR1        WCD9335_REG(0x00, 0x09a)
0044 #define WCD9335_INTR_PIN1_CLEAR2        WCD9335_REG(0x00, 0x09b)
0045 #define WCD9335_INTR_PIN1_CLEAR3        WCD9335_REG(0x00, 0x09c)
0046 #define WCD9335_INTR_PIN2_MASK0         WCD9335_REG(0x00, 0x0a1)
0047 #define WCD9335_INTR_PIN2_MASK1         WCD9335_REG(0x00, 0x0a2)
0048 #define WCD9335_INTR_PIN2_MASK2         WCD9335_REG(0x00, 0x0a3)
0049 #define WCD9335_INTR_PIN2_MASK3         WCD9335_REG(0x00, 0x0a4)
0050 #define WCD9335_INTR_PIN2_STATUS0       WCD9335_REG(0x00, 0x0a9)
0051 #define WCD9335_INTR_PIN2_STATUS1       WCD9335_REG(0x00, 0x0aa)
0052 #define WCD9335_INTR_PIN2_STATUS2       WCD9335_REG(0x00, 0x0ab)
0053 #define WCD9335_INTR_PIN2_STATUS3       WCD9335_REG(0x00, 0x0ac)
0054 #define WCD9335_INTR_PIN2_CLEAR0        WCD9335_REG(0x00, 0x0b1)
0055 #define WCD9335_INTR_PIN2_CLEAR1        WCD9335_REG(0x00, 0x0b2)
0056 #define WCD9335_INTR_PIN2_CLEAR2        WCD9335_REG(0x00, 0x0b3)
0057 #define WCD9335_INTR_PIN2_CLEAR3        WCD9335_REG(0x00, 0x0b4)
0058 #define WCD9335_INTR_LEVEL0         WCD9335_REG(0x00, 0x0e1)
0059 #define WCD9335_INTR_LEVEL1         WCD9335_REG(0x00, 0x0e2)
0060 #define WCD9335_INTR_LEVEL2         WCD9335_REG(0x00, 0x0e3)
0061 #define WCD9335_INTR_LEVEL3         WCD9335_REG(0x00, 0x0e4)
0062
0063 /* Page-1 Registers */
0064 #define WCD9335_CPE_FLL_USER_CTL_0      WCD9335_REG(0x01, 0x001)
0065 #define WCD9335_CPE_FLL_USER_CTL_1      WCD9335_REG(0x01, 0x002)
0066 #define WCD9335_CPE_FLL_USER_CTL_2      WCD9335_REG(0x01, 0x003)
0067 #define WCD9335_CPE_FLL_USER_CTL_3      WCD9335_REG(0x01, 0x004)
0068 #define WCD9335_CPE_FLL_USER_CTL_4      WCD9335_REG(0x01, 0x005)
0069 #define WCD9335_CPE_FLL_USER_CTL_5      WCD9335_REG(0x01, 0x006)
0070 #define WCD9335_CPE_FLL_USER_CTL_6      WCD9335_REG(0x01, 0x007)
0071 #define WCD9335_CPE_FLL_USER_CTL_7      WCD9335_REG(0x01, 0x008)
0072 #define WCD9335_CPE_FLL_USER_CTL_8      WCD9335_REG(0x01, 0x009)
0073 #define WCD9335_CPE_FLL_USER_CTL_9      WCD9335_REG(0x01, 0x00a)
0074 #define WCD9335_CPE_FLL_L_VAL_CTL_0     WCD9335_REG(0x01, 0x00b)
0075 #define WCD9335_CPE_FLL_L_VAL_CTL_1     WCD9335_REG(0x01, 0x00c)
0076 #define WCD9335_CPE_FLL_DSM_FRAC_CTL_0      WCD9335_REG(0x01, 0x00d)
0077 #define WCD9335_CPE_FLL_DSM_FRAC_CTL_1      WCD9335_REG(0x01, 0x00e)
0078 #define WCD9335_CPE_FLL_CONFIG_CTL_0        WCD9335_REG(0x01, 0x00f)
0079 #define WCD9335_CPE_FLL_CONFIG_CTL_1        WCD9335_REG(0x01, 0x010)
0080 #define WCD9335_CPE_FLL_CONFIG_CTL_2        WCD9335_REG(0x01, 0x011)
0081 #define WCD9335_CPE_FLL_CONFIG_CTL_3        WCD9335_REG(0x01, 0x012)
0082 #define WCD9335_CPE_FLL_CONFIG_CTL_4        WCD9335_REG(0x01, 0x013)
0083 #define WCD9335_CPE_FLL_TEST_CTL_0      WCD9335_REG(0x01, 0x014)
0084 #define WCD9335_CPE_FLL_TEST_CTL_1      WCD9335_REG(0x01, 0x015)
0085 #define WCD9335_CPE_FLL_TEST_CTL_2      WCD9335_REG(0x01, 0x016)
0086 #define WCD9335_CPE_FLL_TEST_CTL_3      WCD9335_REG(0x01, 0x017)
0087 #define WCD9335_CPE_FLL_TEST_CTL_4      WCD9335_REG(0x01, 0x018)
0088 #define WCD9335_CPE_FLL_TEST_CTL_5      WCD9335_REG(0x01, 0x019)
0089 #define WCD9335_CPE_FLL_TEST_CTL_6      WCD9335_REG(0x01, 0x01a)
0090 #define WCD9335_CPE_FLL_TEST_CTL_7      WCD9335_REG(0x01, 0x01b)
0091 #define WCD9335_CPE_FLL_FREQ_CTL_0      WCD9335_REG(0x01, 0x01c)
0092 #define WCD9335_CPE_FLL_FREQ_CTL_1      WCD9335_REG(0x01, 0x01d)
0093 #define WCD9335_CPE_FLL_FREQ_CTL_2      WCD9335_REG(0x01, 0x01e)
0094 #define WCD9335_CPE_FLL_FREQ_CTL_3      WCD9335_REG(0x01, 0x01f)
0095 #define WCD9335_CPE_FLL_SSC_CTL_0       WCD9335_REG(0x01, 0x020)
0096 #define WCD9335_CPE_FLL_SSC_CTL_1       WCD9335_REG(0x01, 0x021)
0097 #define WCD9335_CPE_FLL_SSC_CTL_2       WCD9335_REG(0x01, 0x022)
0098 #define WCD9335_CPE_FLL_SSC_CTL_3       WCD9335_REG(0x01, 0x023)
0099 #define WCD9335_CPE_FLL_FLL_MODE        WCD9335_REG(0x01, 0x024)
0100 #define WCD9335_CPE_FLL_STATUS_0        WCD9335_REG(0x01, 0x025)
0101 #define WCD9335_CPE_FLL_STATUS_1        WCD9335_REG(0x01, 0x026)
0102 #define WCD9335_CPE_FLL_STATUS_2        WCD9335_REG(0x01, 0x027)
0103 #define WCD9335_CPE_FLL_STATUS_3        WCD9335_REG(0x01, 0x028)
0104 #define WCD9335_I2S_FLL_USER_CTL_0      WCD9335_REG(0x01, 0x041)
0105 #define WCD9335_I2S_FLL_USER_CTL_1      WCD9335_REG(0x01, 0x042)
0106 #define WCD9335_I2S_FLL_USER_CTL_2      WCD9335_REG(0x01, 0x043)
0107 #define WCD9335_I2S_FLL_USER_CTL_3      WCD9335_REG(0x01, 0x044)
0108 #define WCD9335_I2S_FLL_USER_CTL_4      WCD9335_REG(0x01, 0x045)
0109 #define WCD9335_I2S_FLL_USER_CTL_5      WCD9335_REG(0x01, 0x046)
0110 #define WCD9335_I2S_FLL_USER_CTL_6      WCD9335_REG(0x01, 0x047)
0111 #define WCD9335_I2S_FLL_USER_CTL_7      WCD9335_REG(0x01, 0x048)
0112 #define WCD9335_I2S_FLL_USER_CTL_8      WCD9335_REG(0x01, 0x049)
0113 #define WCD9335_I2S_FLL_USER_CTL_9      WCD9335_REG(0x01, 0x04a)
0114 #define WCD9335_I2S_FLL_L_VAL_CTL_0     WCD9335_REG(0x01, 0x04b)
0115 #define WCD9335_I2S_FLL_L_VAL_CTL_1     WCD9335_REG(0x01, 0x04c)
0116 #define WCD9335_I2S_FLL_DSM_FRAC_CTL_0      WCD9335_REG(0x01, 0x04d)
0117 #define WCD9335_I2S_FLL_DSM_FRAC_CTL_1      WCD9335_REG(0x01, 0x04e)
0118 #define WCD9335_I2S_FLL_CONFIG_CTL_0        WCD9335_REG(0x01, 0x04f)
0119 #define WCD9335_I2S_FLL_CONFIG_CTL_1        WCD9335_REG(0x01, 0x050)
0120 #define WCD9335_I2S_FLL_CONFIG_CTL_2        WCD9335_REG(0x01, 0x051)
0121 #define WCD9335_I2S_FLL_CONFIG_CTL_3        WCD9335_REG(0x01, 0x052)
0122 #define WCD9335_I2S_FLL_CONFIG_CTL_4        WCD9335_REG(0x01, 0x053)
0123 #define WCD9335_I2S_FLL_TEST_CTL_0      WCD9335_REG(0x01, 0x054)
0124 #define WCD9335_I2S_FLL_TEST_CTL_1      WCD9335_REG(0x01, 0x055)
0125 #define WCD9335_I2S_FLL_TEST_CTL_2      WCD9335_REG(0x01, 0x056)
0126 #define WCD9335_I2S_FLL_TEST_CTL_3      WCD9335_REG(0x01, 0x057)
0127 #define WCD9335_I2S_FLL_TEST_CTL_4      WCD9335_REG(0x01, 0x058)
0128 #define WCD9335_I2S_FLL_TEST_CTL_5      WCD9335_REG(0x01, 0x059)
0129 #define WCD9335_I2S_FLL_TEST_CTL_6      WCD9335_REG(0x01, 0x05a)
0130 #define WCD9335_I2S_FLL_TEST_CTL_7      WCD9335_REG(0x01, 0x05b)
0131 #define WCD9335_I2S_FLL_FREQ_CTL_0      WCD9335_REG(0x01, 0x05c)
0132 #define WCD9335_I2S_FLL_FREQ_CTL_1      WCD9335_REG(0x01, 0x05d)
0133 #define WCD9335_I2S_FLL_FREQ_CTL_2      WCD9335_REG(0x01, 0x05e)
0134 #define WCD9335_I2S_FLL_FREQ_CTL_3      WCD9335_REG(0x01, 0x05f)
0135 #define WCD9335_I2S_FLL_SSC_CTL_0       WCD9335_REG(0x01, 0x060)
0136 #define WCD9335_I2S_FLL_SSC_CTL_1       WCD9335_REG(0x01, 0x061)
0137 #define WCD9335_I2S_FLL_SSC_CTL_2       WCD9335_REG(0x01, 0x062)
0138 #define WCD9335_I2S_FLL_SSC_CTL_3       WCD9335_REG(0x01, 0x063)
0139 #define WCD9335_I2S_FLL_FLL_MODE        WCD9335_REG(0x01, 0x064)
0140 #define WCD9335_I2S_FLL_STATUS_0        WCD9335_REG(0x01, 0x065)
0141 #define WCD9335_I2S_FLL_STATUS_1        WCD9335_REG(0x01, 0x066)
0142 #define WCD9335_I2S_FLL_STATUS_2        WCD9335_REG(0x01, 0x067)
0143 #define WCD9335_I2S_FLL_STATUS_3        WCD9335_REG(0x01, 0x068)
0144 #define WCD9335_SB_FLL_USER_CTL_0       WCD9335_REG(0x01, 0x081)
0145 #define WCD9335_SB_FLL_USER_CTL_1       WCD9335_REG(0x01, 0x082)
0146 #define WCD9335_SB_FLL_USER_CTL_2       WCD9335_REG(0x01, 0x083)
0147 #define WCD9335_SB_FLL_USER_CTL_3       WCD9335_REG(0x01, 0x084)
0148 #define WCD9335_SB_FLL_USER_CTL_4       WCD9335_REG(0x01, 0x085)
0149 #define WCD9335_SB_FLL_USER_CTL_5       WCD9335_REG(0x01, 0x086)
0150 #define WCD9335_SB_FLL_USER_CTL_6       WCD9335_REG(0x01, 0x087)
0151 #define WCD9335_SB_FLL_USER_CTL_7       WCD9335_REG(0x01, 0x088)
0152 #define WCD9335_SB_FLL_USER_CTL_8       WCD9335_REG(0x01, 0x089)
0153 #define WCD9335_SB_FLL_USER_CTL_9       WCD9335_REG(0x01, 0x08a)
0154 #define WCD9335_SB_FLL_L_VAL_CTL_0      WCD9335_REG(0x01, 0x08b)
0155 #define WCD9335_SB_FLL_L_VAL_CTL_1      WCD9335_REG(0x01, 0x08c)
0156 #define WCD9335_SB_FLL_DSM_FRAC_CTL_0       WCD9335_REG(0x01, 0x08d)
0157 #define WCD9335_SB_FLL_DSM_FRAC_CTL_1       WCD9335_REG(0x01, 0x08e)
0158 #define WCD9335_SB_FLL_CONFIG_CTL_0     WCD9335_REG(0x01, 0x08f)
0159 #define WCD9335_SB_FLL_CONFIG_CTL_1     WCD9335_REG(0x01, 0x090)
0160 #define WCD9335_SB_FLL_CONFIG_CTL_2     WCD9335_REG(0x01, 0x091)
0161 #define WCD9335_SB_FLL_CONFIG_CTL_3     WCD9335_REG(0x01, 0x092)
0162 #define WCD9335_SB_FLL_CONFIG_CTL_4     WCD9335_REG(0x01, 0x093)
0163 #define WCD9335_SB_FLL_TEST_CTL_0       WCD9335_REG(0x01, 0x094)
0164 #define WCD9335_SB_FLL_TEST_CTL_1       WCD9335_REG(0x01, 0x095)
0165 #define WCD9335_SB_FLL_TEST_CTL_2       WCD9335_REG(0x01, 0x096)
0166 #define WCD9335_SB_FLL_TEST_CTL_3       WCD9335_REG(0x01, 0x097)
0167 #define WCD9335_SB_FLL_TEST_CTL_4       WCD9335_REG(0x01, 0x098)
0168 #define WCD9335_SB_FLL_TEST_CTL_5       WCD9335_REG(0x01, 0x099)
0169 #define WCD9335_SB_FLL_TEST_CTL_6       WCD9335_REG(0x01, 0x09a)
0170 #define WCD9335_SB_FLL_TEST_CTL_7       WCD9335_REG(0x01, 0x09b)
0171 #define WCD9335_SB_FLL_FREQ_CTL_0       WCD9335_REG(0x01, 0x09c)
0172 #define WCD9335_SB_FLL_FREQ_CTL_1       WCD9335_REG(0x01, 0x09d)
0173 #define WCD9335_SB_FLL_FREQ_CTL_2       WCD9335_REG(0x01, 0x09e)
0174 #define WCD9335_SB_FLL_FREQ_CTL_3       WCD9335_REG(0x01, 0x09f)
0175 #define WCD9335_SB_FLL_SSC_CTL_0        WCD9335_REG(0x01, 0x0a0)
0176 #define WCD9335_SB_FLL_SSC_CTL_1        WCD9335_REG(0x01, 0x0a1)
0177 #define WCD9335_SB_FLL_SSC_CTL_2        WCD9335_REG(0x01, 0x0a2)
0178 #define WCD9335_SB_FLL_SSC_CTL_3        WCD9335_REG(0x01, 0x0a3)
0179 #define WCD9335_SB_FLL_FLL_MODE         WCD9335_REG(0x01, 0x0a4)
0180 #define WCD9335_SB_FLL_STATUS_0         WCD9335_REG(0x01, 0x0a5)
0181 #define WCD9335_SB_FLL_STATUS_1         WCD9335_REG(0x01, 0x0a6)
0182 #define WCD9335_SB_FLL_STATUS_2         WCD9335_REG(0x01, 0x0a7)
0183 #define WCD9335_SB_FLL_STATUS_3         WCD9335_REG(0x01, 0x0a8)
0184
0185 /* Page-2 Registers */
0186 #define WCD9335_PAGE2_PAGE_REGISTER     WCD9335_REG(0x02, 0x000)
0187 #define WCD9335_CPE_SS_DMIC0_CTL        WCD9335_REG(0x02, 0x063)
0188 #define WCD9335_CPE_SS_DMIC1_CTL        WCD9335_REG(0x02, 0x064)
0189 #define WCD9335_CPE_SS_DMIC2_CTL        WCD9335_REG(0x02, 0x065)
0190 #define WCD9335_CPE_SS_DMIC_CFG         WCD9335_REG(0x02, 0x066)
0191 #define WCD9335_SOC_MAD_AUDIO_CTL_2     WCD9335_REG(0x02, 0x084)
0192
0193 /* Page-6 Registers */
0194 #define WCD9335_PAGE6_PAGE_REGISTER     WCD9335_REG(0x06, 0x000)
0195 #define WCD9335_ANA_BIAS            WCD9335_REG(0x06, 0x001)
0196 #define WCD9335_ANA_BIAS_EN_MASK        BIT(7)
0197 #define WCD9335_ANA_BIAS_ENABLE         BIT(7)
0198 #define WCD9335_ANA_BIAS_DISABLE        0
0199 #define WCD9335_ANA_BIAS_PRECHRG_EN_MASK    BIT(6)
0200 #define WCD9335_ANA_BIAS_PRECHRG_ENABLE     BIT(6)
0201 #define WCD9335_ANA_BIAS_PRECHRG_DISABLE    0
0202 #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE   BIT(5)
0203 #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_AUTO  BIT(5)
0204 #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL    0
0205 #define WCD9335_ANA_CLK_TOP         WCD9335_REG(0x06, 0x002)
0206 #define WCD9335_ANA_CLK_MCLK_EN_MASK        BIT(2)
0207 #define WCD9335_ANA_CLK_MCLK_ENABLE     BIT(2)
0208 #define WCD9335_ANA_CLK_MCLK_DISABLE        0
0209 #define WCD9335_ANA_CLK_MCLK_SRC_MASK       BIT(3)
0210 #define WCD9335_ANA_CLK_MCLK_SRC_RCO        BIT(3)
0211 #define WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL   0
0212 #define WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK  BIT(7)
0213 #define WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE   BIT(7)
0214 #define WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE  0
0215 #define WCD9335_ANA_RCO             WCD9335_REG(0x06, 0x003)
0216 #define WCD9335_ANA_RCO_BG_EN_MASK      BIT(7)
0217 #define WCD9335_ANA_RCO_BG_ENABLE       BIT(7)
0218 #define WCD9335_ANA_BUCK_VOUT_D         WCD9335_REG(0x06, 0x005)
0219 #define WCD9335_ANA_BUCK_VOUT_MASK      GENMASK(7, 0)
0220 #define WCD9335_ANA_BUCK_CTL            WCD9335_REG(0x06, 0x006)
0221 #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK   BIT(1)
0222 #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT    BIT(1)
0223 #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_INT    0
0224 #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK   BIT(2)
0225 #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT    BIT(2)
0226 #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_INT    0
0227 #define WCD9335_ANA_BUCK_CTL_RAMP_START_MASK    BIT(7)
0228 #define WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE  BIT(7)
0229 #define WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE 0
0230 #define WCD9335_ANA_RX_SUPPLIES         WCD9335_REG(0x06, 0x008)
0231 #define WCD9335_ANA_RX_BIAS_ENABLE_MASK     BIT(0)
0232 #define WCD9335_ANA_RX_BIAS_ENABLE      BIT(0)
0233 #define WCD9335_ANA_RX_BIAS_DISABLE     0
0234 #define WCD9335_ANA_HPH             WCD9335_REG(0x06, 0x009)
0235 #define WCD9335_ANA_EAR             WCD9335_REG(0x06, 0x00a)
0236 #define WCD9335_ANA_LO_1_2          WCD9335_REG(0x06, 0x00b)
0237 #define WCD9335_ANA_LO_3_4          WCD9335_REG(0x06, 0x00c)
0238 #define WCD9335_ANA_AMIC1           WCD9335_REG(0x06, 0x00e)
0239 #define WCD9335_ANA_AMIC2           WCD9335_REG(0x06, 0x00f)
0240 #define WCD9335_ANA_AMIC3           WCD9335_REG(0x06, 0x010)
0241 #define WCD9335_ANA_AMIC4           WCD9335_REG(0x06, 0x011)
0242 #define WCD9335_ANA_AMIC5           WCD9335_REG(0x06, 0x012)
0243 #define WCD9335_ANA_AMIC6           WCD9335_REG(0x06, 0x013)
0244 #define WCD9335_ANA_MBHC_MECH           WCD9335_REG(0x06, 0x014)
0245 #define WCD9335_MBHC_L_DET_EN_MASK      BIT(7)
0246 #define WCD9335_MBHC_L_DET_EN           BIT(7)
0247 #define WCD9335_MBHC_GND_DET_EN_MASK        BIT(6)
0248 #define WCD9335_MBHC_MECH_DETECT_TYPE_MASK  BIT(5)
0249 #define WCD9335_MBHC_MECH_DETECT_TYPE_SHIFT 5
0250 #define WCD9335_MBHC_HPHL_PLUG_TYPE_MASK    BIT(4)
0251 #define WCD9335_MBHC_HPHL_PLUG_TYPE_NO      BIT(4)
0252 #define WCD9335_MBHC_GND_PLUG_TYPE_MASK     BIT(3)
0253 #define WCD9335_MBHC_GND_PLUG_TYPE_NO       BIT(3)
0254 #define WCD9335_MBHC_HSL_PULLUP_COMP_EN     BIT(2)
0255 #define WCD9335_MBHC_HPHL_100K_TO_GND_EN    BIT(0)
0256
0257 #define WCD9335_ANA_MBHC_ELECT          WCD9335_REG(0x06, 0x015)
0258 #define WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK   GENMASK(6, 4)
0259 #define WCD9335_ANA_MBHC_BD_ISRC_100UA      GENMASK(5, 4)
0260 #define WCD9335_ANA_MBHC_BD_ISRC_OFF        0
0261 #define WCD9335_ANA_MBHC_BIAS_EN_MASK       BIT(0)
0262 #define WCD9335_ANA_MBHC_BIAS_EN        BIT(0)
0263 #define WCD9335_ANA_MBHC_ZDET           WCD9335_REG(0x06, 0x016)
0264 #define WCD9335_ANA_MBHC_RESULT_1       WCD9335_REG(0x06, 0x017)
0265 #define WCD9335_ANA_MBHC_RESULT_2       WCD9335_REG(0x06, 0x018)
0266 #define WCD9335_ANA_MBHC_RESULT_3       WCD9335_REG(0x06, 0x019)
0267 #define WCD9335_MBHC_BTN_RESULT_MASK        GENMASK(2, 0)
0268 #define WCD9335_ANA_MBHC_BTN0           WCD9335_REG(0x06, 0x01a)
0269 #define WCD9335_ANA_MBHC_BTN1           WCD9335_REG(0x06, 0x01b)
0270 #define WCD9335_ANA_MBHC_BTN2           WCD9335_REG(0x06, 0x01c)
0271 #define WCD9335_ANA_MBHC_BTN3           WCD9335_REG(0x06, 0x01d)
0272 #define WCD9335_ANA_MBHC_BTN4           WCD9335_REG(0x06, 0x01e)
0273 #define WCD9335_ANA_MBHC_BTN5           WCD9335_REG(0x06, 0x01f)
0274 #define WCD9335_ANA_MBHC_BTN6           WCD9335_REG(0x06, 0x020)
0275 #define WCD9335_ANA_MBHC_BTN7           WCD9335_REG(0x06, 0x021)
0276 #define WCD9335_ANA_MICB1           WCD9335_REG(0x06, 0x022)
0277 #define WCD9335_ANA_MICB2           WCD9335_REG(0x06, 0x023)
0278 #define WCD9335_ANA_MICB2_ENABLE        BIT(6)
0279 #define WCD9335_ANA_MICB2_RAMP          WCD9335_REG(0x06, 0x024)
0280 #define WCD9335_ANA_MICB3           WCD9335_REG(0x06, 0x025)
0281 #define WCD9335_ANA_MICB4           WCD9335_REG(0x06, 0x026)
0282 #define WCD9335_ANA_VBADC           WCD9335_REG(0x06, 0x027)
0283 #define WCD9335_BIAS_VBG_FINE_ADJ       WCD9335_REG(0x06, 0x029)
0284 #define WCD9335_RCO_CTRL_2          WCD9335_REG(0x06, 0x02f)
0285 #define WCD9335_SIDO_SIDO_CCL_2         WCD9335_REG(0x06, 0x042)
0286 #define WCD9335_SIDO_SIDO_CCL_4         WCD9335_REG(0x06, 0x044)
0287 #define WCD9335_SIDO_SIDO_CCL_8         WCD9335_REG(0x06, 0x048)
0288 #define WCD9335_SIDO_SIDO_CCL_10        WCD9335_REG(0x06, 0x04a)
0289 #define WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF      0x2
0290 /* Comparator 1 and 2 Bias current at 1P0UA with start pulse width of C320FF */
0291 #define WCD9335_SIDO_SIDO_CCL_DEF_VALUE     0x6e
0292 #define WCD9335_SIDO_SIDO_TEST_2        WCD9335_REG(0x06, 0x055)
0293 #define WCD9335_MBHC_CTL_1          WCD9335_REG(0x06, 0x056)
0294 #define WCD9335_MBHC_BTN_DBNC_MASK      GENMASK(1, 0)
0295 #define WCD9335_MBHC_BTN_DBNC_T_16_MS       0x2
0296 #define WCD9335_MBHC_CTL_RCO_EN_MASK        BIT(7)
0297 #define WCD9335_MBHC_CTL_RCO_EN         BIT(7)
0298
0299 #define WCD9335_MBHC_CTL_2          WCD9335_REG(0x06, 0x057)
0300 #define WCD9335_MBHC_HS_VREF_CTL_MASK       GENMASK(1, 0)
0301 #define WCD9335_MBHC_HS_VREF_1P5_V      0x1
0302 #define WCD9335_MBHC_PLUG_DETECT_CTL        WCD9335_REG(0x06, 0x058)
0303 #define WCD9335_MBHC_HSDET_PULLUP_CTL_MASK  GENMASK(7, 6)
0304 #define WCD9335_MBHC_HSDET_PULLUP_CTL_SHIFT 6
0305 #define WCD9335_MBHC_HSDET_PULLUP_CTL_1_2P0_UA  0x80
0306 #define WCD9335_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS 0x6
0307
0308 #define WCD9335_MBHC_ZDET_RAMP_CTL      WCD9335_REG(0x06, 0x05a)
0309 #define WCD9335_VBADC_IBIAS_FE          WCD9335_REG(0x06, 0x05e)
0310 #define WCD9335_FLYBACK_CTRL_1          WCD9335_REG(0x06, 0x0b1)
0311 #define WCD9335_RX_BIAS_HPH_PA          WCD9335_REG(0x06, 0x0bb)
0312 #define WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK    GENMASK(3, 0)
0313 #define WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2   WCD9335_REG(0x06, 0x0bc)
0314 #define WCD9335_RX_BIAS_HPH_RDAC_LDO        WCD9335_REG(0x06, 0x0bd)
0315 #define WCD9335_RX_BIAS_FLYB_BUFF       WCD9335_REG(0x06, 0x0c7)
0316 #define WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0)
0317 #define WCD9335_RX_BIAS_FLYB_I_0P0_UA       0
0318 #define WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4)
0319 #define WCD9335_RX_BIAS_FLYB_MID_RST        WCD9335_REG(0x06, 0x0c8)
0320 #define WCD9335_HPH_CNP_WG_CTL          WCD9335_REG(0x06, 0x0cc)
0321 #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK   GENMASK(2, 0)
0322 #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500 0x2
0323 #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000 0x3
0324 #define WCD9335_HPH_OCP_CTL         WCD9335_REG(0x06, 0x0ce)
0325 #define WCD9335_HPH_AUTO_CHOP           WCD9335_REG(0x06, 0x0cf)
0326 #define WCD9335_HPH_AUTO_CHOP_MASK      BIT(5)
0327 #define WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE      BIT(5)
0328 #define WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN      0
0329 #define WCD9335_HPH_PA_CTL1         WCD9335_REG(0x06, 0x0d1)
0330 #define WCD9335_HPH_PA_GM3_IB_SCALE_MASK        GENMASK(3, 1)
0331 #define WCD9335_HPH_PA_CTL2         WCD9335_REG(0x06, 0x0d2)
0332 #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK   BIT(2)
0333 #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE BIT(2)
0334 #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE 0
0335 #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK   BIT(3)
0336 #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE BIT(3)
0337 #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE    0
0338 #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK   BIT(5)
0339 #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE BIT(5)
0340 #define WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE    0
0341 #define WCD9335_HPH_L_EN            WCD9335_REG(0x06, 0x0d3)
0342 #define WCD9335_HPH_CONST_SEL_L_MASK        GENMASK(7, 6)
0343 #define WCD9335_HPH_CONST_SEL_L_BYPASS      0
0344 #define WCD9335_HPH_CONST_SEL_L_LP_PATH     0x40
0345 #define WCD9335_HPH_CONST_SEL_L_HQ_PATH     0x80
0346 #define WCD9335_HPH_PA_GAIN_MASK        GENMASK(4, 0)
0347 #define WCD9335_HPH_GAIN_SRC_SEL_MASK       BIT(5)
0348 #define WCD9335_HPH_GAIN_SRC_SEL_COMPANDER  0
0349 #define WCD9335_HPH_GAIN_SRC_SEL_REGISTER   BIT(5)
0350 #define WCD9335_HPH_L_TEST          WCD9335_REG(0x06, 0x0d4)
0351 #define WCD9335_HPH_R_EN            WCD9335_REG(0x06, 0x0d6)
0352 #define WCD9335_HPH_R_TEST          WCD9335_REG(0x06, 0x0d7)
0353 #define WCD9335_HPH_R_ATEST         WCD9335_REG(0x06, 0x0d8)
0354 #define WCD9335_HPH_RDAC_LDO_CTL        WCD9335_REG(0x06, 0x0db)
0355 #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK   GENMASK(2, 0)
0356 #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60    0x1
0357 #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK    GENMASK(6, 4)
0358 #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60 0x10
0359 #define WCD9335_HPH_REFBUFF_LP_CTL      WCD9335_REG(0x06, 0x0de)
0360 #define WCD9335_HPH_L_DAC_CTL           WCD9335_REG(0x06, 0x0df)
0361 #define WCD9335_HPH_DAC_LDO_POWERMODE_MASK  BIT(0)
0362 #define WCD9335_HPH_DAC_LDO_POWERMODE_LOWPOWER  0
0363 #define WCD9335_HPH_DAC_LDO_POWERMODE_UHQA  BIT(0)
0364 #define WCD9335_HPH_DAC_LDO_UHQA_OV_MASK    BIT(1)
0365 #define WCD9335_HPH_DAC_LDO_UHQA_OV_ENABLE  BIT(1)
0366 #define WCD9335_HPH_DAC_LDO_UHQA_OV_DISABLE 0
0367
0368 #define WCD9335_EAR_CMBUFF          WCD9335_REG(0x06, 0x0e2)
0369 #define WCD9335_DIFF_LO_LO2_COMPANDER       WCD9335_REG(0x06, 0x0ea)
0370 #define WCD9335_DIFF_LO_LO1_COMPANDER       WCD9335_REG(0x06, 0x0eb)
0371 #define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ   WCD9335_REG(0x06, 0x0f1)
0372 #define WCD9335_DIFF_LO_COM_PA_FREQ     WCD9335_REG(0x06, 0x0f2)
0373 #define WCD9335_SE_LO_LO3_GAIN          WCD9335_REG(0x06, 0x0f8)
0374 #define WCD9335_SE_LO_LO3_CTRL          WCD9335_REG(0x06, 0x0f9)
0375 #define WCD9335_SE_LO_LO4_GAIN          WCD9335_REG(0x06, 0x0fa)
0376
0377 /* Page-10 Registers */
0378 #define WCD9335_CDC_TX0_TX_PATH_CTL     WCD9335_REG(0x0a, 0x031)
0379 #define WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK   GENMASK(3, 0)
0380 #define WCD9335_CDC_TX_PATH_CTL(dec)    WCD9335_REG(0xa, (0x31 + dec * 0x10))
0381 #define WCD9335_CDC_TX0_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x032)
0382 #define WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK   BIT(7)
0383 #define WCD9335_CDC_TX_ADC_DMIC_SEL     BIT(7)
0384 #define WCD9335_CDC_TX_ADC_AMIC_SEL     0
0385 #define WCD9335_CDC_TX0_TX_VOL_CTL      WCD9335_REG(0x0a, 0x034)
0386 #define WCD9335_CDC_TX0_TX_PATH_SEC2        WCD9335_REG(0x0a, 0x039)
0387 #define WCD9335_CDC_TX0_TX_PATH_SEC7        WCD9335_REG(0x0a, 0x03e)
0388 #define WCD9335_CDC_TX1_TX_PATH_CTL     WCD9335_REG(0x0a, 0x041)
0389 #define WCD9335_CDC_TX1_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x042)
0390 #define WCD9335_CDC_TX2_TX_PATH_CTL     WCD9335_REG(0x0a, 0x051)
0391 #define WCD9335_CDC_TX2_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x052)
0392 #define WCD9335_CDC_TX2_TX_VOL_CTL      WCD9335_REG(0x0a, 0x054)
0393 #define WCD9335_CDC_TX3_TX_PATH_CTL     WCD9335_REG(0x0a, 0x061)
0394 #define WCD9335_CDC_TX3_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x062)
0395 #define WCD9335_CDC_TX3_TX_VOL_CTL      WCD9335_REG(0x0a, 0x064)
0396 #define WCD9335_CDC_TX4_TX_PATH_CTL     WCD9335_REG(0x0a, 0x071)
0397 #define WCD9335_CDC_TX4_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x072)
0398 #define WCD9335_CDC_TX4_TX_VOL_CTL      WCD9335_REG(0x0a, 0x074)
0399 #define WCD9335_CDC_TX5_TX_PATH_CTL     WCD9335_REG(0x0a, 0x081)
0400 #define WCD9335_CDC_TX5_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x082)
0401 #define WCD9335_CDC_TX5_TX_VOL_CTL      WCD9335_REG(0x0a, 0x084)
0402 #define WCD9335_CDC_TX6_TX_PATH_CTL     WCD9335_REG(0x0a, 0x091)
0403 #define WCD9335_CDC_TX6_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x092)
0404 #define WCD9335_CDC_TX6_TX_VOL_CTL      WCD9335_REG(0x0a, 0x094)
0405 #define WCD9335_CDC_TX7_TX_PATH_CTL     WCD9335_REG(0x0a, 0x0a1)
0406 #define WCD9335_CDC_TX7_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x0a2)
0407 #define WCD9335_CDC_TX7_TX_VOL_CTL      WCD9335_REG(0x0a, 0x0a4)
0408 #define WCD9335_CDC_TX8_TX_PATH_CTL     WCD9335_REG(0x0a, 0x0b1)
0409 #define WCD9335_CDC_TX8_TX_PATH_CFG0        WCD9335_REG(0x0a, 0x0b2)
0410 #define WCD9335_CDC_TX8_TX_VOL_CTL      WCD9335_REG(0x0a, 0x0b4)
0411 #define WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c3)
0412 #define WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0    WCD9335_REG(0x0a, 0x0c7)
0413 #define WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0    WCD9335_REG(0x0a, 0x0cb)
0414 #define WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0    WCD9335_REG(0x0a, 0x0cf)
0415
0416 /* Page-11 Registers */
0417 #define WCD9335_PAGE11_PAGE_REGISTER        WCD9335_REG(0x0b, 0x000)
0418 #define WCD9335_CDC_COMPANDER1_CTL0     WCD9335_REG(0x0b, 0x001)
0419 #define WCD9335_CDC_COMPANDER1_CTL(c)   WCD9335_REG(0x0b, (0x001 + c * 0x8))
0420 #define WCD9335_CDC_COMPANDER_CLK_EN_MASK   BIT(0)
0421 #define WCD9335_CDC_COMPANDER_CLK_ENABLE    BIT(0)
0422 #define WCD9335_CDC_COMPANDER_CLK_DISABLE   0
0423 #define WCD9335_CDC_COMPANDER_SOFT_RST_MASK BIT(1)
0424 #define WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE   BIT(1)
0425 #define WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE  0
0426 #define WCD9335_CDC_COMPANDER_HALT_MASK     BIT(2)
0427 #define WCD9335_CDC_COMPANDER_HALT      BIT(2)
0428 #define WCD9335_CDC_COMPANDER_NOHALT        0
0429 #define WCD9335_CDC_COMPANDER7_CTL3     WCD9335_REG(0x0b, 0x034)
0430 #define WCD9335_CDC_COMPANDER7_CTL7     WCD9335_REG(0x0b, 0x038)
0431 #define WCD9335_CDC_COMPANDER8_CTL3     WCD9335_REG(0x0b, 0x03c)
0432 #define WCD9335_CDC_COMPANDER8_CTL7     WCD9335_REG(0x0b, 0x040)
0433 #define WCD9335_CDC_RX0_RX_PATH_CTL     WCD9335_REG(0x0b, 0x041)
0434 #define WCD9335_CDC_RX_PGA_MUTE_EN_MASK     BIT(4)
0435 #define WCD9335_CDC_RX_PGA_MUTE_ENABLE      BIT(4)
0436 #define WCD9335_CDC_RX_PGA_MUTE_DISABLE     0
0437 #define WCD9335_CDC_RX_CLK_EN_MASK      BIT(5)
0438 #define WCD9335_CDC_RX_CLK_ENABLE       BIT(5)
0439 #define WCD9335_CDC_RX_CLK_DISABLE      0
0440 #define WCD9335_CDC_RX_RESET_MASK       BIT(6)
0441 #define WCD9335_CDC_RX_RESET_ENABLE     BIT(6)
0442 #define WCD9335_CDC_RX_RESET_DISABLE        0
0443 #define WCD9335_CDC_RX_PATH_CTL(rx) WCD9335_REG(0x0b, (0x041 + rx * 0x14))
0444 #define WCD9335_CDC_RX0_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x042)
0445 #define WCD9335_CDC_RX0_RX_PATH_CFG1        WCD9335_REG(0x0b, 0x043)
0446 #define WCD9335_CDC_RX0_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x044)
0447 #define WCD9335_CDC_RX0_RX_VOL_CTL      WCD9335_REG(0x0b, 0x045)
0448 #define WCD9335_CDC_RX0_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x046)
0449 #define WCD9335_CDC_MIX_PCM_RATE_MASK       GENMASK(3, 0)
0450 #define WCD9335_CDC_RX_PATH_MIX_CTL(rx) WCD9335_REG(0x0b, (0x46 + rx * 0x14))
0451 #define WCD9335_CDC_RX0_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x047)
0452 #define WCD9335_CDC_RX0_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x048)
0453 #define WCD9335_CDC_RX0_RX_PATH_SEC0        WCD9335_REG(0x0b, 0x049)
0454 #define WCD9335_CDC_RX0_RX_PATH_SEC7        WCD9335_REG(0x0b, 0x050)
0455 #define WCD9335_CDC_RX0_RX_PATH_MIX_SEC0    WCD9335_REG(0x0b, 0x051)
0456 #define WCD9335_CDC_RX1_RX_PATH_CTL     WCD9335_REG(0x0b, 0x055)
0457 #define WCD9335_CDC_RX1_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x056)
0458 #define WCD9335_CDC_RX1_RX_PATH_CFG(c)  WCD9335_REG(0x0b, (0x056 + c * 0x14))
0459 #define WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK BIT(1)
0460 #define WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE  BIT(1)
0461 #define WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE 0
0462 #define WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2)
0463 #define WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE  BIT(2)
0464 #define WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE 0
0465 #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK BIT(3)
0466 #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN  BIT(3)
0467 #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_DISABLE 0
0468 #define WCD9335_CDC_RX1_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x058)
0469 #define WCD9335_CDC_RX1_RX_VOL_CTL      WCD9335_REG(0x0b, 0x059)
0470 #define WCD9335_CDC_RX1_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x05a)
0471 #define WCD9335_CDC_RX1_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x05b)
0472 #define WCD9335_CDC_RX1_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x05c)
0473 #define WCD9335_CDC_RX1_RX_PATH_SEC0        WCD9335_REG(0x0b, 0x05d)
0474 #define WCD9335_CDC_RX1_RX_PATH_SEC3        WCD9335_REG(0x0b, 0x060)
0475 #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK  GENMASK(1, 0)
0476 #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2 0x1
0477 #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1 0
0478 #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK  GENMASK(5, 2)
0479 #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500    0x10
0480 #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000    0
0481 #define WCD9335_CDC_RX2_RX_PATH_CTL     WCD9335_REG(0x0b, 0x069)
0482 #define WCD9335_CDC_RX2_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x06a)
0483 #define WCD9335_CDC_RX2_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x06c)
0484 #define WCD9335_CDC_RX2_RX_VOL_CTL      WCD9335_REG(0x0b, 0x06d)
0485 #define WCD9335_CDC_RX2_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x06e)
0486 #define WCD9335_CDC_RX2_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x06f)
0487 #define WCD9335_CDC_RX2_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x070)
0488 #define WCD9335_CDC_RX2_RX_PATH_SEC0        WCD9335_REG(0x0b, 0x071)
0489 #define WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK    GENMASK(1, 0)
0490 #define WCD9335_CDC_RX2_RX_PATH_SEC3        WCD9335_REG(0x0b, 0x074)
0491 #define WCD9335_CDC_RX3_RX_PATH_CTL     WCD9335_REG(0x0b, 0x07d)
0492 #define WCD9335_CDC_RX3_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x07e)
0493 #define WCD9335_CDC_RX3_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x080)
0494 #define WCD9335_CDC_RX3_RX_VOL_CTL      WCD9335_REG(0x0b, 0x081)
0495 #define WCD9335_CDC_RX3_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x082)
0496 #define WCD9335_CDC_RX3_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x083)
0497 #define WCD9335_CDC_RX3_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x084)
0498 #define WCD9335_CDC_RX4_RX_PATH_CTL     WCD9335_REG(0x0b, 0x091)
0499 #define WCD9335_CDC_RX4_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x092)
0500 #define WCD9335_CDC_RX4_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x094)
0501 #define WCD9335_CDC_RX4_RX_VOL_CTL      WCD9335_REG(0x0b, 0x095)
0502 #define WCD9335_CDC_RX4_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x096)
0503 #define WCD9335_CDC_RX4_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x097)
0504 #define WCD9335_CDC_RX4_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x098)
0505 #define WCD9335_CDC_RX5_RX_PATH_CTL     WCD9335_REG(0x0b, 0x0a5)
0506 #define WCD9335_CDC_RX5_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x0a6)
0507 #define WCD9335_CDC_RX5_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x0a8)
0508 #define WCD9335_CDC_RX5_RX_VOL_CTL      WCD9335_REG(0x0b, 0x0a9)
0509 #define WCD9335_CDC_RX5_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x0aa)
0510 #define WCD9335_CDC_RX5_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x0ab)
0511 #define WCD9335_CDC_RX5_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x0ac)
0512 #define WCD9335_CDC_RX6_RX_PATH_CTL     WCD9335_REG(0x0b, 0x0b9)
0513 #define WCD9335_CDC_RX6_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x0ba)
0514 #define WCD9335_CDC_RX6_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x0bc)
0515 #define WCD9335_CDC_RX6_RX_VOL_CTL      WCD9335_REG(0x0b, 0x0bd)
0516 #define WCD9335_CDC_RX6_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x0be)
0517 #define WCD9335_CDC_RX6_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x0bf)
0518 #define WCD9335_CDC_RX6_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x0c0)
0519 #define WCD9335_CDC_RX7_RX_PATH_CTL     WCD9335_REG(0x0b, 0x0cd)
0520 #define WCD9335_CDC_RX7_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x0ce)
0521 #define WCD9335_CDC_RX7_RX_PATH_CFG1        WCD9335_REG(0x0b, 0x0cf)
0522 #define WCD9335_CDC_RX7_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x0d0)
0523 #define WCD9335_CDC_RX7_RX_VOL_CTL      WCD9335_REG(0x0b, 0x0d1)
0524 #define WCD9335_CDC_RX7_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x0d2)
0525 #define WCD9335_CDC_RX7_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x0d3)
0526 #define WCD9335_CDC_RX7_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x0d4)
0527 #define WCD9335_CDC_RX8_RX_PATH_CTL     WCD9335_REG(0x0b, 0x0e1)
0528 #define WCD9335_CDC_RX8_RX_PATH_CFG0        WCD9335_REG(0x0b, 0x0e2)
0529 #define WCD9335_CDC_RX8_RX_PATH_CFG1        WCD9335_REG(0x0b, 0x0e3)
0530 #define WCD9335_CDC_RX8_RX_PATH_CFG2        WCD9335_REG(0x0b, 0x0e4)
0531 #define WCD9335_CDC_RX8_RX_VOL_CTL      WCD9335_REG(0x0b, 0x0e5)
0532 #define WCD9335_CDC_RX8_RX_PATH_MIX_CTL     WCD9335_REG(0x0b, 0x0e6)
0533 #define WCD9335_CDC_RX8_RX_PATH_MIX_CFG     WCD9335_REG(0x0b, 0x0e7)
0534 #define WCD9335_CDC_RX8_RX_VOL_MIX_CTL      WCD9335_REG(0x0b, 0x0e8)
0535
0536 /* Page-12 Registers */
0537 #define WCD9335_PAGE12_PAGE_REGISTER        WCD9335_REG(0x0c, 0x000)
0538 #define WCD9335_CDC_CLSH_K2_MSB         WCD9335_REG(0x0c, 0x00a)
0539 #define WCD9335_CDC_CLSH_K2_LSB         WCD9335_REG(0x0c, 0x00b)
0540 #define WCD9335_CDC_BOOST0_BOOST_CTL        WCD9335_REG(0x0c, 0x01a)
0541 #define WCD9335_CDC_BOOST0_BOOST_CFG1       WCD9335_REG(0x0c, 0x01b)
0542 #define WCD9335_CDC_BOOST0_BOOST_CFG2       WCD9335_REG(0x0c, 0x01c)
0543 #define WCD9335_CDC_BOOST1_BOOST_CTL        WCD9335_REG(0x0c, 0x022)
0544 #define WCD9335_CDC_BOOST1_BOOST_CFG1       WCD9335_REG(0x0c, 0x023)
0545 #define WCD9335_CDC_BOOST1_BOOST_CFG2       WCD9335_REG(0x0c, 0x024)
0546
0547 /* Page-13 Registers */
0548 #define WCD9335_PAGE13_PAGE_REGISTER        WCD9335_REG(0x0d, 0x000)
0549 #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0 WCD9335_REG(0x0d, 0x001)
0550 #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(i) WCD9335_REG(0xd, (0x1 + i * 0x2))
0551 #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1 WCD9335_REG(0xd, 0x002)
0552 #define WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK  GENMASK(3, 0)
0553 #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(i) WCD9335_REG(0xd, (0x2 + i * 0x2))
0554
0555 #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0 WCD9335_REG(0x0d, 0x003)
0556 #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1 WCD9335_REG(0x0d, 0x004)
0557 #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0 WCD9335_REG(0x0d, 0x005)
0558 #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1 WCD9335_REG(0x0d, 0x006)
0559 #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0 WCD9335_REG(0x0d, 0x007)
0560 #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1 WCD9335_REG(0x0d, 0x008)
0561 #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0 WCD9335_REG(0x0d, 0x009)
0562 #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1 WCD9335_REG(0x0d, 0x00a)
0563 #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0 WCD9335_REG(0x0d, 0x00b)
0564 #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1 WCD9335_REG(0x0d, 0x00c)
0565 #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0 WCD9335_REG(0x0d, 0x00d)
0566 #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1 WCD9335_REG(0x0d, 0x00e)
0567 #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0 WCD9335_REG(0x0d, 0x00f)
0568 #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1 WCD9335_REG(0x0d, 0x010)
0569 #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0 WCD9335_REG(0x0d, 0x011)
0570 #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1 WCD9335_REG(0x0d, 0x012)
0571 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0    WCD9335_REG(0x0d, 0x01d)
0572 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1    WCD9335_REG(0x0d, 0x01e)
0573 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0    WCD9335_REG(0x0d, 0x01f)
0574 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1    WCD9335_REG(0x0d, 0x020)
0575 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0    WCD9335_REG(0x0d, 0x021)
0576 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1    WCD9335_REG(0x0d, 0x022)
0577 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0    WCD9335_REG(0x0d, 0x023)
0578 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1    WCD9335_REG(0x0d, 0x024)
0579 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0    WCD9335_REG(0x0d, 0x025)
0580 #define WCD9335_CDC_TX_INP_MUX_SEL_AMIC 0x1
0581 #define WCD9335_CDC_TX_INP_MUX_SEL_DMIC 0
0582 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0    WCD9335_REG(0x0d, 0x026)
0583 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0    WCD9335_REG(0x0d, 0x027)
0584 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0    WCD9335_REG(0x0d, 0x028)
0585 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0    WCD9335_REG(0x0d, 0x029)
0586 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0   WCD9335_REG(0x0d, 0x02b)
0587 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0   WCD9335_REG(0x0d, 0x02c)
0588 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0   WCD9335_REG(0x0d, 0x02d)
0589 #define WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0   WCD9335_REG(0x0d, 0x02e)
0590 #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0   WCD9335_REG(0x0d, 0x03a)
0591 #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1   WCD9335_REG(0x0d, 0x03b)
0592 #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2   WCD9335_REG(0x0d, 0x03c)
0593 #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3   WCD9335_REG(0x0d, 0x03d)
0594 #define WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL   WCD9335_REG(0x0d, 0x041)
0595 #define WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK   BIT(0)
0596 #define WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE    BIT(0)
0597 #define WCD9335_CDC_CLK_RST_CTRL_MCLK_DISABLE   0
0598 #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL WCD9335_REG(0x0d, 0x042)
0599 #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK BIT(0)
0600 #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE  BIT(0)
0601 #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_DISABLE 0
0602 #define WCD9335_CDC_TOP_TOP_CFG1    WCD9335_REG(0x0d, 0x082)
0603 #define WCD9335_MAX_REGISTER    0xffff
0604 #define WCD9335_SEL_REGISTER    0x800
0605
0606 /* SLIMBUS Slave Registers */
0607 #define WCD9335_SLIM_PGD_PORT_INT_EN0   WCD9335_REG(0, 0x30)
0608 #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0   WCD9335_REG(0, 0x34)
0609 #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_1   WCD9335_REG(0, 0x35)
0610 #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_0   WCD9335_REG(0, 0x36)
0611 #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1   WCD9335_REG(0, 0x37)
0612 #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0  WCD9335_REG(0, 0x38)
0613 #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_1  WCD9335_REG(0, 0x39)
0614 #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_0  WCD9335_REG(0, 0x3A)
0615 #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_1  WCD9335_REG(0, 0x3B)
0616 #define WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0    WCD9335_REG(0, 0x60)
0617 #define WCD9335_SLIM_PGD_PORT_INT_TX_SOURCE0    WCD9335_REG(0, 0x70)
0618 #define WCD9335_SLIM_PGD_RX_PORT_CFG(p) WCD9335_REG(0, (0x30 + p))
0619 #define WCD9335_SLIM_PGD_PORT_CFG(p)    WCD9335_REG(0, (0x40 + p))
0620 #define WCD9335_SLIM_PGD_TX_PORT_CFG(p) WCD9335_REG(0, (0x50 + p))
0621 #define WCD9335_SLIM_PGD_PORT_INT_SRC(p)    WCD9335_REG(0, (0x60 + p))
0622 #define WCD9335_SLIM_PGD_PORT_INT_STATUS(p) WCD9335_REG(0, (0x80 + p))
0623 #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x100 + 4 * p))
0624 /* ports range from 10-16 */
0625 #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) WCD9335_REG(0, (0x101 + 4 * p))
0626 #define WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x140 + 4 * p))
0627
0628 #define WCD9335_IRQ_SLIMBUS         0
0629 #define WCD9335_IRQ_MBHC_SW_DET         8
0630 #define WCD9335_IRQ_MBHC_ELECT_INS_REM_DET  9
0631 #define WCD9335_IRQ_MBHC_BUTTON_PRESS_DET   10
0632 #define WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET 11
0633 #define WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET  12
0634
0635 #define SLIM_MANF_ID_QCOM           0x217
0636 #define SLIM_PROD_CODE_WCD9335          0x1a0
0637
0638 #define WCD9335_VERSION_2_0     2
0639 #define WCD9335_MAX_SUPPLY  5
0640
0641 #endif /* __WCD9335_H__ */