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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * uda1380.c - Philips UDA1380 ALSA SoC audio driver
0004  *
0005  * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
0006  *
0007  * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
0008  * codec model.
0009  *
0010  * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
0011  * Copyright 2005 Openedhand Ltd.
0012  */
0013 
0014 #include <linux/module.h>
0015 #include <linux/init.h>
0016 #include <linux/types.h>
0017 #include <linux/slab.h>
0018 #include <linux/errno.h>
0019 #include <linux/gpio.h>
0020 #include <linux/delay.h>
0021 #include <linux/i2c.h>
0022 #include <linux/workqueue.h>
0023 #include <sound/core.h>
0024 #include <sound/control.h>
0025 #include <sound/initval.h>
0026 #include <sound/soc.h>
0027 #include <sound/tlv.h>
0028 #include <sound/uda1380.h>
0029 
0030 #include "uda1380.h"
0031 
0032 /* codec private data */
0033 struct uda1380_priv {
0034     struct snd_soc_component *component;
0035     unsigned int dac_clk;
0036     struct work_struct work;
0037     struct i2c_client *i2c;
0038     u16 *reg_cache;
0039 };
0040 
0041 /*
0042  * uda1380 register cache
0043  */
0044 static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
0045     0x0502, 0x0000, 0x0000, 0x3f3f,
0046     0x0202, 0x0000, 0x0000, 0x0000,
0047     0x0000, 0x0000, 0x0000, 0x0000,
0048     0x0000, 0x0000, 0x0000, 0x0000,
0049     0x0000, 0xff00, 0x0000, 0x4800,
0050     0x0000, 0x0000, 0x0000, 0x0000,
0051     0x0000, 0x0000, 0x0000, 0x0000,
0052     0x0000, 0x0000, 0x0000, 0x0000,
0053     0x0000, 0x8000, 0x0002, 0x0000,
0054 };
0055 
0056 static unsigned long uda1380_cache_dirty;
0057 
0058 /*
0059  * read uda1380 register cache
0060  */
0061 static inline unsigned int uda1380_read_reg_cache(struct snd_soc_component *component,
0062     unsigned int reg)
0063 {
0064     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0065     u16 *cache = uda1380->reg_cache;
0066 
0067     if (reg == UDA1380_RESET)
0068         return 0;
0069     if (reg >= UDA1380_CACHEREGNUM)
0070         return -1;
0071     return cache[reg];
0072 }
0073 
0074 /*
0075  * write uda1380 register cache
0076  */
0077 static inline void uda1380_write_reg_cache(struct snd_soc_component *component,
0078     u16 reg, unsigned int value)
0079 {
0080     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0081     u16 *cache = uda1380->reg_cache;
0082 
0083     if (reg >= UDA1380_CACHEREGNUM)
0084         return;
0085     if ((reg >= 0x10) && (cache[reg] != value))
0086         set_bit(reg - 0x10, &uda1380_cache_dirty);
0087     cache[reg] = value;
0088 }
0089 
0090 /*
0091  * write to the UDA1380 register space
0092  */
0093 static int uda1380_write(struct snd_soc_component *component, unsigned int reg,
0094     unsigned int value)
0095 {
0096     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0097     u8 data[3];
0098 
0099     /* data is
0100      *   data[0] is register offset
0101      *   data[1] is MS byte
0102      *   data[2] is LS byte
0103      */
0104     data[0] = reg;
0105     data[1] = (value & 0xff00) >> 8;
0106     data[2] = value & 0x00ff;
0107 
0108     uda1380_write_reg_cache(component, reg, value);
0109 
0110     /* the interpolator & decimator regs must only be written when the
0111      * codec DAI is active.
0112      */
0113     if (!snd_soc_component_active(component) && (reg >= UDA1380_MVOL))
0114         return 0;
0115     pr_debug("uda1380: hw write %x val %x\n", reg, value);
0116     if (i2c_master_send(uda1380->i2c, data, 3) == 3) {
0117         unsigned int val;
0118         i2c_master_send(uda1380->i2c, data, 1);
0119         i2c_master_recv(uda1380->i2c, data, 2);
0120         val = (data[0]<<8) | data[1];
0121         if (val != value) {
0122             pr_debug("uda1380: READ BACK VAL %x\n",
0123                     (data[0]<<8) | data[1]);
0124             return -EIO;
0125         }
0126         if (reg >= 0x10)
0127             clear_bit(reg - 0x10, &uda1380_cache_dirty);
0128         return 0;
0129     } else
0130         return -EIO;
0131 }
0132 
0133 static void uda1380_sync_cache(struct snd_soc_component *component)
0134 {
0135     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0136     int reg;
0137     u8 data[3];
0138     u16 *cache = uda1380->reg_cache;
0139 
0140     /* Sync reg_cache with the hardware */
0141     for (reg = 0; reg < UDA1380_MVOL; reg++) {
0142         data[0] = reg;
0143         data[1] = (cache[reg] & 0xff00) >> 8;
0144         data[2] = cache[reg] & 0x00ff;
0145         if (i2c_master_send(uda1380->i2c, data, 3) != 3)
0146             dev_err(component->dev, "%s: write to reg 0x%x failed\n",
0147                 __func__, reg);
0148     }
0149 }
0150 
0151 static int uda1380_reset(struct snd_soc_component *component)
0152 {
0153     struct uda1380_platform_data *pdata = component->dev->platform_data;
0154     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0155 
0156     if (gpio_is_valid(pdata->gpio_reset)) {
0157         gpio_set_value(pdata->gpio_reset, 1);
0158         mdelay(1);
0159         gpio_set_value(pdata->gpio_reset, 0);
0160     } else {
0161         u8 data[3];
0162 
0163         data[0] = UDA1380_RESET;
0164         data[1] = 0;
0165         data[2] = 0;
0166 
0167         if (i2c_master_send(uda1380->i2c, data, 3) != 3) {
0168             dev_err(component->dev, "%s: failed\n", __func__);
0169             return -EIO;
0170         }
0171     }
0172 
0173     return 0;
0174 }
0175 
0176 static void uda1380_flush_work(struct work_struct *work)
0177 {
0178     struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
0179     struct snd_soc_component *uda1380_component = uda1380->component;
0180     int bit, reg;
0181 
0182     for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
0183         reg = 0x10 + bit;
0184         pr_debug("uda1380: flush reg %x val %x:\n", reg,
0185                 uda1380_read_reg_cache(uda1380_component, reg));
0186         uda1380_write(uda1380_component, reg,
0187                 uda1380_read_reg_cache(uda1380_component, reg));
0188         clear_bit(bit, &uda1380_cache_dirty);
0189     }
0190 
0191 }
0192 
0193 /* declarations of ALSA reg_elem_REAL controls */
0194 static const char *uda1380_deemp[] = {
0195     "None",
0196     "32kHz",
0197     "44.1kHz",
0198     "48kHz",
0199     "96kHz",
0200 };
0201 static const char *uda1380_input_sel[] = {
0202     "Line",
0203     "Mic + Line R",
0204     "Line L",
0205     "Mic",
0206 };
0207 static const char *uda1380_output_sel[] = {
0208     "DAC",
0209     "Analog Mixer",
0210 };
0211 static const char *uda1380_spf_mode[] = {
0212     "Flat",
0213     "Minimum1",
0214     "Minimum2",
0215     "Maximum"
0216 };
0217 static const char *uda1380_capture_sel[] = {
0218     "ADC",
0219     "Digital Mixer"
0220 };
0221 static const char *uda1380_sel_ns[] = {
0222     "3rd-order",
0223     "5th-order"
0224 };
0225 static const char *uda1380_mix_control[] = {
0226     "off",
0227     "PCM only",
0228     "before sound processing",
0229     "after sound processing"
0230 };
0231 static const char *uda1380_sdet_setting[] = {
0232     "3200",
0233     "4800",
0234     "9600",
0235     "19200"
0236 };
0237 static const char *uda1380_os_setting[] = {
0238     "single-speed",
0239     "double-speed (no mixing)",
0240     "quad-speed (no mixing)"
0241 };
0242 
0243 static const struct soc_enum uda1380_deemp_enum[] = {
0244     SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, ARRAY_SIZE(uda1380_deemp),
0245             uda1380_deemp),
0246     SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, ARRAY_SIZE(uda1380_deemp),
0247             uda1380_deemp),
0248 };
0249 static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum,
0250                 UDA1380_ADC, 2, uda1380_input_sel);     /* SEL_MIC, SEL_LNA */
0251 static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum,
0252                 UDA1380_PM, 7, uda1380_output_sel);     /* R02_EN_AVC */
0253 static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum,
0254                 UDA1380_MODE, 14, uda1380_spf_mode);        /* M */
0255 static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum,
0256                 UDA1380_IFACE, 6, uda1380_capture_sel); /* SEL_SOURCE */
0257 static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum,
0258                 UDA1380_MIXER, 14, uda1380_sel_ns);     /* SEL_NS */
0259 static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum,
0260                 UDA1380_MIXER, 12, uda1380_mix_control);    /* MIX, MIX_POS */
0261 static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum,
0262                 UDA1380_MIXER, 4, uda1380_sdet_setting);    /* SD_VALUE */
0263 static SOC_ENUM_SINGLE_DECL(uda1380_os_enum,
0264                 UDA1380_MIXER, 0, uda1380_os_setting);  /* OS */
0265 
0266 /*
0267  * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
0268  */
0269 static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
0270 
0271 /*
0272  * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
0273  * from -66 dB in 0.5 dB steps (2 dB steps, really) and
0274  * from -52 dB in 0.25 dB steps
0275  */
0276 static const DECLARE_TLV_DB_RANGE(mvol_tlv,
0277     0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
0278     16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
0279     44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0)
0280 );
0281 
0282 /*
0283  * from -72 dB in 1.5 dB steps (6 dB steps really),
0284  * from -66 dB in 0.75 dB steps (3 dB steps really),
0285  * from -60 dB in 0.5 dB steps (2 dB steps really) and
0286  * from -46 dB in 0.25 dB steps
0287  */
0288 static const DECLARE_TLV_DB_RANGE(vc_tlv,
0289     0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
0290     8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
0291     16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
0292     44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0)
0293 );
0294 
0295 /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
0296 static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
0297 
0298 /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
0299  * off at 18 dB max) */
0300 static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
0301 
0302 /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
0303 static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
0304 
0305 /* from 0 to 24 dB in 3 dB steps */
0306 static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
0307 
0308 /* from 0 to 30 dB in 2 dB steps */
0309 static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
0310 
0311 static const struct snd_kcontrol_new uda1380_snd_controls[] = {
0312     SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
0313     SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
0314     SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv),   /* VC2 */
0315     SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv),   /* VC1 */
0316     SOC_ENUM("Sound Processing Filter", uda1380_spf_enum),              /* M */
0317     SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv),     /* TRL, TRR */
0318     SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv),   /* BBL, BBR */
0319 /**/    SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1),      /* MTM */
0320     SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1),     /* MT2 from decimation filter */
0321     SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]),        /* DE2 */
0322     SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1),      /* MT1, from digital data input */
0323     SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]),        /* DE1 */
0324     SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0),   /* DA_POL_INV */
0325     SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum),              /* SEL_NS */
0326     SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum),     /* MIX_POS, MIX */
0327     SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0),      /* SDET_ON */
0328     SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum),        /* SD_VALUE */
0329     SOC_ENUM("Oversampling Input", uda1380_os_enum),            /* OS */
0330     SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv),    /* ML_DEC, MR_DEC */
0331 /**/    SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1),        /* MT_ADC */
0332     SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
0333     SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
0334     SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv),   /* VGA_CTRL */
0335     SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0),        /* SKIP_DCFIL (before decimator) */
0336     SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0),        /* EN_DCFIL (at output of decimator) */
0337     SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0),         /* TODO: enum, see table 62 */
0338     SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1),           /* AGC_LEVEL */
0339     /* -5.5, -8, -11.5, -14 dBFS */
0340     SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
0341 };
0342 
0343 /* Input mux */
0344 static const struct snd_kcontrol_new uda1380_input_mux_control =
0345     SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
0346 
0347 /* Output mux */
0348 static const struct snd_kcontrol_new uda1380_output_mux_control =
0349     SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
0350 
0351 /* Capture mux */
0352 static const struct snd_kcontrol_new uda1380_capture_mux_control =
0353     SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
0354 
0355 
0356 static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
0357     SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
0358         &uda1380_input_mux_control),
0359     SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
0360         &uda1380_output_mux_control),
0361     SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
0362         &uda1380_capture_mux_control),
0363     SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
0364     SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
0365     SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
0366     SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
0367     SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
0368     SND_SOC_DAPM_INPUT("VINM"),
0369     SND_SOC_DAPM_INPUT("VINL"),
0370     SND_SOC_DAPM_INPUT("VINR"),
0371     SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
0372     SND_SOC_DAPM_OUTPUT("VOUTLHP"),
0373     SND_SOC_DAPM_OUTPUT("VOUTRHP"),
0374     SND_SOC_DAPM_OUTPUT("VOUTL"),
0375     SND_SOC_DAPM_OUTPUT("VOUTR"),
0376     SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
0377     SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
0378 };
0379 
0380 static const struct snd_soc_dapm_route uda1380_dapm_routes[] = {
0381 
0382     /* output mux */
0383     {"HeadPhone Driver", NULL, "Output Mux"},
0384     {"VOUTR", NULL, "Output Mux"},
0385     {"VOUTL", NULL, "Output Mux"},
0386 
0387     {"Analog Mixer", NULL, "VINR"},
0388     {"Analog Mixer", NULL, "VINL"},
0389     {"Analog Mixer", NULL, "DAC"},
0390 
0391     {"Output Mux", "DAC", "DAC"},
0392     {"Output Mux", "Analog Mixer", "Analog Mixer"},
0393 
0394     /* {"DAC", "Digital Mixer", "I2S" } */
0395 
0396     /* headphone driver */
0397     {"VOUTLHP", NULL, "HeadPhone Driver"},
0398     {"VOUTRHP", NULL, "HeadPhone Driver"},
0399 
0400     /* input mux */
0401     {"Left ADC", NULL, "Input Mux"},
0402     {"Input Mux", "Mic", "Mic LNA"},
0403     {"Input Mux", "Mic + Line R", "Mic LNA"},
0404     {"Input Mux", "Line L", "Left PGA"},
0405     {"Input Mux", "Line", "Left PGA"},
0406 
0407     /* right input */
0408     {"Right ADC", "Mic + Line R", "Right PGA"},
0409     {"Right ADC", "Line", "Right PGA"},
0410 
0411     /* inputs */
0412     {"Mic LNA", NULL, "VINM"},
0413     {"Left PGA", NULL, "VINL"},
0414     {"Right PGA", NULL, "VINR"},
0415 };
0416 
0417 static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
0418         unsigned int fmt)
0419 {
0420     struct snd_soc_component *component = codec_dai->component;
0421     int iface;
0422 
0423     /* set up DAI based upon fmt */
0424     iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
0425     iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
0426 
0427     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0428     case SND_SOC_DAIFMT_I2S:
0429         iface |= R01_SFORI_I2S | R01_SFORO_I2S;
0430         break;
0431     case SND_SOC_DAIFMT_LSB:
0432         iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
0433         break;
0434     case SND_SOC_DAIFMT_MSB:
0435         iface |= R01_SFORI_MSB | R01_SFORO_MSB;
0436     }
0437 
0438     /* DATAI is consumer only */
0439     if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)
0440         return -EINVAL;
0441 
0442     uda1380_write_reg_cache(component, UDA1380_IFACE, iface);
0443 
0444     return 0;
0445 }
0446 
0447 static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
0448         unsigned int fmt)
0449 {
0450     struct snd_soc_component *component = codec_dai->component;
0451     int iface;
0452 
0453     /* set up DAI based upon fmt */
0454     iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
0455     iface &= ~R01_SFORI_MASK;
0456 
0457     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0458     case SND_SOC_DAIFMT_I2S:
0459         iface |= R01_SFORI_I2S;
0460         break;
0461     case SND_SOC_DAIFMT_LSB:
0462         iface |= R01_SFORI_LSB16;
0463         break;
0464     case SND_SOC_DAIFMT_MSB:
0465         iface |= R01_SFORI_MSB;
0466     }
0467 
0468     /* DATAI is consumer only */
0469     if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)
0470         return -EINVAL;
0471 
0472     uda1380_write(component, UDA1380_IFACE, iface);
0473 
0474     return 0;
0475 }
0476 
0477 static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
0478         unsigned int fmt)
0479 {
0480     struct snd_soc_component *component = codec_dai->component;
0481     int iface;
0482 
0483     /* set up DAI based upon fmt */
0484     iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
0485     iface &= ~(R01_SIM | R01_SFORO_MASK);
0486 
0487     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
0488     case SND_SOC_DAIFMT_I2S:
0489         iface |= R01_SFORO_I2S;
0490         break;
0491     case SND_SOC_DAIFMT_LSB:
0492         iface |= R01_SFORO_LSB16;
0493         break;
0494     case SND_SOC_DAIFMT_MSB:
0495         iface |= R01_SFORO_MSB;
0496     }
0497 
0498     if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == SND_SOC_DAIFMT_CBP_CFP)
0499         iface |= R01_SIM;
0500 
0501     uda1380_write(component, UDA1380_IFACE, iface);
0502 
0503     return 0;
0504 }
0505 
0506 static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
0507         struct snd_soc_dai *dai)
0508 {
0509     struct snd_soc_component *component = dai->component;
0510     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0511     int mixer = uda1380_read_reg_cache(component, UDA1380_MIXER);
0512 
0513     switch (cmd) {
0514     case SNDRV_PCM_TRIGGER_START:
0515     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0516         uda1380_write_reg_cache(component, UDA1380_MIXER,
0517                     mixer & ~R14_SILENCE);
0518         schedule_work(&uda1380->work);
0519         break;
0520     case SNDRV_PCM_TRIGGER_STOP:
0521     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0522         uda1380_write_reg_cache(component, UDA1380_MIXER,
0523                     mixer | R14_SILENCE);
0524         schedule_work(&uda1380->work);
0525         break;
0526     }
0527     return 0;
0528 }
0529 
0530 static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
0531                  struct snd_pcm_hw_params *params,
0532                  struct snd_soc_dai *dai)
0533 {
0534     struct snd_soc_component *component = dai->component;
0535     u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);
0536 
0537     /* set WSPLL power and divider if running from this clock */
0538     if (clk & R00_DAC_CLK) {
0539         int rate = params_rate(params);
0540         u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);
0541         clk &= ~0x3; /* clear SEL_LOOP_DIV */
0542         switch (rate) {
0543         case 6250 ... 12500:
0544             clk |= 0x0;
0545             break;
0546         case 12501 ... 25000:
0547             clk |= 0x1;
0548             break;
0549         case 25001 ... 50000:
0550             clk |= 0x2;
0551             break;
0552         case 50001 ... 100000:
0553             clk |= 0x3;
0554             break;
0555         }
0556         uda1380_write(component, UDA1380_PM, R02_PON_PLL | pm);
0557     }
0558 
0559     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0560         clk |= R00_EN_DAC | R00_EN_INT;
0561     else
0562         clk |= R00_EN_ADC | R00_EN_DEC;
0563 
0564     uda1380_write(component, UDA1380_CLK, clk);
0565     return 0;
0566 }
0567 
0568 static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
0569                  struct snd_soc_dai *dai)
0570 {
0571     struct snd_soc_component *component = dai->component;
0572     u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);
0573 
0574     /* shut down WSPLL power if running from this clock */
0575     if (clk & R00_DAC_CLK) {
0576         u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);
0577         uda1380_write(component, UDA1380_PM, ~R02_PON_PLL & pm);
0578     }
0579 
0580     if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
0581         clk &= ~(R00_EN_DAC | R00_EN_INT);
0582     else
0583         clk &= ~(R00_EN_ADC | R00_EN_DEC);
0584 
0585     uda1380_write(component, UDA1380_CLK, clk);
0586 }
0587 
0588 static int uda1380_set_bias_level(struct snd_soc_component *component,
0589     enum snd_soc_bias_level level)
0590 {
0591     int pm = uda1380_read_reg_cache(component, UDA1380_PM);
0592     int reg;
0593     struct uda1380_platform_data *pdata = component->dev->platform_data;
0594 
0595     switch (level) {
0596     case SND_SOC_BIAS_ON:
0597     case SND_SOC_BIAS_PREPARE:
0598         /* ADC, DAC on */
0599         uda1380_write(component, UDA1380_PM, R02_PON_BIAS | pm);
0600         break;
0601     case SND_SOC_BIAS_STANDBY:
0602         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0603             if (gpio_is_valid(pdata->gpio_power)) {
0604                 gpio_set_value(pdata->gpio_power, 1);
0605                 mdelay(1);
0606                 uda1380_reset(component);
0607             }
0608 
0609             uda1380_sync_cache(component);
0610         }
0611         uda1380_write(component, UDA1380_PM, 0x0);
0612         break;
0613     case SND_SOC_BIAS_OFF:
0614         if (!gpio_is_valid(pdata->gpio_power))
0615             break;
0616 
0617         gpio_set_value(pdata->gpio_power, 0);
0618 
0619         /* Mark mixer regs cache dirty to sync them with
0620          * codec regs on power on.
0621          */
0622         for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
0623             set_bit(reg - 0x10, &uda1380_cache_dirty);
0624     }
0625     return 0;
0626 }
0627 
0628 #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
0629                SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
0630                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
0631 
0632 static const struct snd_soc_dai_ops uda1380_dai_ops = {
0633     .hw_params  = uda1380_pcm_hw_params,
0634     .shutdown   = uda1380_pcm_shutdown,
0635     .trigger    = uda1380_trigger,
0636     .set_fmt    = uda1380_set_dai_fmt_both,
0637 };
0638 
0639 static const struct snd_soc_dai_ops uda1380_dai_ops_playback = {
0640     .hw_params  = uda1380_pcm_hw_params,
0641     .shutdown   = uda1380_pcm_shutdown,
0642     .trigger    = uda1380_trigger,
0643     .set_fmt    = uda1380_set_dai_fmt_playback,
0644 };
0645 
0646 static const struct snd_soc_dai_ops uda1380_dai_ops_capture = {
0647     .hw_params  = uda1380_pcm_hw_params,
0648     .shutdown   = uda1380_pcm_shutdown,
0649     .trigger    = uda1380_trigger,
0650     .set_fmt    = uda1380_set_dai_fmt_capture,
0651 };
0652 
0653 static struct snd_soc_dai_driver uda1380_dai[] = {
0654 {
0655     .name = "uda1380-hifi",
0656     .playback = {
0657         .stream_name = "Playback",
0658         .channels_min = 1,
0659         .channels_max = 2,
0660         .rates = UDA1380_RATES,
0661         .formats = SNDRV_PCM_FMTBIT_S16_LE,},
0662     .capture = {
0663         .stream_name = "Capture",
0664         .channels_min = 1,
0665         .channels_max = 2,
0666         .rates = UDA1380_RATES,
0667         .formats = SNDRV_PCM_FMTBIT_S16_LE,},
0668     .ops = &uda1380_dai_ops,
0669 },
0670 { /* playback only - dual interface */
0671     .name = "uda1380-hifi-playback",
0672     .playback = {
0673         .stream_name = "Playback",
0674         .channels_min = 1,
0675         .channels_max = 2,
0676         .rates = UDA1380_RATES,
0677         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0678     },
0679     .ops = &uda1380_dai_ops_playback,
0680 },
0681 { /* capture only - dual interface*/
0682     .name = "uda1380-hifi-capture",
0683     .capture = {
0684         .stream_name = "Capture",
0685         .channels_min = 1,
0686         .channels_max = 2,
0687         .rates = UDA1380_RATES,
0688         .formats = SNDRV_PCM_FMTBIT_S16_LE,
0689     },
0690     .ops = &uda1380_dai_ops_capture,
0691 },
0692 };
0693 
0694 static int uda1380_probe(struct snd_soc_component *component)
0695 {
0696     struct uda1380_platform_data *pdata =component->dev->platform_data;
0697     struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
0698     int ret;
0699 
0700     uda1380->component = component;
0701 
0702     if (!gpio_is_valid(pdata->gpio_power)) {
0703         ret = uda1380_reset(component);
0704         if (ret)
0705             return ret;
0706     }
0707 
0708     INIT_WORK(&uda1380->work, uda1380_flush_work);
0709 
0710     /* set clock input */
0711     switch (pdata->dac_clk) {
0712     case UDA1380_DAC_CLK_SYSCLK:
0713         uda1380_write_reg_cache(component, UDA1380_CLK, 0);
0714         break;
0715     case UDA1380_DAC_CLK_WSPLL:
0716         uda1380_write_reg_cache(component, UDA1380_CLK,
0717             R00_DAC_CLK);
0718         break;
0719     }
0720 
0721     return 0;
0722 }
0723 
0724 static const struct snd_soc_component_driver soc_component_dev_uda1380 = {
0725     .probe          = uda1380_probe,
0726     .read           = uda1380_read_reg_cache,
0727     .write          = uda1380_write,
0728     .set_bias_level     = uda1380_set_bias_level,
0729     .controls       = uda1380_snd_controls,
0730     .num_controls       = ARRAY_SIZE(uda1380_snd_controls),
0731     .dapm_widgets       = uda1380_dapm_widgets,
0732     .num_dapm_widgets   = ARRAY_SIZE(uda1380_dapm_widgets),
0733     .dapm_routes        = uda1380_dapm_routes,
0734     .num_dapm_routes    = ARRAY_SIZE(uda1380_dapm_routes),
0735     .suspend_bias_off   = 1,
0736     .idle_bias_on       = 1,
0737     .use_pmdown_time    = 1,
0738     .endianness     = 1,
0739 };
0740 
0741 static int uda1380_i2c_probe(struct i2c_client *i2c)
0742 {
0743     struct uda1380_platform_data *pdata = i2c->dev.platform_data;
0744     struct uda1380_priv *uda1380;
0745     int ret;
0746 
0747     if (!pdata)
0748         return -EINVAL;
0749 
0750     uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv),
0751                    GFP_KERNEL);
0752     if (uda1380 == NULL)
0753         return -ENOMEM;
0754 
0755     if (gpio_is_valid(pdata->gpio_reset)) {
0756         ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_reset,
0757             GPIOF_OUT_INIT_LOW, "uda1380 reset");
0758         if (ret)
0759             return ret;
0760     }
0761 
0762     if (gpio_is_valid(pdata->gpio_power)) {
0763         ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_power,
0764             GPIOF_OUT_INIT_LOW, "uda1380 power");
0765         if (ret)
0766             return ret;
0767     }
0768 
0769     uda1380->reg_cache = devm_kmemdup(&i2c->dev,
0770                     uda1380_reg,
0771                     ARRAY_SIZE(uda1380_reg) * sizeof(u16),
0772                     GFP_KERNEL);
0773     if (!uda1380->reg_cache)
0774         return -ENOMEM;
0775 
0776     i2c_set_clientdata(i2c, uda1380);
0777     uda1380->i2c = i2c;
0778 
0779     ret = devm_snd_soc_register_component(&i2c->dev,
0780             &soc_component_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
0781     return ret;
0782 }
0783 
0784 static const struct i2c_device_id uda1380_i2c_id[] = {
0785     { "uda1380", 0 },
0786     { }
0787 };
0788 MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
0789 
0790 static const struct of_device_id uda1380_of_match[] = {
0791     { .compatible = "nxp,uda1380", },
0792     { }
0793 };
0794 MODULE_DEVICE_TABLE(of, uda1380_of_match);
0795 
0796 static struct i2c_driver uda1380_i2c_driver = {
0797     .driver = {
0798         .name =  "uda1380-codec",
0799         .of_match_table = uda1380_of_match,
0800     },
0801     .probe_new = uda1380_i2c_probe,
0802     .id_table = uda1380_i2c_id,
0803 };
0804 
0805 module_i2c_driver(uda1380_i2c_driver);
0806 
0807 MODULE_AUTHOR("Giorgio Padrin");
0808 MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
0809 MODULE_LICENSE("GPL");
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