soc/codecs/tscs454.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // tscs454.c -- TSCS454 ALSA SoC Audio driver
0003 // Copyright 2018 Tempo Semiconductor, Inc.
0004 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
0005
0006 #include <linux/kernel.h>
0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/regmap.h>
0010 #include <linux/i2c.h>
0011 #include <linux/err.h>
0012 #include <linux/string.h>
0013 #include <linux/module.h>
0014 #include <linux/delay.h>
0015 #include <linux/mutex.h>
0016
0017 #include <sound/tlv.h>
0018 #include <sound/pcm_params.h>
0019 #include <sound/pcm.h>
0020 #include <sound/soc.h>
0021 #include <sound/soc-dapm.h>
0022
0023 #include "tscs454.h"
0024
0025 static const unsigned int PLL_44_1K_RATE = (44100 * 256);
0026
0027 #define COEFF_SIZE 3
0028 #define BIQUAD_COEFF_COUNT 5
0029 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
0030
0031 #define COEFF_RAM_MAX_ADDR 0xcd
0032 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
0033 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
0034
0035 enum {
0036     TSCS454_DAI1_ID,
0037     TSCS454_DAI2_ID,
0038     TSCS454_DAI3_ID,
0039     TSCS454_DAI_COUNT,
0040 };
0041
0042 struct pll {
0043     int id;
0044     unsigned int users;
0045     struct mutex lock;
0046 };
0047
0048 static inline void pll_init(struct pll *pll, int id)
0049 {
0050     pll->id = id;
0051     mutex_init(&pll->lock);
0052 }
0053
0054 struct internal_rate {
0055     struct pll *pll;
0056 };
0057
0058 struct aif {
0059     unsigned int id;
0060     bool provider;
0061     struct pll *pll;
0062 };
0063
0064 static inline void aif_init(struct aif *aif, unsigned int id)
0065 {
0066     aif->id = id;
0067 }
0068
0069 struct coeff_ram {
0070     u8 cache[COEFF_RAM_SIZE];
0071     bool synced;
0072     struct mutex lock;
0073 };
0074
0075 static inline void init_coeff_ram_cache(u8 *cache)
0076 {
0077     static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
0078         0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
0079         0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
0080         0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
0081         0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
0082     int i;
0083
0084     for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
0085         cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
0086 }
0087
0088 static inline void coeff_ram_init(struct coeff_ram *ram)
0089 {
0090     init_coeff_ram_cache(ram->cache);
0091     mutex_init(&ram->lock);
0092 }
0093
0094 struct aifs_status {
0095     u8 streams;
0096 };
0097
0098 static inline void set_aif_status_active(struct aifs_status *status,
0099         int aif_id, bool playback)
0100 {
0101     u8 mask = 0x01 << (aif_id * 2 + !playback);
0102
0103     status->streams |= mask;
0104 }
0105
0106 static inline void set_aif_status_inactive(struct aifs_status *status,
0107         int aif_id, bool playback)
0108 {
0109     u8 mask = ~(0x01 << (aif_id * 2 + !playback));
0110
0111     status->streams &= mask;
0112 }
0113
0114 static bool aifs_active(struct aifs_status *status)
0115 {
0116     return status->streams;
0117 }
0118
0119 static bool aif_active(struct aifs_status *status, int aif_id)
0120 {
0121     return (0x03 << aif_id * 2) & status->streams;
0122 }
0123
0124 struct tscs454 {
0125     struct regmap *regmap;
0126     struct aif aifs[TSCS454_DAI_COUNT];
0127
0128     struct aifs_status aifs_status;
0129     struct mutex aifs_status_lock;
0130
0131     struct pll pll1;
0132     struct pll pll2;
0133     struct internal_rate internal_rate;
0134
0135     struct coeff_ram dac_ram;
0136     struct coeff_ram spk_ram;
0137     struct coeff_ram sub_ram;
0138
0139     struct clk *sysclk;
0140     int sysclk_src_id;
0141     unsigned int bclk_freq;
0142 };
0143
0144 struct coeff_ram_ctl {
0145     unsigned int addr;
0146     struct soc_bytes_ext bytes_ext;
0147 };
0148
0149 static const struct reg_sequence tscs454_patch[] = {
0150     /* Assign ASRC out of the box so DAI 1 just works */
0151     { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
0152     { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
0153     { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
0154     { R_TDMCTL0, FV_TDMMD_256 },
0155     { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
0156 };
0157
0158 static bool tscs454_volatile(struct device *dev, unsigned int reg)
0159 {
0160     switch (reg) {
0161     case R_PLLSTAT:
0162
0163     case R_SPKCRRDL:
0164     case R_SPKCRRDM:
0165     case R_SPKCRRDH:
0166     case R_SPKCRS:
0167
0168     case R_DACCRRDL:
0169     case R_DACCRRDM:
0170     case R_DACCRRDH:
0171     case R_DACCRS:
0172
0173     case R_SUBCRRDL:
0174     case R_SUBCRRDM:
0175     case R_SUBCRRDH:
0176     case R_SUBCRS:
0177         return true;
0178     default:
0179         return false;
0180     }
0181 }
0182
0183 static bool tscs454_writable(struct device *dev, unsigned int reg)
0184 {
0185     switch (reg) {
0186     case R_SPKCRRDL:
0187     case R_SPKCRRDM:
0188     case R_SPKCRRDH:
0189
0190     case R_DACCRRDL:
0191     case R_DACCRRDM:
0192     case R_DACCRRDH:
0193
0194     case R_SUBCRRDL:
0195     case R_SUBCRRDM:
0196     case R_SUBCRRDH:
0197         return false;
0198     default:
0199         return true;
0200     }
0201 }
0202
0203 static bool tscs454_readable(struct device *dev, unsigned int reg)
0204 {
0205     switch (reg) {
0206     case R_SPKCRWDL:
0207     case R_SPKCRWDM:
0208     case R_SPKCRWDH:
0209
0210     case R_DACCRWDL:
0211     case R_DACCRWDM:
0212     case R_DACCRWDH:
0213
0214     case R_SUBCRWDL:
0215     case R_SUBCRWDM:
0216     case R_SUBCRWDH:
0217         return false;
0218     default:
0219         return true;
0220     }
0221 }
0222
0223 static bool tscs454_precious(struct device *dev, unsigned int reg)
0224 {
0225     switch (reg) {
0226     case R_SPKCRWDL:
0227     case R_SPKCRWDM:
0228     case R_SPKCRWDH:
0229     case R_SPKCRRDL:
0230     case R_SPKCRRDM:
0231     case R_SPKCRRDH:
0232
0233     case R_DACCRWDL:
0234     case R_DACCRWDM:
0235     case R_DACCRWDH:
0236     case R_DACCRRDL:
0237     case R_DACCRRDM:
0238     case R_DACCRRDH:
0239
0240     case R_SUBCRWDL:
0241     case R_SUBCRWDM:
0242     case R_SUBCRWDH:
0243     case R_SUBCRRDL:
0244     case R_SUBCRRDM:
0245     case R_SUBCRRDH:
0246         return true;
0247     default:
0248         return false;
0249     }
0250 }
0251
0252 static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
0253     .name = "Pages",
0254     .range_min = VIRT_BASE,
0255     .range_max = VIRT_ADDR(0xFE, 0x02),
0256     .selector_reg = R_PAGESEL,
0257     .selector_mask = 0xff,
0258     .selector_shift = 0,
0259     .window_start = 0,
0260     .window_len = 0x100,
0261 };
0262
0263 static struct regmap_config const tscs454_regmap_cfg = {
0264     .reg_bits = 8,
0265     .val_bits = 8,
0266     .writeable_reg = tscs454_writable,
0267     .readable_reg = tscs454_readable,
0268     .volatile_reg = tscs454_volatile,
0269     .precious_reg = tscs454_precious,
0270     .ranges = &tscs454_regmap_range_cfg,
0271     .num_ranges = 1,
0272     .max_register = VIRT_ADDR(0xFE, 0x02),
0273     .cache_type = REGCACHE_RBTREE,
0274 };
0275
0276 static inline int tscs454_data_init(struct tscs454 *tscs454,
0277         struct i2c_client *i2c)
0278 {
0279     int i;
0280     int ret;
0281
0282     tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
0283     if (IS_ERR(tscs454->regmap)) {
0284         ret = PTR_ERR(tscs454->regmap);
0285         return ret;
0286     }
0287
0288     for (i = 0; i < TSCS454_DAI_COUNT; i++)
0289         aif_init(&tscs454->aifs[i], i);
0290
0291     mutex_init(&tscs454->aifs_status_lock);
0292     pll_init(&tscs454->pll1, 1);
0293     pll_init(&tscs454->pll2, 2);
0294
0295     coeff_ram_init(&tscs454->dac_ram);
0296     coeff_ram_init(&tscs454->spk_ram);
0297     coeff_ram_init(&tscs454->sub_ram);
0298
0299     return 0;
0300 }
0301
0302 struct reg_setting {
0303     unsigned int addr;
0304     unsigned int val;
0305 };
0306
0307 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
0308     struct snd_ctl_elem_value *ucontrol)
0309 {
0310     struct snd_soc_component *component =
0311         snd_soc_kcontrol_component(kcontrol);
0312     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0313     struct coeff_ram_ctl *ctl =
0314         (struct coeff_ram_ctl *)kcontrol->private_value;
0315     struct soc_bytes_ext *params = &ctl->bytes_ext;
0316     u8 *coeff_ram;
0317     struct mutex *coeff_ram_lock;
0318
0319     if (strstr(kcontrol->id.name, "DAC")) {
0320         coeff_ram = tscs454->dac_ram.cache;
0321         coeff_ram_lock = &tscs454->dac_ram.lock;
0322     } else if (strstr(kcontrol->id.name, "Speaker")) {
0323         coeff_ram = tscs454->spk_ram.cache;
0324         coeff_ram_lock = &tscs454->spk_ram.lock;
0325     } else if (strstr(kcontrol->id.name, "Sub")) {
0326         coeff_ram = tscs454->sub_ram.cache;
0327         coeff_ram_lock = &tscs454->sub_ram.lock;
0328     } else {
0329         return -EINVAL;
0330     }
0331
0332     mutex_lock(coeff_ram_lock);
0333
0334     memcpy(ucontrol->value.bytes.data,
0335         &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
0336
0337     mutex_unlock(coeff_ram_lock);
0338
0339     return 0;
0340 }
0341
0342 #define DACCRSTAT_MAX_TRYS 10
0343 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
0344         unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
0345         unsigned int coeff_addr, unsigned int coeff_cnt)
0346 {
0347     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0348     unsigned int val;
0349     int cnt;
0350     int trys;
0351     int ret;
0352
0353     for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
0354
0355         for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
0356             val = snd_soc_component_read(component, r_stat);
0357             if (!val)
0358                 break;
0359         }
0360
0361         if (trys == DACCRSTAT_MAX_TRYS) {
0362             ret = -EIO;
0363             dev_err(component->dev,
0364                 "Coefficient write error (%d)\n", ret);
0365             return ret;
0366         }
0367
0368         ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
0369         if (ret < 0) {
0370             dev_err(component->dev,
0371                 "Failed to write dac ram address (%d)\n", ret);
0372             return ret;
0373         }
0374
0375         ret = regmap_bulk_write(tscs454->regmap, r_wr,
0376             &coeff_ram[coeff_addr * COEFF_SIZE],
0377             COEFF_SIZE);
0378         if (ret < 0) {
0379             dev_err(component->dev,
0380                 "Failed to write dac ram (%d)\n", ret);
0381             return ret;
0382         }
0383     }
0384
0385     return 0;
0386 }
0387
0388 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
0389     struct snd_ctl_elem_value *ucontrol)
0390 {
0391     struct snd_soc_component *component =
0392         snd_soc_kcontrol_component(kcontrol);
0393     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0394     struct coeff_ram_ctl *ctl =
0395         (struct coeff_ram_ctl *)kcontrol->private_value;
0396     struct soc_bytes_ext *params = &ctl->bytes_ext;
0397     unsigned int coeff_cnt = params->max / COEFF_SIZE;
0398     u8 *coeff_ram;
0399     struct mutex *coeff_ram_lock;
0400     bool *coeff_ram_synced;
0401     unsigned int r_stat;
0402     unsigned int r_addr;
0403     unsigned int r_wr;
0404     unsigned int val;
0405     int ret;
0406
0407     if (strstr(kcontrol->id.name, "DAC")) {
0408         coeff_ram = tscs454->dac_ram.cache;
0409         coeff_ram_lock = &tscs454->dac_ram.lock;
0410         coeff_ram_synced = &tscs454->dac_ram.synced;
0411         r_stat = R_DACCRS;
0412         r_addr = R_DACCRADD;
0413         r_wr = R_DACCRWDL;
0414     } else if (strstr(kcontrol->id.name, "Speaker")) {
0415         coeff_ram = tscs454->spk_ram.cache;
0416         coeff_ram_lock = &tscs454->spk_ram.lock;
0417         coeff_ram_synced = &tscs454->spk_ram.synced;
0418         r_stat = R_SPKCRS;
0419         r_addr = R_SPKCRADD;
0420         r_wr = R_SPKCRWDL;
0421     } else if (strstr(kcontrol->id.name, "Sub")) {
0422         coeff_ram = tscs454->sub_ram.cache;
0423         coeff_ram_lock = &tscs454->sub_ram.lock;
0424         coeff_ram_synced = &tscs454->sub_ram.synced;
0425         r_stat = R_SUBCRS;
0426         r_addr = R_SUBCRADD;
0427         r_wr = R_SUBCRWDL;
0428     } else {
0429         return -EINVAL;
0430     }
0431
0432     mutex_lock(coeff_ram_lock);
0433
0434     *coeff_ram_synced = false;
0435
0436     memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
0437         ucontrol->value.bytes.data, params->max);
0438
0439     mutex_lock(&tscs454->pll1.lock);
0440     mutex_lock(&tscs454->pll2.lock);
0441
0442     val = snd_soc_component_read(component, R_PLLSTAT);
0443     if (val) { /* PLLs locked */
0444         ret = write_coeff_ram(component, coeff_ram,
0445             r_stat, r_addr, r_wr,
0446             ctl->addr, coeff_cnt);
0447         if (ret < 0) {
0448             dev_err(component->dev,
0449                 "Failed to flush coeff ram cache (%d)\n", ret);
0450             goto exit;
0451         }
0452         *coeff_ram_synced = true;
0453     }
0454
0455     ret = 0;
0456 exit:
0457     mutex_unlock(&tscs454->pll2.lock);
0458     mutex_unlock(&tscs454->pll1.lock);
0459     mutex_unlock(coeff_ram_lock);
0460
0461     return ret;
0462 }
0463
0464 static inline int coeff_ram_sync(struct snd_soc_component *component,
0465         struct tscs454 *tscs454)
0466 {
0467     int ret;
0468
0469     mutex_lock(&tscs454->dac_ram.lock);
0470     if (!tscs454->dac_ram.synced) {
0471         ret = write_coeff_ram(component, tscs454->dac_ram.cache,
0472                 R_DACCRS, R_DACCRADD, R_DACCRWDL,
0473                 0x00, COEFF_RAM_COEFF_COUNT);
0474         if (ret < 0) {
0475             mutex_unlock(&tscs454->dac_ram.lock);
0476             return ret;
0477         }
0478     }
0479     mutex_unlock(&tscs454->dac_ram.lock);
0480
0481     mutex_lock(&tscs454->spk_ram.lock);
0482     if (!tscs454->spk_ram.synced) {
0483         ret = write_coeff_ram(component, tscs454->spk_ram.cache,
0484                 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
0485                 0x00, COEFF_RAM_COEFF_COUNT);
0486         if (ret < 0) {
0487             mutex_unlock(&tscs454->spk_ram.lock);
0488             return ret;
0489         }
0490     }
0491     mutex_unlock(&tscs454->spk_ram.lock);
0492
0493     mutex_lock(&tscs454->sub_ram.lock);
0494     if (!tscs454->sub_ram.synced) {
0495         ret = write_coeff_ram(component, tscs454->sub_ram.cache,
0496                 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
0497                 0x00, COEFF_RAM_COEFF_COUNT);
0498         if (ret < 0) {
0499             mutex_unlock(&tscs454->sub_ram.lock);
0500             return ret;
0501         }
0502     }
0503     mutex_unlock(&tscs454->sub_ram.lock);
0504
0505     return 0;
0506 }
0507
0508 #define PLL_REG_SETTINGS_COUNT 11
0509 struct pll_ctl {
0510     int freq_in;
0511     struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
0512 };
0513
0514 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h)   \
0515     {                               \
0516         .freq_in = f,                       \
0517         .settings = {                       \
0518             {R_PLL1CTL, c1},                \
0519             {R_PLL1RDIV,    r1},                \
0520             {R_PLL1ODIV,    o1},                \
0521             {R_PLL1FDIVL,   f1l},               \
0522             {R_PLL1FDIVH,   f1h},               \
0523             {R_PLL2CTL, c2},                \
0524             {R_PLL2RDIV,    r2},                \
0525             {R_PLL2ODIV,    o2},                \
0526             {R_PLL2FDIVL,   f2l},               \
0527             {R_PLL2FDIVH,   f2h},               \
0528             {R_TIMEBASE,    t},             \
0529         },                          \
0530     }
0531
0532 static const struct pll_ctl pll_ctls[] = {
0533     PLL_CTL(1411200, 0x05,
0534         0xB9, 0x07, 0x02, 0xC3, 0x04,
0535         0x5A, 0x02, 0x03, 0xE0, 0x01),
0536     PLL_CTL(1536000, 0x05,
0537         0x5A, 0x02, 0x03, 0xE0, 0x01,
0538         0x5A, 0x02, 0x03, 0xB9, 0x01),
0539     PLL_CTL(2822400, 0x0A,
0540         0x63, 0x07, 0x04, 0xC3, 0x04,
0541         0x62, 0x07, 0x03, 0x48, 0x03),
0542     PLL_CTL(3072000, 0x0B,
0543         0x62, 0x07, 0x03, 0x48, 0x03,
0544         0x5A, 0x04, 0x03, 0xB9, 0x01),
0545     PLL_CTL(5644800, 0x15,
0546         0x63, 0x0E, 0x04, 0xC3, 0x04,
0547         0x5A, 0x08, 0x03, 0xE0, 0x01),
0548     PLL_CTL(6144000, 0x17,
0549         0x5A, 0x08, 0x03, 0xE0, 0x01,
0550         0x5A, 0x08, 0x03, 0xB9, 0x01),
0551     PLL_CTL(12000000, 0x2E,
0552         0x5B, 0x19, 0x03, 0x00, 0x03,
0553         0x6A, 0x19, 0x05, 0x98, 0x04),
0554     PLL_CTL(19200000, 0x4A,
0555         0x53, 0x14, 0x03, 0x80, 0x01,
0556         0x5A, 0x19, 0x03, 0xB9, 0x01),
0557     PLL_CTL(22000000, 0x55,
0558         0x6A, 0x37, 0x05, 0x00, 0x06,
0559         0x62, 0x26, 0x03, 0x49, 0x02),
0560     PLL_CTL(22579200, 0x57,
0561         0x62, 0x31, 0x03, 0x20, 0x03,
0562         0x53, 0x1D, 0x03, 0xB3, 0x01),
0563     PLL_CTL(24000000, 0x5D,
0564         0x53, 0x19, 0x03, 0x80, 0x01,
0565         0x5B, 0x19, 0x05, 0x4C, 0x02),
0566     PLL_CTL(24576000, 0x5F,
0567         0x53, 0x1D, 0x03, 0xB3, 0x01,
0568         0x62, 0x40, 0x03, 0x72, 0x03),
0569     PLL_CTL(27000000, 0x68,
0570         0x62, 0x4B, 0x03, 0x00, 0x04,
0571         0x6A, 0x7D, 0x03, 0x20, 0x06),
0572     PLL_CTL(36000000, 0x8C,
0573         0x5B, 0x4B, 0x03, 0x00, 0x03,
0574         0x6A, 0x7D, 0x03, 0x98, 0x04),
0575     PLL_CTL(11289600, 0x2B,
0576         0x6A, 0x31, 0x03, 0x40, 0x06,
0577         0x5A, 0x12, 0x03, 0x1C, 0x02),
0578     PLL_CTL(26000000, 0x65,
0579         0x63, 0x41, 0x05, 0x00, 0x06,
0580         0x5A, 0x26, 0x03, 0xEF, 0x01),
0581     PLL_CTL(12288000, 0x2F,
0582         0x5A, 0x12, 0x03, 0x1C, 0x02,
0583         0x62, 0x20, 0x03, 0x72, 0x03),
0584     PLL_CTL(40000000, 0x9B,
0585         0xA2, 0x7D, 0x03, 0x80, 0x04,
0586         0x63, 0x7D, 0x05, 0xE4, 0x06),
0587     PLL_CTL(512000, 0x01,
0588         0x62, 0x01, 0x03, 0xD0, 0x02,
0589         0x5B, 0x01, 0x04, 0x72, 0x03),
0590     PLL_CTL(705600, 0x02,
0591         0x62, 0x02, 0x03, 0x15, 0x04,
0592         0x62, 0x01, 0x04, 0x80, 0x02),
0593     PLL_CTL(1024000, 0x03,
0594         0x62, 0x02, 0x03, 0xD0, 0x02,
0595         0x5B, 0x02, 0x04, 0x72, 0x03),
0596     PLL_CTL(2048000, 0x07,
0597         0x62, 0x04, 0x03, 0xD0, 0x02,
0598         0x5B, 0x04, 0x04, 0x72, 0x03),
0599     PLL_CTL(2400000, 0x08,
0600         0x62, 0x05, 0x03, 0x00, 0x03,
0601         0x63, 0x05, 0x05, 0x98, 0x04),
0602 };
0603
0604 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
0605 {
0606     int i;
0607     struct pll_ctl const *pll_ctl = NULL;
0608
0609     for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
0610         if (pll_ctls[i].freq_in == freq_in) {
0611             pll_ctl = &pll_ctls[i];
0612             break;
0613         }
0614
0615     return pll_ctl;
0616 }
0617
0618 enum {
0619     PLL_INPUT_XTAL = 0,
0620     PLL_INPUT_MCLK1,
0621     PLL_INPUT_MCLK2,
0622     PLL_INPUT_BCLK,
0623 };
0624
0625 static int set_sysclk(struct snd_soc_component *component)
0626 {
0627     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0628     struct pll_ctl const *pll_ctl;
0629     unsigned long freq;
0630     int i;
0631     int ret;
0632
0633     if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
0634         freq = clk_get_rate(tscs454->sysclk);
0635     else
0636         freq = tscs454->bclk_freq;
0637     pll_ctl = get_pll_ctl(freq);
0638     if (!pll_ctl) {
0639         ret = -EINVAL;
0640         dev_err(component->dev,
0641                 "Invalid PLL input %lu (%d)\n", freq, ret);
0642         return ret;
0643     }
0644
0645     for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
0646         ret = snd_soc_component_write(component,
0647                 pll_ctl->settings[i].addr,
0648                 pll_ctl->settings[i].val);
0649         if (ret < 0) {
0650             dev_err(component->dev,
0651                     "Failed to set pll setting (%d)\n",
0652                     ret);
0653             return ret;
0654         }
0655     }
0656
0657     return 0;
0658 }
0659
0660 static inline void reserve_pll(struct pll *pll)
0661 {
0662     mutex_lock(&pll->lock);
0663     pll->users++;
0664     mutex_unlock(&pll->lock);
0665 }
0666
0667 static inline void free_pll(struct pll *pll)
0668 {
0669     mutex_lock(&pll->lock);
0670     pll->users--;
0671     mutex_unlock(&pll->lock);
0672 }
0673
0674 static int pll_connected(struct snd_soc_dapm_widget *source,
0675         struct snd_soc_dapm_widget *sink)
0676 {
0677     struct snd_soc_component *component =
0678         snd_soc_dapm_to_component(source->dapm);
0679     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0680     int users;
0681
0682     if (strstr(source->name, "PLL 1")) {
0683         mutex_lock(&tscs454->pll1.lock);
0684         users = tscs454->pll1.users;
0685         mutex_unlock(&tscs454->pll1.lock);
0686         dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
0687                 users);
0688     } else {
0689         mutex_lock(&tscs454->pll2.lock);
0690         users = tscs454->pll2.users;
0691         mutex_unlock(&tscs454->pll2.lock);
0692         dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
0693                 users);
0694     }
0695
0696     return users;
0697 }
0698
0699 /*
0700  * PLL must be enabled after power up and must be disabled before power down
0701  * for proper clock switching.
0702  */
0703 static int pll_power_event(struct snd_soc_dapm_widget *w,
0704         struct snd_kcontrol *kcontrol, int event)
0705 {
0706     struct snd_soc_component *component =
0707         snd_soc_dapm_to_component(w->dapm);
0708     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0709     bool enable;
0710     bool pll1;
0711     unsigned int msk;
0712     unsigned int val;
0713     int ret;
0714
0715     if (strstr(w->name, "PLL 1"))
0716         pll1 = true;
0717     else
0718         pll1 = false;
0719
0720     msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
0721
0722     if (event == SND_SOC_DAPM_POST_PMU)
0723         enable = true;
0724     else
0725         enable = false;
0726
0727     if (enable)
0728         val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
0729     else
0730         /*
0731          * FV_PLL1CLKEN_DISABLE and FV_PLL2CLKEN_DISABLE are
0732          * identical zero vzalues, there is no need to test
0733          * the PLL index
0734          */
0735         val = FV_PLL1CLKEN_DISABLE;
0736
0737     ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
0738     if (ret < 0) {
0739         dev_err(component->dev, "Failed to %s PLL %d  (%d)\n",
0740                 enable ? "enable" : "disable",
0741                 pll1 ? 1 : 2,
0742                 ret);
0743         return ret;
0744     }
0745
0746     if (enable) {
0747         msleep(20); // Wait for lock
0748         ret = coeff_ram_sync(component, tscs454);
0749         if (ret < 0) {
0750             dev_err(component->dev,
0751                     "Failed to sync coeff ram (%d)\n", ret);
0752             return ret;
0753         }
0754     }
0755
0756     return 0;
0757 }
0758
0759 static inline int aif_set_provider(struct snd_soc_component *component,
0760         unsigned int aif_id, bool provider)
0761 {
0762     unsigned int reg;
0763     unsigned int mask;
0764     unsigned int val;
0765     int ret;
0766
0767     switch (aif_id) {
0768     case TSCS454_DAI1_ID:
0769         reg = R_I2SP1CTL;
0770         break;
0771     case TSCS454_DAI2_ID:
0772         reg = R_I2SP2CTL;
0773         break;
0774     case TSCS454_DAI3_ID:
0775         reg = R_I2SP3CTL;
0776         break;
0777     default:
0778         ret = -ENODEV;
0779         dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
0780         return ret;
0781     }
0782     mask = FM_I2SPCTL_PORTMS;
0783     val = provider ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
0784
0785     ret = snd_soc_component_update_bits(component, reg, mask, val);
0786     if (ret < 0) {
0787         dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
0788             aif_id, provider ? "provider" : "consumer", ret);
0789         return ret;
0790     }
0791
0792     return 0;
0793 }
0794
0795 static inline
0796 int aif_prepare(struct snd_soc_component *component, struct aif *aif)
0797 {
0798     int ret;
0799
0800     ret = aif_set_provider(component, aif->id, aif->provider);
0801     if (ret < 0)
0802         return ret;
0803
0804     return 0;
0805 }
0806
0807 static inline int aif_free(struct snd_soc_component *component,
0808         struct aif *aif, bool playback)
0809 {
0810     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
0811
0812     mutex_lock(&tscs454->aifs_status_lock);
0813
0814     dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
0815
0816     set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
0817
0818     dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
0819         aif->id, tscs454->aifs_status.streams);
0820
0821     if (!aif_active(&tscs454->aifs_status, aif->id)) {
0822         /* Do config in slave mode */
0823         aif_set_provider(component, aif->id, false);
0824         dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
0825                 aif->pll->id, aif->id);
0826         free_pll(aif->pll);
0827     }
0828
0829     if (!aifs_active(&tscs454->aifs_status)) {
0830         dev_dbg(component->dev, "Freeing pll %d from ir\n",
0831                 tscs454->internal_rate.pll->id);
0832         free_pll(tscs454->internal_rate.pll);
0833     }
0834
0835     mutex_unlock(&tscs454->aifs_status_lock);
0836
0837     return 0;
0838 }
0839
0840 /* R_PLLCTL PG 0 ADDR 0x15 */
0841 static char const * const bclk_sel_txt[] = {
0842         "BCLK 1", "BCLK 2", "BCLK 3"};
0843
0844 static struct soc_enum const bclk_sel_enum =
0845         SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
0846                 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
0847
0848 /* R_ISRC PG 0 ADDR 0x16 */
0849 static char const * const isrc_br_txt[] = {
0850         "44.1kHz", "48kHz"};
0851
0852 static struct soc_enum const isrc_br_enum =
0853         SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
0854                 ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
0855
0856 static char const * const isrc_bm_txt[] = {
0857         "0.25x", "0.5x", "1.0x", "2.0x"};
0858
0859 static struct soc_enum const isrc_bm_enum =
0860         SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
0861                 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
0862
0863 /* R_SCLKCTL PG 0 ADDR 0x18 */
0864 static char const * const modular_rate_txt[] = {
0865     "Reserved", "Half", "Full", "Auto",};
0866
0867 static struct soc_enum const adc_modular_rate_enum =
0868     SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
0869             ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
0870
0871 static struct soc_enum const dac_modular_rate_enum =
0872     SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
0873             ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
0874
0875 /* R_I2SIDCTL PG 0 ADDR 0x38 */
0876 static char const * const data_ctrl_txt[] = {
0877     "L/R", "L/L", "R/R", "R/L"};
0878
0879 static struct soc_enum const data_in_ctrl_enums[] = {
0880     SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
0881             ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
0882     SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
0883             ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
0884     SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
0885             ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
0886 };
0887
0888 /* R_I2SODCTL PG 0 ADDR 0x39 */
0889 static struct soc_enum const data_out_ctrl_enums[] = {
0890     SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
0891             ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
0892     SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
0893             ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
0894     SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
0895             ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
0896 };
0897
0898 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
0899 static char const * const asrc_mux_txt[] = {
0900         "None", "DAI 1", "DAI 2", "DAI 3"};
0901
0902 static struct soc_enum const asrc_in_mux_enum =
0903         SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
0904                 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
0905
0906 static char const * const dai_mux_txt[] = {
0907         "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
0908         "DMic 2", "ClassD", "DAC", "Sub"};
0909
0910 static struct soc_enum const dai2_mux_enum =
0911         SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
0912                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
0913
0914 static struct snd_kcontrol_new const dai2_mux_dapm_enum =
0915         SOC_DAPM_ENUM("DAI 2 Mux",  dai2_mux_enum);
0916
0917 static struct soc_enum const dai1_mux_enum =
0918         SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
0919                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
0920
0921 static struct snd_kcontrol_new const dai1_mux_dapm_enum =
0922         SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
0923
0924 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
0925 static struct soc_enum const asrc_out_mux_enum =
0926         SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
0927                 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
0928
0929 static struct soc_enum const dac_mux_enum =
0930         SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
0931                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
0932
0933 static struct snd_kcontrol_new const dac_mux_dapm_enum =
0934         SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
0935
0936 static struct soc_enum const dai3_mux_enum =
0937         SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
0938                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
0939
0940 static struct snd_kcontrol_new const dai3_mux_dapm_enum =
0941         SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
0942
0943 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
0944 static char const * const sub_mux_txt[] = {
0945         "CH 0", "CH 1", "CH 0 + 1",
0946         "CH 2", "CH 3", "CH 2 + 3",
0947         "CH 4", "CH 5", "CH 4 + 5",
0948         "ADC/DMic 1 Left", "ADC/DMic 1 Right",
0949         "ADC/DMic 1 Left Plus Right",
0950         "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
0951         "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
0952
0953 static struct soc_enum const sub_mux_enum =
0954         SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
0955                 ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
0956
0957 static struct snd_kcontrol_new const sub_mux_dapm_enum =
0958         SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
0959
0960 static struct soc_enum const classd_mux_enum =
0961         SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
0962                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
0963
0964 static struct snd_kcontrol_new const classd_mux_dapm_enum =
0965         SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
0966
0967 /* R_HSDCTL1 PG 1 ADDR 0x01 */
0968 static char const * const jack_type_txt[] = {
0969         "3 Terminal", "4 Terminal"};
0970
0971 static struct soc_enum const hp_jack_type_enum =
0972         SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
0973                 ARRAY_SIZE(jack_type_txt), jack_type_txt);
0974
0975 static char const * const hs_det_pol_txt[] = {
0976         "Rising", "Falling"};
0977
0978 static struct soc_enum const hs_det_pol_enum =
0979         SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
0980                 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
0981
0982 /* R_HSDCTL1 PG 1 ADDR 0x02 */
0983 static char const * const hs_mic_bias_force_txt[] = {
0984         "Off", "Ring", "Sleeve"};
0985
0986 static struct soc_enum const hs_mic_bias_force_enum =
0987         SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
0988                 ARRAY_SIZE(hs_mic_bias_force_txt),
0989                 hs_mic_bias_force_txt);
0990
0991 static char const * const plug_type_txt[] = {
0992         "OMTP", "CTIA", "Reserved", "Headphone"};
0993
0994 static struct soc_enum const plug_type_force_enum =
0995         SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
0996         ARRAY_SIZE(plug_type_txt), plug_type_txt);
0997
0998
0999 /* R_CH0AIC PG 1 ADDR 0x06 */
1000 static char const * const in_bst_mux_txt[] = {
1001         "Input 1", "Input 2", "Input 3", "D2S"};
1002
1003 static struct soc_enum const in_bst_mux_ch0_enum =
1004         SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
1005                 ARRAY_SIZE(in_bst_mux_txt),
1006                 in_bst_mux_txt);
1007 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
1008         SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1009                 in_bst_mux_ch0_enum);
1010
1011 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
1012
1013 static char const * const adc_mux_txt[] = {
1014         "Input 1 Boost Bypass", "Input 2 Boost Bypass",
1015         "Input 3 Boost Bypass", "Input Boost"};
1016
1017 static struct soc_enum const adc_mux_ch0_enum =
1018         SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
1019                 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1020 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
1021         SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1022
1023 static char const * const in_proc_mux_txt[] = {
1024         "ADC", "DMic"};
1025
1026 static struct soc_enum const in_proc_ch0_enum =
1027         SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
1028                 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1029 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
1030         SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1031                 in_proc_ch0_enum);
1032
1033 /* R_CH1AIC PG 1 ADDR 0x07 */
1034 static struct soc_enum const in_bst_mux_ch1_enum =
1035         SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
1036                 ARRAY_SIZE(in_bst_mux_txt),
1037                 in_bst_mux_txt);
1038 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
1039         SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1040                 in_bst_mux_ch1_enum);
1041
1042 static struct soc_enum const adc_mux_ch1_enum =
1043         SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
1044                 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1045 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
1046         SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1047
1048 static struct soc_enum const in_proc_ch1_enum =
1049         SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
1050                 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1051 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
1052         SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1053                 in_proc_ch1_enum);
1054
1055 /* R_ICTL0 PG 1 ADDR 0x0A */
1056 static char const * const pol_txt[] = {
1057         "Normal", "Invert"};
1058
1059 static struct soc_enum const in_pol_ch1_enum =
1060         SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
1061                 ARRAY_SIZE(pol_txt), pol_txt);
1062
1063 static struct soc_enum const in_pol_ch0_enum =
1064         SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
1065                 ARRAY_SIZE(pol_txt), pol_txt);
1066
1067 static char const * const in_proc_ch_sel_txt[] = {
1068         "Normal", "Mono Mix to Channel 0",
1069         "Mono Mix to Channel 1", "Add"};
1070
1071 static struct soc_enum const in_proc_ch01_sel_enum =
1072         SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
1073                 ARRAY_SIZE(in_proc_ch_sel_txt),
1074                 in_proc_ch_sel_txt);
1075
1076 /* R_ICTL1 PG 1 ADDR 0x0B */
1077 static struct soc_enum const in_pol_ch3_enum =
1078         SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
1079                 ARRAY_SIZE(pol_txt), pol_txt);
1080
1081 static struct soc_enum const in_pol_ch2_enum =
1082         SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
1083                 ARRAY_SIZE(pol_txt), pol_txt);
1084
1085 static struct soc_enum const in_proc_ch23_sel_enum =
1086         SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
1087                 ARRAY_SIZE(in_proc_ch_sel_txt),
1088                 in_proc_ch_sel_txt);
1089
1090 /* R_MICBIAS PG 1 ADDR 0x0C */
1091 static char const * const mic_bias_txt[] = {
1092         "2.5V", "2.1V", "1.8V", "Vdd"};
1093
1094 static struct soc_enum const mic_bias_2_enum =
1095         SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
1096                 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1097
1098 static struct soc_enum const mic_bias_1_enum =
1099         SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
1100                 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1101
1102 /* R_PGACTL0 PG 1 ADDR 0x0D */
1103 /* R_PGACTL1 PG 1 ADDR 0x0E */
1104 /* R_PGACTL2 PG 1 ADDR 0x0F */
1105 /* R_PGACTL3 PG 1 ADDR 0x10 */
1106 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1107
1108 /* R_ICH0VOL PG1 ADDR 0x12 */
1109 /* R_ICH1VOL PG1 ADDR 0x13 */
1110 /* R_ICH2VOL PG1 ADDR 0x14 */
1111 /* R_ICH3VOL PG1 ADDR 0x15 */
1112 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1113
1114 /* R_ASRCILVOL PG1 ADDR 0x16 */
1115 /* R_ASRCIRVOL PG1 ADDR 0x17 */
1116 /* R_ASRCOLVOL PG1 ADDR 0x18 */
1117 /* R_ASRCORVOL PG1 ADDR 0x19 */
1118 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1119
1120 /* R_ALCCTL0 PG1 ADDR 0x1D */
1121 static char const * const alc_mode_txt[] = {
1122         "ALC", "Limiter"};
1123
1124 static struct soc_enum const alc_mode_enum =
1125         SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
1126                 ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
1127
1128 static char const * const alc_ref_text[] = {
1129         "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1130
1131 static struct soc_enum const alc_ref_enum =
1132         SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
1133                 ARRAY_SIZE(alc_ref_text), alc_ref_text);
1134
1135 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1136 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1137 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1138
1139 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1140 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1141
1142 /* R_NGATE PG 1 ADDR 0x21 */
1143 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1144
1145 static char const * const ngate_type_txt[] = {
1146         "PGA Constant", "ADC Mute"};
1147
1148 static struct soc_enum const ngate_type_enum =
1149         SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
1150                 ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
1151
1152 /* R_DMICCTL PG 1 ADDR 0x22 */
1153 static char const * const dmic_mono_sel_txt[] = {
1154         "Stereo", "Mono"};
1155
1156 static struct soc_enum const dmic_mono_sel_enum =
1157         SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
1158             ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
1159
1160 /* R_DACCTL PG 2 ADDR 0x01 */
1161 static struct soc_enum const dac_pol_r_enum =
1162         SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
1163             ARRAY_SIZE(pol_txt), pol_txt);
1164
1165 static struct soc_enum const dac_pol_l_enum =
1166         SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
1167             ARRAY_SIZE(pol_txt), pol_txt);
1168
1169 static char const * const dac_dith_txt[] = {
1170         "Half", "Full", "Disabled", "Static"};
1171
1172 static struct soc_enum const dac_dith_enum =
1173         SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
1174             ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
1175
1176 /* R_SPKCTL PG 2 ADDR 0x02 */
1177 static struct soc_enum const spk_pol_r_enum =
1178         SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
1179                 ARRAY_SIZE(pol_txt), pol_txt);
1180
1181 static struct soc_enum const spk_pol_l_enum =
1182         SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
1183                 ARRAY_SIZE(pol_txt), pol_txt);
1184
1185 /* R_SUBCTL PG 2 ADDR 0x03 */
1186 static struct soc_enum const sub_pol_enum =
1187         SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
1188                 ARRAY_SIZE(pol_txt), pol_txt);
1189
1190 /* R_MVOLL PG 2 ADDR 0x08 */
1191 /* R_MVOLR PG 2 ADDR 0x09 */
1192 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1193
1194 /* R_HPVOLL PG 2 ADDR 0x0A */
1195 /* R_HPVOLR PG 2 ADDR 0x0B */
1196 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1197
1198 /* R_SPKVOLL PG 2 ADDR 0x0C */
1199 /* R_SPKVOLR PG 2 ADDR 0x0D */
1200 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1201
1202 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1203 static char const * const eq_txt[] = {
1204     "Pre Scale",
1205     "Pre Scale + EQ Band 0",
1206     "Pre Scale + EQ Band 0 - 1",
1207     "Pre Scale + EQ Band 0 - 2",
1208     "Pre Scale + EQ Band 0 - 3",
1209     "Pre Scale + EQ Band 0 - 4",
1210     "Pre Scale + EQ Band 0 - 5",
1211 };
1212
1213 static struct soc_enum const spk_eq_enums[] = {
1214     SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
1215         ARRAY_SIZE(eq_txt), eq_txt),
1216     SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
1217         ARRAY_SIZE(eq_txt), eq_txt),
1218 };
1219
1220 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1221 static char const * const lvl_mode_txt[] = {
1222         "Average", "Peak"};
1223
1224 static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
1225         SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
1226                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1227
1228 static char const * const win_sel_txt[] = {
1229         "512", "64"};
1230
1231 static struct soc_enum const spk_mbc3_win_sel_enum =
1232         SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
1233                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1234
1235 static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
1236         SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
1237                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1238
1239 static struct soc_enum const spk_mbc2_win_sel_enum =
1240         SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
1241                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1242
1243 static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
1244         SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
1245                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1246
1247 static struct soc_enum const spk_mbc1_win_sel_enum =
1248         SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
1249                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1250
1251 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1252 static struct soc_enum const spk_mbc1_phase_pol_enum =
1253         SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
1254                 ARRAY_SIZE(pol_txt), pol_txt);
1255
1256 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1257
1258 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1259 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1260
1261 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1262 static char const * const comp_rat_txt[] = {
1263         "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1264         "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
1265         "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
1266
1267 static struct soc_enum const spk_mbc1_comp_rat_enum =
1268         SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
1269                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1270
1271 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1272 static struct soc_enum const spk_mbc2_phase_pol_enum =
1273         SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
1274                 ARRAY_SIZE(pol_txt), pol_txt);
1275
1276 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1277 static struct soc_enum const spk_mbc2_comp_rat_enum =
1278         SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
1279                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1280
1281 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1282 static struct soc_enum const spk_mbc3_phase_pol_enum =
1283         SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
1284                 ARRAY_SIZE(pol_txt), pol_txt);
1285
1286 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1287 static struct soc_enum const spk_mbc3_comp_rat_enum =
1288         SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
1289                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1290
1291 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1292 static struct soc_enum const spk_cle_lvl_mode_enum =
1293         SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
1294                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1295
1296 static struct soc_enum const spk_cle_win_sel_enum =
1297         SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
1298                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1299
1300 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1301 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
1302
1303 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1304 static struct soc_enum const spk_comp_rat_enum =
1305         SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
1306                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1307
1308 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1309 static char const * const exp_rat_txt[] = {
1310         "Reserved", "Reserved", "1:2", "1:3",
1311         "1:4", "1:5", "1:6", "1:7"};
1312
1313 static struct soc_enum const spk_exp_rat_enum =
1314         SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
1315                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1316
1317 /* R_DACEQFILT PG 4 ADDR 0x01 */
1318 static struct soc_enum const dac_eq_enums[] = {
1319     SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
1320         ARRAY_SIZE(eq_txt), eq_txt),
1321     SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
1322         ARRAY_SIZE(eq_txt), eq_txt),
1323 };
1324
1325 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1326 static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
1327         SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
1328                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1329
1330 static struct soc_enum const dac_mbc3_win_sel_enum =
1331         SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
1332                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1333
1334 static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
1335         SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
1336                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1337
1338 static struct soc_enum const dac_mbc2_win_sel_enum =
1339         SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
1340                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1341
1342 static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
1343         SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
1344                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1345
1346 static struct soc_enum const dac_mbc1_win_sel_enum =
1347         SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
1348                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1349
1350 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1351 static struct soc_enum const dac_mbc1_phase_pol_enum =
1352         SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
1353                 ARRAY_SIZE(pol_txt), pol_txt);
1354
1355 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1356 static struct soc_enum const dac_mbc1_comp_rat_enum =
1357         SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
1358                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1359
1360 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1361 static struct soc_enum const dac_mbc2_phase_pol_enum =
1362         SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
1363                 ARRAY_SIZE(pol_txt), pol_txt);
1364
1365 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1366 static struct soc_enum const dac_mbc2_comp_rat_enum =
1367         SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
1368                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1369
1370 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1371 static struct soc_enum const dac_mbc3_phase_pol_enum =
1372         SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
1373                 ARRAY_SIZE(pol_txt), pol_txt);
1374
1375 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1376 static struct soc_enum const dac_mbc3_comp_rat_enum =
1377         SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
1378                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1379
1380 /* R_DACCLECTL PG 4 ADDR 0x21 */
1381 static struct soc_enum const dac_cle_lvl_mode_enum =
1382         SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
1383                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1384
1385 static struct soc_enum const dac_cle_win_sel_enum =
1386         SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
1387                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1388
1389 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1390 static struct soc_enum const dac_comp_rat_enum =
1391         SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
1392                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1393
1394 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1395 static struct soc_enum const dac_exp_rat_enum =
1396         SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
1397                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1398
1399 /* R_SUBEQFILT PG 5 ADDR 0x01 */
1400 static struct soc_enum const sub_eq_enums[] = {
1401     SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
1402         ARRAY_SIZE(eq_txt), eq_txt),
1403     SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
1404         ARRAY_SIZE(eq_txt), eq_txt),
1405 };
1406
1407 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
1408 static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
1409         SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
1410                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1411
1412 static struct soc_enum const sub_mbc3_win_sel_enum =
1413         SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
1414                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1415
1416 static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
1417         SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
1418                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1419
1420 static struct soc_enum const sub_mbc2_win_sel_enum =
1421         SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
1422                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1423
1424 static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
1425         SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
1426                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1427
1428 static struct soc_enum const sub_mbc1_win_sel_enum =
1429         SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
1430                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1431
1432 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1433 static struct soc_enum const sub_mbc1_phase_pol_enum =
1434         SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
1435                 ARRAY_SIZE(pol_txt), pol_txt);
1436
1437 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1438 static struct soc_enum const sub_mbc1_comp_rat_enum =
1439         SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
1440                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1441
1442 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1443 static struct soc_enum const sub_mbc2_phase_pol_enum =
1444         SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
1445                 ARRAY_SIZE(pol_txt), pol_txt);
1446
1447 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1448 static struct soc_enum const sub_mbc2_comp_rat_enum =
1449         SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
1450                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1451
1452 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1453 static struct soc_enum const sub_mbc3_phase_pol_enum =
1454         SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
1455                 ARRAY_SIZE(pol_txt), pol_txt);
1456
1457 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1458 static struct soc_enum const sub_mbc3_comp_rat_enum =
1459         SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
1460                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1461
1462 /* R_SUBCLECTL PG 5 ADDR 0x21 */
1463 static struct soc_enum const sub_cle_lvl_mode_enum =
1464         SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
1465                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1466 static struct soc_enum const sub_cle_win_sel_enum =
1467         SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
1468                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1469
1470 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1471 static struct soc_enum const sub_comp_rat_enum =
1472         SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
1473                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1474
1475 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
1476 static struct soc_enum const sub_exp_rat_enum =
1477         SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
1478                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1479
1480 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
1481     struct snd_ctl_elem_info *ucontrol)
1482 {
1483     struct coeff_ram_ctl *ctl =
1484         (struct coeff_ram_ctl *)kcontrol->private_value;
1485     struct soc_bytes_ext *params = &ctl->bytes_ext;
1486
1487     ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1488     ucontrol->count = params->max;
1489
1490     return 0;
1491 }
1492
1493 /* CH 0_1 Input Mux */
1494 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
1495
1496 static struct soc_enum const ch_0_1_mux_enum =
1497         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1498                 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
1499
1500 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
1501         SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
1502
1503 /* CH 2_3 Input Mux */
1504 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
1505
1506 static struct soc_enum const ch_2_3_mux_enum =
1507         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1508                 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
1509
1510 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
1511         SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
1512
1513 /* CH 4_5 Input Mux */
1514 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
1515
1516 static struct soc_enum const ch_4_5_mux_enum =
1517         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1518                 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
1519
1520 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
1521         SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
1522
1523 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
1524 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1525     .info = bytes_info_ext, \
1526     .get = coeff_ram_get, .put = coeff_ram_put, \
1527     .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
1528         .addr = xaddr, \
1529         .bytes_ext = {.max = xcount, }, \
1530     } \
1531 }
1532
1533 static struct snd_kcontrol_new const tscs454_snd_controls[] = {
1534     /* R_PLLCTL PG 0 ADDR 0x15 */
1535     SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
1536     /* R_ISRC PG 0 ADDR 0x16 */
1537     SOC_ENUM("Internal Rate", isrc_br_enum),
1538     SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
1539     /* R_SCLKCTL PG 0 ADDR 0x18 */
1540     SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
1541     SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1542     /* R_ASRC PG 0 ADDR 0x28 */
1543     SOC_SINGLE("ASRC Out High Bandwidth Switch",
1544             R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
1545     SOC_SINGLE("ASRC In High Bandwidth Switch",
1546             R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
1547     /* R_I2SIDCTL PG 0 ADDR 0x38 */
1548     SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
1549     SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
1550     SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
1551     /* R_I2SODCTL PG 0 ADDR 0x39 */
1552     SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
1553     SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
1554     SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
1555     /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
1556     SOC_ENUM("ASRC In", asrc_in_mux_enum),
1557     /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
1558     SOC_ENUM("ASRC Out", asrc_out_mux_enum),
1559     /* R_HSDCTL1 PG 1 ADDR 0x01 */
1560     SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
1561     SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
1562     SOC_SINGLE("Headphone Detection Switch",
1563             R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
1564     SOC_SINGLE("Headset OMTP/CTIA Switch",
1565             R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
1566     /* R_HSDCTL1 PG 1 ADDR 0x02 */
1567     SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
1568     SOC_SINGLE("Manual Mic Bias Switch",
1569             R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
1570     SOC_SINGLE("Ring/Sleeve Auto Switch",
1571             R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
1572     SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1573     /* R_CH0AIC PG 1 ADDR 0x06 */
1574     SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1575             FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1576     /* R_CH1AIC PG 1 ADDR 0x07 */
1577     SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1578             FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1579     /* R_CH2AIC PG 1 ADDR 0x08 */
1580     SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1581             FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1582     /* R_CH3AIC PG 1 ADDR 0x09 */
1583     SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1584             FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1585     /* R_ICTL0 PG 1 ADDR 0x0A */
1586     SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1587     SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1588     SOC_ENUM("Input Processor Channel 0/1 Operation",
1589             in_proc_ch01_sel_enum),
1590     SOC_SINGLE("Input Channel 1 Mute Switch",
1591             R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
1592     SOC_SINGLE("Input Channel 0 Mute Switch",
1593             R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
1594     SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1595             R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
1596     SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1597             R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
1598     /* R_ICTL1 PG 1 ADDR 0x0B */
1599     SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1600     SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1601     SOC_ENUM("Input Processor Channel 2/3 Operation",
1602             in_proc_ch23_sel_enum),
1603     SOC_SINGLE("Input Channel 3 Mute Switch",
1604             R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
1605     SOC_SINGLE("Input Channel 2 Mute Switch",
1606             R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
1607     SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1608             R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
1609     SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1610             R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
1611     /* R_MICBIAS PG 1 ADDR 0x0C */
1612     SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
1613     SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
1614     /* R_PGACTL0 PG 1 ADDR 0x0D */
1615     SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1616             R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
1617     SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1618             FB_PGACTL_PGAVOL,
1619             FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1620     /* R_PGACTL1 PG 1 ADDR 0x0E */
1621     SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1622             R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
1623     SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1624             FB_PGACTL_PGAVOL,
1625             FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1626     /* R_PGACTL2 PG 1 ADDR 0x0F */
1627     SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1628             R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
1629     SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1630             FB_PGACTL_PGAVOL,
1631             FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1632     /* R_PGACTL3 PG 1 ADDR 0x10 */
1633     SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1634             R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
1635     SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1636             FB_PGACTL_PGAVOL,
1637             FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1638     /* R_ICH0VOL PG 1 ADDR 0x12 */
1639     SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1640             FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1641     /* R_ICH1VOL PG 1 ADDR 0x13 */
1642     SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1643             FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1644     /* R_ICH2VOL PG 1 ADDR 0x14 */
1645     SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1646             FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1647     /* R_ICH3VOL PG 1 ADDR 0x15 */
1648     SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1649             FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1650     /* R_ASRCILVOL PG 1 ADDR 0x16 */
1651     SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
1652             FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
1653             0, asrc_vol_tlv_arr),
1654     /* R_ASRCIRVOL PG 1 ADDR 0x17 */
1655     SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
1656             FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
1657             0, asrc_vol_tlv_arr),
1658     /* R_ASRCOLVOL PG 1 ADDR 0x18 */
1659     SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
1660             FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
1661             0, asrc_vol_tlv_arr),
1662     /* R_ASRCORVOL PG 1 ADDR 0x19 */
1663     SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
1664             FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
1665             0, asrc_vol_tlv_arr),
1666     /* R_IVOLCTLU PG 1 ADDR 0x1C */
1667     /* R_ALCCTL0 PG 1 ADDR 0x1D */
1668     SOC_ENUM("ALC Mode", alc_mode_enum),
1669     SOC_ENUM("ALC Reference", alc_ref_enum),
1670     SOC_SINGLE("Input Channel 3 ALC Switch",
1671             R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
1672     SOC_SINGLE("Input Channel 2 ALC Switch",
1673             R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
1674     SOC_SINGLE("Input Channel 1 ALC Switch",
1675             R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
1676     SOC_SINGLE("Input Channel 0 ALC Switch",
1677             R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
1678     /* R_ALCCTL1 PG 1 ADDR 0x1E */
1679     SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
1680             FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
1681             0, alc_max_gain_tlv_arr),
1682     SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
1683             FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
1684             0, alc_target_tlv_arr),
1685     /* R_ALCCTL2 PG 1 ADDR 0x1F */
1686     SOC_SINGLE("ALC Zero Cross Switch",
1687             R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
1688     SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
1689             FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
1690             0, alc_min_gain_tlv_arr),
1691     SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
1692             FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
1693     /* R_ALCCTL3 PG 1 ADDR 0x20 */
1694     SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
1695             FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
1696     SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
1697             FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
1698     /* R_NGATE PG 1 ADDR 0x21 */
1699     SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
1700             FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
1701     SOC_ENUM("Noise Gate Type", ngate_type_enum),
1702     SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
1703     /* R_DMICCTL PG 1 ADDR 0x22 */
1704     SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
1705     SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
1706     SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
1707     /* R_DACCTL PG 2 ADDR 0x01 */
1708     SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1709     SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1710     SOC_ENUM("DAC Dither", dac_dith_enum),
1711     SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1712     SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1713     /* R_SPKCTL PG 2 ADDR 0x02 */
1714     SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
1715     SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
1716     SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
1717     SOC_SINGLE("Speaker De-Emphasis Switch",
1718             R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
1719     /* R_SUBCTL PG 2 ADDR 0x03 */
1720     SOC_ENUM("Sub Polarity", sub_pol_enum),
1721     SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1722     SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1723     /* R_DCCTL PG 2 ADDR 0x04 */
1724     SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1725     SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1726     SOC_SINGLE("Speaker DC Removal Switch",
1727             R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
1728     SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
1729             FM_DCCTL_DCCOEFSEL, 0),
1730     /* R_OVOLCTLU PG 2 ADDR 0x06 */
1731     SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
1732     /* R_MVOLL PG 2 ADDR 0x08 */
1733     /* R_MVOLR PG 2 ADDR 0x09 */
1734     SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
1735             FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
1736     /* R_HPVOLL PG 2 ADDR 0x0A */
1737     /* R_HPVOLR PG 2 ADDR 0x0B */
1738     SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
1739             FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
1740             hp_vol_tlv_arr),
1741     /* R_SPKVOLL PG 2 ADDR 0x0C */
1742     /* R_SPKVOLR PG 2 ADDR 0x0D */
1743     SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
1744             FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
1745             spk_vol_tlv_arr),
1746     /* R_SUBVOL PG 2 ADDR 0x10 */
1747     SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1748             FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
1749     /* R_SPKEQFILT PG 3 ADDR 0x01 */
1750     SOC_SINGLE("Speaker EQ 2 Switch",
1751             R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
1752     SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
1753     SOC_SINGLE("Speaker EQ 1 Switch",
1754             R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
1755     SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
1756     /* R_SPKMBCEN PG 3 ADDR 0x0A */
1757     SOC_SINGLE("Speaker MBC 3 Switch",
1758             R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
1759     SOC_SINGLE("Speaker MBC 2 Switch",
1760             R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
1761     SOC_SINGLE("Speaker MBC 1 Switch",
1762             R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
1763     /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1764     SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1765     SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
1766     SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1767     SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
1768     SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1769     SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
1770     /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1771     SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
1772     SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1773             FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1774             0, mbc_mug_tlv_arr),
1775     /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1776     SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
1777             R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1778             0, thr_tlv_arr),
1779     /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1780     SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
1781     /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
1782     /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
1783     SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
1784     /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
1785     /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
1786     SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
1787     /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1788     SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
1789     SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1790             FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1791             0, mbc_mug_tlv_arr),
1792     /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
1793     SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
1794             R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1795             0, thr_tlv_arr),
1796     /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1797     SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
1798     /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
1799     /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
1800     SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
1801     /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
1802     /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
1803     SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
1804     /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1805     SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
1806     SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1807             FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1808             0, mbc_mug_tlv_arr),
1809     /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
1810     SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
1811             FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1812             0, thr_tlv_arr),
1813     /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1814     SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
1815     /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
1816     /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
1817     SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
1818     /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
1819     /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
1820     SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
1821     /* R_SPKCLECTL PG 3 ADDR 0x21 */
1822     SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1823     SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
1824     SOC_SINGLE("Speaker CLE Expander Switch",
1825             R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
1826     SOC_SINGLE("Speaker CLE Limiter Switch",
1827             R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
1828     SOC_SINGLE("Speaker CLE Compressor Switch",
1829             R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
1830     /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1831     SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1832             FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
1833             0, cle_mug_tlv_arr),
1834     /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
1835     SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
1836             FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
1837             0, thr_tlv_arr),
1838     /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1839     SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
1840     /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
1841     /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
1842     SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
1843     /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
1844     /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
1845     SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
1846     /* R_SPKLIMTHR PG 3 ADDR 0x29 */
1847     SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
1848             FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
1849             0, thr_tlv_arr),
1850     /* R_SPKLIMTGT PG 3 ADDR 0x2A */
1851     SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
1852             FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
1853             0, thr_tlv_arr),
1854     /* R_SPKLIMATKL PG 3 ADDR 0x2B */
1855     /* R_SPKLIMATKH PG 3 ADDR 0x2C */
1856     SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
1857     /* R_SPKLIMRELL PG 3 ADDR 0x2D */
1858     /* R_SPKLIMRELR PG 3 ADDR 0x2E */
1859     SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
1860     /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1861     SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
1862             FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
1863             0, thr_tlv_arr),
1864     /* R_SPKEXPRAT PG 3 ADDR 0x30 */
1865     SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
1866     /* R_SPKEXPATKL PG 3 ADDR 0x31 */
1867     /* R_SPKEXPATKR PG 3 ADDR 0x32 */
1868     SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
1869     /* R_SPKEXPRELL PG 3 ADDR 0x33 */
1870     /* R_SPKEXPRELR PG 3 ADDR 0x34 */
1871     SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
1872     /* R_SPKFXCTL PG 3 ADDR 0x35 */
1873     SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
1874     SOC_SINGLE("Speaker Treble Enhancement Switch",
1875             R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
1876     SOC_SINGLE("Speaker Treble NLF Switch",
1877             R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
1878     SOC_SINGLE("Speaker Bass Enhancement Switch",
1879             R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
1880     SOC_SINGLE("Speaker Bass NLF Switch",
1881             R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
1882     /* R_DACEQFILT PG 4 ADDR 0x01 */
1883     SOC_SINGLE("DAC EQ 2 Switch",
1884             R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
1885     SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1886     SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1887     SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1888     /* R_DACMBCEN PG 4 ADDR 0x0A */
1889     SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1890     SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1891     SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1892     /* R_DACMBCCTL PG 4 ADDR 0x0B */
1893     SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1894     SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1895     SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1896     SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1897     SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1898     SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1899     /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1900     SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1901     SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1902             FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1903             0, mbc_mug_tlv_arr),
1904     /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
1905     SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1906             FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1907             0, thr_tlv_arr),
1908     /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1909     SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1910     /* R_DACMBCATK1L PG 4 ADDR 0x0F */
1911     /* R_DACMBCATK1H PG 4 ADDR 0x10 */
1912     SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1913     /* R_DACMBCREL1L PG 4 ADDR 0x11 */
1914     /* R_DACMBCREL1H PG 4 ADDR 0x12 */
1915     SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1916     /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1917     SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1918     SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1919             FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1920             0, mbc_mug_tlv_arr),
1921     /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
1922     SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1923             FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1924             0, thr_tlv_arr),
1925     /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1926     SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1927     /* R_DACMBCATK2L PG 4 ADDR 0x16 */
1928     /* R_DACMBCATK2H PG 4 ADDR 0x17 */
1929     SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1930     /* R_DACMBCREL2L PG 4 ADDR 0x18 */
1931     /* R_DACMBCREL2H PG 4 ADDR 0x19 */
1932     SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1933     /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1934     SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1935     SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1936             FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1937             0, mbc_mug_tlv_arr),
1938     /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
1939     SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1940             FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1941             0, thr_tlv_arr),
1942     /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1943     SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1944     /* R_DACMBCATK3L PG 4 ADDR 0x1D */
1945     /* R_DACMBCATK3H PG 4 ADDR 0x1E */
1946     SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1947     /* R_DACMBCREL3L PG 4 ADDR 0x1F */
1948     /* R_DACMBCREL3H PG 4 ADDR 0x20 */
1949     SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1950     /* R_DACCLECTL PG 4 ADDR 0x21 */
1951     SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1952     SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1953     SOC_SINGLE("DAC CLE Expander Switch",
1954             R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
1955     SOC_SINGLE("DAC CLE Limiter Switch",
1956             R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
1957     SOC_SINGLE("DAC CLE Compressor Switch",
1958             R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
1959     /* R_DACCLEMUG PG 4 ADDR 0x22 */
1960     SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1961             FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
1962             0, cle_mug_tlv_arr),
1963     /* R_DACCOMPTHR PG 4 ADDR 0x23 */
1964     SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1965             FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
1966             0, thr_tlv_arr),
1967     /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1968     SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1969     /* R_DACCOMPATKL PG 4 ADDR 0x25 */
1970     /* R_DACCOMPATKH PG 4 ADDR 0x26 */
1971     SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1972     /* R_DACCOMPRELL PG 4 ADDR 0x27 */
1973     /* R_DACCOMPRELH PG 4 ADDR 0x28 */
1974     SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1975     /* R_DACLIMTHR PG 4 ADDR 0x29 */
1976     SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1977             FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
1978             0, thr_tlv_arr),
1979     /* R_DACLIMTGT PG 4 ADDR 0x2A */
1980     SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1981             FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
1982             0, thr_tlv_arr),
1983     /* R_DACLIMATKL PG 4 ADDR 0x2B */
1984     /* R_DACLIMATKH PG 4 ADDR 0x2C */
1985     SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1986     /* R_DACLIMRELL PG 4 ADDR 0x2D */
1987     /* R_DACLIMRELR PG 4 ADDR 0x2E */
1988     SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1989     /* R_DACEXPTHR PG 4 ADDR 0x2F */
1990     SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1991             FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
1992             0, thr_tlv_arr),
1993     /* R_DACEXPRAT PG 4 ADDR 0x30 */
1994     SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
1995     /* R_DACEXPATKL PG 4 ADDR 0x31 */
1996     /* R_DACEXPATKR PG 4 ADDR 0x32 */
1997     SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
1998     /* R_DACEXPRELL PG 4 ADDR 0x33 */
1999     /* R_DACEXPRELR PG 4 ADDR 0x34 */
2000     SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
2001     /* R_DACFXCTL PG 4 ADDR 0x35 */
2002     SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
2003     SOC_SINGLE("DAC Treble Enhancement Switch",
2004             R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
2005     SOC_SINGLE("DAC Treble NLF Switch",
2006             R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
2007     SOC_SINGLE("DAC Bass Enhancement Switch",
2008             R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
2009     SOC_SINGLE("DAC Bass NLF Switch",
2010             R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
2011     /* R_SUBEQFILT PG 5 ADDR 0x01 */
2012     SOC_SINGLE("Sub EQ 2 Switch",
2013             R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
2014     SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2015     SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2016     SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2017     /* R_SUBMBCEN PG 5 ADDR 0x0A */
2018     SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2019     SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2020     SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2021     /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2022     SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2023     SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2024     SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2025     SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2026     SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2027     SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2028     /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2029     SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2030     SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2031             FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2032             0, mbc_mug_tlv_arr),
2033     /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2034     SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2035             FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2036             0, thr_tlv_arr),
2037     /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2038     SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2039     /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2040     /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2041     SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2042     /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2043     /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2044     SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2045     /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2046     SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2047     SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2048             FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2049             0, mbc_mug_tlv_arr),
2050     /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2051     SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2052             FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2053             0, thr_tlv_arr),
2054     /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2055     SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2056     /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2057     /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2058     SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2059     /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2060     /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2061     SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2062     /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2063     SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2064     SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2065             FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2066             0, mbc_mug_tlv_arr),
2067     /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2068     SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2069             FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2070             0, thr_tlv_arr),
2071     /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2072     SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2073     /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2074     /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2075     SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2076     /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2077     /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2078     SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2079     /* R_SUBCLECTL PG 5 ADDR 0x21 */
2080     SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2081     SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2082     SOC_SINGLE("Sub CLE Expander Switch",
2083             R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
2084     SOC_SINGLE("Sub CLE Limiter Switch",
2085             R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
2086     SOC_SINGLE("Sub CLE Compressor Switch",
2087             R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
2088     /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2089     SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2090             FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
2091             0, cle_mug_tlv_arr),
2092     /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2093     SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2094             FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
2095             0, thr_tlv_arr),
2096     /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2097     SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2098     /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2099     /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2100     SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2101     /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2102     /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2103     SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2104     /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2105     SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2106             FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
2107             0, thr_tlv_arr),
2108     /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2109     SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2110             FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
2111             0, thr_tlv_arr),
2112     /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2113     /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2114     SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2115     /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2116     /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2117     SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2118     /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2119     SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2120             FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
2121             0, thr_tlv_arr),
2122     /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2123     SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2124     /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2125     /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2126     SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2127     /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2128     /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2129     SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2130     /* R_SUBFXCTL PG 5 ADDR 0x35 */
2131     SOC_SINGLE("Sub Treble Enhancement Switch",
2132             R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
2133     SOC_SINGLE("Sub Treble NLF Switch",
2134             R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
2135     SOC_SINGLE("Sub Bass Enhancement Switch",
2136             R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
2137     SOC_SINGLE("Sub Bass NLF Switch",
2138             R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
2139     COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2140     COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2141     COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2142     COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2143     COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2144     COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2145
2146     COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2147     COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2148     COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2149     COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2150     COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2151     COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2152
2153     COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2154     COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2155
2156     COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2157     COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2158     COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2159     COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2160     COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2161     COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2162
2163     COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2164     COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2165     COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2166     COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2167     COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2168     COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2169
2170     COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2171     COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2172
2173     COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2174     COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2175
2176     COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2177     COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2178
2179     COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2180
2181     COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2182
2183     COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2184
2185     COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2186     COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2187
2188     COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2189     COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2190
2191     COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2192
2193     COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2194
2195     COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2196
2197     COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2198
2199     COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2200
2201     COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2202     COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2203
2204     COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2205     COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2206
2207     COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2208     COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2209
2210     COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2211     COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2212     COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2213     COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2214     COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2215     COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2216
2217     COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2218     COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2219     COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2220     COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2221     COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2222     COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2223
2224     COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2225     COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2226
2227     COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2228     COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2229     COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2230     COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2231     COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2232     COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2233
2234     COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2235     COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2236     COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2237     COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2238     COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2239     COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2240
2241     COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2242     COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2243
2244     COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2245     COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2246
2247     COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2248     COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2249
2250     COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2251
2252     COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2253
2254     COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
2255
2256     COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2257     COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2258
2259     COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2260     COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2261
2262     COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2263
2264     COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2265
2266     COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
2267
2268     COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
2269
2270     COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
2271
2272     COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2273     COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2274
2275     COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2276     COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2277
2278     COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2279     COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2280
2281     COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2282     COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2283     COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2284     COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2285     COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2286     COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2287
2288     COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2289     COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2290     COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2291     COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2292     COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2293     COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2294
2295     COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2296     COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2297
2298     COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2299     COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2300     COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2301     COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2302     COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2303     COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2304
2305     COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2306     COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2307     COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2308     COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2309     COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2310     COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2311
2312     COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2313     COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2314
2315     COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2316     COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2317
2318     COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2319     COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2320
2321     COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2322
2323     COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2324
2325     COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2326
2327     COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2328     COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2329
2330     COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2331     COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2332
2333     COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2334
2335     COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2336
2337     COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2338
2339     COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2340
2341     COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2342
2343     COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2344     COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2345
2346     COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2347     COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2348
2349     COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2350     COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2351 };
2352
2353 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
2354     /* R_PLLCTL PG 0 ADDR 0x15 */
2355     SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
2356             pll_power_event,
2357             SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2358     SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
2359             pll_power_event,
2360             SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2361     /* R_I2SPINC0 PG 0 ADDR 0x22 */
2362     SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
2363             R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
2364     SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
2365             R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
2366     SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
2367             R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
2368     /* R_PWRM0 PG 0 ADDR 0x33 */
2369     SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2370             R_PWRM0, FB_PWRM0_INPROC3PU, 0),
2371     SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2372             R_PWRM0, FB_PWRM0_INPROC2PU, 0),
2373     SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2374             R_PWRM0, FB_PWRM0_INPROC1PU, 0),
2375     SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2376             R_PWRM0, FB_PWRM0_INPROC0PU, 0),
2377     SND_SOC_DAPM_SUPPLY("Mic Bias 2",
2378             R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
2379     SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
2380             FB_PWRM0_MICB1PU, 0, NULL, 0),
2381     /* R_PWRM1 PG 0 ADDR 0x34 */
2382     SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2383     SND_SOC_DAPM_SUPPLY("Headphone Left Power",
2384             R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
2385     SND_SOC_DAPM_SUPPLY("Headphone Right Power",
2386             R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
2387     SND_SOC_DAPM_SUPPLY("Speaker Left Power",
2388             R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
2389     SND_SOC_DAPM_SUPPLY("Speaker Right Power",
2390             R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
2391     SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
2392             R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
2393     SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
2394             R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
2395     /* R_PWRM2 PG 0 ADDR 0x35 */
2396     SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
2397             R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
2398     SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
2399             R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
2400     SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
2401             R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
2402     SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
2403             R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
2404     SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
2405             R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
2406     SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
2407             R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
2408     /* R_PWRM3 PG 0 ADDR 0x36 */
2409     SND_SOC_DAPM_SUPPLY("Line Out Left Power",
2410             R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
2411     SND_SOC_DAPM_SUPPLY("Line Out Right Power",
2412             R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
2413     /* R_PWRM4 PG 0 ADDR 0x37 */
2414     SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2415     SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2416     SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2417     SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
2418     SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
2419     /* R_AUDIOMUX1  PG 0 ADDR 0x3A */
2420     SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
2421             &dai2_mux_dapm_enum),
2422     SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
2423             &dai1_mux_dapm_enum),
2424     /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
2425     SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2426             &dac_mux_dapm_enum),
2427     SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
2428             &dai3_mux_dapm_enum),
2429     /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
2430     SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2431             &sub_mux_dapm_enum),
2432     SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
2433             &classd_mux_dapm_enum),
2434     /* R_HSDCTL1 PG 1 ADDR 0x01 */
2435     SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
2436             FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
2437     /* R_CH0AIC PG 1 ADDR 0x06 */
2438     SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2439             &in_bst_mux_ch0_dapm_enum),
2440     SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2441             &adc_mux_ch0_dapm_enum),
2442     SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2443             &in_proc_mux_ch0_dapm_enum),
2444     /* R_CH1AIC PG 1 ADDR 0x07 */
2445     SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2446             &in_bst_mux_ch1_dapm_enum),
2447     SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2448             &adc_mux_ch1_dapm_enum),
2449     SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2450             &in_proc_mux_ch1_dapm_enum),
2451     /* Virtual */
2452     SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
2453             SND_SOC_NOPM, 0, 0),
2454     SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
2455             SND_SOC_NOPM, 0, 0),
2456     SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
2457             SND_SOC_NOPM, 0, 0),
2458     SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
2459     SND_SOC_DAPM_OUTPUT("Sub Out"),
2460     SND_SOC_DAPM_OUTPUT("Headphone Left"),
2461     SND_SOC_DAPM_OUTPUT("Headphone Right"),
2462     SND_SOC_DAPM_OUTPUT("Speaker Left"),
2463     SND_SOC_DAPM_OUTPUT("Speaker Right"),
2464     SND_SOC_DAPM_OUTPUT("Line Out Left"),
2465     SND_SOC_DAPM_OUTPUT("Line Out Right"),
2466     SND_SOC_DAPM_INPUT("D2S 2"),
2467     SND_SOC_DAPM_INPUT("D2S 1"),
2468     SND_SOC_DAPM_INPUT("Line In 1 Left"),
2469     SND_SOC_DAPM_INPUT("Line In 1 Right"),
2470     SND_SOC_DAPM_INPUT("Line In 2 Left"),
2471     SND_SOC_DAPM_INPUT("Line In 2 Right"),
2472     SND_SOC_DAPM_INPUT("Line In 3 Left"),
2473     SND_SOC_DAPM_INPUT("Line In 3 Right"),
2474     SND_SOC_DAPM_INPUT("DMic 1"),
2475     SND_SOC_DAPM_INPUT("DMic 2"),
2476
2477     SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
2478             &ch_0_1_mux_dapm_enum),
2479     SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
2480             &ch_2_3_mux_dapm_enum),
2481     SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
2482             &ch_4_5_mux_dapm_enum),
2483 };
2484
2485 static struct snd_soc_dapm_route const tscs454_intercon[] = {
2486     /* PLLs */
2487     {"PLLs", NULL, "PLL 1 Power", pll_connected},
2488     {"PLLs", NULL, "PLL 2 Power", pll_connected},
2489     /* Inputs */
2490     {"DAI 3 In", NULL, "DAI 3 In Power"},
2491     {"DAI 2 In", NULL, "DAI 2 In Power"},
2492     {"DAI 1 In", NULL, "DAI 1 In Power"},
2493     /* Outputs */
2494     {"DAI 3 Out", NULL, "DAI 3 Out Power"},
2495     {"DAI 2 Out", NULL, "DAI 2 Out Power"},
2496     {"DAI 1 Out", NULL, "DAI 1 Out Power"},
2497     /* Ch Muxing */
2498     {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
2499     {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
2500     {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
2501     {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
2502     {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
2503     {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
2504     /* In/Out Muxing */
2505     {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2506     {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2507     {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2508     {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2509     {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2510     {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2511     {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2512     {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2513     {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2514     /******************
2515      * Playback Paths *
2516      ******************/
2517     /* DAC Path */
2518     {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2519     {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2520     {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2521     {"DAC Left", NULL, "DAC Mux"},
2522     {"DAC Right", NULL, "DAC Mux"},
2523     {"DAC Left", NULL, "PLLs"},
2524     {"DAC Right", NULL, "PLLs"},
2525     {"Headphone Left", NULL, "Headphone Left Power"},
2526     {"Headphone Right", NULL, "Headphone Right Power"},
2527     {"Headphone Left", NULL, "DAC Left"},
2528     {"Headphone Right", NULL, "DAC Right"},
2529     /* Line Out */
2530     {"Line Out Left", NULL, "Line Out Left Power"},
2531     {"Line Out Right", NULL, "Line Out Right Power"},
2532     {"Line Out Left", NULL, "DAC Left"},
2533     {"Line Out Right", NULL, "DAC Right"},
2534     /* ClassD Path */
2535     {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
2536     {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
2537     {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
2538     {"ClassD Left", NULL, "Speaker Mux"},
2539     {"ClassD Right", NULL, "Speaker Mux"},
2540     {"ClassD Left", NULL, "PLLs"},
2541     {"ClassD Right", NULL, "PLLs"},
2542     {"Speaker Left", NULL, "Speaker Left Power"},
2543     {"Speaker Right", NULL, "Speaker Right Power"},
2544     {"Speaker Left", NULL, "ClassD Left"},
2545     {"Speaker Right", NULL, "ClassD Right"},
2546     /* Sub Path */
2547     {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2548     {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2549     {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2550     {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2551     {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2552     {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2553     {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2554     {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2555     {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2556     {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2557     {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2558     {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2559     {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2560     {"Sub Mux", "DMic 2 Left", "DMic 2"},
2561     {"Sub Mux", "DMic 2 Right", "DMic 2"},
2562     {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2563     {"Sub Mux", "ClassD Left", "ClassD Left"},
2564     {"Sub Mux", "ClassD Right", "ClassD Right"},
2565     {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2566     {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2567     {"Sub", NULL, "Sub Mux"},
2568     {"Sub", NULL, "PLLs"},
2569     {"Sub Out", NULL, "Sub Power"},
2570     {"Sub Out", NULL, "Sub"},
2571     /*****************
2572      * Capture Paths *
2573      *****************/
2574     {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2575     {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2576     {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2577     {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2578
2579     {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2580     {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2581     {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2582     {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2583
2584     {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2585     {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2586     {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2587     {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2588
2589     {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2590     {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2591     {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2592     {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2593
2594     {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2595     {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2596
2597     {"Input Processor Channel 0", NULL, "PLLs"},
2598     {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2599
2600     {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2601     {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2602
2603     {"Input Processor Channel 1", NULL, "PLLs"},
2604     {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2605
2606     {"Input Processor Channel 2", NULL, "PLLs"},
2607     {"Input Processor Channel 2", NULL, "DMic 2"},
2608
2609     {"Input Processor Channel 3", NULL, "PLLs"},
2610     {"Input Processor Channel 3", NULL, "DMic 2"},
2611
2612     {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2613     {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2614     {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2615     {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2616
2617     {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2618     {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2619     {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2620     {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2621
2622     {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2623     {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2624     {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2625     {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2626
2627     {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
2628     {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
2629     {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
2630 };
2631
2632 /* This is used when BCLK is sourcing the PLLs */
2633 static int tscs454_set_sysclk(struct snd_soc_dai *dai,
2634         int clk_id, unsigned int freq, int dir)
2635 {
2636     struct snd_soc_component *component = dai->component;
2637     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2638     unsigned int val;
2639     int bclk_dai;
2640
2641     dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2642
2643     val = snd_soc_component_read(component, R_PLLCTL);
2644
2645     bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2646     if (bclk_dai != dai->id)
2647         return 0;
2648
2649     tscs454->bclk_freq = freq;
2650     return set_sysclk(component);
2651 }
2652
2653 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
2654         unsigned int ratio)
2655 {
2656     unsigned int mask;
2657     int ret;
2658     struct snd_soc_component *component = dai->component;
2659     unsigned int val;
2660     int shift;
2661
2662     dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
2663             dai->id, ratio);
2664
2665     switch (dai->id) {
2666     case TSCS454_DAI1_ID:
2667         mask = FM_I2SCMC_BCMP1;
2668         shift = FB_I2SCMC_BCMP1;
2669         break;
2670     case TSCS454_DAI2_ID:
2671         mask = FM_I2SCMC_BCMP2;
2672         shift = FB_I2SCMC_BCMP2;
2673         break;
2674     case TSCS454_DAI3_ID:
2675         mask = FM_I2SCMC_BCMP3;
2676         shift = FB_I2SCMC_BCMP3;
2677         break;
2678     default:
2679         ret = -EINVAL;
2680         dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
2681         return ret;
2682     }
2683
2684     switch (ratio) {
2685     case 32:
2686         val = I2SCMC_BCMP_32X;
2687         break;
2688     case 40:
2689         val = I2SCMC_BCMP_40X;
2690         break;
2691     case 64:
2692         val = I2SCMC_BCMP_64X;
2693         break;
2694     default:
2695         ret = -EINVAL;
2696         dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
2697         return ret;
2698     }
2699
2700     ret = snd_soc_component_update_bits(component,
2701             R_I2SCMC, mask, val << shift);
2702     if (ret < 0) {
2703         dev_err(component->dev,
2704                 "Failed to set DAI BCLK ratio (%d)\n", ret);
2705         return ret;
2706     }
2707
2708     return 0;
2709 }
2710
2711 static inline int set_aif_provider_from_fmt(struct snd_soc_component *component,
2712         struct aif *aif, unsigned int fmt)
2713 {
2714     int ret;
2715
2716     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
2717     case SND_SOC_DAIFMT_CBP_CFP:
2718         aif->provider = true;
2719         break;
2720     case SND_SOC_DAIFMT_CBC_CFC:
2721         aif->provider = false;
2722         break;
2723     default:
2724         ret = -EINVAL;
2725         dev_err(component->dev, "Unsupported format (%d)\n", ret);
2726         return ret;
2727     }
2728
2729     return 0;
2730 }
2731
2732 static inline int set_aif_tdm_delay(struct snd_soc_component *component,
2733         unsigned int dai_id, bool delay)
2734 {
2735     unsigned int reg;
2736     int ret;
2737
2738     switch (dai_id) {
2739     case TSCS454_DAI1_ID:
2740         reg = R_TDMCTL0;
2741         break;
2742     case TSCS454_DAI2_ID:
2743         reg = R_PCMP2CTL0;
2744         break;
2745     case TSCS454_DAI3_ID:
2746         reg = R_PCMP3CTL0;
2747         break;
2748     default:
2749         ret = -EINVAL;
2750         dev_err(component->dev,
2751                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2752         return ret;
2753     }
2754     ret = snd_soc_component_update_bits(component,
2755             reg, FM_TDMCTL0_BDELAY, delay);
2756     if (ret < 0) {
2757         dev_err(component->dev, "Failed to setup tdm format (%d)\n",
2758                 ret);
2759         return ret;
2760     }
2761
2762     return 0;
2763 }
2764
2765 static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
2766         unsigned int dai_id, unsigned int fmt)
2767 {
2768     unsigned int reg;
2769     unsigned int val;
2770     int ret;
2771
2772     switch (dai_id) {
2773     case TSCS454_DAI1_ID:
2774         reg = R_I2SP1CTL;
2775         break;
2776     case TSCS454_DAI2_ID:
2777         reg = R_I2SP2CTL;
2778         break;
2779     case TSCS454_DAI3_ID:
2780         reg = R_I2SP3CTL;
2781         break;
2782     default:
2783         ret = -EINVAL;
2784         dev_err(component->dev,
2785                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2786         return ret;
2787     }
2788
2789     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2790     case SND_SOC_DAIFMT_RIGHT_J:
2791         val = FV_FORMAT_RIGHT;
2792         break;
2793     case SND_SOC_DAIFMT_LEFT_J:
2794         val = FV_FORMAT_LEFT;
2795         break;
2796     case SND_SOC_DAIFMT_I2S:
2797         val = FV_FORMAT_I2S;
2798         break;
2799     case SND_SOC_DAIFMT_DSP_A:
2800         ret = set_aif_tdm_delay(component, dai_id, true);
2801         if (ret < 0)
2802             return ret;
2803         val = FV_FORMAT_TDM;
2804         break;
2805     case SND_SOC_DAIFMT_DSP_B:
2806         ret = set_aif_tdm_delay(component, dai_id, false);
2807         if (ret < 0)
2808             return ret;
2809         val = FV_FORMAT_TDM;
2810         break;
2811     default:
2812         ret = -EINVAL;
2813         dev_err(component->dev, "Format unsupported (%d)\n", ret);
2814         return ret;
2815     }
2816
2817     ret = snd_soc_component_update_bits(component,
2818             reg, FM_I2SPCTL_FORMAT, val);
2819     if (ret < 0) {
2820         dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
2821                 dai_id + 1, ret);
2822         return ret;
2823     }
2824
2825     return 0;
2826 }
2827
2828 static inline int
2829 set_aif_clock_format_from_fmt(struct snd_soc_component *component,
2830         unsigned int dai_id, unsigned int fmt)
2831 {
2832     unsigned int reg;
2833     unsigned int val;
2834     int ret;
2835
2836     switch (dai_id) {
2837     case TSCS454_DAI1_ID:
2838         reg = R_I2SP1CTL;
2839         break;
2840     case TSCS454_DAI2_ID:
2841         reg = R_I2SP2CTL;
2842         break;
2843     case TSCS454_DAI3_ID:
2844         reg = R_I2SP3CTL;
2845         break;
2846     default:
2847         ret = -EINVAL;
2848         dev_err(component->dev,
2849                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2850         return ret;
2851     }
2852
2853     switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2854     case SND_SOC_DAIFMT_NB_NF:
2855         val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
2856         break;
2857     case SND_SOC_DAIFMT_NB_IF:
2858         val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
2859         break;
2860     case SND_SOC_DAIFMT_IB_NF:
2861         val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
2862         break;
2863     case SND_SOC_DAIFMT_IB_IF:
2864         val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
2865         break;
2866     default:
2867         ret = -EINVAL;
2868         dev_err(component->dev, "Format unknown (%d)\n", ret);
2869         return ret;
2870     }
2871
2872     ret = snd_soc_component_update_bits(component, reg,
2873             FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
2874     if (ret < 0) {
2875         dev_err(component->dev,
2876                 "Failed to set clock polarity for DAI%d (%d)\n",
2877                 dai_id + 1, ret);
2878         return ret;
2879     }
2880
2881     return 0;
2882 }
2883
2884 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2885 {
2886     struct snd_soc_component *component = dai->component;
2887     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2888     struct aif *aif = &tscs454->aifs[dai->id];
2889     int ret;
2890
2891     ret = set_aif_provider_from_fmt(component, aif, fmt);
2892     if (ret < 0)
2893         return ret;
2894
2895     ret = set_aif_format_from_fmt(component, dai->id, fmt);
2896     if (ret < 0)
2897         return ret;
2898
2899     ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
2900     if (ret < 0)
2901         return ret;
2902
2903     return 0;
2904 }
2905
2906 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
2907         unsigned int tx_mask, unsigned int rx_mask, int slots,
2908         int slot_width)
2909 {
2910     struct snd_soc_component *component = dai->component;
2911     unsigned int val;
2912     int ret;
2913
2914     if (!slots)
2915         return 0;
2916
2917     if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2918         ret = -EINVAL;
2919         dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2920         return ret;
2921     }
2922
2923     switch (slots) {
2924     case 2:
2925         val = FV_TDMSO_2 | FV_TDMSI_2;
2926         break;
2927     case 4:
2928         val = FV_TDMSO_4 | FV_TDMSI_4;
2929         break;
2930     case 6:
2931         val = FV_TDMSO_6 | FV_TDMSI_6;
2932         break;
2933     default:
2934         ret = -EINVAL;
2935         dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
2936         return ret;
2937     }
2938
2939     switch (slot_width) {
2940     case 16:
2941         val = val | FV_TDMDSS_16;
2942         break;
2943     case 24:
2944         val = val | FV_TDMDSS_24;
2945         break;
2946     case 32:
2947         val = val | FV_TDMDSS_32;
2948         break;
2949     default:
2950         ret = -EINVAL;
2951         dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
2952         return ret;
2953     }
2954     ret = snd_soc_component_write(component, R_TDMCTL1, val);
2955     if (ret < 0) {
2956         dev_err(component->dev, "Failed to set slots (%d)\n", ret);
2957         return ret;
2958     }
2959
2960     return 0;
2961 }
2962
2963 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
2964         unsigned int tx_mask, unsigned int rx_mask, int slots,
2965         int slot_width)
2966 {
2967     struct snd_soc_component *component = dai->component;
2968     unsigned int reg;
2969     unsigned int val;
2970     int ret;
2971
2972     if (!slots)
2973         return 0;
2974
2975     if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2976         ret = -EINVAL;
2977         dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2978         return ret;
2979     }
2980
2981     switch (dai->id) {
2982     case TSCS454_DAI2_ID:
2983         reg = R_PCMP2CTL1;
2984         break;
2985     case TSCS454_DAI3_ID:
2986         reg = R_PCMP3CTL1;
2987         break;
2988     default:
2989         ret = -EINVAL;
2990         dev_err(component->dev, "Unrecognized interface %d (%d)\n",
2991                 dai->id, ret);
2992         return ret;
2993     }
2994
2995     switch (slots) {
2996     case 1:
2997         val = FV_PCMSOP_1 | FV_PCMSIP_1;
2998         break;
2999     case 2:
3000         val = FV_PCMSOP_2 | FV_PCMSIP_2;
3001         break;
3002     default:
3003         ret = -EINVAL;
3004         dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
3005         return ret;
3006     }
3007
3008     switch (slot_width) {
3009     case 16:
3010         val = val | FV_PCMDSSP_16;
3011         break;
3012     case 24:
3013         val = val | FV_PCMDSSP_24;
3014         break;
3015     case 32:
3016         val = val | FV_PCMDSSP_32;
3017         break;
3018     default:
3019         ret = -EINVAL;
3020         dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
3021         return ret;
3022     }
3023     ret = snd_soc_component_write(component, reg, val);
3024     if (ret < 0) {
3025         dev_err(component->dev, "Failed to set slots (%d)\n", ret);
3026         return ret;
3027     }
3028
3029     return 0;
3030 }
3031
3032 static int set_aif_fs(struct snd_soc_component *component,
3033         unsigned int id,
3034         unsigned int rate)
3035 {
3036     unsigned int reg;
3037     unsigned int br;
3038     unsigned int bm;
3039     int ret;
3040
3041     switch (rate) {
3042     case 8000:
3043         br = FV_I2SMBR_32;
3044         bm = FV_I2SMBM_0PT25;
3045         break;
3046     case 16000:
3047         br = FV_I2SMBR_32;
3048         bm = FV_I2SMBM_0PT5;
3049         break;
3050     case 24000:
3051         br = FV_I2SMBR_48;
3052         bm = FV_I2SMBM_0PT5;
3053         break;
3054     case 32000:
3055         br = FV_I2SMBR_32;
3056         bm = FV_I2SMBM_1;
3057         break;
3058     case 48000:
3059         br = FV_I2SMBR_48;
3060         bm = FV_I2SMBM_1;
3061         break;
3062     case 96000:
3063         br = FV_I2SMBR_48;
3064         bm = FV_I2SMBM_2;
3065         break;
3066     case 11025:
3067         br = FV_I2SMBR_44PT1;
3068         bm = FV_I2SMBM_0PT25;
3069         break;
3070     case 22050:
3071         br = FV_I2SMBR_44PT1;
3072         bm = FV_I2SMBM_0PT5;
3073         break;
3074     case 44100:
3075         br = FV_I2SMBR_44PT1;
3076         bm = FV_I2SMBM_1;
3077         break;
3078     case 88200:
3079         br = FV_I2SMBR_44PT1;
3080         bm = FV_I2SMBM_2;
3081         break;
3082     default:
3083         ret = -EINVAL;
3084         dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
3085         return ret;
3086     }
3087
3088     switch (id) {
3089     case TSCS454_DAI1_ID:
3090         reg = R_I2S1MRATE;
3091         break;
3092     case TSCS454_DAI2_ID:
3093         reg = R_I2S2MRATE;
3094         break;
3095     case TSCS454_DAI3_ID:
3096         reg = R_I2S3MRATE;
3097         break;
3098     default:
3099         ret = -EINVAL;
3100         dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
3101         return ret;
3102     }
3103
3104     ret = snd_soc_component_update_bits(component, reg,
3105             FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
3106     if (ret < 0) {
3107         dev_err(component->dev,
3108                 "Failed to update register (%d)\n", ret);
3109         return ret;
3110     }
3111
3112     return 0;
3113 }
3114
3115 static int set_aif_sample_format(struct snd_soc_component *component,
3116         snd_pcm_format_t format,
3117         int aif_id)
3118 {
3119     unsigned int reg;
3120     unsigned int width;
3121     int ret;
3122
3123     switch (snd_pcm_format_width(format)) {
3124     case 16:
3125         width = FV_WL_16;
3126         break;
3127     case 20:
3128         width = FV_WL_20;
3129         break;
3130     case 24:
3131         width = FV_WL_24;
3132         break;
3133     case 32:
3134         width = FV_WL_32;
3135         break;
3136     default:
3137         ret = -EINVAL;
3138         dev_err(component->dev, "Unsupported format width (%d)\n", ret);
3139         return ret;
3140     }
3141
3142     switch (aif_id) {
3143     case TSCS454_DAI1_ID:
3144         reg = R_I2SP1CTL;
3145         break;
3146     case TSCS454_DAI2_ID:
3147         reg = R_I2SP2CTL;
3148         break;
3149     case TSCS454_DAI3_ID:
3150         reg = R_I2SP3CTL;
3151         break;
3152     default:
3153         ret = -EINVAL;
3154         dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
3155         return ret;
3156     }
3157
3158     ret = snd_soc_component_update_bits(component,
3159             reg, FM_I2SPCTL_WL, width);
3160     if (ret < 0) {
3161         dev_err(component->dev,
3162                 "Failed to set sample width (%d)\n", ret);
3163         return ret;
3164     }
3165
3166     return 0;
3167 }
3168
3169 static int tscs454_hw_params(struct snd_pcm_substream *substream,
3170         struct snd_pcm_hw_params *params,
3171         struct snd_soc_dai *dai)
3172 {
3173     struct snd_soc_component *component = dai->component;
3174     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3175     unsigned int fs = params_rate(params);
3176     struct aif *aif = &tscs454->aifs[dai->id];
3177     unsigned int val;
3178     int ret;
3179
3180     mutex_lock(&tscs454->aifs_status_lock);
3181
3182     dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
3183             aif->id, fs);
3184
3185     if (!aif_active(&tscs454->aifs_status, aif->id)) {
3186         if (PLL_44_1K_RATE % fs)
3187             aif->pll = &tscs454->pll1;
3188         else
3189             aif->pll = &tscs454->pll2;
3190
3191         dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
3192                 aif->pll->id, aif->id);
3193
3194         reserve_pll(aif->pll);
3195     }
3196
3197     if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3198         val = snd_soc_component_read(component, R_ISRC);
3199         if ((val & FM_ISRC_IBR) == FV_IBR_48)
3200             tscs454->internal_rate.pll = &tscs454->pll1;
3201         else
3202             tscs454->internal_rate.pll = &tscs454->pll2;
3203
3204         dev_dbg(component->dev, "Reserving pll %d for ir\n",
3205                 tscs454->internal_rate.pll->id);
3206
3207         reserve_pll(tscs454->internal_rate.pll);
3208     }
3209
3210     ret = set_aif_fs(component, aif->id, fs);
3211     if (ret < 0) {
3212         dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
3213         goto exit;
3214     }
3215
3216     ret = set_aif_sample_format(component, params_format(params), aif->id);
3217     if (ret < 0) {
3218         dev_err(component->dev,
3219                 "Failed to set aif sample format (%d)\n", ret);
3220         goto exit;
3221     }
3222
3223     set_aif_status_active(&tscs454->aifs_status, aif->id,
3224             substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3225
3226     dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
3227         aif->id, tscs454->aifs_status.streams);
3228
3229     ret = 0;
3230 exit:
3231     mutex_unlock(&tscs454->aifs_status_lock);
3232
3233     return ret;
3234 }
3235
3236 static int tscs454_hw_free(struct snd_pcm_substream *substream,
3237         struct snd_soc_dai *dai)
3238 {
3239     struct snd_soc_component *component = dai->component;
3240     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3241     struct aif *aif = &tscs454->aifs[dai->id];
3242
3243     return aif_free(component, aif,
3244             substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3245 }
3246
3247 static int tscs454_prepare(struct snd_pcm_substream *substream,
3248         struct snd_soc_dai *dai)
3249 {
3250     int ret;
3251     struct snd_soc_component *component = dai->component;
3252     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3253     struct aif *aif = &tscs454->aifs[dai->id];
3254
3255     ret = aif_prepare(component, aif);
3256     if (ret < 0)
3257         return ret;
3258
3259     return 0;
3260 }
3261
3262 static struct snd_soc_dai_ops const tscs454_dai1_ops = {
3263     .set_sysclk = tscs454_set_sysclk,
3264     .set_bclk_ratio = tscs454_set_bclk_ratio,
3265     .set_fmt    = tscs454_set_dai_fmt,
3266     .set_tdm_slot   = tscs454_dai1_set_tdm_slot,
3267     .hw_params  = tscs454_hw_params,
3268     .hw_free    = tscs454_hw_free,
3269     .prepare    = tscs454_prepare,
3270 };
3271
3272 static struct snd_soc_dai_ops const tscs454_dai23_ops = {
3273     .set_sysclk = tscs454_set_sysclk,
3274     .set_bclk_ratio = tscs454_set_bclk_ratio,
3275     .set_fmt    = tscs454_set_dai_fmt,
3276     .set_tdm_slot   = tscs454_dai23_set_tdm_slot,
3277     .hw_params  = tscs454_hw_params,
3278     .hw_free    = tscs454_hw_free,
3279     .prepare    = tscs454_prepare,
3280 };
3281
3282 static int tscs454_probe(struct snd_soc_component *component)
3283 {
3284     struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3285     unsigned int val;
3286     int ret = 0;
3287
3288     switch (tscs454->sysclk_src_id) {
3289     case PLL_INPUT_XTAL:
3290         val = FV_PLLISEL_XTAL;
3291         break;
3292     case PLL_INPUT_MCLK1:
3293         val = FV_PLLISEL_MCLK1;
3294         break;
3295     case PLL_INPUT_MCLK2:
3296         val = FV_PLLISEL_MCLK2;
3297         break;
3298     case PLL_INPUT_BCLK:
3299         val = FV_PLLISEL_BCLK;
3300         break;
3301     default:
3302         ret = -EINVAL;
3303         dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
3304         return ret;
3305     }
3306
3307     ret = snd_soc_component_update_bits(component, R_PLLCTL,
3308             FM_PLLCTL_PLLISEL, val);
3309     if (ret < 0) {
3310         dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
3311         return ret;
3312     }
3313
3314     if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
3315         ret = set_sysclk(component);
3316
3317     return ret;
3318 }
3319
3320 static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
3321     .probe =    tscs454_probe,
3322     .dapm_widgets = tscs454_dapm_widgets,
3323     .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
3324     .dapm_routes = tscs454_intercon,
3325     .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3326     .controls = tscs454_snd_controls,
3327     .num_controls = ARRAY_SIZE(tscs454_snd_controls),
3328     .endianness = 1,
3329 };
3330
3331 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
3332
3333 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
3334     | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
3335     | SNDRV_PCM_FMTBIT_S32_LE)
3336
3337 static struct snd_soc_dai_driver tscs454_dais[] = {
3338     {
3339         .name = "tscs454-dai1",
3340         .id = TSCS454_DAI1_ID,
3341         .playback = {
3342             .stream_name = "DAI 1 Playback",
3343             .channels_min = 1,
3344             .channels_max = 6,
3345             .rates = TSCS454_RATES,
3346             .formats = TSCS454_FORMATS,},
3347         .capture = {
3348             .stream_name = "DAI 1 Capture",
3349             .channels_min = 1,
3350             .channels_max = 6,
3351             .rates = TSCS454_RATES,
3352             .formats = TSCS454_FORMATS,},
3353         .ops = &tscs454_dai1_ops,
3354         .symmetric_rate = 1,
3355         .symmetric_channels = 1,
3356         .symmetric_sample_bits = 1,
3357     },
3358     {
3359         .name = "tscs454-dai2",
3360         .id = TSCS454_DAI2_ID,
3361         .playback = {
3362             .stream_name = "DAI 2 Playback",
3363             .channels_min = 1,
3364             .channels_max = 2,
3365             .rates = TSCS454_RATES,
3366             .formats = TSCS454_FORMATS,},
3367         .capture = {
3368             .stream_name = "DAI 2 Capture",
3369             .channels_min = 1,
3370             .channels_max = 2,
3371             .rates = TSCS454_RATES,
3372             .formats = TSCS454_FORMATS,},
3373         .ops = &tscs454_dai23_ops,
3374         .symmetric_rate = 1,
3375         .symmetric_channels = 1,
3376         .symmetric_sample_bits = 1,
3377     },
3378     {
3379         .name = "tscs454-dai3",
3380         .id = TSCS454_DAI3_ID,
3381         .playback = {
3382             .stream_name = "DAI 3 Playback",
3383             .channels_min = 1,
3384             .channels_max = 2,
3385             .rates = TSCS454_RATES,
3386             .formats = TSCS454_FORMATS,},
3387         .capture = {
3388             .stream_name = "DAI 3 Capture",
3389             .channels_min = 1,
3390             .channels_max = 2,
3391             .rates = TSCS454_RATES,
3392             .formats = TSCS454_FORMATS,},
3393         .ops = &tscs454_dai23_ops,
3394         .symmetric_rate = 1,
3395         .symmetric_channels = 1,
3396         .symmetric_sample_bits = 1,
3397     },
3398 };
3399
3400 static char const * const src_names[] = {
3401     "xtal", "mclk1", "mclk2", "bclk"};
3402
3403 static int tscs454_i2c_probe(struct i2c_client *i2c)
3404 {
3405     struct tscs454 *tscs454;
3406     int src;
3407     int ret;
3408
3409     tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
3410     if (!tscs454)
3411         return -ENOMEM;
3412
3413     ret = tscs454_data_init(tscs454, i2c);
3414     if (ret < 0)
3415         return ret;
3416
3417     i2c_set_clientdata(i2c, tscs454);
3418
3419     for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
3420         tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
3421         if (!IS_ERR(tscs454->sysclk)) {
3422             break;
3423         } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
3424             ret = PTR_ERR(tscs454->sysclk);
3425             dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
3426             return ret;
3427         }
3428     }
3429     dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
3430     tscs454->sysclk_src_id = src;
3431
3432     ret = regmap_write(tscs454->regmap,
3433             R_RESET, FV_RESET_PWR_ON_DEFAULTS);
3434     if (ret < 0) {
3435         dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
3436         return ret;
3437     }
3438     regcache_mark_dirty(tscs454->regmap);
3439
3440     ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
3441             ARRAY_SIZE(tscs454_patch));
3442     if (ret < 0) {
3443         dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
3444         return ret;
3445     }
3446     /* Sync pg sel reg with cache */
3447     regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3448
3449     ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3450             tscs454_dais, ARRAY_SIZE(tscs454_dais));
3451     if (ret) {
3452         dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
3453         return ret;
3454     }
3455
3456     return 0;
3457 }
3458
3459 static const struct i2c_device_id tscs454_i2c_id[] = {
3460     { "tscs454", 0 },
3461     { }
3462 };
3463 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
3464
3465 static const struct of_device_id tscs454_of_match[] = {
3466     { .compatible = "tempo,tscs454", },
3467     { }
3468 };
3469 MODULE_DEVICE_TABLE(of, tscs454_of_match);
3470
3471 static struct i2c_driver tscs454_i2c_driver = {
3472     .driver = {
3473         .name = "tscs454",
3474         .of_match_table = tscs454_of_match,
3475     },
3476     .probe_new = tscs454_i2c_probe,
3477     .id_table = tscs454_i2c_id,
3478 };
3479
3480 module_i2c_driver(tscs454_i2c_driver);
3481
3482 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
3483 MODULE_DESCRIPTION("ASoC TSCS454 driver");
3484 MODULE_LICENSE("GPL v2");