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0001 // SPDX-License-Identifier: GPL-2.0
0002 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver
0003 // Copyright 2017 Tempo Semiconductor, Inc.
0004 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
0005 
0006 #include <linux/kernel.h>
0007 #include <linux/device.h>
0008 #include <linux/regmap.h>
0009 #include <linux/i2c.h>
0010 #include <linux/err.h>
0011 #include <linux/string.h>
0012 #include <linux/module.h>
0013 #include <linux/delay.h>
0014 #include <linux/mutex.h>
0015 #include <linux/clk.h>
0016 #include <sound/tlv.h>
0017 #include <sound/pcm_params.h>
0018 #include <sound/soc.h>
0019 #include <sound/soc-dapm.h>
0020 
0021 #include "tscs42xx.h"
0022 
0023 #define COEFF_SIZE 3
0024 #define BIQUAD_COEFF_COUNT 5
0025 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
0026 
0027 #define COEFF_RAM_MAX_ADDR 0xcd
0028 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
0029 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
0030 
0031 struct tscs42xx {
0032 
0033     int bclk_ratio;
0034     int samplerate;
0035     struct mutex audio_params_lock;
0036 
0037     u8 coeff_ram[COEFF_RAM_SIZE];
0038     bool coeff_ram_synced;
0039     struct mutex coeff_ram_lock;
0040 
0041     struct mutex pll_lock;
0042 
0043     struct regmap *regmap;
0044 
0045     struct clk *sysclk;
0046     int sysclk_src_id;
0047 };
0048 
0049 struct coeff_ram_ctl {
0050     unsigned int addr;
0051     struct soc_bytes_ext bytes_ext;
0052 };
0053 
0054 static bool tscs42xx_volatile(struct device *dev, unsigned int reg)
0055 {
0056     switch (reg) {
0057     case R_DACCRWRL:
0058     case R_DACCRWRM:
0059     case R_DACCRWRH:
0060     case R_DACCRRDL:
0061     case R_DACCRRDM:
0062     case R_DACCRRDH:
0063     case R_DACCRSTAT:
0064     case R_DACCRADDR:
0065     case R_PLLCTL0:
0066         return true;
0067     default:
0068         return false;
0069     }
0070 }
0071 
0072 static bool tscs42xx_precious(struct device *dev, unsigned int reg)
0073 {
0074     switch (reg) {
0075     case R_DACCRWRL:
0076     case R_DACCRWRM:
0077     case R_DACCRWRH:
0078     case R_DACCRRDL:
0079     case R_DACCRRDM:
0080     case R_DACCRRDH:
0081         return true;
0082     default:
0083         return false;
0084     }
0085 }
0086 
0087 static const struct regmap_config tscs42xx_regmap = {
0088     .reg_bits = 8,
0089     .val_bits = 8,
0090 
0091     .volatile_reg = tscs42xx_volatile,
0092     .precious_reg = tscs42xx_precious,
0093     .max_register = R_DACMBCREL3H,
0094 
0095     .cache_type = REGCACHE_RBTREE,
0096     .can_multi_write = true,
0097 };
0098 
0099 #define MAX_PLL_LOCK_20MS_WAITS 1
0100 static bool plls_locked(struct snd_soc_component *component)
0101 {
0102     int ret;
0103     int count = MAX_PLL_LOCK_20MS_WAITS;
0104 
0105     do {
0106         ret = snd_soc_component_read(component, R_PLLCTL0);
0107         if (ret < 0) {
0108             dev_err(component->dev,
0109                 "Failed to read PLL lock status (%d)\n", ret);
0110             return false;
0111         } else if (ret > 0) {
0112             return true;
0113         }
0114         msleep(20);
0115     } while (count--);
0116 
0117     return false;
0118 }
0119 
0120 static int sample_rate_to_pll_freq_out(int sample_rate)
0121 {
0122     switch (sample_rate) {
0123     case 11025:
0124     case 22050:
0125     case 44100:
0126     case 88200:
0127         return 112896000;
0128     case 8000:
0129     case 16000:
0130     case 32000:
0131     case 48000:
0132     case 96000:
0133         return 122880000;
0134     default:
0135         return -EINVAL;
0136     }
0137 }
0138 
0139 #define DACCRSTAT_MAX_TRYS 10
0140 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
0141     unsigned int addr, unsigned int coeff_cnt)
0142 {
0143     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0144     int cnt;
0145     int trys;
0146     int ret;
0147 
0148     for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) {
0149 
0150         for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
0151             ret = snd_soc_component_read(component, R_DACCRSTAT);
0152             if (ret < 0) {
0153                 dev_err(component->dev,
0154                     "Failed to read stat (%d)\n", ret);
0155                 return ret;
0156             }
0157             if (!ret)
0158                 break;
0159         }
0160 
0161         if (trys == DACCRSTAT_MAX_TRYS) {
0162             ret = -EIO;
0163             dev_err(component->dev,
0164                 "dac coefficient write error (%d)\n", ret);
0165             return ret;
0166         }
0167 
0168         ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr);
0169         if (ret < 0) {
0170             dev_err(component->dev,
0171                 "Failed to write dac ram address (%d)\n", ret);
0172             return ret;
0173         }
0174 
0175         ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL,
0176             &coeff_ram[addr * COEFF_SIZE],
0177             COEFF_SIZE);
0178         if (ret < 0) {
0179             dev_err(component->dev,
0180                 "Failed to write dac ram (%d)\n", ret);
0181             return ret;
0182         }
0183     }
0184 
0185     return 0;
0186 }
0187 
0188 static int power_up_audio_plls(struct snd_soc_component *component)
0189 {
0190     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0191     int freq_out;
0192     int ret;
0193     unsigned int mask;
0194     unsigned int val;
0195 
0196     freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate);
0197     switch (freq_out) {
0198     case 122880000: /* 48k */
0199         mask = RM_PLLCTL1C_PDB_PLL1;
0200         val = RV_PLLCTL1C_PDB_PLL1_ENABLE;
0201         break;
0202     case 112896000: /* 44.1k */
0203         mask = RM_PLLCTL1C_PDB_PLL2;
0204         val = RV_PLLCTL1C_PDB_PLL2_ENABLE;
0205         break;
0206     default:
0207         ret = -EINVAL;
0208         dev_err(component->dev,
0209                 "Unrecognized PLL output freq (%d)\n", ret);
0210         return ret;
0211     }
0212 
0213     mutex_lock(&tscs42xx->pll_lock);
0214 
0215     ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val);
0216     if (ret < 0) {
0217         dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret);
0218         goto exit;
0219     }
0220 
0221     if (!plls_locked(component)) {
0222         dev_err(component->dev, "Failed to lock plls\n");
0223         ret = -ENOMSG;
0224         goto exit;
0225     }
0226 
0227     ret = 0;
0228 exit:
0229     mutex_unlock(&tscs42xx->pll_lock);
0230 
0231     return ret;
0232 }
0233 
0234 static int power_down_audio_plls(struct snd_soc_component *component)
0235 {
0236     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0237     int ret;
0238 
0239     mutex_lock(&tscs42xx->pll_lock);
0240 
0241     ret = snd_soc_component_update_bits(component, R_PLLCTL1C,
0242             RM_PLLCTL1C_PDB_PLL1,
0243             RV_PLLCTL1C_PDB_PLL1_DISABLE);
0244     if (ret < 0) {
0245         dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret);
0246         goto exit;
0247     }
0248     ret = snd_soc_component_update_bits(component, R_PLLCTL1C,
0249             RM_PLLCTL1C_PDB_PLL2,
0250             RV_PLLCTL1C_PDB_PLL2_DISABLE);
0251     if (ret < 0) {
0252         dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret);
0253         goto exit;
0254     }
0255 
0256     ret = 0;
0257 exit:
0258     mutex_unlock(&tscs42xx->pll_lock);
0259 
0260     return ret;
0261 }
0262 
0263 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
0264     struct snd_ctl_elem_value *ucontrol)
0265 {
0266     struct snd_soc_component *component =
0267         snd_soc_kcontrol_component(kcontrol);
0268     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0269     struct coeff_ram_ctl *ctl =
0270         (struct coeff_ram_ctl *)kcontrol->private_value;
0271     struct soc_bytes_ext *params = &ctl->bytes_ext;
0272 
0273     mutex_lock(&tscs42xx->coeff_ram_lock);
0274 
0275     memcpy(ucontrol->value.bytes.data,
0276         &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max);
0277 
0278     mutex_unlock(&tscs42xx->coeff_ram_lock);
0279 
0280     return 0;
0281 }
0282 
0283 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
0284     struct snd_ctl_elem_value *ucontrol)
0285 {
0286     struct snd_soc_component *component =
0287         snd_soc_kcontrol_component(kcontrol);
0288     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0289     struct coeff_ram_ctl *ctl =
0290         (struct coeff_ram_ctl *)kcontrol->private_value;
0291     struct soc_bytes_ext *params = &ctl->bytes_ext;
0292     unsigned int coeff_cnt = params->max / COEFF_SIZE;
0293     int ret;
0294 
0295     mutex_lock(&tscs42xx->coeff_ram_lock);
0296 
0297     tscs42xx->coeff_ram_synced = false;
0298 
0299     memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE],
0300         ucontrol->value.bytes.data, params->max);
0301 
0302     mutex_lock(&tscs42xx->pll_lock);
0303 
0304     if (plls_locked(component)) {
0305         ret = write_coeff_ram(component, tscs42xx->coeff_ram,
0306             ctl->addr, coeff_cnt);
0307         if (ret < 0) {
0308             dev_err(component->dev,
0309                 "Failed to flush coeff ram cache (%d)\n", ret);
0310             goto exit;
0311         }
0312         tscs42xx->coeff_ram_synced = true;
0313     }
0314 
0315     ret = 0;
0316 exit:
0317     mutex_unlock(&tscs42xx->pll_lock);
0318 
0319     mutex_unlock(&tscs42xx->coeff_ram_lock);
0320 
0321     return ret;
0322 }
0323 
0324 /* Input L Capture Route */
0325 static char const * const input_select_text[] = {
0326     "Line 1", "Line 2", "Line 3", "D2S"
0327 };
0328 
0329 static const struct soc_enum left_input_select_enum =
0330 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text),
0331         input_select_text);
0332 
0333 static const struct snd_kcontrol_new left_input_select =
0334 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum);
0335 
0336 /* Input R Capture Route */
0337 static const struct soc_enum right_input_select_enum =
0338 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text),
0339         input_select_text);
0340 
0341 static const struct snd_kcontrol_new right_input_select =
0342 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum);
0343 
0344 /* Input Channel Mapping */
0345 static char const * const ch_map_select_text[] = {
0346     "Normal", "Left to Right", "Right to Left", "Swap"
0347 };
0348 
0349 static const struct soc_enum ch_map_select_enum =
0350 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text),
0351         ch_map_select_text);
0352 
0353 static int dapm_vref_event(struct snd_soc_dapm_widget *w,
0354              struct snd_kcontrol *kcontrol, int event)
0355 {
0356     msleep(20);
0357     return 0;
0358 }
0359 
0360 static int dapm_micb_event(struct snd_soc_dapm_widget *w,
0361              struct snd_kcontrol *kcontrol, int event)
0362 {
0363     msleep(20);
0364     return 0;
0365 }
0366 
0367 static int pll_event(struct snd_soc_dapm_widget *w,
0368              struct snd_kcontrol *kcontrol, int event)
0369 {
0370     struct snd_soc_component *component =
0371         snd_soc_dapm_to_component(w->dapm);
0372     int ret;
0373 
0374     if (SND_SOC_DAPM_EVENT_ON(event))
0375         ret = power_up_audio_plls(component);
0376     else
0377         ret = power_down_audio_plls(component);
0378 
0379     return ret;
0380 }
0381 
0382 static int dac_event(struct snd_soc_dapm_widget *w,
0383              struct snd_kcontrol *kcontrol, int event)
0384 {
0385     struct snd_soc_component *component =
0386         snd_soc_dapm_to_component(w->dapm);
0387     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0388     int ret;
0389 
0390     mutex_lock(&tscs42xx->coeff_ram_lock);
0391 
0392     if (!tscs42xx->coeff_ram_synced) {
0393         ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00,
0394             COEFF_RAM_COEFF_COUNT);
0395         if (ret < 0)
0396             goto exit;
0397         tscs42xx->coeff_ram_synced = true;
0398     }
0399 
0400     ret = 0;
0401 exit:
0402     mutex_unlock(&tscs42xx->coeff_ram_lock);
0403 
0404     return ret;
0405 }
0406 
0407 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = {
0408     /* Vref */
0409     SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0,
0410         dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
0411 
0412     /* PLL */
0413     SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event,
0414         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
0415 
0416     /* Headphone */
0417     SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0,
0418             dac_event, SND_SOC_DAPM_POST_PMU),
0419     SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0,
0420             dac_event, SND_SOC_DAPM_POST_PMU),
0421     SND_SOC_DAPM_OUTPUT("Headphone L"),
0422     SND_SOC_DAPM_OUTPUT("Headphone R"),
0423 
0424     /* Speaker */
0425     SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback",
0426         R_PWRM2, FB_PWRM2_SPKL, 0,
0427         dac_event, SND_SOC_DAPM_POST_PMU),
0428     SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback",
0429         R_PWRM2, FB_PWRM2_SPKR, 0,
0430         dac_event, SND_SOC_DAPM_POST_PMU),
0431     SND_SOC_DAPM_OUTPUT("Speaker L"),
0432     SND_SOC_DAPM_OUTPUT("Speaker R"),
0433 
0434     /* Capture */
0435     SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0),
0436     SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0),
0437     SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0),
0438     SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0),
0439     SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0),
0440     SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0),
0441     SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0),
0442 
0443     /* Capture Input */
0444     SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2,
0445             FB_PWRM2_INSELL, 0, &left_input_select),
0446     SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2,
0447             FB_PWRM2_INSELR, 0, &right_input_select),
0448 
0449     /* Digital Mic */
0450     SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL,
0451         FB_DMICCTL_DMICEN, 0, NULL,
0452         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
0453 
0454     /* Analog Mic */
0455     SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB,
0456         0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
0457 
0458     /* Line In */
0459     SND_SOC_DAPM_INPUT("Line In 1 L"),
0460     SND_SOC_DAPM_INPUT("Line In 1 R"),
0461     SND_SOC_DAPM_INPUT("Line In 2 L"),
0462     SND_SOC_DAPM_INPUT("Line In 2 R"),
0463     SND_SOC_DAPM_INPUT("Line In 3 L"),
0464     SND_SOC_DAPM_INPUT("Line In 3 R"),
0465 };
0466 
0467 static const struct snd_soc_dapm_route tscs42xx_intercon[] = {
0468     {"DAC L", NULL, "PLL"},
0469     {"DAC R", NULL, "PLL"},
0470     {"DAC L", NULL, "Vref"},
0471     {"DAC R", NULL, "Vref"},
0472     {"Headphone L", NULL, "DAC L"},
0473     {"Headphone R", NULL, "DAC R"},
0474 
0475     {"ClassD L", NULL, "PLL"},
0476     {"ClassD R", NULL, "PLL"},
0477     {"ClassD L", NULL, "Vref"},
0478     {"ClassD R", NULL, "Vref"},
0479     {"Speaker L", NULL, "ClassD L"},
0480     {"Speaker R", NULL, "ClassD R"},
0481 
0482     {"Input L Capture Route", NULL, "Vref"},
0483     {"Input R Capture Route", NULL, "Vref"},
0484 
0485     {"Mic Bias", NULL, "Vref"},
0486 
0487     {"Input L Capture Route", "Line 1", "Line In 1 L"},
0488     {"Input R Capture Route", "Line 1", "Line In 1 R"},
0489     {"Input L Capture Route", "Line 2", "Line In 2 L"},
0490     {"Input R Capture Route", "Line 2", "Line In 2 R"},
0491     {"Input L Capture Route", "Line 3", "Line In 3 L"},
0492     {"Input R Capture Route", "Line 3", "Line In 3 R"},
0493 
0494     {"Analog In PGA L", NULL, "Input L Capture Route"},
0495     {"Analog In PGA R", NULL, "Input R Capture Route"},
0496     {"Analog Boost L", NULL, "Analog In PGA L"},
0497     {"Analog Boost R", NULL, "Analog In PGA R"},
0498     {"ADC Mute", NULL, "Analog Boost L"},
0499     {"ADC Mute", NULL, "Analog Boost R"},
0500     {"ADC L", NULL, "PLL"},
0501     {"ADC R", NULL, "PLL"},
0502     {"ADC L", NULL, "ADC Mute"},
0503     {"ADC R", NULL, "ADC Mute"},
0504 };
0505 
0506 /************
0507  * CONTROLS *
0508  ************/
0509 
0510 static char const * const eq_band_enable_text[] = {
0511     "Prescale only",
0512     "Band1",
0513     "Band1:2",
0514     "Band1:3",
0515     "Band1:4",
0516     "Band1:5",
0517     "Band1:6",
0518 };
0519 
0520 static char const * const level_detection_text[] = {
0521     "Average",
0522     "Peak",
0523 };
0524 
0525 static char const * const level_detection_window_text[] = {
0526     "512 Samples",
0527     "64 Samples",
0528 };
0529 
0530 static char const * const compressor_ratio_text[] = {
0531     "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
0532     "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
0533     "15:1", "16:1", "17:1", "18:1", "19:1", "20:1",
0534 };
0535 
0536 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0);
0537 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0);
0538 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0);
0539 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0);
0540 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0);
0541 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0);
0542 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650);
0543 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0);
0544 
0545 static const struct soc_enum eq1_band_enable_enum =
0546     SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE,
0547         ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text);
0548 
0549 static const struct soc_enum eq2_band_enable_enum =
0550     SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE,
0551         ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text);
0552 
0553 static const struct soc_enum cle_level_detection_enum =
0554     SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE,
0555         ARRAY_SIZE(level_detection_text),
0556         level_detection_text);
0557 
0558 static const struct soc_enum cle_level_detection_window_enum =
0559     SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL,
0560         ARRAY_SIZE(level_detection_window_text),
0561         level_detection_window_text);
0562 
0563 static const struct soc_enum mbc_level_detection_enums[] = {
0564     SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
0565         ARRAY_SIZE(level_detection_text),
0566             level_detection_text),
0567     SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
0568         ARRAY_SIZE(level_detection_text),
0569             level_detection_text),
0570     SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
0571         ARRAY_SIZE(level_detection_text),
0572             level_detection_text),
0573 };
0574 
0575 static const struct soc_enum mbc_level_detection_window_enums[] = {
0576     SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
0577         ARRAY_SIZE(level_detection_window_text),
0578             level_detection_window_text),
0579     SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
0580         ARRAY_SIZE(level_detection_window_text),
0581             level_detection_window_text),
0582     SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
0583         ARRAY_SIZE(level_detection_window_text),
0584             level_detection_window_text),
0585 };
0586 
0587 static const struct soc_enum compressor_ratio_enum =
0588     SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT,
0589         ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
0590 
0591 static const struct soc_enum dac_mbc1_compressor_ratio_enum =
0592     SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO,
0593         ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
0594 
0595 static const struct soc_enum dac_mbc2_compressor_ratio_enum =
0596     SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO,
0597         ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
0598 
0599 static const struct soc_enum dac_mbc3_compressor_ratio_enum =
0600     SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO,
0601         ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
0602 
0603 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
0604     struct snd_ctl_elem_info *ucontrol)
0605 {
0606     struct coeff_ram_ctl *ctl =
0607         (struct coeff_ram_ctl *)kcontrol->private_value;
0608     struct soc_bytes_ext *params = &ctl->bytes_ext;
0609 
0610     ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
0611     ucontrol->count = params->max;
0612 
0613     return 0;
0614 }
0615 
0616 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
0617 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
0618     .info = bytes_info_ext, \
0619     .get = coeff_ram_get, .put = coeff_ram_put, \
0620     .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
0621         .addr = xaddr, \
0622         .bytes_ext = {.max = xcount, }, \
0623     } \
0624 }
0625 
0626 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = {
0627     /* Volumes */
0628     SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
0629             FB_HPVOLL, 0x7F, 0, hpvol_scale),
0630     SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
0631             FB_SPKVOLL, 0x7F, 0, spkvol_scale),
0632     SOC_DOUBLE_R_TLV("Master Volume", R_DACVOLL, R_DACVOLR,
0633             FB_DACVOLL, 0xFF, 0, dacvol_scale),
0634     SOC_DOUBLE_R_TLV("PCM Volume", R_ADCVOLL, R_ADCVOLR,
0635             FB_ADCVOLL, 0xFF, 0, adcvol_scale),
0636     SOC_DOUBLE_R_TLV("Input Volume", R_INVOLL, R_INVOLR,
0637             FB_INVOLL, 0x3F, 0, invol_scale),
0638 
0639     /* INSEL */
0640     SOC_DOUBLE_R_TLV("Mic Boost Volume", R_INSELL, R_INSELR,
0641             FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB,
0642             0, mic_boost_scale),
0643 
0644     /* Input Channel Map */
0645     SOC_ENUM("Input Channel Map", ch_map_select_enum),
0646 
0647     /* Mic Bias */
0648     SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0),
0649 
0650     /* Headphone Auto Switching */
0651     SOC_SINGLE("Headphone Auto Switching Switch",
0652             R_CTL, FB_CTL_HPSWEN, 1, 0),
0653     SOC_SINGLE("Headphone Detect Polarity Toggle Switch",
0654             R_CTL, FB_CTL_HPSWPOL, 1, 0),
0655 
0656     /* Coefficient Ram */
0657     COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00),
0658     COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05),
0659     COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a),
0660     COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f),
0661     COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14),
0662     COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19),
0663 
0664     COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20),
0665     COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25),
0666     COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a),
0667     COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f),
0668     COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34),
0669     COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39),
0670 
0671     COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f),
0672     COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f),
0673 
0674     COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40),
0675     COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45),
0676     COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a),
0677     COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f),
0678     COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54),
0679     COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59),
0680 
0681     COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60),
0682     COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65),
0683     COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a),
0684     COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f),
0685     COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74),
0686     COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79),
0687 
0688     COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f),
0689     COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f),
0690 
0691     COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80),
0692     COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85),
0693 
0694     COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
0695     COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
0696 
0697     COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
0698 
0699     COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
0700 
0701     COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96),
0702 
0703     COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97),
0704     COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c),
0705 
0706     COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
0707     COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
0708 
0709     COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
0710 
0711     COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
0712 
0713     COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad),
0714 
0715     COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae),
0716 
0717     COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf),
0718 
0719     COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0),
0720     COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5),
0721 
0722     COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba),
0723     COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf),
0724 
0725     COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4),
0726     COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9),
0727 
0728     /* EQ */
0729     SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0),
0730     SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0),
0731     SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum),
0732     SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum),
0733 
0734     /* CLE */
0735     SOC_ENUM("CLE Level Detect",
0736         cle_level_detection_enum),
0737     SOC_ENUM("CLE Level Detect Win",
0738         cle_level_detection_window_enum),
0739     SOC_SINGLE("Expander Switch",
0740         R_CLECTL, FB_CLECTL_EXP_EN, 1, 0),
0741     SOC_SINGLE("Limiter Switch",
0742         R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0),
0743     SOC_SINGLE("Comp Switch",
0744         R_CLECTL, FB_CLECTL_COMP_EN, 1, 0),
0745     SOC_SINGLE_TLV("CLE Make-Up Gain Volume",
0746         R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale),
0747     SOC_SINGLE_TLV("Comp Thresh Volume",
0748         R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale),
0749     SOC_ENUM("Comp Ratio", compressor_ratio_enum),
0750     SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2),
0751 
0752     /* Effects */
0753     SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0),
0754     SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0),
0755     SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0),
0756     SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0),
0757     SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0),
0758 
0759     /* MBC */
0760     SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
0761     SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
0762     SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
0763     SOC_ENUM("MBC Band1 Level Detect",
0764         mbc_level_detection_enums[0]),
0765     SOC_ENUM("MBC Band2 Level Detect",
0766         mbc_level_detection_enums[1]),
0767     SOC_ENUM("MBC Band3 Level Detect",
0768         mbc_level_detection_enums[2]),
0769     SOC_ENUM("MBC Band1 Level Detect Win",
0770         mbc_level_detection_window_enums[0]),
0771     SOC_ENUM("MBC Band2 Level Detect Win",
0772         mbc_level_detection_window_enums[1]),
0773     SOC_ENUM("MBC Band3 Level Detect Win",
0774         mbc_level_detection_window_enums[2]),
0775 
0776     SOC_SINGLE("MBC1 Phase Invert Switch",
0777         R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0),
0778     SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Volume",
0779         R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale),
0780     SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Volume",
0781         R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale),
0782     SOC_ENUM("DAC MBC1 Comp Ratio",
0783         dac_mbc1_compressor_ratio_enum),
0784     SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2),
0785     SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const",
0786         R_DACMBCREL1L, 2),
0787 
0788     SOC_SINGLE("MBC2 Phase Invert Switch",
0789         R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0),
0790     SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Volume",
0791         R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale),
0792     SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Volume",
0793         R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale),
0794     SOC_ENUM("DAC MBC2 Comp Ratio",
0795         dac_mbc2_compressor_ratio_enum),
0796     SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2),
0797     SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const",
0798         R_DACMBCREL2L, 2),
0799 
0800     SOC_SINGLE("MBC3 Phase Invert Switch",
0801         R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0),
0802     SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Volume",
0803         R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale),
0804     SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Volume",
0805         R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale),
0806     SOC_ENUM("DAC MBC3 Comp Ratio",
0807         dac_mbc3_compressor_ratio_enum),
0808     SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2),
0809     SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const",
0810         R_DACMBCREL3L, 2),
0811 };
0812 
0813 static int setup_sample_format(struct snd_soc_component *component,
0814         snd_pcm_format_t format)
0815 {
0816     unsigned int width;
0817     int ret;
0818 
0819     switch (format) {
0820     case SNDRV_PCM_FORMAT_S16_LE:
0821         width = RV_AIC1_WL_16;
0822         break;
0823     case SNDRV_PCM_FORMAT_S20_3LE:
0824         width = RV_AIC1_WL_20;
0825         break;
0826     case SNDRV_PCM_FORMAT_S24_LE:
0827         width = RV_AIC1_WL_24;
0828         break;
0829     case SNDRV_PCM_FORMAT_S32_LE:
0830         width = RV_AIC1_WL_32;
0831         break;
0832     default:
0833         ret = -EINVAL;
0834         dev_err(component->dev, "Unsupported format width (%d)\n", ret);
0835         return ret;
0836     }
0837     ret = snd_soc_component_update_bits(component,
0838             R_AIC1, RM_AIC1_WL, width);
0839     if (ret < 0) {
0840         dev_err(component->dev,
0841                 "Failed to set sample width (%d)\n", ret);
0842         return ret;
0843     }
0844 
0845     return 0;
0846 }
0847 
0848 static int setup_sample_rate(struct snd_soc_component *component,
0849         unsigned int rate)
0850 {
0851     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
0852     unsigned int br, bm;
0853     int ret;
0854 
0855     switch (rate) {
0856     case 8000:
0857         br = RV_DACSR_DBR_32;
0858         bm = RV_DACSR_DBM_PT25;
0859         break;
0860     case 16000:
0861         br = RV_DACSR_DBR_32;
0862         bm = RV_DACSR_DBM_PT5;
0863         break;
0864     case 24000:
0865         br = RV_DACSR_DBR_48;
0866         bm = RV_DACSR_DBM_PT5;
0867         break;
0868     case 32000:
0869         br = RV_DACSR_DBR_32;
0870         bm = RV_DACSR_DBM_1;
0871         break;
0872     case 48000:
0873         br = RV_DACSR_DBR_48;
0874         bm = RV_DACSR_DBM_1;
0875         break;
0876     case 96000:
0877         br = RV_DACSR_DBR_48;
0878         bm = RV_DACSR_DBM_2;
0879         break;
0880     case 11025:
0881         br = RV_DACSR_DBR_44_1;
0882         bm = RV_DACSR_DBM_PT25;
0883         break;
0884     case 22050:
0885         br = RV_DACSR_DBR_44_1;
0886         bm = RV_DACSR_DBM_PT5;
0887         break;
0888     case 44100:
0889         br = RV_DACSR_DBR_44_1;
0890         bm = RV_DACSR_DBM_1;
0891         break;
0892     case 88200:
0893         br = RV_DACSR_DBR_44_1;
0894         bm = RV_DACSR_DBM_2;
0895         break;
0896     default:
0897         dev_err(component->dev, "Unsupported sample rate %d\n", rate);
0898         return -EINVAL;
0899     }
0900 
0901     /* DAC and ADC share bit and frame clock */
0902     ret = snd_soc_component_update_bits(component,
0903             R_DACSR, RM_DACSR_DBR, br);
0904     if (ret < 0) {
0905         dev_err(component->dev,
0906                 "Failed to update register (%d)\n", ret);
0907         return ret;
0908     }
0909     ret = snd_soc_component_update_bits(component,
0910             R_DACSR, RM_DACSR_DBM, bm);
0911     if (ret < 0) {
0912         dev_err(component->dev,
0913                 "Failed to update register (%d)\n", ret);
0914         return ret;
0915     }
0916     ret = snd_soc_component_update_bits(component,
0917             R_ADCSR, RM_DACSR_DBR, br);
0918     if (ret < 0) {
0919         dev_err(component->dev,
0920                 "Failed to update register (%d)\n", ret);
0921         return ret;
0922     }
0923     ret = snd_soc_component_update_bits(component,
0924             R_ADCSR, RM_DACSR_DBM, bm);
0925     if (ret < 0) {
0926         dev_err(component->dev,
0927                 "Failed to update register (%d)\n", ret);
0928         return ret;
0929     }
0930 
0931     mutex_lock(&tscs42xx->audio_params_lock);
0932 
0933     tscs42xx->samplerate = rate;
0934 
0935     mutex_unlock(&tscs42xx->audio_params_lock);
0936 
0937     return 0;
0938 }
0939 
0940 struct reg_setting {
0941     unsigned int addr;
0942     unsigned int val;
0943     unsigned int mask;
0944 };
0945 
0946 #define PLL_REG_SETTINGS_COUNT 13
0947 struct pll_ctl {
0948     int input_freq;
0949     struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
0950 };
0951 
0952 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb,       \
0953         rc, r12, r1b_h, re, rf, r10, r11)   \
0954     {                       \
0955         .input_freq = f,            \
0956         .settings = {               \
0957             {R_TIMEBASE,  rt,   0xFF},  \
0958             {R_PLLCTLD,   rd,   0xFF},  \
0959             {R_PLLCTL1B, r1b_l, 0x0F},  \
0960             {R_PLLCTL9,   r9,   0xFF},  \
0961             {R_PLLCTLA,   ra,   0xFF},  \
0962             {R_PLLCTLB,   rb,   0xFF},  \
0963             {R_PLLCTLC,   rc,   0xFF},  \
0964             {R_PLLCTL12, r12,   0xFF},  \
0965             {R_PLLCTL1B, r1b_h, 0xF0},  \
0966             {R_PLLCTLE,   re,   0xFF},  \
0967             {R_PLLCTLF,   rf,   0xFF},  \
0968             {R_PLLCTL10, r10,   0xFF},  \
0969             {R_PLLCTL11, r11,   0xFF},  \
0970         },                  \
0971     }
0972 
0973 static const struct pll_ctl pll_ctls[] = {
0974     PLL_CTL(1411200, 0x05,
0975         0x39, 0x04, 0x07, 0x02, 0xC3, 0x04,
0976         0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02),
0977     PLL_CTL(1536000, 0x05,
0978         0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01,
0979         0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01),
0980     PLL_CTL(2822400, 0x0A,
0981         0x23, 0x04, 0x07, 0x04, 0xC3, 0x04,
0982         0x22, 0x10, 0x05, 0x03, 0x58, 0x02),
0983     PLL_CTL(3072000, 0x0B,
0984         0x22, 0x04, 0x07, 0x03, 0x48, 0x03,
0985         0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01),
0986     PLL_CTL(5644800, 0x15,
0987         0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04,
0988         0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01),
0989     PLL_CTL(6144000, 0x17,
0990         0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01,
0991         0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01),
0992     PLL_CTL(12000000, 0x2E,
0993         0x1B, 0x04, 0x19, 0x03, 0x00, 0x03,
0994         0x2A, 0x10, 0x19, 0x05, 0x98, 0x04),
0995     PLL_CTL(19200000, 0x4A,
0996         0x13, 0x04, 0x14, 0x03, 0x80, 0x01,
0997         0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01),
0998     PLL_CTL(22000000, 0x55,
0999         0x2A, 0x04, 0x37, 0x05, 0x00, 0x06,
1000         0x22, 0x10, 0x26, 0x03, 0x49, 0x02),
1001     PLL_CTL(22579200, 0x57,
1002         0x22, 0x04, 0x31, 0x03, 0x20, 0x03,
1003         0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01),
1004     PLL_CTL(24000000, 0x5D,
1005         0x13, 0x04, 0x19, 0x03, 0x80, 0x01,
1006         0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02),
1007     PLL_CTL(24576000, 0x5F,
1008         0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01,
1009         0x22, 0x10, 0x40, 0x03, 0x72, 0x03),
1010     PLL_CTL(27000000, 0x68,
1011         0x22, 0x04, 0x4B, 0x03, 0x00, 0x04,
1012         0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06),
1013     PLL_CTL(36000000, 0x8C,
1014         0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03,
1015         0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04),
1016     PLL_CTL(25000000, 0x61,
1017         0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03,
1018         0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02),
1019     PLL_CTL(26000000, 0x65,
1020         0x23, 0x04, 0x41, 0x05, 0x00, 0x06,
1021         0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01),
1022     PLL_CTL(12288000, 0x2F,
1023         0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02,
1024         0x22, 0x10, 0x20, 0x03, 0x72, 0x03),
1025     PLL_CTL(40000000, 0x9B,
1026         0x22, 0x08, 0x7D, 0x03, 0x80, 0x04,
1027         0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06),
1028     PLL_CTL(512000, 0x01,
1029         0x22, 0x04, 0x01, 0x03, 0xD0, 0x02,
1030         0x1B, 0x10, 0x01, 0x04, 0x72, 0x03),
1031     PLL_CTL(705600, 0x02,
1032         0x22, 0x04, 0x02, 0x03, 0x15, 0x04,
1033         0x22, 0x10, 0x01, 0x04, 0x80, 0x02),
1034     PLL_CTL(1024000, 0x03,
1035         0x22, 0x04, 0x02, 0x03, 0xD0, 0x02,
1036         0x1B, 0x10, 0x02, 0x04, 0x72, 0x03),
1037     PLL_CTL(2048000, 0x07,
1038         0x22, 0x04, 0x04, 0x03, 0xD0, 0x02,
1039         0x1B, 0x10, 0x04, 0x04, 0x72, 0x03),
1040     PLL_CTL(2400000, 0x08,
1041         0x22, 0x04, 0x05, 0x03, 0x00, 0x03,
1042         0x23, 0x10, 0x05, 0x05, 0x98, 0x04),
1043 };
1044 
1045 static const struct pll_ctl *get_pll_ctl(int input_freq)
1046 {
1047     int i;
1048     const struct pll_ctl *pll_ctl = NULL;
1049 
1050     for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
1051         if (input_freq == pll_ctls[i].input_freq) {
1052             pll_ctl = &pll_ctls[i];
1053             break;
1054         }
1055 
1056     return pll_ctl;
1057 }
1058 
1059 static int set_pll_ctl_from_input_freq(struct snd_soc_component *component,
1060         const int input_freq)
1061 {
1062     int ret;
1063     int i;
1064     const struct pll_ctl *pll_ctl;
1065 
1066     pll_ctl = get_pll_ctl(input_freq);
1067     if (!pll_ctl) {
1068         ret = -EINVAL;
1069         dev_err(component->dev, "No PLL input entry for %d (%d)\n",
1070             input_freq, ret);
1071         return ret;
1072     }
1073 
1074     for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
1075         ret = snd_soc_component_update_bits(component,
1076             pll_ctl->settings[i].addr,
1077             pll_ctl->settings[i].mask,
1078             pll_ctl->settings[i].val);
1079         if (ret < 0) {
1080             dev_err(component->dev, "Failed to set pll ctl (%d)\n",
1081                 ret);
1082             return ret;
1083         }
1084     }
1085 
1086     return 0;
1087 }
1088 
1089 static int tscs42xx_hw_params(struct snd_pcm_substream *substream,
1090         struct snd_pcm_hw_params *params,
1091         struct snd_soc_dai *codec_dai)
1092 {
1093     struct snd_soc_component *component = codec_dai->component;
1094     int ret;
1095 
1096     ret = setup_sample_format(component, params_format(params));
1097     if (ret < 0) {
1098         dev_err(component->dev, "Failed to setup sample format (%d)\n",
1099             ret);
1100         return ret;
1101     }
1102 
1103     ret = setup_sample_rate(component, params_rate(params));
1104     if (ret < 0) {
1105         dev_err(component->dev,
1106                 "Failed to setup sample rate (%d)\n", ret);
1107         return ret;
1108     }
1109 
1110     return 0;
1111 }
1112 
1113 static inline int dac_mute(struct snd_soc_component *component)
1114 {
1115     int ret;
1116 
1117     ret = snd_soc_component_update_bits(component,
1118             R_CNVRTR1, RM_CNVRTR1_DACMU,
1119         RV_CNVRTR1_DACMU_ENABLE);
1120     if (ret < 0) {
1121         dev_err(component->dev, "Failed to mute DAC (%d)\n",
1122                 ret);
1123         return ret;
1124     }
1125 
1126     return 0;
1127 }
1128 
1129 static inline int dac_unmute(struct snd_soc_component *component)
1130 {
1131     int ret;
1132 
1133     ret = snd_soc_component_update_bits(component,
1134             R_CNVRTR1, RM_CNVRTR1_DACMU,
1135         RV_CNVRTR1_DACMU_DISABLE);
1136     if (ret < 0) {
1137         dev_err(component->dev, "Failed to unmute DAC (%d)\n",
1138                 ret);
1139         return ret;
1140     }
1141 
1142     return 0;
1143 }
1144 
1145 static inline int adc_mute(struct snd_soc_component *component)
1146 {
1147     int ret;
1148 
1149     ret = snd_soc_component_update_bits(component,
1150             R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE);
1151     if (ret < 0) {
1152         dev_err(component->dev, "Failed to mute ADC (%d)\n",
1153                 ret);
1154         return ret;
1155     }
1156 
1157     return 0;
1158 }
1159 
1160 static inline int adc_unmute(struct snd_soc_component *component)
1161 {
1162     int ret;
1163 
1164     ret = snd_soc_component_update_bits(component,
1165             R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE);
1166     if (ret < 0) {
1167         dev_err(component->dev, "Failed to unmute ADC (%d)\n",
1168                 ret);
1169         return ret;
1170     }
1171 
1172     return 0;
1173 }
1174 
1175 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1176 {
1177     struct snd_soc_component *component = dai->component;
1178     int ret;
1179 
1180     if (mute)
1181         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1182             ret = dac_mute(component);
1183         else
1184             ret = adc_mute(component);
1185     else
1186         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1187             ret = dac_unmute(component);
1188         else
1189             ret = adc_unmute(component);
1190 
1191     return ret;
1192 }
1193 
1194 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
1195         unsigned int fmt)
1196 {
1197     struct snd_soc_component *component = codec_dai->component;
1198     int ret;
1199 
1200     /* Consumer mode not supported since it needs always-on frame clock */
1201     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1202     case SND_SOC_DAIFMT_CBP_CFP:
1203         ret = snd_soc_component_update_bits(component,
1204                 R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER);
1205         if (ret < 0) {
1206             dev_err(component->dev,
1207                 "Failed to set codec DAI master (%d)\n", ret);
1208             return ret;
1209         }
1210         break;
1211     default:
1212         ret = -EINVAL;
1213         dev_err(component->dev, "Unsupported format (%d)\n", ret);
1214         return ret;
1215     }
1216 
1217     return 0;
1218 }
1219 
1220 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai,
1221         unsigned int ratio)
1222 {
1223     struct snd_soc_component *component = codec_dai->component;
1224     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
1225     unsigned int value;
1226     int ret = 0;
1227 
1228     switch (ratio) {
1229     case 32:
1230         value = RV_DACSR_DBCM_32;
1231         break;
1232     case 40:
1233         value = RV_DACSR_DBCM_40;
1234         break;
1235     case 64:
1236         value = RV_DACSR_DBCM_64;
1237         break;
1238     default:
1239         dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
1240         return -EINVAL;
1241     }
1242 
1243     ret = snd_soc_component_update_bits(component,
1244             R_DACSR, RM_DACSR_DBCM, value);
1245     if (ret < 0) {
1246         dev_err(component->dev,
1247                 "Failed to set DAC BCLK ratio (%d)\n", ret);
1248         return ret;
1249     }
1250     ret = snd_soc_component_update_bits(component,
1251             R_ADCSR, RM_ADCSR_ABCM, value);
1252     if (ret < 0) {
1253         dev_err(component->dev,
1254                 "Failed to set ADC BCLK ratio (%d)\n", ret);
1255         return ret;
1256     }
1257 
1258     mutex_lock(&tscs42xx->audio_params_lock);
1259 
1260     tscs42xx->bclk_ratio = ratio;
1261 
1262     mutex_unlock(&tscs42xx->audio_params_lock);
1263 
1264     return 0;
1265 }
1266 
1267 static const struct snd_soc_dai_ops tscs42xx_dai_ops = {
1268     .hw_params  = tscs42xx_hw_params,
1269     .mute_stream    = tscs42xx_mute_stream,
1270     .set_fmt    = tscs42xx_set_dai_fmt,
1271     .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio,
1272 };
1273 
1274 static int part_is_valid(struct tscs42xx *tscs42xx)
1275 {
1276     int val;
1277     int ret;
1278     unsigned int reg;
1279 
1280     ret = regmap_read(tscs42xx->regmap, R_DEVIDH, &reg);
1281     if (ret < 0)
1282         return ret;
1283 
1284     val = reg << 8;
1285     ret = regmap_read(tscs42xx->regmap, R_DEVIDL, &reg);
1286     if (ret < 0)
1287         return ret;
1288 
1289     val |= reg;
1290 
1291     switch (val) {
1292     case 0x4A74:
1293     case 0x4A73:
1294         return true;
1295     default:
1296         return false;
1297     }
1298 }
1299 
1300 static int set_sysclk(struct snd_soc_component *component)
1301 {
1302     struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
1303     unsigned long freq;
1304     int ret;
1305 
1306     switch (tscs42xx->sysclk_src_id) {
1307     case TSCS42XX_PLL_SRC_XTAL:
1308     case TSCS42XX_PLL_SRC_MCLK1:
1309         ret = snd_soc_component_write(component, R_PLLREFSEL,
1310                 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 |
1311                 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1);
1312         if (ret < 0) {
1313             dev_err(component->dev,
1314                 "Failed to set pll reference input (%d)\n",
1315                 ret);
1316             return ret;
1317         }
1318         break;
1319     case TSCS42XX_PLL_SRC_MCLK2:
1320         ret = snd_soc_component_write(component, R_PLLREFSEL,
1321                 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 |
1322                 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2);
1323         if (ret < 0) {
1324             dev_err(component->dev,
1325                 "Failed to set PLL reference (%d)\n", ret);
1326             return ret;
1327         }
1328         break;
1329     default:
1330         dev_err(component->dev, "pll src is unsupported\n");
1331         return -EINVAL;
1332     }
1333 
1334     freq = clk_get_rate(tscs42xx->sysclk);
1335     ret = set_pll_ctl_from_input_freq(component, freq);
1336     if (ret < 0) {
1337         dev_err(component->dev,
1338             "Failed to setup PLL input freq (%d)\n", ret);
1339         return ret;
1340     }
1341 
1342     return 0;
1343 }
1344 
1345 static int tscs42xx_probe(struct snd_soc_component *component)
1346 {
1347     return set_sysclk(component);
1348 }
1349 
1350 static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = {
1351     .probe          = tscs42xx_probe,
1352     .dapm_widgets       = tscs42xx_dapm_widgets,
1353     .num_dapm_widgets   = ARRAY_SIZE(tscs42xx_dapm_widgets),
1354     .dapm_routes        = tscs42xx_intercon,
1355     .num_dapm_routes    = ARRAY_SIZE(tscs42xx_intercon),
1356     .controls       = tscs42xx_snd_controls,
1357     .num_controls       = ARRAY_SIZE(tscs42xx_snd_controls),
1358     .idle_bias_on       = 1,
1359     .use_pmdown_time    = 1,
1360     .endianness     = 1,
1361 };
1362 
1363 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx)
1364 {
1365     static const u8 norm_addrs[] = {
1366         0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a,
1367         0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59,
1368         0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85,
1369         0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0,
1370         0xb5, 0xba, 0xbf, 0xc4, 0xc9,
1371     };
1372     u8 *coeff_ram = tscs42xx->coeff_ram;
1373     int i;
1374 
1375     for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
1376         coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
1377 }
1378 
1379 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000
1380 
1381 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1382     | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1383 
1384 static struct snd_soc_dai_driver tscs42xx_dai = {
1385     .name = "tscs42xx-HiFi",
1386     .playback = {
1387         .stream_name = "HiFi Playback",
1388         .channels_min = 2,
1389         .channels_max = 2,
1390         .rates = TSCS42XX_RATES,
1391         .formats = TSCS42XX_FORMATS,},
1392     .capture = {
1393         .stream_name = "HiFi Capture",
1394         .channels_min = 2,
1395         .channels_max = 2,
1396         .rates = TSCS42XX_RATES,
1397         .formats = TSCS42XX_FORMATS,},
1398     .ops = &tscs42xx_dai_ops,
1399     .symmetric_rate = 1,
1400     .symmetric_channels = 1,
1401     .symmetric_sample_bits = 1,
1402 };
1403 
1404 static const struct reg_sequence tscs42xx_patch[] = {
1405     { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED },
1406 };
1407 
1408 static char const * const src_names[TSCS42XX_PLL_SRC_CNT] = {
1409     "xtal", "mclk1", "mclk2"};
1410 
1411 static int tscs42xx_i2c_probe(struct i2c_client *i2c)
1412 {
1413     struct tscs42xx *tscs42xx;
1414     int src;
1415     int ret;
1416 
1417     tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL);
1418     if (!tscs42xx) {
1419         ret = -ENOMEM;
1420         dev_err(&i2c->dev,
1421             "Failed to allocate memory for data (%d)\n", ret);
1422         return ret;
1423     }
1424     i2c_set_clientdata(i2c, tscs42xx);
1425 
1426     for (src = TSCS42XX_PLL_SRC_XTAL; src < TSCS42XX_PLL_SRC_CNT; src++) {
1427         tscs42xx->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
1428         if (!IS_ERR(tscs42xx->sysclk)) {
1429             break;
1430         } else if (PTR_ERR(tscs42xx->sysclk) != -ENOENT) {
1431             ret = PTR_ERR(tscs42xx->sysclk);
1432             dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
1433             return ret;
1434         }
1435     }
1436     if (src == TSCS42XX_PLL_SRC_CNT) {
1437         ret = -EINVAL;
1438         dev_err(&i2c->dev, "Failed to get a valid clock name (%d)\n",
1439                 ret);
1440         return ret;
1441     }
1442     tscs42xx->sysclk_src_id = src;
1443 
1444     tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap);
1445     if (IS_ERR(tscs42xx->regmap)) {
1446         ret = PTR_ERR(tscs42xx->regmap);
1447         dev_err(&i2c->dev, "Failed to allocate regmap (%d)\n", ret);
1448         return ret;
1449     }
1450 
1451     init_coeff_ram_cache(tscs42xx);
1452 
1453     ret = part_is_valid(tscs42xx);
1454     if (ret <= 0) {
1455         dev_err(&i2c->dev, "No valid part (%d)\n", ret);
1456         ret = -ENODEV;
1457         return ret;
1458     }
1459 
1460     ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE);
1461     if (ret < 0) {
1462         dev_err(&i2c->dev, "Failed to reset device (%d)\n", ret);
1463         return ret;
1464     }
1465 
1466     ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch,
1467             ARRAY_SIZE(tscs42xx_patch));
1468     if (ret < 0) {
1469         dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
1470         return ret;
1471     }
1472 
1473     mutex_init(&tscs42xx->audio_params_lock);
1474     mutex_init(&tscs42xx->coeff_ram_lock);
1475     mutex_init(&tscs42xx->pll_lock);
1476 
1477     ret = devm_snd_soc_register_component(&i2c->dev,
1478             &soc_codec_dev_tscs42xx, &tscs42xx_dai, 1);
1479     if (ret) {
1480         dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
1481         return ret;
1482     }
1483 
1484     return 0;
1485 }
1486 
1487 static const struct i2c_device_id tscs42xx_i2c_id[] = {
1488     { "tscs42A1", 0 },
1489     { "tscs42A2", 0 },
1490     { }
1491 };
1492 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id);
1493 
1494 static const struct of_device_id tscs42xx_of_match[] = {
1495     { .compatible = "tempo,tscs42A1", },
1496     { .compatible = "tempo,tscs42A2", },
1497     { }
1498 };
1499 MODULE_DEVICE_TABLE(of, tscs42xx_of_match);
1500 
1501 static struct i2c_driver tscs42xx_i2c_driver = {
1502     .driver = {
1503         .name = "tscs42xx",
1504         .of_match_table = tscs42xx_of_match,
1505     },
1506     .probe_new = tscs42xx_i2c_probe,
1507     .id_table = tscs42xx_i2c_id,
1508 };
1509 
1510 module_i2c_driver(tscs42xx_i2c_driver);
1511 
1512 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
1513 MODULE_DESCRIPTION("ASoC TSCS42xx driver");
1514 MODULE_LICENSE("GPL");
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