soc/codecs/tlv320dac33.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
0004  *
0005  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0006  *
0007  * Copyright:   (C) 2009 Nokia Corporation
0008  */
0009
0010 #ifndef __TLV320DAC33_H
0011 #define __TLV320DAC33_H
0012
0013 #define DAC33_PAGE_SELECT       0x00
0014 #define DAC33_PWR_CTRL          0x01
0015 #define DAC33_PLL_CTRL_A        0x02
0016 #define DAC33_PLL_CTRL_B        0x03
0017 #define DAC33_PLL_CTRL_C        0x04
0018 #define DAC33_PLL_CTRL_D        0x05
0019 #define DAC33_PLL_CTRL_E        0x06
0020 #define DAC33_INT_OSC_CTRL      0x07
0021 #define DAC33_INT_OSC_FREQ_RAT_A    0x08
0022 #define DAC33_INT_OSC_FREQ_RAT_B    0x09
0023 #define DAC33_INT_OSC_DAC_RATIO_SET 0x0A
0024 #define DAC33_CALIB_TIME        0x0B
0025 #define DAC33_INT_OSC_CTRL_B        0x0C
0026 #define DAC33_INT_OSC_CTRL_C        0x0D
0027 #define DAC33_INT_OSC_STATUS        0x0E
0028 #define DAC33_INT_OSC_DAC_RATIO_READ    0x0F
0029 #define DAC33_INT_OSC_FREQ_RAT_READ_A   0x10
0030 #define DAC33_INT_OSC_FREQ_RAT_READ_B   0x11
0031 #define DAC33_SER_AUDIOIF_CTRL_A    0x12
0032 #define DAC33_SER_AUDIOIF_CTRL_B    0x13
0033 #define DAC33_SER_AUDIOIF_CTRL_C    0x14
0034 #define DAC33_FIFO_CTRL_A       0x15
0035 #define DAC33_UTHR_MSB          0x16
0036 #define DAC33_UTHR_LSB          0x17
0037 #define DAC33_ATHR_MSB          0x18
0038 #define DAC33_ATHR_LSB          0x19
0039 #define DAC33_LTHR_MSB          0x1A
0040 #define DAC33_LTHR_LSB          0x1B
0041 #define DAC33_PREFILL_MSB       0x1C
0042 #define DAC33_PREFILL_LSB       0x1D
0043 #define DAC33_NSAMPLE_MSB       0x1E
0044 #define DAC33_NSAMPLE_LSB       0x1F
0045 #define DAC33_FIFO_WPTR_MSB     0x20
0046 #define DAC33_FIFO_WPTR_LSB     0x21
0047 #define DAC33_FIFO_RPTR_MSB     0x22
0048 #define DAC33_FIFO_RPTR_LSB     0x23
0049 #define DAC33_FIFO_DEPTH_MSB        0x24
0050 #define DAC33_FIFO_DEPTH_LSB        0x25
0051 #define DAC33_SAMPLES_REMAINING_MSB 0x26
0052 #define DAC33_SAMPLES_REMAINING_LSB 0x27
0053 #define DAC33_FIFO_IRQ_FLAG     0x28
0054 #define DAC33_FIFO_IRQ_MASK     0x29
0055 #define DAC33_FIFO_IRQ_MODE_A       0x2A
0056 #define DAC33_FIFO_IRQ_MODE_B       0x2B
0057 #define DAC33_DAC_CTRL_A        0x2C
0058 #define DAC33_DAC_CTRL_B        0x2D
0059 #define DAC33_DAC_CTRL_C        0x2E
0060 #define DAC33_LDAC_DIG_VOL_CTRL     0x2F
0061 #define DAC33_RDAC_DIG_VOL_CTRL     0x30
0062 #define DAC33_DAC_STATUS_FLAGS      0x31
0063 #define DAC33_ASRC_CTRL_A       0x32
0064 #define DAC33_ASRC_CTRL_B       0x33
0065 #define DAC33_SRC_REF_CLK_RATIO_A   0x34
0066 #define DAC33_SRC_REF_CLK_RATIO_B   0x35
0067 #define DAC33_SRC_EST_REF_CLK_RATIO_A   0x36
0068 #define DAC33_SRC_EST_REF_CLK_RATIO_B   0x37
0069 #define DAC33_INTP_CTRL_A       0x38
0070 #define DAC33_INTP_CTRL_B       0x39
0071 /* Registers 0x3A - 0x3F Reserved */
0072 #define DAC33_LDAC_PWR_CTRL     0x40
0073 #define DAC33_RDAC_PWR_CTRL     0x41
0074 #define DAC33_OUT_AMP_CM_CTRL       0x42
0075 #define DAC33_OUT_AMP_PWR_CTRL      0x43
0076 #define DAC33_OUT_AMP_CTRL      0x44
0077 #define DAC33_LINEL_TO_LLO_VOL      0x45
0078 /* Registers 0x45 - 0x47 Reserved */
0079 #define DAC33_LINER_TO_RLO_VOL      0x48
0080 #define DAC33_ANA_VOL_SOFT_STEP_CTRL    0x49
0081 #define DAC33_OSC_TRIM          0x4A
0082 /* Registers 0x4B - 0x7C Reserved */
0083 #define DAC33_DEVICE_ID_MSB     0x7D
0084 #define DAC33_DEVICE_ID_LSB     0x7E
0085 #define DAC33_DEVICE_REV_ID     0x7F
0086
0087 #define DAC33_CACHEREGNUM               128
0088
0089 /* Bit definitions */
0090
0091 /* DAC33_PWR_CTRL (0x01) */
0092 #define DAC33_DACRPDNB          (0x01 << 0)
0093 #define DAC33_DACLPDNB          (0x01 << 1)
0094 #define DAC33_OSCPDNB           (0x01 << 2)
0095 #define DAC33_PLLPDNB           (0x01 << 3)
0096 #define DAC33_PDNALLB           (0x01 << 4)
0097 #define DAC33_SOFT_RESET        (0x01 << 7)
0098
0099 /* DAC33_INT_OSC_CTRL (0x07) */
0100 #define DAC33_REFSEL            (0x01 << 1)
0101
0102 /* DAC33_INT_OSC_CTRL_B (0x0C) */
0103 #define DAC33_ADJSTEP(x)        (x << 0)
0104 #define DAC33_ADJTHRSHLD(x)     (x << 4)
0105
0106 /* DAC33_INT_OSC_CTRL_C (0x0D) */
0107 #define DAC33_REFDIV(x)         (x << 4)
0108
0109 /* DAC33_INT_OSC_STATUS (0x0E) */
0110 #define DAC33_OSCSTATUS_IDLE_CALIB  (0x00)
0111 #define DAC33_OSCSTATUS_NORMAL      (0x01)
0112 #define DAC33_OSCSTATUS_ADJUSTMENT  (0x03)
0113 #define DAC33_OSCSTATUS_NOT_USED    (0x02)
0114
0115 /* DAC33_SER_AUDIOIF_CTRL_A (0x12) */
0116 #define DAC33_MSWCLK            (0x01 << 0)
0117 #define DAC33_MSBCLK            (0x01 << 1)
0118 #define DAC33_AFMT_MASK         (0x03 << 2)
0119 #define DAC33_AFMT_I2S          (0x00 << 2)
0120 #define DAC33_AFMT_DSP          (0x01 << 2)
0121 #define DAC33_AFMT_RIGHT_J      (0x02 << 2)
0122 #define DAC33_AFMT_LEFT_J       (0x03 << 2)
0123 #define DAC33_WLEN_MASK         (0x03 << 4)
0124 #define DAC33_WLEN_16           (0x00 << 4)
0125 #define DAC33_WLEN_20           (0x01 << 4)
0126 #define DAC33_WLEN_24           (0x02 << 4)
0127 #define DAC33_WLEN_32           (0x03 << 4)
0128 #define DAC33_NCYCL_MASK        (0x03 << 6)
0129 #define DAC33_NCYCL_16          (0x00 << 6)
0130 #define DAC33_NCYCL_20          (0x01 << 6)
0131 #define DAC33_NCYCL_24          (0x02 << 6)
0132 #define DAC33_NCYCL_32          (0x03 << 6)
0133
0134 /* DAC33_SER_AUDIOIF_CTRL_B (0x13) */
0135 #define DAC33_DATA_DELAY_MASK       (0x03 << 2)
0136 #define DAC33_DATA_DELAY(x)     (x << 2)
0137 #define DAC33_BCLKON            (0x01 << 5)
0138
0139 /* DAC33_FIFO_CTRL_A (0x15) */
0140 #define DAC33_WIDTH             (0x01 << 0)
0141 #define DAC33_FBYPAS                (0x01 << 1)
0142 #define DAC33_FAUTO             (0x01 << 2)
0143 #define DAC33_FIFOFLUSH         (0x01 << 3)
0144
0145 /*
0146  * UTHR, ATHR, LTHR, PREFILL, NSAMPLE (0x16 - 0x1F)
0147  * 13-bit values
0148 */
0149 #define DAC33_THRREG(x)         (((x) & 0x1FFF) << 3)
0150
0151 /* DAC33_FIFO_IRQ_MASK (0x29) */
0152 #define DAC33_MNS           (0x01 << 0)
0153 #define DAC33_MPS           (0x01 << 1)
0154 #define DAC33_MAT           (0x01 << 2)
0155 #define DAC33_MLT           (0x01 << 3)
0156 #define DAC33_MUT           (0x01 << 4)
0157 #define DAC33_MUF           (0x01 << 5)
0158 #define DAC33_MOF           (0x01 << 6)
0159
0160 #define DAC33_FIFO_IRQ_MODE_MASK    (0x03)
0161 #define DAC33_FIFO_IRQ_MODE_RISING  (0x00)
0162 #define DAC33_FIFO_IRQ_MODE_FALLING (0x01)
0163 #define DAC33_FIFO_IRQ_MODE_LEVEL   (0x02)
0164 #define DAC33_FIFO_IRQ_MODE_EDGE    (0x03)
0165
0166 /* DAC33_FIFO_IRQ_MODE_A (0x2A) */
0167 #define DAC33_UTM(x)            (x << 0)
0168 #define DAC33_UFM(x)            (x << 2)
0169 #define DAC33_OFM(x)            (x << 4)
0170
0171 /* DAC33_FIFO_IRQ_MODE_B (0x2B) */
0172 #define DAC33_NSM(x)            (x << 0)
0173 #define DAC33_PSM(x)            (x << 2)
0174 #define DAC33_ATM(x)            (x << 4)
0175 #define DAC33_LTM(x)            (x << 6)
0176
0177 /* DAC33_DAC_CTRL_A (0x2C) */
0178 #define DAC33_DACRATE(x)        (x << 0)
0179 #define DAC33_DACDUAL           (0x01 << 4)
0180 #define DAC33_DACLKSEL_MASK     (0x03 << 5)
0181 #define DAC33_DACLKSEL_INTSOC       (0x00 << 5)
0182 #define DAC33_DACLKSEL_PLL      (0x01 << 5)
0183 #define DAC33_DACLKSEL_MCLK     (0x02 << 5)
0184 #define DAC33_DACLKSEL_BCLK     (0x03 << 5)
0185
0186 /* DAC33_DAC_CTRL_B (0x2D) */
0187 #define DAC33_DACSRCR_MASK      (0x03 << 0)
0188 #define DAC33_DACSRCR_MUTE      (0x00 << 0)
0189 #define DAC33_DACSRCR_RIGHT     (0x01 << 0)
0190 #define DAC33_DACSRCR_LEFT      (0x02 << 0)
0191 #define DAC33_DACSRCR_MONOMIX       (0x03 << 0)
0192 #define DAC33_DACSRCL_MASK      (0x03 << 2)
0193 #define DAC33_DACSRCL_MUTE      (0x00 << 2)
0194 #define DAC33_DACSRCL_LEFT      (0x01 << 2)
0195 #define DAC33_DACSRCL_RIGHT     (0x02 << 2)
0196 #define DAC33_DACSRCL_MONOMIX       (0x03 << 2)
0197 #define DAC33_DVOLSTEP_MASK     (0x03 << 4)
0198 #define DAC33_DVOLSTEP_SS_PERFS     (0x00 << 4)
0199 #define DAC33_DVOLSTEP_SS_PER2FS    (0x01 << 4)
0200 #define DAC33_DVOLSTEP_SS_DISABLED  (0x02 << 4)
0201 #define DAC33_DVOLCTRL_MASK     (0x03 << 6)
0202 #define DAC33_DVOLCTRL_LR_INDEPENDENT1  (0x00 << 6)
0203 #define DAC33_DVOLCTRL_LR_RIGHT_CONTROL (0x01 << 6)
0204 #define DAC33_DVOLCTRL_LR_LEFT_CONTROL  (0x02 << 6)
0205 #define DAC33_DVOLCTRL_LR_INDEPENDENT2  (0x03 << 6)
0206
0207 /* DAC33_DAC_CTRL_C (0x2E) */
0208 #define DAC33_DEEMENR           (0x01 << 0)
0209 #define DAC33_EFFENR            (0x01 << 1)
0210 #define DAC33_DEEMENL           (0x01 << 2)
0211 #define DAC33_EFFENL            (0x01 << 3)
0212 #define DAC33_EN3D          (0x01 << 4)
0213 #define DAC33_RESYNMUTE         (0x01 << 5)
0214 #define DAC33_RESYNEN           (0x01 << 6)
0215
0216 /* DAC33_ASRC_CTRL_A (0x32) */
0217 #define DAC33_SRCBYP            (0x01 << 0)
0218 #define DAC33_SRCLKSEL_MASK     (0x03 << 1)
0219 #define DAC33_SRCLKSEL_INTSOC       (0x00 << 1)
0220 #define DAC33_SRCLKSEL_PLL      (0x01 << 1)
0221 #define DAC33_SRCLKSEL_MCLK     (0x02 << 1)
0222 #define DAC33_SRCLKSEL_BCLK     (0x03 << 1)
0223 #define DAC33_SRCLKDIV(x)       (x << 3)
0224
0225 /* DAC33_ASRC_CTRL_B (0x33) */
0226 #define DAC33_SRCSETUP(x)       (x << 0)
0227 #define DAC33_SRCREFSEL         (0x01 << 4)
0228 #define DAC33_SRCREFDIV(x)      (x << 5)
0229
0230 /* DAC33_INTP_CTRL_A (0x38) */
0231 #define DAC33_INTPSEL           (0x01 << 0)
0232 #define DAC33_INTPM_MASK        (0x03 << 1)
0233 #define DAC33_INTPM_ALOW_OPENDRAIN  (0x00 << 1)
0234 #define DAC33_INTPM_ALOW        (0x01 << 1)
0235 #define DAC33_INTPM_AHIGH       (0x02 << 1)
0236
0237 /* DAC33_LDAC_PWR_CTRL (0x40) */
0238 /* DAC33_RDAC_PWR_CTRL (0x41) */
0239 #define DAC33_DACLRNUM          (0x01 << 2)
0240 #define DAC33_LROUT_GAIN(x)     (x << 0)
0241
0242 /* DAC33_ANA_VOL_SOFT_STEP_CTRL (0x49) */
0243 #define DAC33_VOLCLKSEL         (0x01 << 0)
0244 #define DAC33_VOLCLKEN          (0x01 << 1)
0245 #define DAC33_VOLBYPASS         (0x01 << 2)
0246
0247 #define TLV320DAC33_MCLK        0
0248 #define TLV320DAC33_SLEEPCLK        1
0249
0250 #endif /* __TLV320DAC33_H */