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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
0004  *
0005  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0006  *
0007  * Copyright:   (C) 2009 Nokia Corporation
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/delay.h>
0014 #include <linux/pm.h>
0015 #include <linux/i2c.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/gpio.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/slab.h>
0020 #include <sound/core.h>
0021 #include <sound/pcm.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include <sound/initval.h>
0025 #include <sound/tlv.h>
0026 
0027 #include <sound/tlv320dac33-plat.h>
0028 #include "tlv320dac33.h"
0029 
0030 /*
0031  * The internal FIFO is 24576 bytes long
0032  * It can be configured to hold 16bit or 24bit samples
0033  * In 16bit configuration the FIFO can hold 6144 stereo samples
0034  * In 24bit configuration the FIFO can hold 4096 stereo samples
0035  */
0036 #define DAC33_FIFO_SIZE_16BIT   6144
0037 #define DAC33_FIFO_SIZE_24BIT   4096
0038 #define DAC33_MODE7_MARGIN  10  /* Safety margin for FIFO in Mode7 */
0039 
0040 #define BURST_BASEFREQ_HZ   49152000
0041 
0042 #define SAMPLES_TO_US(rate, samples) \
0043     (1000000000 / (((rate) * 1000) / (samples)))
0044 
0045 #define US_TO_SAMPLES(rate, us) \
0046     ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
0047 
0048 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
0049     (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
0050 
0051 static void dac33_calculate_times(struct snd_pcm_substream *substream,
0052                   struct snd_soc_component *component);
0053 static int dac33_prepare_chip(struct snd_pcm_substream *substream,
0054                   struct snd_soc_component *component);
0055 
0056 enum dac33_state {
0057     DAC33_IDLE = 0,
0058     DAC33_PREFILL,
0059     DAC33_PLAYBACK,
0060     DAC33_FLUSH,
0061 };
0062 
0063 enum dac33_fifo_modes {
0064     DAC33_FIFO_BYPASS = 0,
0065     DAC33_FIFO_MODE1,
0066     DAC33_FIFO_MODE7,
0067     DAC33_FIFO_LAST_MODE,
0068 };
0069 
0070 #define DAC33_NUM_SUPPLIES 3
0071 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
0072     "AVDD",
0073     "DVDD",
0074     "IOVDD",
0075 };
0076 
0077 struct tlv320dac33_priv {
0078     struct mutex mutex;
0079     struct work_struct work;
0080     struct snd_soc_component *component;
0081     struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
0082     struct snd_pcm_substream *substream;
0083     int power_gpio;
0084     int chip_power;
0085     int irq;
0086     unsigned int refclk;
0087 
0088     unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
0089     enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
0090     unsigned int fifo_size;     /* Size of the FIFO in samples */
0091     unsigned int nsample;       /* burst read amount from host */
0092     int mode1_latency;      /* latency caused by the i2c writes in
0093                      * us */
0094     u8 burst_bclkdiv;       /* BCLK divider value in burst mode */
0095     u8 *reg_cache;
0096     unsigned int burst_rate;    /* Interface speed in Burst modes */
0097 
0098     int keep_bclk;          /* Keep the BCLK continuously running
0099                      * in FIFO modes */
0100     spinlock_t lock;
0101     unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
0102     unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
0103 
0104     unsigned int mode1_us_burst;    /* Time to burst read n number of
0105                      * samples */
0106     unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
0107 
0108     unsigned int uthr;
0109 
0110     enum dac33_state state;
0111     struct i2c_client *i2c;
0112 };
0113 
0114 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
0115 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
0116 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
0117 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
0118 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
0119 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
0120 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
0121 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
0122 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
0123 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
0124 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
0125 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
0126 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
0127 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
0128 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
0129 0x00, 0x00,             /* 0x38 - 0x39 */
0130 /* Registers 0x3a - 0x3f are reserved  */
0131             0x00, 0x00, /* 0x3a - 0x3b */
0132 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
0133 
0134 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
0135 0x00, 0x80,             /* 0x44 - 0x45 */
0136 /* Registers 0x46 - 0x47 are reserved  */
0137             0x80, 0x80, /* 0x46 - 0x47 */
0138 
0139 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
0140 /* Registers 0x4b - 0x7c are reserved  */
0141                   0x00, /* 0x4b        */
0142 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
0143 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
0144 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
0145 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
0146 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
0147 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
0148 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
0149 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
0150 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
0151 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
0152 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
0153 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
0154 0x00,                   /* 0x7c        */
0155 
0156       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
0157 };
0158 
0159 /* Register read and write */
0160 static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component,
0161                         unsigned reg)
0162 {
0163     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0164     u8 *cache = dac33->reg_cache;
0165     if (reg >= DAC33_CACHEREGNUM)
0166         return 0;
0167 
0168     return cache[reg];
0169 }
0170 
0171 static inline void dac33_write_reg_cache(struct snd_soc_component *component,
0172                      u8 reg, u8 value)
0173 {
0174     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0175     u8 *cache = dac33->reg_cache;
0176     if (reg >= DAC33_CACHEREGNUM)
0177         return;
0178 
0179     cache[reg] = value;
0180 }
0181 
0182 static int dac33_read(struct snd_soc_component *component, unsigned int reg,
0183               u8 *value)
0184 {
0185     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0186     int val, ret = 0;
0187 
0188     *value = reg & 0xff;
0189 
0190     /* If powered off, return the cached value */
0191     if (dac33->chip_power) {
0192         val = i2c_smbus_read_byte_data(dac33->i2c, value[0]);
0193         if (val < 0) {
0194             dev_err(component->dev, "Read failed (%d)\n", val);
0195             value[0] = dac33_read_reg_cache(component, reg);
0196             ret = val;
0197         } else {
0198             value[0] = val;
0199             dac33_write_reg_cache(component, reg, val);
0200         }
0201     } else {
0202         value[0] = dac33_read_reg_cache(component, reg);
0203     }
0204 
0205     return ret;
0206 }
0207 
0208 static int dac33_write(struct snd_soc_component *component, unsigned int reg,
0209                unsigned int value)
0210 {
0211     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0212     u8 data[2];
0213     int ret = 0;
0214 
0215     /*
0216      * data is
0217      *   D15..D8 dac33 register offset
0218      *   D7...D0 register data
0219      */
0220     data[0] = reg & 0xff;
0221     data[1] = value & 0xff;
0222 
0223     dac33_write_reg_cache(component, data[0], data[1]);
0224     if (dac33->chip_power) {
0225         ret = i2c_master_send(dac33->i2c, data, 2);
0226         if (ret != 2)
0227             dev_err(component->dev, "Write failed (%d)\n", ret);
0228         else
0229             ret = 0;
0230     }
0231 
0232     return ret;
0233 }
0234 
0235 static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg,
0236                   unsigned int value)
0237 {
0238     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0239     int ret;
0240 
0241     mutex_lock(&dac33->mutex);
0242     ret = dac33_write(component, reg, value);
0243     mutex_unlock(&dac33->mutex);
0244 
0245     return ret;
0246 }
0247 
0248 #define DAC33_I2C_ADDR_AUTOINC  0x80
0249 static int dac33_write16(struct snd_soc_component *component, unsigned int reg,
0250                unsigned int value)
0251 {
0252     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0253     u8 data[3];
0254     int ret = 0;
0255 
0256     /*
0257      * data is
0258      *   D23..D16 dac33 register offset
0259      *   D15..D8  register data MSB
0260      *   D7...D0  register data LSB
0261      */
0262     data[0] = reg & 0xff;
0263     data[1] = (value >> 8) & 0xff;
0264     data[2] = value & 0xff;
0265 
0266     dac33_write_reg_cache(component, data[0], data[1]);
0267     dac33_write_reg_cache(component, data[0] + 1, data[2]);
0268 
0269     if (dac33->chip_power) {
0270         /* We need to set autoincrement mode for 16 bit writes */
0271         data[0] |= DAC33_I2C_ADDR_AUTOINC;
0272         ret = i2c_master_send(dac33->i2c, data, 3);
0273         if (ret != 3)
0274             dev_err(component->dev, "Write failed (%d)\n", ret);
0275         else
0276             ret = 0;
0277     }
0278 
0279     return ret;
0280 }
0281 
0282 static void dac33_init_chip(struct snd_soc_component *component)
0283 {
0284     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0285 
0286     if (unlikely(!dac33->chip_power))
0287         return;
0288 
0289     /* A : DAC sample rate Fsref/1.5 */
0290     dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
0291     /* B : DAC src=normal, not muted */
0292     dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
0293                          DAC33_DACSRCL_LEFT);
0294     /* C : (defaults) */
0295     dac33_write(component, DAC33_DAC_CTRL_C, 0x00);
0296 
0297     /* 73 : volume soft stepping control,
0298      clock source = internal osc (?) */
0299     dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
0300 
0301     /* Restore only selected registers (gains mostly) */
0302     dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL,
0303             dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL));
0304     dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL,
0305             dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL));
0306 
0307     dac33_write(component, DAC33_LINEL_TO_LLO_VOL,
0308             dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL));
0309     dac33_write(component, DAC33_LINER_TO_RLO_VOL,
0310             dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL));
0311 
0312     dac33_write(component, DAC33_OUT_AMP_CTRL,
0313             dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL));
0314 
0315     dac33_write(component, DAC33_LDAC_PWR_CTRL,
0316             dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL));
0317     dac33_write(component, DAC33_RDAC_PWR_CTRL,
0318             dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL));
0319 }
0320 
0321 static inline int dac33_read_id(struct snd_soc_component *component)
0322 {
0323     int i, ret = 0;
0324     u8 reg;
0325 
0326     for (i = 0; i < 3; i++) {
0327         ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, &reg);
0328         if (ret < 0)
0329             break;
0330     }
0331 
0332     return ret;
0333 }
0334 
0335 static inline void dac33_soft_power(struct snd_soc_component *component, int power)
0336 {
0337     u8 reg;
0338 
0339     reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
0340     if (power)
0341         reg |= DAC33_PDNALLB;
0342     else
0343         reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
0344              DAC33_DACRPDNB | DAC33_DACLPDNB);
0345     dac33_write(component, DAC33_PWR_CTRL, reg);
0346 }
0347 
0348 static inline void dac33_disable_digital(struct snd_soc_component *component)
0349 {
0350     u8 reg;
0351 
0352     /* Stop the DAI clock */
0353     reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
0354     reg &= ~DAC33_BCLKON;
0355     dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg);
0356 
0357     /* Power down the Oscillator, and DACs */
0358     reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
0359     reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
0360     dac33_write(component, DAC33_PWR_CTRL, reg);
0361 }
0362 
0363 static int dac33_hard_power(struct snd_soc_component *component, int power)
0364 {
0365     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0366     int ret = 0;
0367 
0368     mutex_lock(&dac33->mutex);
0369 
0370     /* Safety check */
0371     if (unlikely(power == dac33->chip_power)) {
0372         dev_dbg(component->dev, "Trying to set the same power state: %s\n",
0373             power ? "ON" : "OFF");
0374         goto exit;
0375     }
0376 
0377     if (power) {
0378         ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
0379                       dac33->supplies);
0380         if (ret != 0) {
0381             dev_err(component->dev,
0382                 "Failed to enable supplies: %d\n", ret);
0383             goto exit;
0384         }
0385 
0386         if (dac33->power_gpio >= 0)
0387             gpio_set_value(dac33->power_gpio, 1);
0388 
0389         dac33->chip_power = 1;
0390     } else {
0391         dac33_soft_power(component, 0);
0392         if (dac33->power_gpio >= 0)
0393             gpio_set_value(dac33->power_gpio, 0);
0394 
0395         ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
0396                          dac33->supplies);
0397         if (ret != 0) {
0398             dev_err(component->dev,
0399                 "Failed to disable supplies: %d\n", ret);
0400             goto exit;
0401         }
0402 
0403         dac33->chip_power = 0;
0404     }
0405 
0406 exit:
0407     mutex_unlock(&dac33->mutex);
0408     return ret;
0409 }
0410 
0411 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
0412         struct snd_kcontrol *kcontrol, int event)
0413 {
0414     struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
0415     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0416 
0417     switch (event) {
0418     case SND_SOC_DAPM_PRE_PMU:
0419         if (likely(dac33->substream)) {
0420             dac33_calculate_times(dac33->substream, component);
0421             dac33_prepare_chip(dac33->substream, component);
0422         }
0423         break;
0424     case SND_SOC_DAPM_POST_PMD:
0425         dac33_disable_digital(component);
0426         break;
0427     }
0428     return 0;
0429 }
0430 
0431 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
0432              struct snd_ctl_elem_value *ucontrol)
0433 {
0434     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0435     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0436 
0437     ucontrol->value.enumerated.item[0] = dac33->fifo_mode;
0438 
0439     return 0;
0440 }
0441 
0442 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
0443              struct snd_ctl_elem_value *ucontrol)
0444 {
0445     struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
0446     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0447     int ret = 0;
0448 
0449     if (dac33->fifo_mode == ucontrol->value.enumerated.item[0])
0450         return 0;
0451     /* Do not allow changes while stream is running*/
0452     if (snd_soc_component_active(component))
0453         return -EPERM;
0454 
0455     if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE)
0456         ret = -EINVAL;
0457     else
0458         dac33->fifo_mode = ucontrol->value.enumerated.item[0];
0459 
0460     return ret;
0461 }
0462 
0463 /* Codec operation modes */
0464 static const char *dac33_fifo_mode_texts[] = {
0465     "Bypass", "Mode 1", "Mode 7"
0466 };
0467 
0468 static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts);
0469 
0470 /* L/R Line Output Gain */
0471 static const char *lr_lineout_gain_texts[] = {
0472     "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
0473     "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
0474 };
0475 
0476 static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum,
0477                 DAC33_LDAC_PWR_CTRL, 0,
0478                 lr_lineout_gain_texts);
0479 
0480 static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum,
0481                 DAC33_RDAC_PWR_CTRL, 0,
0482                 lr_lineout_gain_texts);
0483 
0484 /*
0485  * DACL/R digital volume control:
0486  * from 0 dB to -63.5 in 0.5 dB steps
0487  * Need to be inverted later on:
0488  * 0x00 == 0 dB
0489  * 0x7f == -63.5 dB
0490  */
0491 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
0492 
0493 static const struct snd_kcontrol_new dac33_snd_controls[] = {
0494     SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
0495         DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
0496         0, 0x7f, 1, dac_digivol_tlv),
0497     SOC_DOUBLE_R("DAC Digital Playback Switch",
0498          DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
0499     SOC_DOUBLE_R("Line to Line Out Volume",
0500          DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
0501     SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
0502     SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
0503 };
0504 
0505 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
0506     SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
0507          dac33_get_fifo_mode, dac33_set_fifo_mode),
0508 };
0509 
0510 /* Analog bypass */
0511 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
0512     SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
0513 
0514 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
0515     SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
0516 
0517 /* LOP L/R invert selection */
0518 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
0519 
0520 static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum,
0521                 DAC33_OUT_AMP_CTRL, 3,
0522                 dac33_lr_lom_texts);
0523 
0524 static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
0525 SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
0526 
0527 static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum,
0528                 DAC33_OUT_AMP_CTRL, 2,
0529                 dac33_lr_lom_texts);
0530 
0531 static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
0532 SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
0533 
0534 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
0535     SND_SOC_DAPM_OUTPUT("LEFT_LO"),
0536     SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
0537 
0538     SND_SOC_DAPM_INPUT("LINEL"),
0539     SND_SOC_DAPM_INPUT("LINER"),
0540 
0541     SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
0542     SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
0543 
0544     /* Analog bypass */
0545     SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
0546                 &dac33_dapm_abypassl_control),
0547     SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
0548                 &dac33_dapm_abypassr_control),
0549 
0550     SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
0551         &dac33_dapm_left_lom_control),
0552     SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
0553         &dac33_dapm_right_lom_control),
0554     /*
0555      * For DAPM path, when only the anlog bypass path is enabled, and the
0556      * LOP inverted from the corresponding DAC side.
0557      * This is needed, so we can attach the DAC power supply in this case.
0558      */
0559     SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
0560     SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
0561 
0562     SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
0563              DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
0564     SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
0565              DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
0566 
0567     SND_SOC_DAPM_SUPPLY("Left DAC Power",
0568                 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
0569     SND_SOC_DAPM_SUPPLY("Right DAC Power",
0570                 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
0571 
0572     SND_SOC_DAPM_SUPPLY("Codec Power",
0573                 DAC33_PWR_CTRL, 4, 0, NULL, 0),
0574 
0575     SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
0576     SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
0577 };
0578 
0579 static const struct snd_soc_dapm_route audio_map[] = {
0580     /* Analog bypass */
0581     {"Analog Left Bypass", "Switch", "LINEL"},
0582     {"Analog Right Bypass", "Switch", "LINER"},
0583 
0584     {"Output Left Amplifier", NULL, "DACL"},
0585     {"Output Right Amplifier", NULL, "DACR"},
0586 
0587     {"Left Bypass PGA", NULL, "Analog Left Bypass"},
0588     {"Right Bypass PGA", NULL, "Analog Right Bypass"},
0589 
0590     {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
0591     {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
0592     {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
0593     {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
0594 
0595     {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
0596     {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
0597 
0598     {"DACL", NULL, "Left DAC Power"},
0599     {"DACR", NULL, "Right DAC Power"},
0600 
0601     {"Left Bypass PGA", NULL, "Left DAC Power"},
0602     {"Right Bypass PGA", NULL, "Right DAC Power"},
0603 
0604     /* output */
0605     {"LEFT_LO", NULL, "Output Left Amplifier"},
0606     {"RIGHT_LO", NULL, "Output Right Amplifier"},
0607 
0608     {"LEFT_LO", NULL, "Codec Power"},
0609     {"RIGHT_LO", NULL, "Codec Power"},
0610 };
0611 
0612 static int dac33_set_bias_level(struct snd_soc_component *component,
0613                 enum snd_soc_bias_level level)
0614 {
0615     int ret;
0616 
0617     switch (level) {
0618     case SND_SOC_BIAS_ON:
0619         break;
0620     case SND_SOC_BIAS_PREPARE:
0621         break;
0622     case SND_SOC_BIAS_STANDBY:
0623         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
0624             /* Coming from OFF, switch on the component */
0625             ret = dac33_hard_power(component, 1);
0626             if (ret != 0)
0627                 return ret;
0628 
0629             dac33_init_chip(component);
0630         }
0631         break;
0632     case SND_SOC_BIAS_OFF:
0633         /* Do not power off, when the component is already off */
0634         if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
0635             return 0;
0636         ret = dac33_hard_power(component, 0);
0637         if (ret != 0)
0638             return ret;
0639         break;
0640     }
0641 
0642     return 0;
0643 }
0644 
0645 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
0646 {
0647     struct snd_soc_component *component = dac33->component;
0648     unsigned int delay;
0649     unsigned long flags;
0650 
0651     switch (dac33->fifo_mode) {
0652     case DAC33_FIFO_MODE1:
0653         dac33_write16(component, DAC33_NSAMPLE_MSB,
0654             DAC33_THRREG(dac33->nsample));
0655 
0656         /* Take the timestamps */
0657         spin_lock_irqsave(&dac33->lock, flags);
0658         dac33->t_stamp2 = ktime_to_us(ktime_get());
0659         dac33->t_stamp1 = dac33->t_stamp2;
0660         spin_unlock_irqrestore(&dac33->lock, flags);
0661 
0662         dac33_write16(component, DAC33_PREFILL_MSB,
0663                 DAC33_THRREG(dac33->alarm_threshold));
0664         /* Enable Alarm Threshold IRQ with a delay */
0665         delay = SAMPLES_TO_US(dac33->burst_rate,
0666                      dac33->alarm_threshold) + 1000;
0667         usleep_range(delay, delay + 500);
0668         dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
0669         break;
0670     case DAC33_FIFO_MODE7:
0671         /* Take the timestamp */
0672         spin_lock_irqsave(&dac33->lock, flags);
0673         dac33->t_stamp1 = ktime_to_us(ktime_get());
0674         /* Move back the timestamp with drain time */
0675         dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
0676         spin_unlock_irqrestore(&dac33->lock, flags);
0677 
0678         dac33_write16(component, DAC33_PREFILL_MSB,
0679                 DAC33_THRREG(DAC33_MODE7_MARGIN));
0680 
0681         /* Enable Upper Threshold IRQ */
0682         dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
0683         break;
0684     default:
0685         dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
0686                             dac33->fifo_mode);
0687         break;
0688     }
0689 }
0690 
0691 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
0692 {
0693     struct snd_soc_component *component = dac33->component;
0694     unsigned long flags;
0695 
0696     switch (dac33->fifo_mode) {
0697     case DAC33_FIFO_MODE1:
0698         /* Take the timestamp */
0699         spin_lock_irqsave(&dac33->lock, flags);
0700         dac33->t_stamp2 = ktime_to_us(ktime_get());
0701         spin_unlock_irqrestore(&dac33->lock, flags);
0702 
0703         dac33_write16(component, DAC33_NSAMPLE_MSB,
0704                 DAC33_THRREG(dac33->nsample));
0705         break;
0706     case DAC33_FIFO_MODE7:
0707         /* At the moment we are not using interrupts in mode7 */
0708         break;
0709     default:
0710         dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
0711                             dac33->fifo_mode);
0712         break;
0713     }
0714 }
0715 
0716 static void dac33_work(struct work_struct *work)
0717 {
0718     struct snd_soc_component *component;
0719     struct tlv320dac33_priv *dac33;
0720     u8 reg;
0721 
0722     dac33 = container_of(work, struct tlv320dac33_priv, work);
0723     component = dac33->component;
0724 
0725     mutex_lock(&dac33->mutex);
0726     switch (dac33->state) {
0727     case DAC33_PREFILL:
0728         dac33->state = DAC33_PLAYBACK;
0729         dac33_prefill_handler(dac33);
0730         break;
0731     case DAC33_PLAYBACK:
0732         dac33_playback_handler(dac33);
0733         break;
0734     case DAC33_IDLE:
0735         break;
0736     case DAC33_FLUSH:
0737         dac33->state = DAC33_IDLE;
0738         /* Mask all interrupts from dac33 */
0739         dac33_write(component, DAC33_FIFO_IRQ_MASK, 0);
0740 
0741         /* flush fifo */
0742         reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
0743         reg |= DAC33_FIFOFLUSH;
0744         dac33_write(component, DAC33_FIFO_CTRL_A, reg);
0745         break;
0746     }
0747     mutex_unlock(&dac33->mutex);
0748 }
0749 
0750 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
0751 {
0752     struct snd_soc_component *component = dev;
0753     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0754     unsigned long flags;
0755 
0756     spin_lock_irqsave(&dac33->lock, flags);
0757     dac33->t_stamp1 = ktime_to_us(ktime_get());
0758     spin_unlock_irqrestore(&dac33->lock, flags);
0759 
0760     /* Do not schedule the workqueue in Mode7 */
0761     if (dac33->fifo_mode != DAC33_FIFO_MODE7)
0762         schedule_work(&dac33->work);
0763 
0764     return IRQ_HANDLED;
0765 }
0766 
0767 static void dac33_oscwait(struct snd_soc_component *component)
0768 {
0769     int timeout = 60;
0770     u8 reg;
0771 
0772     do {
0773         usleep_range(1000, 2000);
0774         dac33_read(component, DAC33_INT_OSC_STATUS, &reg);
0775     } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
0776     if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
0777         dev_err(component->dev,
0778             "internal oscillator calibration failed\n");
0779 }
0780 
0781 static int dac33_startup(struct snd_pcm_substream *substream,
0782                struct snd_soc_dai *dai)
0783 {
0784     struct snd_soc_component *component = dai->component;
0785     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0786 
0787     /* Stream started, save the substream pointer */
0788     dac33->substream = substream;
0789 
0790     return 0;
0791 }
0792 
0793 static void dac33_shutdown(struct snd_pcm_substream *substream,
0794                  struct snd_soc_dai *dai)
0795 {
0796     struct snd_soc_component *component = dai->component;
0797     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0798 
0799     dac33->substream = NULL;
0800 }
0801 
0802 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
0803     (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
0804 static int dac33_hw_params(struct snd_pcm_substream *substream,
0805                struct snd_pcm_hw_params *params,
0806                struct snd_soc_dai *dai)
0807 {
0808     struct snd_soc_component *component = dai->component;
0809     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0810 
0811     /* Check parameters for validity */
0812     switch (params_rate(params)) {
0813     case 44100:
0814     case 48000:
0815         break;
0816     default:
0817         dev_err(component->dev, "unsupported rate %d\n",
0818             params_rate(params));
0819         return -EINVAL;
0820     }
0821 
0822     switch (params_width(params)) {
0823     case 16:
0824         dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
0825         dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
0826         break;
0827     case 32:
0828         dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
0829         dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
0830         break;
0831     default:
0832         dev_err(component->dev, "unsupported width %d\n",
0833             params_width(params));
0834         return -EINVAL;
0835     }
0836 
0837     return 0;
0838 }
0839 
0840 #define CALC_OSCSET(rate, refclk) ( \
0841     ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
0842 #define CALC_RATIOSET(rate, refclk) ( \
0843     ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
0844 
0845 /*
0846  * tlv320dac33 is strict on the sequence of the register writes, if the register
0847  * writes happens in different order, than dac33 might end up in unknown state.
0848  * Use the known, working sequence of register writes to initialize the dac33.
0849  */
0850 static int dac33_prepare_chip(struct snd_pcm_substream *substream,
0851                   struct snd_soc_component *component)
0852 {
0853     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
0854     unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
0855     u8 aictrl_a, aictrl_b, fifoctrl_a;
0856 
0857     switch (substream->runtime->rate) {
0858     case 44100:
0859     case 48000:
0860         oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
0861         ratioset = CALC_RATIOSET(substream->runtime->rate,
0862                      dac33->refclk);
0863         break;
0864     default:
0865         dev_err(component->dev, "unsupported rate %d\n",
0866             substream->runtime->rate);
0867         return -EINVAL;
0868     }
0869 
0870 
0871     aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
0872     aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
0873     /* Read FIFO control A, and clear FIFO flush bit */
0874     fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A);
0875     fifoctrl_a &= ~DAC33_FIFOFLUSH;
0876 
0877     fifoctrl_a &= ~DAC33_WIDTH;
0878     switch (substream->runtime->format) {
0879     case SNDRV_PCM_FORMAT_S16_LE:
0880         aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
0881         fifoctrl_a |= DAC33_WIDTH;
0882         break;
0883     case SNDRV_PCM_FORMAT_S32_LE:
0884         aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
0885         break;
0886     default:
0887         dev_err(component->dev, "unsupported format %d\n",
0888             substream->runtime->format);
0889         return -EINVAL;
0890     }
0891 
0892     mutex_lock(&dac33->mutex);
0893 
0894     if (!dac33->chip_power) {
0895         /*
0896          * Chip is not powered yet.
0897          * Do the init in the dac33_set_bias_level later.
0898          */
0899         mutex_unlock(&dac33->mutex);
0900         return 0;
0901     }
0902 
0903     dac33_soft_power(component, 0);
0904     dac33_soft_power(component, 1);
0905 
0906     reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
0907     dac33_write(component, DAC33_INT_OSC_CTRL, reg_tmp);
0908 
0909     /* Write registers 0x08 and 0x09 (MSB, LSB) */
0910     dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, oscset);
0911 
0912     /* OSC calibration time */
0913     dac33_write(component, DAC33_CALIB_TIME, 96);
0914 
0915     /* adjustment treshold & step */
0916     dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
0917                          DAC33_ADJSTEP(1));
0918 
0919     /* div=4 / gain=1 / div */
0920     dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
0921 
0922     pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL);
0923     pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
0924     dac33_write(component, DAC33_PWR_CTRL, pwr_ctrl);
0925 
0926     dac33_oscwait(component);
0927 
0928     if (dac33->fifo_mode) {
0929         /* Generic for all FIFO modes */
0930         /* 50-51 : ASRC Control registers */
0931         dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
0932         dac33_write(component, DAC33_ASRC_CTRL_B, 1); /* ??? */
0933 
0934         /* Write registers 0x34 and 0x35 (MSB, LSB) */
0935         dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
0936 
0937         /* Set interrupts to high active */
0938         dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
0939     } else {
0940         /* FIFO bypass mode */
0941         /* 50-51 : ASRC Control registers */
0942         dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
0943         dac33_write(component, DAC33_ASRC_CTRL_B, 0); /* ??? */
0944     }
0945 
0946     /* Interrupt behaviour configuration */
0947     switch (dac33->fifo_mode) {
0948     case DAC33_FIFO_MODE1:
0949         dac33_write(component, DAC33_FIFO_IRQ_MODE_B,
0950                 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
0951         break;
0952     case DAC33_FIFO_MODE7:
0953         dac33_write(component, DAC33_FIFO_IRQ_MODE_A,
0954             DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
0955         break;
0956     default:
0957         /* in FIFO bypass mode, the interrupts are not used */
0958         break;
0959     }
0960 
0961     aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
0962 
0963     switch (dac33->fifo_mode) {
0964     case DAC33_FIFO_MODE1:
0965         /*
0966          * For mode1:
0967          * Disable the FIFO bypass (Enable the use of FIFO)
0968          * Select nSample mode
0969          * BCLK is only running when data is needed by DAC33
0970          */
0971         fifoctrl_a &= ~DAC33_FBYPAS;
0972         fifoctrl_a &= ~DAC33_FAUTO;
0973         if (dac33->keep_bclk)
0974             aictrl_b |= DAC33_BCLKON;
0975         else
0976             aictrl_b &= ~DAC33_BCLKON;
0977         break;
0978     case DAC33_FIFO_MODE7:
0979         /*
0980          * For mode1:
0981          * Disable the FIFO bypass (Enable the use of FIFO)
0982          * Select Threshold mode
0983          * BCLK is only running when data is needed by DAC33
0984          */
0985         fifoctrl_a &= ~DAC33_FBYPAS;
0986         fifoctrl_a |= DAC33_FAUTO;
0987         if (dac33->keep_bclk)
0988             aictrl_b |= DAC33_BCLKON;
0989         else
0990             aictrl_b &= ~DAC33_BCLKON;
0991         break;
0992     default:
0993         /*
0994          * For FIFO bypass mode:
0995          * Enable the FIFO bypass (Disable the FIFO use)
0996          * Set the BCLK as continuous
0997          */
0998         fifoctrl_a |= DAC33_FBYPAS;
0999         aictrl_b |= DAC33_BCLKON;
1000         break;
1001     }
1002 
1003     dac33_write(component, DAC33_FIFO_CTRL_A, fifoctrl_a);
1004     dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1005     dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1006 
1007     /*
1008      * BCLK divide ratio
1009      * 0: 1.5
1010      * 1: 1
1011      * 2: 2
1012      * ...
1013      * 254: 254
1014      * 255: 255
1015      */
1016     if (dac33->fifo_mode)
1017         dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C,
1018                             dac33->burst_bclkdiv);
1019     else
1020         if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1021             dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 32);
1022         else
1023             dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, 16);
1024 
1025     switch (dac33->fifo_mode) {
1026     case DAC33_FIFO_MODE1:
1027         dac33_write16(component, DAC33_ATHR_MSB,
1028                   DAC33_THRREG(dac33->alarm_threshold));
1029         break;
1030     case DAC33_FIFO_MODE7:
1031         /*
1032          * Configure the threshold levels, and leave 10 sample space
1033          * at the bottom, and also at the top of the FIFO
1034          */
1035         dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1036         dac33_write16(component, DAC33_LTHR_MSB,
1037                   DAC33_THRREG(DAC33_MODE7_MARGIN));
1038         break;
1039     default:
1040         break;
1041     }
1042 
1043     mutex_unlock(&dac33->mutex);
1044 
1045     return 0;
1046 }
1047 
1048 static void dac33_calculate_times(struct snd_pcm_substream *substream,
1049                   struct snd_soc_component *component)
1050 {
1051     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1052     unsigned int period_size = substream->runtime->period_size;
1053     unsigned int rate = substream->runtime->rate;
1054     unsigned int nsample_limit;
1055 
1056     /* In bypass mode we don't need to calculate */
1057     if (!dac33->fifo_mode)
1058         return;
1059 
1060     switch (dac33->fifo_mode) {
1061     case DAC33_FIFO_MODE1:
1062         /* Number of samples under i2c latency */
1063         dac33->alarm_threshold = US_TO_SAMPLES(rate,
1064                         dac33->mode1_latency);
1065         nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1066 
1067         if (period_size <= dac33->alarm_threshold)
1068             /*
1069              * Configure nSamaple to number of periods,
1070              * which covers the latency requironment.
1071              */
1072             dac33->nsample = period_size *
1073                 ((dac33->alarm_threshold / period_size) +
1074                  ((dac33->alarm_threshold % period_size) ?
1075                 1 : 0));
1076         else if (period_size > nsample_limit)
1077             dac33->nsample = nsample_limit;
1078         else
1079             dac33->nsample = period_size;
1080 
1081         dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1082                               dac33->nsample);
1083         dac33->t_stamp1 = 0;
1084         dac33->t_stamp2 = 0;
1085         break;
1086     case DAC33_FIFO_MODE7:
1087         dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1088                             dac33->burst_rate) + 9;
1089         if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1090             dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1091         if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1092             dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1093 
1094         dac33->mode7_us_to_lthr =
1095                 SAMPLES_TO_US(substream->runtime->rate,
1096                     dac33->uthr - DAC33_MODE7_MARGIN + 1);
1097         dac33->t_stamp1 = 0;
1098         break;
1099     default:
1100         break;
1101     }
1102 
1103 }
1104 
1105 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1106                  struct snd_soc_dai *dai)
1107 {
1108     struct snd_soc_component *component = dai->component;
1109     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1110     int ret = 0;
1111 
1112     switch (cmd) {
1113     case SNDRV_PCM_TRIGGER_START:
1114     case SNDRV_PCM_TRIGGER_RESUME:
1115     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1116         if (dac33->fifo_mode) {
1117             dac33->state = DAC33_PREFILL;
1118             schedule_work(&dac33->work);
1119         }
1120         break;
1121     case SNDRV_PCM_TRIGGER_STOP:
1122     case SNDRV_PCM_TRIGGER_SUSPEND:
1123     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1124         if (dac33->fifo_mode) {
1125             dac33->state = DAC33_FLUSH;
1126             schedule_work(&dac33->work);
1127         }
1128         break;
1129     default:
1130         ret = -EINVAL;
1131     }
1132 
1133     return ret;
1134 }
1135 
1136 static snd_pcm_sframes_t dac33_dai_delay(
1137             struct snd_pcm_substream *substream,
1138             struct snd_soc_dai *dai)
1139 {
1140     struct snd_soc_component *component = dai->component;
1141     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1142     unsigned long long t0, t1, t_now;
1143     unsigned int time_delta, uthr;
1144     int samples_out, samples_in, samples;
1145     snd_pcm_sframes_t delay = 0;
1146     unsigned long flags;
1147 
1148     switch (dac33->fifo_mode) {
1149     case DAC33_FIFO_BYPASS:
1150         break;
1151     case DAC33_FIFO_MODE1:
1152         spin_lock_irqsave(&dac33->lock, flags);
1153         t0 = dac33->t_stamp1;
1154         t1 = dac33->t_stamp2;
1155         spin_unlock_irqrestore(&dac33->lock, flags);
1156         t_now = ktime_to_us(ktime_get());
1157 
1158         /* We have not started to fill the FIFO yet, delay is 0 */
1159         if (!t1)
1160             goto out;
1161 
1162         if (t0 > t1) {
1163             /*
1164              * Phase 1:
1165              * After Alarm threshold, and before nSample write
1166              */
1167             time_delta = t_now - t0;
1168             samples_out = time_delta ? US_TO_SAMPLES(
1169                         substream->runtime->rate,
1170                         time_delta) : 0;
1171 
1172             if (likely(dac33->alarm_threshold > samples_out))
1173                 delay = dac33->alarm_threshold - samples_out;
1174             else
1175                 delay = 0;
1176         } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1177             /*
1178              * Phase 2:
1179              * After nSample write (during burst operation)
1180              */
1181             time_delta = t_now - t0;
1182             samples_out = time_delta ? US_TO_SAMPLES(
1183                         substream->runtime->rate,
1184                         time_delta) : 0;
1185 
1186             time_delta = t_now - t1;
1187             samples_in = time_delta ? US_TO_SAMPLES(
1188                         dac33->burst_rate,
1189                         time_delta) : 0;
1190 
1191             samples = dac33->alarm_threshold;
1192             samples += (samples_in - samples_out);
1193 
1194             if (likely(samples > 0))
1195                 delay = samples;
1196             else
1197                 delay = 0;
1198         } else {
1199             /*
1200              * Phase 3:
1201              * After burst operation, before next alarm threshold
1202              */
1203             time_delta = t_now - t0;
1204             samples_out = time_delta ? US_TO_SAMPLES(
1205                         substream->runtime->rate,
1206                         time_delta) : 0;
1207 
1208             samples_in = dac33->nsample;
1209             samples = dac33->alarm_threshold;
1210             samples += (samples_in - samples_out);
1211 
1212             if (likely(samples > 0))
1213                 delay = samples > dac33->fifo_size ?
1214                     dac33->fifo_size : samples;
1215             else
1216                 delay = 0;
1217         }
1218         break;
1219     case DAC33_FIFO_MODE7:
1220         spin_lock_irqsave(&dac33->lock, flags);
1221         t0 = dac33->t_stamp1;
1222         uthr = dac33->uthr;
1223         spin_unlock_irqrestore(&dac33->lock, flags);
1224         t_now = ktime_to_us(ktime_get());
1225 
1226         /* We have not started to fill the FIFO yet, delay is 0 */
1227         if (!t0)
1228             goto out;
1229 
1230         if (t_now <= t0) {
1231             /*
1232              * Either the timestamps are messed or equal. Report
1233              * maximum delay
1234              */
1235             delay = uthr;
1236             goto out;
1237         }
1238 
1239         time_delta = t_now - t0;
1240         if (time_delta <= dac33->mode7_us_to_lthr) {
1241             /*
1242             * Phase 1:
1243             * After burst (draining phase)
1244             */
1245             samples_out = US_TO_SAMPLES(
1246                     substream->runtime->rate,
1247                     time_delta);
1248 
1249             if (likely(uthr > samples_out))
1250                 delay = uthr - samples_out;
1251             else
1252                 delay = 0;
1253         } else {
1254             /*
1255             * Phase 2:
1256             * During burst operation
1257             */
1258             time_delta = time_delta - dac33->mode7_us_to_lthr;
1259 
1260             samples_out = US_TO_SAMPLES(
1261                     substream->runtime->rate,
1262                     time_delta);
1263             samples_in = US_TO_SAMPLES(
1264                     dac33->burst_rate,
1265                     time_delta);
1266             delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1267 
1268             if (unlikely(delay > uthr))
1269                 delay = uthr;
1270         }
1271         break;
1272     default:
1273         dev_warn(component->dev, "Unhandled FIFO mode: %d\n",
1274                             dac33->fifo_mode);
1275         break;
1276     }
1277 out:
1278     return delay;
1279 }
1280 
1281 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1282         int clk_id, unsigned int freq, int dir)
1283 {
1284     struct snd_soc_component *component = codec_dai->component;
1285     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1286     u8 ioc_reg, asrcb_reg;
1287 
1288     ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL);
1289     asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B);
1290     switch (clk_id) {
1291     case TLV320DAC33_MCLK:
1292         ioc_reg |= DAC33_REFSEL;
1293         asrcb_reg |= DAC33_SRCREFSEL;
1294         break;
1295     case TLV320DAC33_SLEEPCLK:
1296         ioc_reg &= ~DAC33_REFSEL;
1297         asrcb_reg &= ~DAC33_SRCREFSEL;
1298         break;
1299     default:
1300         dev_err(component->dev, "Invalid clock ID (%d)\n", clk_id);
1301         break;
1302     }
1303     dac33->refclk = freq;
1304 
1305     dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, ioc_reg);
1306     dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, asrcb_reg);
1307 
1308     return 0;
1309 }
1310 
1311 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1312                  unsigned int fmt)
1313 {
1314     struct snd_soc_component *component = codec_dai->component;
1315     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1316     u8 aictrl_a, aictrl_b;
1317 
1318     aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A);
1319     aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B);
1320 
1321     switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1322     case SND_SOC_DAIFMT_CBP_CFP:
1323         aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1324         break;
1325     case SND_SOC_DAIFMT_CBC_CFC:
1326         if (dac33->fifo_mode) {
1327             dev_err(component->dev, "FIFO mode requires provider mode\n");
1328             return -EINVAL;
1329         } else
1330             aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1331         break;
1332     default:
1333         return -EINVAL;
1334     }
1335 
1336     aictrl_a &= ~DAC33_AFMT_MASK;
1337     switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1338     case SND_SOC_DAIFMT_I2S:
1339         aictrl_a |= DAC33_AFMT_I2S;
1340         break;
1341     case SND_SOC_DAIFMT_DSP_A:
1342         aictrl_a |= DAC33_AFMT_DSP;
1343         aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1344         aictrl_b |= DAC33_DATA_DELAY(0);
1345         break;
1346     case SND_SOC_DAIFMT_RIGHT_J:
1347         aictrl_a |= DAC33_AFMT_RIGHT_J;
1348         break;
1349     case SND_SOC_DAIFMT_LEFT_J:
1350         aictrl_a |= DAC33_AFMT_LEFT_J;
1351         break;
1352     default:
1353         dev_err(component->dev, "Unsupported format (%u)\n",
1354             fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1355         return -EINVAL;
1356     }
1357 
1358     dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1359     dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1360 
1361     return 0;
1362 }
1363 
1364 static int dac33_soc_probe(struct snd_soc_component *component)
1365 {
1366     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1367     int ret = 0;
1368 
1369     dac33->component = component;
1370 
1371     /* Read the tlv320dac33 ID registers */
1372     ret = dac33_hard_power(component, 1);
1373     if (ret != 0) {
1374         dev_err(component->dev, "Failed to power up component: %d\n", ret);
1375         goto err_power;
1376     }
1377     ret = dac33_read_id(component);
1378     dac33_hard_power(component, 0);
1379 
1380     if (ret < 0) {
1381         dev_err(component->dev, "Failed to read chip ID: %d\n", ret);
1382         ret = -ENODEV;
1383         goto err_power;
1384     }
1385 
1386     /* Check if the IRQ number is valid and request it */
1387     if (dac33->irq >= 0) {
1388         ret = request_irq(dac33->irq, dac33_interrupt_handler,
1389                   IRQF_TRIGGER_RISING,
1390                   component->name, component);
1391         if (ret < 0) {
1392             dev_err(component->dev, "Could not request IRQ%d (%d)\n",
1393                         dac33->irq, ret);
1394             dac33->irq = -1;
1395         }
1396         if (dac33->irq != -1) {
1397             INIT_WORK(&dac33->work, dac33_work);
1398         }
1399     }
1400 
1401     /* Only add the FIFO controls, if we have valid IRQ number */
1402     if (dac33->irq >= 0)
1403         snd_soc_add_component_controls(component, dac33_mode_snd_controls,
1404                      ARRAY_SIZE(dac33_mode_snd_controls));
1405 
1406 err_power:
1407     return ret;
1408 }
1409 
1410 static void dac33_soc_remove(struct snd_soc_component *component)
1411 {
1412     struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(component);
1413 
1414     if (dac33->irq >= 0) {
1415         free_irq(dac33->irq, dac33->component);
1416         flush_work(&dac33->work);
1417     }
1418 }
1419 
1420 static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = {
1421     .read           = dac33_read_reg_cache,
1422     .write          = dac33_write_locked,
1423     .set_bias_level     = dac33_set_bias_level,
1424     .probe          = dac33_soc_probe,
1425     .remove         = dac33_soc_remove,
1426     .controls       = dac33_snd_controls,
1427     .num_controls       = ARRAY_SIZE(dac33_snd_controls),
1428     .dapm_widgets       = dac33_dapm_widgets,
1429     .num_dapm_widgets   = ARRAY_SIZE(dac33_dapm_widgets),
1430     .dapm_routes        = audio_map,
1431     .num_dapm_routes    = ARRAY_SIZE(audio_map),
1432     .use_pmdown_time    = 1,
1433     .endianness     = 1,
1434 };
1435 
1436 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1437              SNDRV_PCM_RATE_48000)
1438 #define DAC33_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1439 
1440 static const struct snd_soc_dai_ops dac33_dai_ops = {
1441     .startup    = dac33_startup,
1442     .shutdown   = dac33_shutdown,
1443     .hw_params  = dac33_hw_params,
1444     .trigger    = dac33_pcm_trigger,
1445     .delay      = dac33_dai_delay,
1446     .set_sysclk = dac33_set_dai_sysclk,
1447     .set_fmt    = dac33_set_dai_fmt,
1448 };
1449 
1450 static struct snd_soc_dai_driver dac33_dai = {
1451     .name = "tlv320dac33-hifi",
1452     .playback = {
1453         .stream_name = "Playback",
1454         .channels_min = 2,
1455         .channels_max = 2,
1456         .rates = DAC33_RATES,
1457         .formats = DAC33_FORMATS,
1458         .sig_bits = 24,
1459     },
1460     .ops = &dac33_dai_ops,
1461 };
1462 
1463 static int dac33_i2c_probe(struct i2c_client *client)
1464 {
1465     struct tlv320dac33_platform_data *pdata;
1466     struct tlv320dac33_priv *dac33;
1467     int ret, i;
1468 
1469     if (client->dev.platform_data == NULL) {
1470         dev_err(&client->dev, "Platform data not set\n");
1471         return -ENODEV;
1472     }
1473     pdata = client->dev.platform_data;
1474 
1475     dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
1476                  GFP_KERNEL);
1477     if (dac33 == NULL)
1478         return -ENOMEM;
1479 
1480     dac33->reg_cache = devm_kmemdup(&client->dev,
1481                     dac33_reg,
1482                     ARRAY_SIZE(dac33_reg) * sizeof(u8),
1483                     GFP_KERNEL);
1484     if (!dac33->reg_cache)
1485         return -ENOMEM;
1486 
1487     dac33->i2c = client;
1488     mutex_init(&dac33->mutex);
1489     spin_lock_init(&dac33->lock);
1490 
1491     i2c_set_clientdata(client, dac33);
1492 
1493     dac33->power_gpio = pdata->power_gpio;
1494     dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1495     dac33->keep_bclk = pdata->keep_bclk;
1496     dac33->mode1_latency = pdata->mode1_latency;
1497     if (!dac33->mode1_latency)
1498         dac33->mode1_latency = 10000; /* 10ms */
1499     dac33->irq = client->irq;
1500     /* Disable FIFO use by default */
1501     dac33->fifo_mode = DAC33_FIFO_BYPASS;
1502 
1503     /* Check if the reset GPIO number is valid and request it */
1504     if (dac33->power_gpio >= 0) {
1505         ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1506         if (ret < 0) {
1507             dev_err(&client->dev,
1508                 "Failed to request reset GPIO (%d)\n",
1509                 dac33->power_gpio);
1510             goto err_gpio;
1511         }
1512         gpio_direction_output(dac33->power_gpio, 0);
1513     }
1514 
1515     for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1516         dac33->supplies[i].supply = dac33_supply_names[i];
1517 
1518     ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1519                  dac33->supplies);
1520 
1521     if (ret != 0) {
1522         dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1523         goto err_get;
1524     }
1525 
1526     ret = devm_snd_soc_register_component(&client->dev,
1527             &soc_component_dev_tlv320dac33, &dac33_dai, 1);
1528     if (ret < 0)
1529         goto err_get;
1530 
1531     return ret;
1532 err_get:
1533     if (dac33->power_gpio >= 0)
1534         gpio_free(dac33->power_gpio);
1535 err_gpio:
1536     return ret;
1537 }
1538 
1539 static int dac33_i2c_remove(struct i2c_client *client)
1540 {
1541     struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1542 
1543     if (unlikely(dac33->chip_power))
1544         dac33_hard_power(dac33->component, 0);
1545 
1546     if (dac33->power_gpio >= 0)
1547         gpio_free(dac33->power_gpio);
1548 
1549     return 0;
1550 }
1551 
1552 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1553     {
1554         .name = "tlv320dac33",
1555         .driver_data = 0,
1556     },
1557     { },
1558 };
1559 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
1560 
1561 static struct i2c_driver tlv320dac33_i2c_driver = {
1562     .driver = {
1563         .name = "tlv320dac33-codec",
1564     },
1565     .probe_new  = dac33_i2c_probe,
1566     .remove     = dac33_i2c_remove,
1567     .id_table   = tlv320dac33_i2c_id,
1568 };
1569 
1570 module_i2c_driver(tlv320dac33_i2c_driver);
1571 
1572 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1573 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1574 MODULE_LICENSE("GPL");
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